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From: Nishanth Menon <nm@ti.com>
To: Santosh Shilimkar <santosh.shilimkar@ti.com>,
	Tony Lindgren <tony@atomide.com>, Tero Kristo <t-kristo@ti.com>,
	Paul Walmsley <paul@pwsan.com>
Cc: "Nishanth Menon" <nm@ti.com>,
	"Kevin Hilman" <khilman@deeprootsystems.com>,
	Keerthy <j-keerthy@ti.com>,
	linux-kernel@vger.kernel.org,
	"Benoît Cousson" <bcousson@baylibre.com>,
	linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 01/10] ARM: OMAP5 / DRA7: PM: Update CPU context register offset
Date: Fri, 22 Aug 2014 09:02:25 -0500	[thread overview]
Message-ID: <1408716154-26101-2-git-send-email-nm@ti.com> (raw)
In-Reply-To: <1408716154-26101-1-git-send-email-nm@ti.com>

From: Santosh Shilimkar <santosh.shilimkar@ti.com>

On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/omap-mpuss-lowpower.c |   13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 4001325..63a1dd7 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -56,6 +56,7 @@
 #include "omap4-sar-layout.h"
 #include "pm.h"
 #include "prcm_mpu44xx.h"
+#include "prcm_mpu54xx.h"
 #include "prminst44xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
@@ -89,6 +90,7 @@ struct cpu_pm_ops {
 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
 static struct powerdomain *mpuss_pd;
 static void __iomem *sar_base;
+static u32 cpu_context_offset;
 
 static int default_finish_suspend(unsigned long cpu_state)
 {
@@ -161,14 +163,14 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
 
 	if (cpu_id) {
 		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
-					OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+					cpu_context_offset);
 		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
-					OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+					cpu_context_offset);
 	} else {
 		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
-					OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+					cpu_context_offset);
 		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
-					OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+					cpu_context_offset);
 	}
 }
 
@@ -392,6 +394,9 @@ int __init omap4_mpuss_init(void)
 		omap_pm_ops.finish_suspend = omap4_finish_suspend;
 		omap_pm_ops.resume = omap4_cpu_resume;
 		omap_pm_ops.scu_prepare = scu_pwrst_prepare;
+		cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
+	} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
+		cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
 	}
 
 	return 0;
-- 
1.7.9.5

  reply	other threads:[~2014-08-22 14:02 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-22 14:02 [PATCH 00/10] ARM: OMAP5 / DRA7: Add framework for suspend and cpuidle Nishanth Menon
2014-08-22 14:02 ` Nishanth Menon [this message]
2014-08-22 14:02 ` [PATCH 02/10] ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency Nishanth Menon
2014-08-27 18:44   ` Kevin Hilman
2014-08-22 14:02 ` [PATCH 03/10] ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default Nishanth Menon
2014-08-22 14:02 ` [PATCH 04/10] ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains Nishanth Menon
2014-08-22 14:02 ` [PATCH 05/10] ARM: OMAP5 / DRA7: PM: Avoid all SAR saves Nishanth Menon
2014-08-22 14:02 ` [PATCH 06/10] ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug Nishanth Menon
2014-08-22 14:02 ` [PATCH 07/10] ARM: OMAP5 / DRA7: Enable CPU RET on suspend Nishanth Menon
2014-08-27 18:58   ` Kevin Hilman
2014-08-27 19:05     ` Nishanth Menon
2014-08-27 19:41       ` Tony Lindgren
2014-08-27 19:43         ` Santosh Shilimkar
2014-08-27 19:45           ` Nishanth Menon
2014-09-05 21:15             ` Nishanth Menon
2014-09-05 21:30               ` Tony Lindgren
2014-09-08 17:23               ` Grazvydas Ignotas
2014-09-08 18:34                 ` Nishanth Menon
2014-08-22 14:02 ` [PATCH 08/10] ARM: OMAP5/DRA7: PM: cpuidle MPU CSWR support Nishanth Menon
2014-08-27 19:13   ` Kevin Hilman
2014-08-27 19:35     ` Nishanth Menon
2014-08-27 19:41       ` Santosh Shilimkar
2014-08-27 20:22         ` Kevin Hilman
2014-09-05 21:18           ` Nishanth Menon
2014-09-16 16:34             ` Nishanth Menon
2014-09-17 18:49   ` Daniel Lezcano
2014-09-17 23:20     ` Shilimkar, Santosh
2014-09-18  0:22       ` Daniel Lezcano
2014-09-18  0:42         ` Shilimkar, Santosh
2014-09-18 13:41         ` Nishanth Menon
2014-09-18 13:50           ` Nishanth Menon
2014-09-22 13:02             ` Nishanth Menon
2014-09-22 13:17               ` Nishanth Menon
2014-08-22 14:02 ` [PATCH 09/10] ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization Nishanth Menon
2014-08-22 14:02 ` [PATCH 10/10] ARM: DRA7: " Nishanth Menon
2014-08-25 16:36 ` [PATCH 00/10] ARM: OMAP5 / DRA7: Add framework for suspend and cpuidle Nishanth Menon
2014-08-27 19:15 ` Kevin Hilman
2014-09-08 16:29   ` Nishanth Menon

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