From: Nishanth Menon <nm@ti.com>
To: Santosh Shilimkar <santosh.shilimkar@ti.com>,
Tony Lindgren <tony@atomide.com>, Tero Kristo <t-kristo@ti.com>,
Paul Walmsley <paul@pwsan.com>
Cc: "Kevin Hilman" <khilman@deeprootsystems.com>,
linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org,
linux-kernel@vger.kernel.org, Keerthy <j-keerthy@ti.com>,
"Benoît Cousson" <bcousson@baylibre.com>,
"Nishanth Menon" <nm@ti.com>
Subject: [PATCH 07/10] ARM: OMAP5 / DRA7: Enable CPU RET on suspend
Date: Fri, 22 Aug 2014 09:02:31 -0500 [thread overview]
Message-ID: <1408716154-26101-8-git-send-email-nm@ti.com> (raw)
In-Reply-To: <1408716154-26101-1-git-send-email-nm@ti.com>
From: Rajendra Nayak <rnayak@ti.com>
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: update to do save_state only on DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 4 ++++
arch/arm/mach-omap2/omap-wakeupgen.c | 2 +-
arch/arm/mach-omap2/pm44xx.c | 9 +++++++--
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 207fce2..0d640eb 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -242,6 +242,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
save_state = 1;
break;
case PWRDM_POWER_RET:
+ if (soc_is_omap54xx() || soc_is_dra7xx()) {
+ save_state = 0;
+ break;
+ }
default:
/*
* CPUx CSWR is invalid hardware state. Also CPUx OSWR
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index e844e16..87c1c0d 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -381,7 +381,7 @@ static struct notifier_block irq_notifier_block = {
static void __init irq_pm_init(void)
{
/* FIXME: Remove this when MPU OSWR support is added */
- if (!soc_is_omap54xx())
+ if (!soc_is_omap54xx() && !soc_is_dra7xx())
cpu_pm_register_notifier(&irq_notifier_block);
}
#else
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index b6f243d..c063833 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -36,6 +36,8 @@ struct power_state {
struct list_head node;
};
+static u32 cpu_suspend_state = PWRDM_POWER_OFF;
+
static LIST_HEAD(pwrst_list);
#ifdef CONFIG_SUSPEND
@@ -66,7 +68,7 @@ static int omap4_pm_suspend(void)
* domain CSWR is not supported by hardware.
* More details can be found in OMAP4430 TRM section 4.3.4.2.
*/
- omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+ omap4_enter_lowpower(cpu_id, cpu_suspend_state);
/* Restore next powerdomain state */
list_for_each_entry(pwrst, &pwrst_list, node) {
@@ -112,8 +114,11 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
* through hotplug path and CPU0 explicitly programmed
* further down in the code path
*/
- if (!strncmp(pwrdm->name, "cpu", 3))
+ if (!strncmp(pwrdm->name, "cpu", 3)) {
+ if (soc_is_omap54xx() || soc_is_dra7xx())
+ cpu_suspend_state = PWRDM_POWER_RET;
return 0;
+ }
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
if (!pwrst)
--
1.7.9.5
next prev parent reply other threads:[~2014-08-22 14:02 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-22 14:02 [PATCH 00/10] ARM: OMAP5 / DRA7: Add framework for suspend and cpuidle Nishanth Menon
2014-08-22 14:02 ` [PATCH 01/10] ARM: OMAP5 / DRA7: PM: Update CPU context register offset Nishanth Menon
2014-08-22 14:02 ` [PATCH 02/10] ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency Nishanth Menon
2014-08-27 18:44 ` Kevin Hilman
2014-08-22 14:02 ` [PATCH 03/10] ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default Nishanth Menon
2014-08-22 14:02 ` [PATCH 04/10] ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains Nishanth Menon
2014-08-22 14:02 ` [PATCH 05/10] ARM: OMAP5 / DRA7: PM: Avoid all SAR saves Nishanth Menon
2014-08-22 14:02 ` [PATCH 06/10] ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug Nishanth Menon
2014-08-22 14:02 ` Nishanth Menon [this message]
2014-08-27 18:58 ` [PATCH 07/10] ARM: OMAP5 / DRA7: Enable CPU RET on suspend Kevin Hilman
2014-08-27 19:05 ` Nishanth Menon
2014-08-27 19:41 ` Tony Lindgren
2014-08-27 19:43 ` Santosh Shilimkar
2014-08-27 19:45 ` Nishanth Menon
2014-09-05 21:15 ` Nishanth Menon
2014-09-05 21:30 ` Tony Lindgren
2014-09-08 17:23 ` Grazvydas Ignotas
2014-09-08 18:34 ` Nishanth Menon
2014-08-22 14:02 ` [PATCH 08/10] ARM: OMAP5/DRA7: PM: cpuidle MPU CSWR support Nishanth Menon
2014-08-27 19:13 ` Kevin Hilman
2014-08-27 19:35 ` Nishanth Menon
2014-08-27 19:41 ` Santosh Shilimkar
2014-08-27 20:22 ` Kevin Hilman
2014-09-05 21:18 ` Nishanth Menon
2014-09-16 16:34 ` Nishanth Menon
2014-09-17 18:49 ` Daniel Lezcano
2014-09-17 23:20 ` Shilimkar, Santosh
2014-09-18 0:22 ` Daniel Lezcano
2014-09-18 0:42 ` Shilimkar, Santosh
2014-09-18 13:41 ` Nishanth Menon
2014-09-18 13:50 ` Nishanth Menon
2014-09-22 13:02 ` Nishanth Menon
2014-09-22 13:17 ` Nishanth Menon
2014-08-22 14:02 ` [PATCH 09/10] ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization Nishanth Menon
2014-08-22 14:02 ` [PATCH 10/10] ARM: DRA7: " Nishanth Menon
2014-08-25 16:36 ` [PATCH 00/10] ARM: OMAP5 / DRA7: Add framework for suspend and cpuidle Nishanth Menon
2014-08-27 19:15 ` Kevin Hilman
2014-09-08 16:29 ` Nishanth Menon
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