From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Parshuram Raju Thombare <pthombar@cadence.com>,
tjoseph@cadence.com, bhelgaas@google.com, robh@kernel.org,
kishon@ti.com, kw@linux.com
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
mparab@cadence.com, linux-pci@vger.kernel.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] PCI: cadence: Clear FLR in device capabilities register
Date: Wed, 11 May 2022 17:02:35 +0100 [thread overview]
Message-ID: <165228494389.11307.11313445181760109588.b4-ty@arm.com> (raw)
In-Reply-To: <1637048356-73662-1-git-send-email-pthombar@cadence.com>
On Mon, 15 Nov 2021 23:39:16 -0800, Parshuram Raju Thombare wrote:
> From: Parshuram Thombare <pthombar@cadence.com>
>
> Clear FLR (Function Level Reset) from device capabilities
> registers for all physical functions.
>
> During FLR, the Margining Lane Status and Margining Lane Control
> registers should not be reset, as per PCIe specification.
> However, the controller incorrectly resets these registers upon FLR.
> This causes PCISIG compliance FLR test to fail. Hence preventing
> all functions from advertising FLR support if flag quirk_disable_flr
> is set.
>
> [...]
Applied to pci/cadence, thanks!
[1/1] PCI: cadence: Clear FLR in device capabilities register
https://git.kernel.org/lpieralisi/pci/c/d3dbd4d862
Thanks,
Lorenzo
next prev parent reply other threads:[~2022-05-11 16:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-16 7:39 [PATCH v2] PCI: cadence: Clear FLR in device capabilities register Parshuram Raju Thombare
2021-12-13 14:26 ` Parshuram Raju Thombare
2022-05-11 16:02 ` Lorenzo Pieralisi [this message]
2022-05-12 19:06 ` Bjorn Helgaas
2022-05-12 21:23 ` Lorenzo Pieralisi
-- strict thread matches above, loose matches on Subject: below --
2021-10-25 12:31 Parshuram Raju Thombare
2021-10-25 12:44 ` Parshuram Raju Thombare
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