Re: clock divisor in mmc_omap_set_ios in drivers/mmc/omap.c wrong

[Tony Lindgren <tony@atomide.com>]

* Frantisek Dufka <dufkaf@seznam.cz> [061110 11:55]:
> Hello,
> 
> anyone knows real reason why the divisor is intentionally lowered in
> mmc_omap_set_ios so the result frequency is _not_ near the one requested?
> 
> First there is a code which tries hard to select the divisor that
> produces highest possible frequency which is lower or equal to the
> requested one
> 
>        fclk_rate = clk_get_rate(host->fclk);
>        dsor = fclk_rate / freq;
>        if (dsor < 1)
>                dsor = 1;
>        if (fclk_rate / dsor > freq)
>                dsor++;
> 
>        if (dsor > 250)
>                dsor = 250;
> 
> and then there is additional
> 
>        dsor++;
> 
> which intentionally makes resulting frequency lower by unknown factor.
> 
> If this is some workaround for specific cards maybe it should be solved
> in different place like blacklisting offending cards and actually
> requesting lower frequency for them. Or is  there some real reason?
> 
> For requested 20Mhz MMC bus speed and 48Mhz omap clock current code
> results in 12Mhz instead of 16Mhz.

This seems like a bug to me (or else the TRMs have a typo). Let's patch
it out and see if it still works.

Regards,

Tony