[PATCH 00/22] omap2 clock: Bugfixes and cleanups in OMAP2 clock framework

[PATCH 00/22] omap2 clock: Bugfixes and cleanups in OMAP2 clock framework

[Paul Walmsley]

Hello,

this patch series contains bugfixes and code cleanups for the OMAP2
clock framework.  Highlights include:

- VLYNQ clock fixes

- Addition of "fixed divisor" clock setup, for clocks that follow their
  parents' rates divided by a fixed divisor, like iva1_mpu_int_ifck and
  func_12m_ck

- Removal of several 2420-only clocks from 2430

- Fix "clock.c: Enable for dpll_ck without enable code" boot message

- osc_ck/sys_ck rate initialization fixes in omap2_get_crystal_rate()

- And many other minor fixes

These patches have been boot-tested on N800.  Comments, review, and
further testing are welcome.

- Paul


diffstat:

 arch/arm/mach-omap2/clock.c                      |  777 +++++++++++------------
 arch/arm/mach-omap2/clock.h                      |  362 ++++------
 include/asm-arm/arch-omap/clock.h                |    7
 linux-omap/arch/arm/mach-omap2/clock.c           |    5
 linux-omap/arch/arm/mach-omap2/clock.h           |   10
 linux-omap/arch/arm/mach-omap2/cm_regbits_24xx.h |    4
 linux-omap/arch/arm/mach-omap2/memory.c          |   50 +
 linux-omap/arch/arm/mach-omap2/memory.h          |    2
 linux-omap/include/asm-arm/arch-omap/clock.h     |    7
 9 files changed, 635 insertions(+), 589 deletions(-)

Object size change:

  text    data     bss     dec     hex filename
2839692  142692  138404 3120788  2f9e94 vmlinux.orig
2840280  143180  138404 3121864  2fa2c8 vmlinux.patched

--

[PATCH 01/22] omap2 clock: drop meaningless RATE_CKCTLs

[Paul Walmsley]

[-- Attachment #1: drop_meaningless_rate_ckctls.patch --]
[-- Type: text/plain, Size: 2206 bytes --]

Drop the RATE_CKCTL clock flag from iva1_mpu_int_ifck, gfx_ick, ssi_l4_ick,
and dss_ick.  These clocks are not source-selectable, which is the practical
meaning of RATE_CKCTL in the 2420 clock framework.  

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.h |    9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -861,7 +861,7 @@ static struct clk iva1_ifck = {
 static struct clk iva1_mpu_int_ifck = {
 	.name		= "iva1_mpu_int_ifck",
 	.parent		= &iva1_ifck,
-	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
+	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP2420_EN_IVA_MPU_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
@@ -964,8 +964,7 @@ static struct clk gfx_2d_fck = {
 static struct clk gfx_ick = {
 	.name		= "gfx_ick",		/* From l3 */
 	.parent		= &core_l3_ck,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				RATE_CKCTL,
+	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),	/* bit 0 */
 	.enable_bit	= OMAP_EN_GFX_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
@@ -1018,7 +1017,7 @@ static struct clk l4_ck = {		/* used bot
 static struct clk ssi_l4_ick = {
 	.name		= "ssi_l4_ick",
 	.parent		= &l4_ck,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
+	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),	/* bit 1 */
 	.enable_bit	= OMAP24XX_EN_SSI_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
@@ -1035,7 +1034,7 @@ static struct clk ssi_l4_ick = {
 static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
 	.name		= "dss_ick",
 	.parent		= &l4_ck,	/* really both l3 and l4 */
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
+	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_DSS1_SHIFT,
 	.recalc		= &omap2_followparent_recalc,

-- 

[PATCH 02/22] omap2 clock: fix incorrect rate calculation for osc_ck, sys_ck

[Paul Walmsley]

[-- Attachment #1: fix_get_crystal_rate_error.patch --]
[-- Type: text/plain, Size: 820 bytes --]

omap2_get_crystal_rate() calculates osc_ck and sys_ck rates
incorrectly.  osc_ck runs at the same rate as the external clock
source.  Also, sys_ck's rate derives from osc_ck's rate, divided (not
multiplied) by PRCM_CLKSRC_CTRL:SYSCLKDIV.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -1126,8 +1126,8 @@ static void __init omap2_get_crystal_rat
 	div &= OMAP_SYSCLKDIV_MASK;
 	div >>= sys->rate_offset;
 
-	osc->rate = sclk * div;
-	sys->rate = sclk;
+	osc->rate = sclk;
+	sys->rate = osc->rate / div;
 }
 
 /*

-- 

[PATCH 03/22] omap2 clock: fix clksel divisor bug

[Paul Walmsley]

[-- Attachment #1: fix_clock_div_error.patch --]
[-- Type: text/plain, Size: 1015 bytes --]

For clksel clocks, omap2_clk_set_rate() incorrectly divides the parent
clock's rate by the actual bits of the register field, rather than the
translated divisor value.  This happens to work for most clksel
clocks, since the register bit fields are equal to the divisor values.
But for some clocks, such as sys_clkout, the code gets the resulting
rate wrong.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -819,7 +819,7 @@ static int omap2_clk_set_rate(struct clk
 		reg_val |= (field_val << div_off);
 		cm_write_reg(reg_val, reg);
 		wmb();
-		clk->rate = clk->parent->rate / field_val;
+		clk->rate = clk->parent->rate / new_div;
 
 		if (clk->flags & DELAYED_APP) {
 			prm_write_reg(OMAP24XX_VALID_CONFIG,

-- 

[PATCH 04/22] omap2 clock: vlynq_fck recalc should be clksel, not followparent

[Paul Walmsley]

[-- Attachment #1: vlynq_recalc_should_be_clksel.patch --]
[-- Type: text/plain, Size: 1929 bytes --]

vlynq_fck is a clksel clock, so its rate is equal to its parent's
rate, divided by whichever divisor is selected.  But its definition in
clock.h specifies omap2_followparent_recalc() as its rate calculation
code, which sets the clock's rate to that of its parent without
accounting for any divisor.  Fix to use omap2_clksel_recalc() instead.
omap2_clksel_recalc() is also missing the appropriate special case to
divide the vlynq_fck rate down; add this in.

Signed-off-by: Paul Walmsley <paul@pwsan.com>


---
 arch/arm/mach-omap2/clock.c |   10 ++++++++++
 arch/arm/mach-omap2/clock.h |    2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -1824,7 +1824,7 @@ static struct clk vlynq_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_VLYNQ_SHIFT,
 	.src_offset	= 15,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &omap2_clksel_recalc,
 };
 
 static struct clk sdrc_ick = {
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -39,6 +39,10 @@
 
 #undef DEBUG
 
+/* CM_CLKSEL1_CORE.CLKSEL_VLYNQ options (2420) */
+#define CLKSEL_VLYNQ_96MHZ		0
+#define CLKSEL_VLYNQ_CORECLK_16		0x10
+
 /* SET_PERFORMANCE_LEVEL PARAMETERS */
 #define PRCM_HALF_SPEED		1
 #define PRCM_FULL_SPEED		2
@@ -358,6 +362,12 @@ static void omap2_clksel_recalc(struct c
 		return;
 	}
 
+	if ((clk == &vlynq_fck) && cpu_is_omap2420() &&
+	    (clksel1_core & OMAP2420_CLKSEL_VLYNQ_MASK) == CLKSEL_VLYNQ_96MHZ) {
+		clk->rate = func_96m_ck.rate;
+		return;
+	}
+
 	if (!fixed) {
 		div = omap2_clksel_get_divisor(clk);
 		if (div == 0)

-- 

[PATCH 05/22] omap2 clock: fix CodingStyle issues

[Paul Walmsley]

[-- Attachment #1: codingstyle-clock.c.patch --]
[-- Type: text/plain, Size: 3899 bytes --]

Clean up some CodingStyle non-conformances in clock.c.

Signed-off-by: Paul Walmsley <paul@pwsan.com>


---
 arch/arm/mach-omap2/clock.c |   40 ++++++++++++++++++++--------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -396,7 +396,7 @@ static inline u32 omap2_divider_from_tab
 	if (div_array == NULL)
 		return ~1;
 
-	for (i=0; i < size; i++) {
+	for (i = 0; i < size; i++) {
 		test_rate = src_rate / *div_array;
 		if (test_rate <= tgt_rate)
 			return *div_array;
@@ -418,45 +418,45 @@ static u32 omap2_clksel_round_rate(struc
 	u32 gfx_div[] = {2, 3, 4};
 	u32 sysclkout_div[] = {1, 2, 4, 8, 16};
 	u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
-	u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
+	u32 vlynq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
 	u32 best_div = ~0, asize = 0;
 	u32 *div_array = NULL;
 
 	switch (tclk->flags & SRC_RATE_SEL_MASK) {
 	case CM_GFX_SEL1:
-		asize = 3;
+		asize = ARRAY_SIZE(gfx_div);
 		div_array = gfx_div;
 		break;
 	case CM_PLL_SEL1:
 		return omap2_dpll_round_rate(target_rate);
 	case CM_SYSCLKOUT_SEL1:
-		asize = 5;
+		asize = ARRAY_SIZE(sysclkout_div);
 		div_array = sysclkout_div;
 		break;
 	case CM_CORE_SEL1:
-		if(tclk == &dss1_fck){
-			if(tclk->parent == &core_ck){
-				asize = 10;
+		if (tclk == &dss1_fck) {
+			if (tclk->parent == &core_ck) {
+				asize = ARRAY_SIZE(dss1_div);
 				div_array = dss1_div;
 			} else {
 				*new_div = 0; /* fixed clk */
 				return(tclk->parent->rate);
 			}
-		} else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
-			if(tclk->parent == &core_ck){
-				asize = 10;
-				div_array = vylnq_div;
+		} else if ((tclk == &vlynq_fck) && cpu_is_omap2420()) {
+			if (tclk->parent == &core_ck) {
+				asize = ARRAY_SIZE(vlynq_div);
+				div_array = vlynq_div;
 			} else {
 				*new_div = 0; /* fixed clk */
-				return(tclk->parent->rate);
+				return (tclk->parent->rate);
 			}
 		}
 		break;
 	}
 
 	best_div = omap2_divider_from_table(asize, div_array,
-	 tclk->parent->rate, target_rate);
-	if (best_div == ~0){
+					    tclk->parent->rate, target_rate);
+	if (best_div == ~0) {
 		*new_div = 1;
 		return best_div; /* signal error */
 	}
@@ -778,7 +778,6 @@ static u32 omap2_clksel_get_divisor(stru
 
 /* Set the clock rate for a clock source */
 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
-
 {
 	int ret = -EINVAL;
 	void __iomem * reg;
@@ -795,7 +794,7 @@ static int omap2_clk_set_rate(struct clk
 
 		validrate = omap2_clksel_round_rate(clk, rate, &new_div);
 		if (validrate != rate)
-			return(ret);
+			return ret;
 
 		field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 		if (div_sel == 0)
@@ -837,8 +836,9 @@ static int omap2_clk_set_rate(struct clk
 			wmb();
 		}
 		ret = 0;
-	} else if (clk->set_rate != 0)
+	} else if (clk->set_rate != 0) {
 		ret = clk->set_rate(clk, rate);
+	}
 
 	if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 		propagate_rate(clk);
@@ -872,10 +872,10 @@ static u32 omap2_get_src_field(u32 *type
 			else if (src_clk == &core_ck)	/* divided clock */
 				val = 0x10;		/* rate needs fixing */
 		} else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
-			   cpu_is_omap2420()){
+			   cpu_is_omap2420()) {
 			mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 			mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
-			if(src_clk == &func_96m_ck)
+			if (src_clk == &func_96m_ck)
 				val = 0;
 			else if (src_clk == &core_ck)
 				val = 0x10;
@@ -1034,7 +1034,7 @@ static int omap2_select_table_rate(struc
 
 	if (!found_speed) {
 		printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
-	 rate / 1000000);
+		       rate / 1000000);
 		return -EINVAL;
 	}
 

-- 

[PATCH 06/22] omap2 clock: drop unnecessary variable in omap2_clk_round_rate()

[Paul Walmsley]

[-- Attachment #1: other-clock.c-cleanups.patch --]
[-- Type: text/plain, Size: 931 bytes --]

Drop an unnecessary variable, valid_rate, in omap2_clk_round_rate().

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |    7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -469,15 +469,12 @@ static u32 omap2_clksel_round_rate(struc
 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 {
 	u32 new_div = 0;
-	int valid_rate;
 
 	if (clk->flags & RATE_FIXED)
 		return clk->rate;
 
-	if (clk->flags & RATE_CKCTL) {
-		valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
-		return valid_rate;
-	}
+	if (clk->flags & RATE_CKCTL)
+		return omap2_clksel_round_rate(clk, rate, &new_div);
 
 	if (clk->round_rate != 0)
 		return clk->round_rate(clk, rate);

-- 

[PATCH 07/22] omap2 clock: get rid of sleep_ck

[Paul Walmsley]

[-- Attachment #1: drop_sleep_ck.patch --]
[-- Type: text/plain, Size: 1190 bytes --]

According to the 2420 TRM rev J, SLEEP_CLK doesn't have any registers
or bits associated with it, so it's outside software control.  It's
also a leaf clock - no software-controllable clocks use it as a
parent.  There's nothing we can do with it in software.  So, drop it.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.h |    9 ---------
 1 file changed, 9 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -684,14 +684,6 @@ static struct clk core_ck = {
 	.recalc		= &omap2_propagate_rate,
 };
 
-static struct clk sleep_ck = {		/* sys_clk or 32k */
-	.name		= "sleep_ck",
-	.parent		= &func_32k_ck,
-	.rate		= 32000,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.recalc		= &omap2_propagate_rate,
-};
-
 static struct clk func_96m_ck = {
 	.name		= "func_96m_ck",
 	.parent		= &apll96_ck,
@@ -2017,7 +2009,6 @@ static struct clk *onchip_clks[] = {
 	/* internal prcm root sources */
 	&func_54m_ck,
 	&core_ck,
-	&sleep_ck,
 	&func_96m_ck,
 	&func_48m_ck,
 	&func_12m_ck,

-- 

[PATCH 08/22] omap2 clock: clean up dss2_fck clock flags

[Paul Walmsley]

[-- Attachment #1: cleanup_dss2_fck.patch --]
[-- Type: text/plain, Size: 1231 bytes --]

dss2_fck is not a fixed-rate clock; its rate is dependent on its parent's
rate.  So, drop the .rate assignment and drop the RATE_FIXED clock flag.  
It also is a leaf clock - no clocks have it as a parent - so it can't 
propagate its rate anywhere.  So, drop the RATE_PROPAGATES and fix the
recalc function pointer accordingly.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.h |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -1059,12 +1059,10 @@ static struct clk dss2_fck = {		/* Alt c
 static struct clk dss_54m_fck = {	/* Alt clk used in power management */
 	.name		= "dss_54m_fck",	/* 54m tv clk */
 	.parent		= &func_54m_ck,
-	.rate		= 54000000,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				RATE_FIXED | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_TV_SHIFT,
-	.recalc		= &omap2_propagate_rate,
+	.recalc		= &omap2_followparent_recalc,
 };
 
 /*

-- 

[PATCH 09/22] omap2 clock: move SDRC-related code from clock.c to memory.c

[Paul Walmsley]

[-- Attachment #1: cleanup-clock.c-sdrc.patch --]
[-- Type: text/plain, Size: 8056 bytes --]

The clock framework contains two functions, omap2_dll_force_needed()
and omap2_reprogram_sdrc(), which are SDRC code, not really clock
code.  So, move these functions to memory.c.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c       |   72 +++++---------------------------------
 arch/arm/mach-omap2/memory.c      |   50 ++++++++++++++++++++++++++
 arch/arm/mach-omap2/memory.h      |    2 +
 include/asm-arm/arch-omap/clock.h |    6 +++
 4 files changed, 68 insertions(+), 62 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -35,7 +35,6 @@
 #include "prm_regbits_24xx.h"
 #include "cm.h"
 #include "cm_regbits_24xx.h"
-#include "sdrc.h"
 
 #undef DEBUG
 
@@ -43,10 +42,6 @@
 #define CLKSEL_VLYNQ_96MHZ		0
 #define CLKSEL_VLYNQ_CORECLK_16		0x10
 
-/* SET_PERFORMANCE_LEVEL PARAMETERS */
-#define PRCM_HALF_SPEED		1
-#define PRCM_FULL_SPEED		2
-
 //#define DOWN_VARIABLE_DPLL 1			/* Experimental */
 
 static struct prcm_config *curr_prcm_set;
@@ -482,53 +477,6 @@ static long omap2_clk_round_rate(struct 
 	return clk->rate;
 }
 
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compensate for the shifted DLL value in unlock mode.
- */
-static u32 omap2_dll_force_needed(void)
-{
-	/* dlla and dllb are a set */
-	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
-
-	if ((dll_state & (1 << 2)) == (1 << 2))
-		return 1;
-	else
-		return 0;
-}
-
-static u32 omap2_reprogram_sdrc(u32 level, u32 force)
-{
-	u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
-	u32 prev = curr_perf_level, flags;
-
-	if ((curr_perf_level == level) && !force)
-		return prev;
-
-	m_type = omap2_memory_get_type();
-	slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
-	fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
-
-	if (level == PRCM_HALF_SPEED) {
-		local_irq_save(flags);
-		prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
-		omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
-					  slow_dll_ctrl, m_type);
-		curr_perf_level = PRCM_HALF_SPEED;
-		local_irq_restore(flags);
-	}
-	if (level == PRCM_FULL_SPEED) {
-		local_irq_save(flags);
-		prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
-		omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
-					  fast_dll_ctrl, m_type);
-		curr_perf_level = PRCM_FULL_SPEED;
-		local_irq_restore(flags);
-	}
-
-	return prev;
-}
-
 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 {
 	u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
@@ -542,9 +490,9 @@ static int omap2_reprogram_dpll(struct c
 	mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
 	if ((rate == (cur_rate / 2)) && (mult == 2)) {
-		omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
+		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-		omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
+		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 	} else if (rate != cur_rate) {
 		valid_rate = omap2_dpll_round_rate(rate);
 		if (valid_rate != rate)
@@ -564,11 +512,11 @@ static int omap2_reprogram_dpll(struct c
 		if (rate > low) {
 			tmpset.cm_clksel2_pll |= 0x2;
 			mult = ((rate / 2) / 1000000);
-			done_rate = PRCM_FULL_SPEED;
+			done_rate = CORE_CLK_SRC_DPLL_X2;
 		} else {
 			tmpset.cm_clksel2_pll |= 0x1;
 			mult = (rate / 1000000);
-			done_rate = PRCM_HALF_SPEED;
+			done_rate = CORE_CLK_SRC_DPLL;
 		}
 		tmpset.cm_clksel1_pll |= (div << OMAP24XX_DPLL_DIV_SHIFT);
 		tmpset.cm_clksel1_pll |= (mult << OMAP24XX_DPLL_MULT_SHIFT);
@@ -579,7 +527,7 @@ static int omap2_reprogram_dpll(struct c
 		if (rate == curr_prcm_set->xtal_speed)	/* If asking for 1-1 */
 			bypass = 1;
 
-		omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
+		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
 
 		/* Force dll lock mode */
 		omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
@@ -1039,9 +987,9 @@ static int omap2_select_table_rate(struc
 	cur_rate = omap2_get_dpll_rate(&dpll_ck);
 
 	if (prcm->dpll_speed == cur_rate / 2) {
-		omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
+		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 	} else if (prcm->dpll_speed == cur_rate * 2) {
-		omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
+		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 	} else if (prcm->dpll_speed != cur_rate) {
 		local_irq_save(flags);
 
@@ -1049,9 +997,9 @@ static int omap2_select_table_rate(struc
 			bypass = 1;
 
 		if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == 2)
-			done_rate = PRCM_FULL_SPEED;
+			done_rate = CORE_CLK_SRC_DPLL_X2;
 		else
-			done_rate = PRCM_HALF_SPEED;
+			done_rate = CORE_CLK_SRC_DPLL;
 
 		/* MPU divider */
 		cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
@@ -1070,7 +1018,7 @@ static int omap2_select_table_rate(struc
 					 OMAP2430_MDM_MOD, CM_CLKSEL);
 
 		/* x2 to enter init_mem */
-		omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
+		omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 
 		omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 			       bypass);
Index: linux-omap/arch/arm/mach-omap2/memory.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/memory.c
+++ linux-omap/arch/arm/mach-omap2/memory.c
@@ -27,12 +27,15 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
 
+#include "prm.h"
+
 #include "memory.h"
 #include "sdrc.h"
 
 #define SMS_SYSCONFIG			(OMAP2_SMS_BASE + 0x010)
 
 static struct memory_timings mem_timings;
+static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
 
 u32 omap2_memory_get_slow_dll_ctrl(void)
 {
@@ -49,6 +52,53 @@ u32 omap2_memory_get_type(void)
 	return mem_timings.m_type;
 }
 
+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compensate for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+	/* dlla and dllb are a set */
+	u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+
+	if ((dll_state & (1 << 2)) == (1 << 2))
+		return 1;
+	else
+		return 0;
+}
+
+/*
+ * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
+ * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
+ * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ */
+u32 omap2_reprogram_sdrc(u32 level, u32 force)
+{
+	u32 dll_ctrl, m_type;
+	u32 prev = curr_perf_level, flags;
+
+	if ((curr_perf_level == level) && !force)
+		return prev;
+
+	if (level == CORE_CLK_SRC_DPLL) {
+		dll_ctrl = omap2_memory_get_slow_dll_ctrl();
+	} else if (level == CORE_CLK_SRC_DPLL_X2) {
+		dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+	} else {
+		return prev;
+	}
+
+	m_type = omap2_memory_get_type();
+
+	local_irq_save(flags);
+	prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
+	omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
+	curr_perf_level = level;
+	local_irq_restore(flags);
+
+	return prev;
+}
+
 void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
 {
 	unsigned long dll_cnt;
Index: linux-omap/arch/arm/mach-omap2/memory.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/memory.h
+++ linux-omap/arch/arm/mach-omap2/memory.h
@@ -32,3 +32,5 @@ extern void omap2_init_memory_params(u32
 extern u32 omap2_memory_get_slow_dll_ctrl(void);
 extern u32 omap2_memory_get_fast_dll_ctrl(void);
 extern u32 omap2_memory_get_type(void);
+u32 omap2_dll_force_needed(void);
+u32 omap2_reprogram_sdrc(u32 level, u32 force);
Index: linux-omap/include/asm-arm/arch-omap/clock.h
===================================================================
--- linux-omap.orig/include/asm-arm/arch-omap/clock.h
+++ linux-omap/include/asm-arm/arch-omap/clock.h
@@ -89,4 +89,10 @@ extern int clk_get_usecount(struct clk *
 #define CLOCK_IN_OMAP243X	(1 << 26)
 #define CLOCK_IN_OMAP343X	(1 << 27)
 
+
+/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
+#define CORE_CLK_SRC_32K		0
+#define CORE_CLK_SRC_DPLL		1
+#define CORE_CLK_SRC_DPLL_X2		2
+
 #endif

-- 

[PATCH 10/22] omap2 clock: use symbolic constants in clock.h rate_offset/src_offset fields

[Paul Walmsley]

[-- Attachment #1: cleanup-clock.h-magic-numbers.patch --]
[-- Type: text/plain, Size: 12563 bytes --]

Convert most of the magic numbers remaining in mach-omap2/clock.h to
symbolic constants.  This primarily affects the src_offset/rate_offset 
fields.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.h           |   78 ++++++++++++++++------------------
 arch/arm/mach-omap2/cm_regbits_24xx.h |    3 +
 2 files changed, 41 insertions(+), 40 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -65,10 +65,8 @@ struct prcm_config {
 			CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
 
 /* Mask for clksel regs which support rate operations */
-#define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
-			CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
-			CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
-			CM_SYSCLKOUT_SEL1)
+#define SRC_RATE_SEL_MASK (SRC_SEL_MASK | CM_MPU_SEL1 | CM_DSP_SEL1 | \
+			CM_GFX_SEL1 | CM_MODEM_SEL1)
 
 /*
  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
@@ -614,7 +612,7 @@ static struct clk sys_ck = {		/* (*12, *
 	.rate		= 13000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-	.rate_offset	= 6, /* sysclkdiv 1 or 2, already handled or no boot */
+	.rate_offset	= OMAP_SYSCLKDIV_SHIFT, /* sysclkdiv 1 or 2, already handled or no boot */
 	.recalc		= &omap2_sys_clk_recalc,
 };
 
@@ -670,7 +668,7 @@ static struct clk func_54m_ck = {
 	.rate		= 54000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
-	.src_offset	= 5,
+	.src_offset	= OMAP24XX_54M_SOURCE_SHIFT,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
@@ -701,7 +699,7 @@ static struct clk func_48m_ck = {
 	.rate		= 48000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
-	.src_offset	= 3,
+	.src_offset	= OMAP24XX_48M_SOURCE_SHIFT,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
@@ -732,10 +730,10 @@ static struct clk sys_clkout = {
 	.rate		= 54000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
-	.src_offset	= 0,
+	.src_offset	= OMAP24XX_CLKOUT_SOURCE_SHIFT,
 	.enable_reg	= OMAP24XX_PRCM_CLKOUT_CTRL,
 	.enable_bit	= OMAP24XX_CLKOUT_EN_SHIFT,
-	.rate_offset	= 3,
+	.rate_offset	= OMAP24XX_CLKOUT_DIV_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -746,10 +744,10 @@ static struct clk sys_clkout2 = {
 	.rate		= 54000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
-	.src_offset	= 8,
+	.src_offset	= OMAP2420_CLKOUT2_SOURCE_SHIFT,
 	.enable_reg	= OMAP24XX_PRCM_CLKOUT_CTRL,
 	.enable_bit	= OMAP2420_CLKOUT2_EN_SHIFT,
-	.rate_offset	= 11,
+	.rate_offset	= OMAP2420_CLKOUT2_DIV_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -779,7 +777,7 @@ static struct clk mpu_ck = {	/* Control 
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 				ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 				CONFIG_PARTICIPANT | RATE_PROPAGATES,
-	.rate_offset	= 0,	/* bits 0-4 */
+	.rate_offset	= OMAP24XX_CLKSEL_MPU_SHIFT,	/* bits 0-4 */
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -795,7 +793,7 @@ static struct clk iva2_1_fck = {
 	.flags		= CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 				DELAYED_APP | RATE_PROPAGATES |
 				CONFIG_PARTICIPANT,
-	.rate_offset	= 0,
+	.rate_offset	= OMAP24XX_CLKSEL_DSP_SHIFT,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
@@ -806,7 +804,7 @@ static struct clk iva2_1_ick = {
 	.parent		= &iva2_1_fck,
 	.flags		= CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 				DELAYED_APP | CONFIG_PARTICIPANT,
-	.rate_offset	= 5,
+	.rate_offset	= OMAP24XX_CLKSEL_DSP_IF_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -821,7 +819,7 @@ static struct clk dsp_fck = {
 	.parent		= &core_ck,
 	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 			DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
-	.rate_offset	= 0,
+	.rate_offset	= OMAP24XX_CLKSEL_DSP_SHIFT,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
@@ -832,7 +830,7 @@ static struct clk dsp_ick = {
 	.parent		= &dsp_fck,
 	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 				DELAYED_APP | CONFIG_PARTICIPANT,
-	.rate_offset	= 5,
+	.rate_offset	= OMAP24XX_CLKSEL_DSP_IF_SHIFT,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP2420_EN_DSP_IPI_SHIFT,		/* for ipi */
 	.recalc		= &omap2_clksel_recalc,
@@ -843,7 +841,7 @@ static struct clk iva1_ifck = {
 	.parent		= &core_ck,
 	.flags		= CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 			CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
-	.rate_offset	= 8,
+	.rate_offset	= OMAP2420_CLKSEL_IVA_SHIFT,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP2420_EN_IVA_COP_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
@@ -885,7 +883,7 @@ static struct clk core_l3_ck = {	/* Used
 				RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 				DELAYED_APP | CONFIG_PARTICIPANT |
 				RATE_PROPAGATES,
-	.rate_offset	= 0,
+	.rate_offset	= OMAP24XX_CLKSEL_L3_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -897,7 +895,7 @@ static struct clk usb_l4_ick = {	/* FS-U
 				CONFIG_PARTICIPANT,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP24XX_EN_USB_SHIFT,
-	.rate_offset	= 25,
+	.rate_offset	= OMAP24XX_CLKSEL_USB_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -916,7 +914,7 @@ static struct clk ssi_ssr_sst_fck = {
 				RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),	/* bit 1 */
 	.enable_bit	= OMAP24XX_EN_SSI_SHIFT,
-	.rate_offset	= 20,
+	.rate_offset	= OMAP24XX_CLKSEL_SSI_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -938,7 +936,7 @@ static struct clk gfx_3d_fck = {
 				RATE_CKCTL | CM_GFX_SEL1,
 	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP24XX_EN_3D_SHIFT,
-	.rate_offset	= 0,
+	.rate_offset	= OMAP_CLKSEL_GFX_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -949,7 +947,7 @@ static struct clk gfx_2d_fck = {
 				RATE_CKCTL | CM_GFX_SEL1,
 	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP24XX_EN_2D_SHIFT,
-	.rate_offset	= 0,
+	.rate_offset	= OMAP_CLKSEL_GFX_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -973,7 +971,7 @@ static struct clk mdm_ick = {		/* used b
 	.parent		= &core_ck,
 	.flags		= CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 				DELAYED_APP | CONFIG_PARTICIPANT,
-	.rate_offset	= 0,
+	.rate_offset	= OMAP2430_CLKSEL_MDM_SHIFT,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
@@ -1002,7 +1000,7 @@ static struct clk l4_ck = {		/* used bot
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 				DELAYED_APP | RATE_PROPAGATES,
-	.rate_offset	= 5,
+	.rate_offset	= OMAP24XX_CLKSEL_L4_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -1039,8 +1037,8 @@ static struct clk dss1_fck = {
 				RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_DSS1_SHIFT,
-	.rate_offset	= 8,
-	.src_offset	= 8,
+	.rate_offset	= OMAP24XX_CLKSEL_DSS1_SHIFT,
+	.src_offset	= OMAP24XX_CLKSEL_DSS1_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
@@ -1052,7 +1050,7 @@ static struct clk dss2_fck = {		/* Alt c
 				DELAYED_APP,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_DSS2_SHIFT,
-	.src_offset	= 13,
+	.src_offset	= OMAP24XX_CLKSEL_DSS2_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1087,7 +1085,7 @@ static struct clk gpt1_fck = {
 				CM_WKUP_SEL1,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),	/* Bit0 */
 	.enable_bit	= OMAP24XX_EN_GPT1_SHIFT,
-	.src_offset	= 0,
+	.src_offset	= OMAP24XX_CLKSEL_GPT1_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1107,7 +1105,7 @@ static struct clk gpt2_fck = {
 				CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT2_SHIFT,
-	.src_offset	= 2,
+	.src_offset	= OMAP24XX_CLKSEL_GPT2_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1127,7 +1125,7 @@ static struct clk gpt3_fck = {
 				CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT3_SHIFT,
-	.src_offset	= 4,
+	.src_offset	= OMAP24XX_CLKSEL_GPT3_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1147,7 +1145,7 @@ static struct clk gpt4_fck = {
 				CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT4_SHIFT,
-	.src_offset	= 6,
+	.src_offset	= OMAP24XX_CLKSEL_GPT4_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1167,7 +1165,7 @@ static struct clk gpt5_fck = {
 				CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT5_SHIFT,
-	.src_offset	= 8,
+	.src_offset	= OMAP24XX_CLKSEL_GPT5_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1187,7 +1185,7 @@ static struct clk gpt6_fck = {
 				CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT6_SHIFT,
-	.src_offset	= 10,
+	.src_offset	= OMAP24XX_CLKSEL_GPT6_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1207,7 +1205,7 @@ static struct clk gpt7_fck = {
 				CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,
-	.src_offset	= 12,
+	.src_offset	= OMAP24XX_CLKSEL_GPT7_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1227,7 +1225,7 @@ static struct clk gpt8_fck = {
 				CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT8_SHIFT,
-	.src_offset	= 14,
+	.src_offset	= OMAP24XX_CLKSEL_GPT8_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1247,7 +1245,7 @@ static struct clk gpt9_fck = {
 					CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT9_SHIFT,
-	.src_offset	= 16,
+	.src_offset	= OMAP24XX_CLKSEL_GPT9_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1267,7 +1265,7 @@ static struct clk gpt10_fck = {
 					CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT10_SHIFT,
-	.src_offset	= 18,
+	.src_offset	= OMAP24XX_CLKSEL_GPT10_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1287,7 +1285,7 @@ static struct clk gpt11_fck = {
 					CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT11_SHIFT,
-	.src_offset	= 20,
+	.src_offset	= OMAP24XX_CLKSEL_GPT11_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1307,7 +1305,7 @@ static struct clk gpt12_fck = {
 					CM_CORE_SEL2,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT12_SHIFT,
-	.src_offset	= 22,
+	.src_offset	= OMAP24XX_CLKSEL_GPT12_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
 };
 
@@ -1813,7 +1811,7 @@ static struct clk vlynq_fck = {
 	.flags		= CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_VLYNQ_SHIFT,
-	.src_offset	= 15,
+	.src_offset	= OMAP2420_CLKSEL_VLYNQ_SHIFT,
 	.recalc		= &omap2_clksel_recalc,
 };
 
Index: linux-omap/arch/arm/mach-omap2/cm_regbits_24xx.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/cm_regbits_24xx.h
+++ linux-omap/arch/arm/mach-omap2/cm_regbits_24xx.h
@@ -323,8 +323,11 @@
 #define OMAP24XX_DPLL_MULT_MASK				(0x3ff << 12)
 #define OMAP24XX_DPLL_DIV_SHIFT				8
 #define OMAP24XX_DPLL_DIV_MASK				(0xf << 8)
+#define OMAP24XX_54M_SOURCE_SHIFT			5
 #define OMAP24XX_54M_SOURCE				(1 << 5)
+#define OMAP2430_96M_SOURCE_SHIFT			4
 #define OMAP2430_96M_SOURCE				(1 << 4)
+#define OMAP24XX_48M_SOURCE_SHIFT			3
 #define OMAP24XX_48M_SOURCE				(1 << 3)
 #define OMAP2430_ALTCLK_SOURCE_SHIFT			0
 #define OMAP2430_ALTCLK_SOURCE_MASK			(0x7 << 0)

-- 

[PATCH 11/22] omap2 clock: fix some clocks incorrectly marked as present on OMAP2430

[Paul Walmsley]

[-- Attachment #1: fix-2420-only-clocks.patch --]
[-- Type: text/plain, Size: 2223 bytes --]

Several clocks are marked as present on OMAP2430, even though they are 
2420-only.  Drop CLOCK_IN_OMAP243X from those clocks' flags.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.h |   11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -742,8 +742,7 @@ static struct clk sys_clkout2 = {
 	.name		= "sys_clkout2",
 	.parent		= &func_54m_ck,
 	.rate		= 54000000,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
+	.flags		= CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 	.src_offset	= OMAP2420_CLKOUT2_SOURCE_SHIFT,
 	.enable_reg	= OMAP24XX_PRCM_CLKOUT_CTRL,
 	.enable_bit	= OMAP2420_CLKOUT2_EN_SHIFT,
@@ -1740,7 +1739,7 @@ static struct clk i2c2_ick = {
 	.name		= "i2c_ick",
 	.id		= 2,
 	.parent		= &l4_ck,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
@@ -1750,7 +1749,7 @@ static struct clk i2c2_fck = {
 	.name		= "i2c_fck",
 	.id		= 2,
 	.parent		= &func_12m_ck,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
@@ -1770,7 +1769,7 @@ static struct clk i2c1_ick = {
 	.name		= "i2c_ick",
 	.id		= 1,
 	.parent		= &l4_ck,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
 	.recalc		= &omap2_followparent_recalc,
@@ -1780,7 +1779,7 @@ static struct clk i2c1_fck = {
 	.name		= "i2c_fck",
 	.id		= 1,
 	.parent		= &func_12m_ck,
-	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
 	.recalc		= &omap2_followparent_recalc,

-- 

[PATCH 12/22] omap2 clock: vlynq_fck is missing clksel divider code

[Paul Walmsley]

[-- Attachment #1: fix-up-vlynq-core-clock.patch --]
[-- Type: text/plain, Size: 1147 bytes --]

vlynq_fck is a clksel clock.  But omap2_clk_set_parent() is missing
the code to divide its parent's rate down appropriately when vlynq_fck
is set to use a core_ck parent.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -823,7 +823,7 @@ static u32 omap2_get_src_field(u32 *type
 			if (src_clk == &func_96m_ck)
 				val = 0;
 			else if (src_clk == &core_ck)
-				val = 0x10;
+				val = 0x10;             /* rate needs fixing */
 		}
 		break;
 	case CM_CORE_SEL2:
@@ -934,7 +934,8 @@ static int omap2_clk_set_parent(struct c
 		clk->parent = new_parent;
 
 		/* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
-		if ((new_parent == &core_ck) && (clk == &dss1_fck))
+		if ((new_parent == &core_ck) &&
+		    (clk == &dss1_fck || clk == &vlynq_fck))
 			clk->rate = new_parent->rate / 0x10;
 		else
 			clk->rate = new_parent->rate;

-- 

[PATCH 13/22] omap2 clock: convert PARENT_CONTROLS_CLOCK into a clock flag

[Paul Walmsley]

[-- Attachment #1: convert-parent-controls-clock-into-clock-flag.patch --]
[-- Type: text/plain, Size: 5321 bytes --]

The clock framework currently uses a magic value in struct clk
.enable_bit to indicate that the clock's parent controls enabling and
disabling the clock.  There's no need to use this type of in-band
special value when there's already a good means to indicate binary
clock parameters: the clock flags field.  This patch converts the
existing PARENT_CONTROLS_CLOCK code to use a clock flag.

Signed-off-by: Paul Walmsley <paul@pwsan.com>


---
 arch/arm/mach-omap2/clock.c       |   15 ++++++---------
 arch/arm/mach-omap2/clock.h       |   23 ++++++++---------------
 include/asm-arm/arch-omap/clock.h |    2 ++
 3 files changed, 16 insertions(+), 24 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -122,9 +122,6 @@ static void omap2_clk_fixed_enable(struc
 {
 	u32 cval, i=0;
 
-	if (clk->enable_bit == PARENT_CONTROLS_CLOCK)	/* Parent will do it */
-		return;
-
 	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 
 	if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
@@ -197,7 +194,7 @@ static int _omap2_clk_enable(struct clk 
 {
 	u32 regval32;
 
-	if (clk->flags & ALWAYS_ENABLED)
+	if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
 		return 0;
 
 	if (unlikely(clk == &osc_ck)) {
@@ -211,7 +208,7 @@ static int _omap2_clk_enable(struct clk 
 		return 0;
 	}
 
-	if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
+	if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 		omap2_clk_fixed_enable(clk);
 		return 0;
 	}
@@ -231,9 +228,6 @@ static void omap2_clk_fixed_disable(stru
 {
 	u32 cval;
 
-	if (clk->enable_bit == PARENT_CONTROLS_CLOCK)
-		return;		/* let parent off do it */
-
 	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 	cval &= ~(0x3 << clk->enable_bit);
 	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
@@ -244,6 +238,9 @@ static void _omap2_clk_disable(struct cl
 {
 	u32 regval32;
 
+	if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
+		return;
+
 	if (unlikely(clk == &osc_ck)) {
 		omap2_set_osc_ck(0);
 		return;
@@ -252,7 +249,7 @@ static void _omap2_clk_disable(struct cl
 	if (clk->enable_reg == 0)
 		return;
 
-	if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
+	if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 		omap2_clk_fixed_disable(clk);
 		return;
 	}
Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -34,9 +34,6 @@ static void omap2_sys_clk_recalc(struct 
 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
 static u32 omap2_clksel_get_divisor(struct clk *clk);
 
-/* REVISIT: should use a clock flag for this, not a magic number */
-#define PARENT_CONTROLS_CLOCK	0xff
-
 #define RATE_IN_242X	(1 << 0)
 #define RATE_IN_243X	(1 << 1)
 #define RATE_IN_343X	(1 << 2)
@@ -667,10 +664,9 @@ static struct clk func_54m_ck = {
 	.parent		= &apll54_ck,	/* can also be alt_clk */
 	.rate		= 54000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
+				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.src_offset	= OMAP24XX_54M_SOURCE_SHIFT,
-	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-	.enable_bit	= PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
 };
 
@@ -687,9 +683,8 @@ static struct clk func_96m_ck = {
 	.parent		= &apll96_ck,
 	.rate		= 96000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				RATE_FIXED | RATE_PROPAGATES,
-	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-	.enable_bit	= PARENT_CONTROLS_CLOCK,
+				RATE_FIXED | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
 };
 
@@ -698,10 +693,9 @@ static struct clk func_48m_ck = {
 	.parent		= &apll96_ck,	 /* 96M or Alt */
 	.rate		= 48000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
+				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.src_offset	= OMAP24XX_48M_SOURCE_SHIFT,
-	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-	.enable_bit	= PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
 };
 
@@ -710,10 +704,9 @@ static struct clk func_12m_ck = {
 	.parent		= &func_48m_ck,
 	.rate		= 12000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				RATE_FIXED | RATE_PROPAGATES,
+				RATE_FIXED | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
-	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-	.enable_bit	= PARENT_CONTROLS_CLOCK,
 };
 
 /* Secure timer, only available in secure mode */
Index: linux-omap/include/asm-arm/arch-omap/clock.h
===================================================================
--- linux-omap.orig/include/asm-arm/arch-omap/clock.h
+++ linux-omap/include/asm-arm/arch-omap/clock.h
@@ -88,6 +88,8 @@ extern int clk_get_usecount(struct clk *
 #define CLOCK_IN_OMAP242X	(1 << 25)
 #define CLOCK_IN_OMAP243X	(1 << 26)
 #define CLOCK_IN_OMAP343X	(1 << 27)
+#define PARENT_CONTROLS_CLOCK	(1 << 28)
+
 
 
 /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */

-- 

[PATCH 14/22] omap2 clock: omap2 clock.c: Consolidate wait-for-lock code

[Paul Walmsley]

[-- Attachment #1: consolidate-wait-for-lock.patch --]
[-- Type: text/plain, Size: 4052 bytes --]

omap2 clock.c contains two nearly identical wait-for-clock-enable routines.
Consolidate them into one omap2_wait_clock_ready() function.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |   77 +++++++++++++++++++++++++-------------------
 1 file changed, 45 insertions(+), 32 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -42,6 +42,8 @@
 #define CLKSEL_VLYNQ_96MHZ		0
 #define CLKSEL_VLYNQ_CORECLK_16		0x10
 
+#define MAX_PLL_LOCK_WAIT		100000
+
 //#define DOWN_VARIABLE_DPLL 1			/* Experimental */
 
 static struct prcm_config *curr_prcm_set;
@@ -117,10 +119,37 @@ static void omap2_set_osc_ck(int enable)
 			      OMAP24XX_PRCM_CLKSRC_CTRL);
 }
 
+/*
+ * omap2_wait_clock_ready - wait for PLL to lock
+ *
+ * Returns 1 if the PLL locked, 0 if it failed to lock.
+ */
+static int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name)
+{
+	int i = 0;
+
+	/* Wait for lock */
+	while (!(cm_read_reg(reg) & cval)) {
+		++i;
+		udelay(1);
+		if (i == MAX_PLL_LOCK_WAIT) {
+			printk(KERN_ERR "Clock %s didn't lock in %d tries\n",
+			       name, MAX_PLL_LOCK_WAIT);
+			break;
+		}
+	}
+
+	if (i)
+		pr_debug("Clock %s stable after %d loops\n", name, i);
+
+	return (i < MAX_PLL_LOCK_WAIT) ? 1 : 0;
+};
+
+
 /* Enable an APLL if off */
 static void omap2_clk_fixed_enable(struct clk *clk)
 {
-	u32 cval, i=0;
+	u32 cval;
 
 	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 
@@ -136,35 +165,27 @@ static void omap2_clk_fixed_enable(struc
 	else if (clk == &apll54_ck)
 		cval = OMAP24XX_ST_54M_CLK;
 
-	/* Wait for lock */
-	while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST) & cval)) {
-		++i;
-		udelay(1);
-		if (i == 100000) {
-			printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
-			break;
-		}
-	}
+	omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+			    clk->name);
 }
 
 static void omap2_clk_wait_ready(struct clk *clk)
 {
-	unsigned long reg, other_reg, st_reg;
+	void __iomem *reg, *other_reg, *st_reg;
 	u32 bit;
-	int i;
 
-	reg = (unsigned long) clk->enable_reg;
-	if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1) ||
-	    reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2))
-		other_reg = (reg & ~0xf0) | 0x10; /* CM_ICLKEN* */
-	else if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1) ||
-		 reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2))
-		other_reg = (reg & ~0xf0) | 0x00; /* CM_FCLKEN* */
+	reg = clk->enable_reg;
+	if (reg == OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1) ||
+	    reg == OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2))
+		other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
+	else if (reg == OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1) ||
+		 reg == OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2))
+		other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
 	else
 		return;
 
 	/* No check for DSS or cam clocks */
-	if ((reg & 0x0f) == 0) {
+	if (((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
 		if (clk->enable_bit <= 1 || clk->enable_bit == 31)
 			return;
 	}
@@ -172,19 +193,11 @@ static void omap2_clk_wait_ready(struct 
 	/* Check if both functional and interface clocks
 	 * are running. */
 	bit = 1 << clk->enable_bit;
-	if (!(cm_read_reg((void __iomem *)other_reg) & bit))
+	if (!(cm_read_reg(other_reg) & bit))
 		return;
-	st_reg = (other_reg & ~0xf0) | 0x20; /* CM_IDLEST* */
-	i = 0;
-	while (!(cm_read_reg((void __iomem *)st_reg) & bit)) {
-		i++;
-		if (i == 100000) {
-			printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
-			break;
-		}
-	}
-	if (i)
-		pr_debug("Clock %s stable after %d loops\n", clk->name, i);
+	st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+
+	omap2_wait_clock_ready(st_reg, bit, clk->name);
 }
 
 /* Enables clock without considering parent dependencies or use count

-- 

[PATCH 15/22] omap2 clock: return -EINVAL if no clock enable code; fix dpll_ck enable

[Paul Walmsley]

[-- Attachment #1: return-einval-if-no-enable-bit-defined.patch --]
[-- Type: text/plain, Size: 2244 bytes --]

If the clock framework can't figure out how to enable a clock, return
-EINVAL to indicate that the clock cannot be enabled.  Previously the
code returned 0, which indicated success.

Also fix the "clock.c: Enable for dpll_ck without enable code" boot
warning by marking dpll_ck as ALWAYS_ENABLED.  This is not technically
true, since the DPLL can be bypassed; but since we currently have no
software infrastructure to control it directly, ALWAYS_ENABLED is a
sufficient fiction for dpll_ck.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |   11 +++++++++--
 arch/arm/mach-omap2/clock.h |    3 ++-
 2 files changed, 11 insertions(+), 3 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -218,7 +218,7 @@ static int _omap2_clk_enable(struct clk 
 	if (unlikely(clk->enable_reg == 0)) {
 		printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 		       clk->name);
-		return 0;
+		return -EINVAL;
 	}
 
 	if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
@@ -259,8 +259,15 @@ static void _omap2_clk_disable(struct cl
 		return;
 	}
 
-	if (clk->enable_reg == 0)
+	if (clk->enable_reg == 0) {
+		/*
+		 * 'Independent' here refers to a clock which is not
+		 * controlled by its parent.
+		 */
+		printk(KERN_ERR "clock: clk_disable called on independent "
+		       "clock %s which has no enable_reg\n", clk->name);
 		return;
+	}
 
 	if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 		omap2_clk_fixed_disable(clk);
Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -630,7 +630,8 @@ static struct clk dpll_ck = {
 	.name		= "dpll_ck",
 	.parent		= &sys_ck,		/* Can be func_32k also */
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
+				RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1 |
+				ALWAYS_ENABLED,
 	.recalc		= &omap2_clksel_recalc,
 };
 

-- 

[PATCH 16/22] omap2 clock: From: Paul Walmsley <paul@pwsan.com> Subject:

[Paul Walmsley]

[-- Attachment #1: set_parent_on_only_clksel_clks.patch --]
[-- Type: text/plain, Size: 3281 bytes --]

Clean up omap2_clk_set_parent() by bailing out early if the clock is not
parent-selectable.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |   77 ++++++++++++++++++++------------------------
 1 file changed, 35 insertions(+), 42 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -913,63 +913,56 @@ static u32 omap2_get_src_field(u32 *type
 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
 	void __iomem * reg;
-	u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
+	u32 src_sel, src_off, field_val, field_mask, reg_val;
 	int ret = -EINVAL;
 
 	if (unlikely(clk->flags & CONFIG_PARTICIPANT))
 		return ret;
 
-	if (clk->flags & SRC_SEL_MASK) {	/* On-chip SEL collection */
-		src_sel = (SRC_RATE_SEL_MASK & clk->flags);
-		src_off = clk->src_offset;
+	if (unlikely(!(clk->flags & SRC_SEL_MASK)))
+		return ret;
 
-		if (src_sel == 0)
-			goto set_parent_error;
+	src_sel = (SRC_RATE_SEL_MASK & clk->flags);
+	src_off = clk->src_offset;
 
-		field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
-						&field_mask);
+	if (src_sel == 0)
+		return ret;
 
-		reg = (void __iomem *)src_sel;
+	field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
+					&field_mask);
 
-		if (clk->usecount > 0)
-			_omap2_clk_disable(clk);
+	reg = (void __iomem *)src_sel;
 
-		/* Set new source value (previous dividers if any in effect) */
-		reg_val = __raw_readl(reg) & ~(field_mask << src_off);
-		reg_val |= (field_val << src_off);
-		__raw_writel(reg_val, reg);
-		wmb();
-
-		if (clk->flags & DELAYED_APP) {
-			prm_write_reg(OMAP24XX_VALID_CONFIG,
-				      OMAP24XX_PRCM_CLKCFG_CTRL);
-			wmb();
-		}
-		if (clk->usecount > 0)
-			_omap2_clk_enable(clk);
+	if (clk->usecount > 0)
+		_omap2_clk_disable(clk);
 
-		clk->parent = new_parent;
+	/* Set new source value (previous dividers if any in effect) */
+	reg_val = __raw_readl(reg) & ~(field_mask << src_off);
+	reg_val |= (field_val << src_off);
+	__raw_writel(reg_val, reg);
+	wmb();
+
+	if (clk->flags & DELAYED_APP) {
+		prm_write_reg(OMAP24XX_VALID_CONFIG,
+			      OMAP24XX_PRCM_CLKCFG_CTRL);
+		wmb();
+	}
+	if (clk->usecount > 0)
+		_omap2_clk_enable(clk);
 
-		/* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
-		if ((new_parent == &core_ck) &&
-		    (clk == &dss1_fck || clk == &vlynq_fck))
-			clk->rate = new_parent->rate / 0x10;
-		else
-			clk->rate = new_parent->rate;
+	clk->parent = new_parent;
 
-		if (unlikely(clk->flags & RATE_PROPAGATES))
-			propagate_rate(clk);
+	/* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
+	if ((new_parent == &core_ck) &&
+	    (clk == &dss1_fck || clk == &vlynq_fck))
+		clk->rate = new_parent->rate / 0x10;
+	else
+		clk->rate = new_parent->rate;
 
-		return 0;
-	} else {
-		clk->parent = new_parent;
-		rate = new_parent->rate;
-		omap2_clk_set_rate(clk, rate);
-		ret = 0;
-	}
+	if (unlikely(clk->flags & RATE_PROPAGATES))
+		propagate_rate(clk);
 
- set_parent_error:
-	return ret;
+	return 0;
 }
 
 /* Sets basic clocks based on the specified rate */

-- 

[PATCH 17/22] omap2 clock: Cleanup in clksel-related code; add sys_clkout2 divisor handling

[Paul Walmsley]

[-- Attachment #1: get_clksel_cleanup.patch --]
[-- Type: text/plain, Size: 11242 bytes --]

Convert omap2_get_clksel to use void __iomem *.  Add
omap2_divisor_to_clksel(), to convert clock divisors into appropriate
register bit field values.  Use non-shifted register bit field masks
in clksel code, rather than masks that have been preshifted down to
bit 0 -- this simplifies existing code and facilitates the use of
symbolic constants from the recent PRCM cleanup.  Also add code to
properly handle divisors for sys_clkout2 on OMAP2420.  Previously
this clock's divisor settings were ignored.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |  192 +++++++++++++++++++++-----------------------
 1 file changed, 93 insertions(+), 99 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -52,6 +52,8 @@ static struct clk *vclk;
 static struct clk *sclk;
 static u8 cpu_mask;
 
+static u32 sysclkout_div[] = {1, 2, 4, 8, 16};
+
 /*-------------------------------------------------------------------------
  * Omap2 specific clock functions
  *-------------------------------------------------------------------------*/
@@ -428,7 +430,6 @@ static u32 omap2_clksel_round_rate(struc
 	u32 *new_div)
 {
 	u32 gfx_div[] = {2, 3, 4};
-	u32 sysclkout_div[] = {1, 2, 4, 8, 16};
 	u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
 	u32 vlynq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
 	u32 best_div = ~0, asize = 0;
@@ -601,38 +602,50 @@ static long omap2_round_to_table_rate(st
 }
 
 /*
- * omap2_convert_field_to_div() - turn field value into integer divider
+ * omap2_clksel_to_divisor() - turn field value into integer divider
  */
 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
 {
 	u32 i;
-	u32 clkout_array[] = {1, 2, 4, 8, 16};
 
 	if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
-		for (i = 0; i < 5; i++) {
+		for (i = 0; i < ARRAY_SIZE(sysclkout_div); i++) {
 			if (field_val == i)
-				return clkout_array[i];
+				return sysclkout_div[i];
 		}
-		return ~0;
+		return 0;
 	} else
 		return field_val;
 }
 
 /*
+ * omap2_divisor_to_clksel() - turn integer divider into field value
+ */
+static u32 omap2_divisor_to_clksel(u32 div_sel, u32 div)
+{
+	u32 i;
+
+	if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
+		for (i = 0; i < ARRAY_SIZE(sysclkout_div); i++) {
+			if (div == sysclkout_div[i])
+				return i;
+		}
+		return ~0;
+	} else
+		return div;
+}
+
+/*
  * Returns the CLKSEL divider register value
- * REVISIT: This should be cleaned up to work nicely with void __iomem *
  */
-static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
-			    struct clk *clk)
+static void __iomem *omap2_get_clksel(u32 *field_mask, struct clk *clk)
 {
-	int ret = ~0;
-	u32 reg_val, div_off;
+	u32 div_off, mask = ~0;
 	void __iomem *div_addr = 0;
-	u32 mask = ~0;
 
 	div_off = clk->rate_offset;
 
-	switch ((*div_sel & SRC_RATE_SEL_MASK)) {
+	switch (clk->flags & SRC_RATE_SEL_MASK) {
 	case CM_MPU_SEL1:
 		div_addr = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL);
 		mask = OMAP24XX_CLKSEL_MPU_MASK;
@@ -696,44 +709,32 @@ static u32 omap2_get_clksel(u32 *div_sel
 		}
 	}
 
-	*field_mask = (mask >> div_off);
-
-	if (unlikely(mask == ~0))
-		div_addr = 0;
-
-	*div_sel = (u32)div_addr;
-
-	if (unlikely(div_addr == 0))
-		return ret;
-
-	/* Isolate field */
-	reg_val = cm_read_reg(div_addr) & mask;
+	if (unlikely((mask == ~0) || (div_addr == 0)))
+		return 0;
 
-	/* Normalize back to divider value */
-	reg_val >>= div_off;
+	*field_mask = mask;
 
-	return reg_val;
+	return div_addr;
 }
 
+
 /*
  * Return divider to be applied to parent clock.
  * Return 0 on error.
  */
 static u32 omap2_clksel_get_divisor(struct clk *clk)
 {
-	int ret = 0;
-	u32 div, div_sel, div_off, field_mask, field_val;
+	u32 div, field_mask, field_val;
+	void __iomem *div_addr;
 
-	/* isolate control register */
-	div_sel = (SRC_RATE_SEL_MASK & clk->flags);
+	div_addr = omap2_get_clksel(&field_mask, clk);
+	if (div_addr == 0)
+		return 0;
 
-	div_off = clk->rate_offset;
-	field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
-	if (div_sel == 0)
-		return ret;
+	field_val = cm_read_reg(div_addr) & field_mask;
+	field_val >>= clk->rate_offset;
 
-	div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-	div = omap2_clksel_to_divisor(div_sel, field_val);
+	div = omap2_clksel_to_divisor(clk->flags, field_val);
 
 	return div;
 }
@@ -742,53 +743,33 @@ static u32 omap2_clksel_get_divisor(stru
 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	int ret = -EINVAL;
-	void __iomem * reg;
-	u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
+	u32 div_off, field_mask, field_val, reg_val, validrate;
 	u32 new_div = 0;
+	void __iomem *div_addr;
 
 	if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
 		if (clk == &dpll_ck)
 			return omap2_reprogram_dpll(clk, rate);
 
 		/* Isolate control register */
-		div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 		div_off = clk->rate_offset;
 
 		validrate = omap2_clksel_round_rate(clk, rate, &new_div);
 		if (validrate != rate)
 			return ret;
 
-		field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
-		if (div_sel == 0)
+		div_addr = omap2_get_clksel(&field_mask, clk);
+		if (div_addr == 0)
 			return ret;
 
-		if (clk->flags & CM_SYSCLKOUT_SEL1) {
-			switch (new_div) {
-			case 16:
-				field_val = 4;
-				break;
-			case 8:
-				field_val = 3;
-				break;
-			case 4:
-				field_val = 2;
-				break;
-			case 2:
-				field_val = 1;
-				break;
-			case 1:
-				field_val = 0;
-				break;
-			}
-		} else
-			field_val = new_div;
-
-		reg = (void __iomem *)div_sel;
+		field_val = omap2_divisor_to_clksel(clk->flags, new_div);
+		if (field_val == ~0)
+			return ret;
 
-		reg_val = cm_read_reg(reg);
-		reg_val &= ~(field_mask << div_off);
+		reg_val = cm_read_reg(div_addr);
+		reg_val &= ~field_mask;
 		reg_val |= (field_val << div_off);
-		cm_write_reg(reg_val, reg);
+		cm_write_reg(reg_val, div_addr);
 		wmb();
 		clk->rate = clk->parent->rate / new_div;
 
@@ -809,26 +790,28 @@ static int omap2_clk_set_rate(struct clk
 }
 
 /* Converts encoded control register address into a full address */
-static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
-			       struct clk *src_clk, u32 *field_mask)
+static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
+				      struct clk *src_clk, u32 *field_mask,
+				      struct clk *clk)
 {
 	u32 val = ~0, mask = 0;
 	void __iomem *src_reg_addr = 0;
+	u32 reg_offset;
+
+	reg_offset = clk->src_offset;
 
 	/* Find target control register.*/
-	switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
+	switch (clk->flags & SRC_RATE_SEL_MASK) {
 	case CM_CORE_SEL1:
 		src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 		if (reg_offset == OMAP24XX_CLKSEL_DSS2_SHIFT) {
 			mask = OMAP24XX_CLKSEL_DSS2_MASK;
-			mask >>= OMAP24XX_CLKSEL_DSS2_SHIFT;
 			if (src_clk == &sys_ck)
 				val = 0;
 			if (src_clk == &func_48m_ck)
 				val = 1;
 		} else if (reg_offset == OMAP24XX_CLKSEL_DSS1_SHIFT) {
 			mask = OMAP24XX_CLKSEL_DSS1_MASK;
-			mask >>= OMAP24XX_CLKSEL_DSS1_SHIFT;
 			if (src_clk == &sys_ck)
 				val = 0;
 			else if (src_clk == &core_ck)	/* divided clock */
@@ -836,16 +819,20 @@ static u32 omap2_get_src_field(u32 *type
 		} else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
 			   cpu_is_omap2420()) {
 			mask = OMAP2420_CLKSEL_VLYNQ_MASK;
-			mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
 			if (src_clk == &func_96m_ck)
 				val = 0;
 			else if (src_clk == &core_ck)
 				val = 0x10;             /* rate needs fixing */
+		} else {
+			WARN_ON(1); /* unknown reg_offset */
 		}
 		break;
 	case CM_CORE_SEL2:
+		WARN_ON(reg_offset < OMAP24XX_CLKSEL_GPT2_SHIFT ||
+			reg_offset > OMAP24XX_CLKSEL_GPT12_SHIFT);
 		src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2);
-		mask = 0x3;
+		mask = OMAP24XX_CLKSEL_GPT2_MASK;
+		mask <<= (reg_offset - OMAP24XX_CLKSEL_GPT2_SHIFT);
 		if (src_clk == &func_32k_ck)
 			val = 0x0;
 		if (src_clk == &sys_ck)
@@ -854,8 +841,9 @@ static u32 omap2_get_src_field(u32 *type
 			val = 0x2;
 		break;
 	case CM_WKUP_SEL1:
+		WARN_ON(reg_offset != 0); /* unknown reg_offset */
 		src_reg_addr = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL);
-		mask = 0x3;
+		mask = OMAP24XX_CLKSEL_GPT1_MASK;
 		if (src_clk == &func_32k_ck)
 			val = 0x0;
 		if (src_clk == &sys_ck)
@@ -865,23 +853,27 @@ static u32 omap2_get_src_field(u32 *type
 		break;
 	case CM_PLL_SEL1:
 		src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1);
-		mask = 0x1;
 		if (reg_offset == 0x3) {
+			mask = OMAP24XX_48M_SOURCE;
 			if (src_clk == &apll96_ck)
 				val = 0;
 			if (src_clk == &alt_ck)
 				val = 1;
 		}
 		else if (reg_offset == 0x5) {
+			mask = OMAP24XX_54M_SOURCE;
 			if (src_clk == &apll54_ck)
 				val = 0;
 			if (src_clk == &alt_ck)
 				val = 1;
+		} else {
+			WARN_ON(1); /* unknown reg_offset */
 		}
 		break;
 	case CM_PLL_SEL2:
+		WARN_ON(reg_offset != 0);
 		src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2);
-		mask = 0x3;
+		mask = OMAP24XX_CORE_CLK_SRC_MASK;
 		if (src_clk == &func_32k_ck)
 			val = 0x0;
 		if (src_clk == &dpll_ck)
@@ -889,7 +881,15 @@ static u32 omap2_get_src_field(u32 *type
 		break;
 	case CM_SYSCLKOUT_SEL1:
 		src_reg_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
-		mask = 0x3;
+
+		if (reg_offset == OMAP24XX_CLKOUT_SOURCE_SHIFT) {
+			mask = OMAP24XX_CLKOUT_SOURCE_MASK;
+		} else if (reg_offset == OMAP2420_CLKOUT2_SOURCE_SHIFT) {
+			mask = OMAP2420_CLKOUT2_SOURCE_MASK;
+		} else {
+			WARN_ON(1); /* unknown reg_offset */
+		}
+
 		if (src_clk == &dpll_ck)
 			val = 0;
 		if (src_clk == &sys_ck)
@@ -902,9 +902,10 @@ static u32 omap2_get_src_field(u32 *type
 	}
 
 	if (val == ~0)			/* Catch errors in offset */
-		*type_to_addr = 0;
+		*src_addr = 0;
 	else
-		*type_to_addr = (u32)src_reg_addr;
+		*src_addr = src_reg_addr;
+
 	*field_mask = mask;
 
 	return val;
@@ -912,34 +913,27 @@ static u32 omap2_get_src_field(u32 *type
 
 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
-	void __iomem * reg;
-	u32 src_sel, src_off, field_val, field_mask, reg_val;
-	int ret = -EINVAL;
+	void __iomem *src_addr;
+	u32 field_val, field_mask, reg_val;
 
 	if (unlikely(clk->flags & CONFIG_PARTICIPANT))
-		return ret;
+		return -EINVAL;
 
 	if (unlikely(!(clk->flags & SRC_SEL_MASK)))
-		return ret;
-
-	src_sel = (SRC_RATE_SEL_MASK & clk->flags);
-	src_off = clk->src_offset;
-
-	if (src_sel == 0)
-		return ret;
-
-	field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
-					&field_mask);
+		return -EINVAL;
 
-	reg = (void __iomem *)src_sel;
+	field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
+					       &field_mask, clk);
+	if (src_addr == 0)
+		return -EINVAL;
 
 	if (clk->usecount > 0)
 		_omap2_clk_disable(clk);
 
 	/* Set new source value (previous dividers if any in effect) */
-	reg_val = __raw_readl(reg) & ~(field_mask << src_off);
-	reg_val |= (field_val << src_off);
-	__raw_writel(reg_val, reg);
+	reg_val = __raw_readl(src_addr) & ~field_mask;
+	reg_val |= (field_val << clk->src_offset);
+	__raw_writel(reg_val, src_addr);
 	wmb();
 
 	if (clk->flags & DELAYED_APP) {

-- 

[PATCH 18/22] omap2 clock: Use symbolic constants in clock.c

[Paul Walmsley]

[-- Attachment #1: cleanup-clock.c-magic-numbers.patch --]
[-- Type: text/plain, Size: 10128 bytes --]

Convert most of the magic numbers remaining in mach-omap2/clock.c to
symbolic constants.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |  158 ++++++++++++++++++++++++++++++--------------
 1 file changed, 109 insertions(+), 49 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -42,12 +42,47 @@
 #define CLKSEL_VLYNQ_96MHZ		0
 #define CLKSEL_VLYNQ_CORECLK_16		0x10
 
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED			0
+#define EN_APLL_LOCKED			3
+
+/* CM_{CLKSEL2_CORE,CLKSEL_WKUP}.CLKSEL_GPT* options (24XX) */
+#define CLKSEL_GPT_32K			0
+#define CLKSEL_GPT_SYSCLK		1
+#define CLKSEL_GPT_EXTALTCLK		2
+
+/* CM_CLKSEL1_CORE.CLKSEL_DSS1 options (24XX) */
+#define CLKSEL_DSS1_SYSCLK		0
+#define CLKSEL_DSS1_CORECLK_16		0x10
+
+/* CM_CLKSEL1_CORE.CLKSEL_DSS2 options (24XX) */
+#define CLKSEL_DSS2_SYSCLK		0
+#define CLKSEL_DSS2_48MHZ		1
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ		0
+#define APLLS_CLKIN_13MHZ		2
+#define APLLS_CLKIN_12MHZ		3
+
+/* CM_CLKSEL1_PLL.54M_SOURCE options (24XX) */
+#define CLK_54M_SOURCE_APLL		0
+#define CLK_54M_SOURCE_EXTALTCLK	1
+
+/* CM_CLKSEL1_PLL.48M_SOURCE options (24XX) */
+#define CLK_48M_SOURCE_APLL		0
+#define CLK_48M_SOURCE_EXTALTCLK	1
+
+/* PRCM_CLKOUT_CTRL.CLKOUT_SOURCE options (2420) */
+#define CLKOUT_SOURCE_CORE_CLK		0
+#define CLKOUT_SOURCE_SYS_CLK		1
+#define CLKOUT_SOURCE_96M_CLK		2
+#define CLKOUT_SOURCE_54M_CLK		3
+
 #define MAX_PLL_LOCK_WAIT		100000
 
 //#define DOWN_VARIABLE_DPLL 1			/* Experimental */
 
 static struct prcm_config *curr_prcm_set;
-static u32 curr_perf_level = PRCM_FULL_SPEED;
 static struct clk *vclk;
 static struct clk *sclk;
 static u8 cpu_mask;
@@ -66,7 +101,7 @@ static void omap2_sys_clk_recalc(struct 
 	if (!cpu_is_omap34xx()) {
 		div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
 		/* Test if ext clk divided by 1 or 2 */
-		div &= (0x3 << OMAP_SYSCLKDIV_SHIFT);
+		div &= OMAP_SYSCLKDIV_MASK;
 		div >>= clk->rate_offset;
 		clk->rate = (clk->parent->rate / div);
 	}
@@ -151,15 +186,17 @@ static int omap2_wait_clock_ready(void _
 /* Enable an APLL if off */
 static void omap2_clk_fixed_enable(struct clk *clk)
 {
-	u32 cval;
+	u32 cval, apll_mask;
+
+	apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 
 	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 
-	if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
-		return;
+	if ((cval & apll_mask) == apll_mask)
+		return;   /* apll already enabled */
 
-	cval &= ~(0x3 << clk->enable_bit);
-	cval |= (0x3 << clk->enable_bit);
+	cval &= ~apll_mask;
+	cval |= apll_mask;
 	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
 	if (clk == &apll96_ck)
@@ -188,7 +225,9 @@ static void omap2_clk_wait_ready(struct 
 
 	/* No check for DSS or cam clocks */
 	if (((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
-		if (clk->enable_bit <= 1 || clk->enable_bit == 31)
+		if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
+		    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
+		    clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
 			return;
 	}
 
@@ -244,7 +283,7 @@ static void omap2_clk_fixed_disable(stru
 	u32 cval;
 
 	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-	cval &= ~(0x3 << clk->enable_bit);
+	cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 }
 
@@ -326,7 +365,7 @@ static u32 omap2_dpll_round_rate(unsigne
 	core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 
-	if (core_clk_src == 1) {	/* DPLL clockout */
+	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
 		high = curr_prcm_set->dpll_speed * 2;
 		low = curr_prcm_set->dpll_speed;
 	} else {				/* DPLL clockout x 2 */
@@ -521,18 +560,18 @@ static int omap2_reprogram_dpll(struct c
 		else
 			low = curr_prcm_set->dpll_speed / 2;
 
-		/* REVISIT: This sets several reserved bits? */
 		tmpset.cm_clksel1_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
-		tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
+		tmpset.cm_clksel1_pll &= ~(OMAP24XX_DPLL_MULT_MASK |
+					   OMAP24XX_DPLL_DIV_MASK);
 		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 		tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 		if (rate > low) {
-			tmpset.cm_clksel2_pll |= 0x2;
+			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
 			mult = ((rate / 2) / 1000000);
 			done_rate = CORE_CLK_SRC_DPLL_X2;
 		} else {
-			tmpset.cm_clksel2_pll |= 0x1;
+			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
 			mult = (rate / 1000000);
 			done_rate = CORE_CLK_SRC_DPLL;
 		}
@@ -807,22 +846,28 @@ static u32 omap2_clksel_get_src_field(vo
 		if (reg_offset == OMAP24XX_CLKSEL_DSS2_SHIFT) {
 			mask = OMAP24XX_CLKSEL_DSS2_MASK;
 			if (src_clk == &sys_ck)
-				val = 0;
-			if (src_clk == &func_48m_ck)
-				val = 1;
+				val = CLKSEL_DSS2_SYSCLK;
+			else if (src_clk == &func_48m_ck)
+				val = CLKSEL_DSS2_48MHZ;
+			else
+				WARN_ON(1); /* unknown src_clk */
 		} else if (reg_offset == OMAP24XX_CLKSEL_DSS1_SHIFT) {
 			mask = OMAP24XX_CLKSEL_DSS1_MASK;
 			if (src_clk == &sys_ck)
-				val = 0;
+				val = CLKSEL_DSS1_SYSCLK;
 			else if (src_clk == &core_ck)	/* divided clock */
-				val = 0x10;		/* rate needs fixing */
+				val = CLKSEL_DSS1_CORECLK_16;	/* rate needs fixing */
+			else
+				WARN_ON(1); /* unknown src clk */
 		} else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
 			   cpu_is_omap2420()) {
 			mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 			if (src_clk == &func_96m_ck)
-				val = 0;
+				val = CLKSEL_VLYNQ_96MHZ;
 			else if (src_clk == &core_ck)
-				val = 0x10;             /* rate needs fixing */
+				val = CLKSEL_VLYNQ_CORECLK_16;
+			else
+				WARN_ON(1); /* unknown src_clk */
 		} else {
 			WARN_ON(1); /* unknown reg_offset */
 		}
@@ -834,38 +879,46 @@ static u32 omap2_clksel_get_src_field(vo
 		mask = OMAP24XX_CLKSEL_GPT2_MASK;
 		mask <<= (reg_offset - OMAP24XX_CLKSEL_GPT2_SHIFT);
 		if (src_clk == &func_32k_ck)
-			val = 0x0;
-		if (src_clk == &sys_ck)
-			val = 0x1;
-		if (src_clk == &alt_ck)
-			val = 0x2;
+			val = CLKSEL_GPT_32K;
+		else if (src_clk == &sys_ck)
+			val = CLKSEL_GPT_SYSCLK;
+		else if (src_clk == &alt_ck)
+			val = CLKSEL_GPT_EXTALTCLK;
+		else
+			WARN_ON(1);  /* unknown src_clk */
 		break;
 	case CM_WKUP_SEL1:
 		WARN_ON(reg_offset != 0); /* unknown reg_offset */
 		src_reg_addr = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL);
 		mask = OMAP24XX_CLKSEL_GPT1_MASK;
 		if (src_clk == &func_32k_ck)
-			val = 0x0;
-		if (src_clk == &sys_ck)
-			val = 0x1;
-		if (src_clk == &alt_ck)
-			val = 0x2;
+			val = CLKSEL_GPT_32K;
+		else if (src_clk == &sys_ck)
+			val = CLKSEL_GPT_SYSCLK;
+		else if (src_clk == &alt_ck)
+			val = CLKSEL_GPT_EXTALTCLK;
+		else
+			WARN_ON(1); /* unknown src_clk */
 		break;
 	case CM_PLL_SEL1:
 		src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1);
 		if (reg_offset == 0x3) {
 			mask = OMAP24XX_48M_SOURCE;
 			if (src_clk == &apll96_ck)
-				val = 0;
-			if (src_clk == &alt_ck)
-				val = 1;
+				val = CLK_48M_SOURCE_APLL;
+			else if (src_clk == &alt_ck)
+				val = CLK_48M_SOURCE_EXTALTCLK;
+			else
+				WARN_ON(1); /* unknown src_clk */
 		}
 		else if (reg_offset == 0x5) {
 			mask = OMAP24XX_54M_SOURCE;
 			if (src_clk == &apll54_ck)
-				val = 0;
-			if (src_clk == &alt_ck)
-				val = 1;
+				val = CLK_54M_SOURCE_APLL;
+			else if (src_clk == &alt_ck)
+				val = CLK_54M_SOURCE_EXTALTCLK;
+			else
+				WARN_ON(1); /* unknown src_clk */
 		} else {
 			WARN_ON(1); /* unknown reg_offset */
 		}
@@ -875,9 +928,11 @@ static u32 omap2_clksel_get_src_field(vo
 		src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2);
 		mask = OMAP24XX_CORE_CLK_SRC_MASK;
 		if (src_clk == &func_32k_ck)
-			val = 0x0;
-		if (src_clk == &dpll_ck)
-			val = 0x2;
+			val = CORE_CLK_SRC_32K;
+		else if (src_clk == &dpll_ck)
+			val = CORE_CLK_SRC_DPLL_X2;
+		else
+			WARN_ON(1); /* unknown src_clk */
 		break;
 	case CM_SYSCLKOUT_SEL1:
 		src_reg_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
@@ -892,12 +947,14 @@ static u32 omap2_clksel_get_src_field(vo
 
 		if (src_clk == &dpll_ck)
 			val = 0;
-		if (src_clk == &sys_ck)
+		else if (src_clk == &sys_ck)
 			val = 1;
-		if (src_clk == &func_96m_ck)
+		else if (src_clk == &func_96m_ck)
 			val = 2;
-		if (src_clk == &func_54m_ck)
+		else if (src_clk == &func_54m_ck)
 			val = 3;
+		else
+			WARN_ON(1); /* unknown src_clk */
 		break;
 	}
 
@@ -906,6 +963,8 @@ static u32 omap2_clksel_get_src_field(vo
 	else
 		*src_addr = src_reg_addr;
 
+	WARN_ON(mask == 0);
+
 	*field_mask = mask;
 
 	return val;
@@ -1001,7 +1060,8 @@ static int omap2_select_table_rate(struc
 		if (prcm->dpll_speed == prcm->xtal_speed)
 			bypass = 1;
 
-		if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == 2)
+		if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+		    CORE_CLK_SRC_DPLL_X2)
 			done_rate = CORE_CLK_SRC_DPLL_X2;
 		else
 			done_rate = CORE_CLK_SRC_DPLL;
@@ -1016,7 +1076,7 @@ static int omap2_select_table_rate(struc
 		cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 
 		/* Major subsystem dividers */
-		tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & 0x2000;
+		tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
 		cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
 		if (cpu_is_omap2430())
 			cm_write_mod_reg(prcm->cm_clksel_mdm,
@@ -1073,13 +1133,13 @@ static void __init omap2_get_crystal_rat
 
 	aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 	aplls &= OMAP24XX_APLLS_CLKIN_MASK;
-	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;	/* Isolate field, 0,2,3 */
+	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 
-	if (aplls == 0)
+	if (aplls == APLLS_CLKIN_19_2MHZ)
 		sclk = 19200000;
-	else if (aplls == 2)
+	else if (aplls == APLLS_CLKIN_13MHZ)
 		sclk = 13000000;
-	else if (aplls == 3)
+	else if (aplls == APLLS_CLKIN_12MHZ)
 		sclk = 12000000;
 
 	div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);

-- 

[PATCH 19/22] omap2 clock: use dedicated omap2_dpll_recalc() for DPLL recalc func

[Paul Walmsley]

[-- Attachment #1: use-dpll-specific-recalc-code.patch --]
[-- Type: text/plain, Size: 2476 bytes --]

dpll_ck is not a clksel clock, and so it does not really fit well into
omap2_clksel_recalc().  Split off its recalc code into its own function,
omap2_dpll_recalc().

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |   17 +++++++++--------
 arch/arm/mach-omap2/clock.h |    3 ++-
 2 files changed, 11 insertions(+), 9 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -387,6 +387,13 @@ static u32 omap2_dpll_round_rate(unsigne
 
 }
 
+static void omap2_dpll_recalc(struct clk *clk)
+{
+	clk->rate = omap2_get_dpll_rate(clk);
+
+	propagate_rate(clk);
+}
+
 /*
  * Used for clocks that are part of CLKSEL_xyz governed clocks.
  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
@@ -396,12 +403,6 @@ static void omap2_clksel_recalc(struct c
 	u32 fixed = 0, div = 0;
 	u32 clksel1_core;
 
-	if (clk == &dpll_ck) {
-		clk->rate = omap2_get_dpll_rate(clk);
-		fixed = 1;
-		div = 0;
-	}
-
 	if (clk == &iva1_mpu_int_ifck) {
 		div = 2;
 		fixed = 1;
@@ -594,7 +595,7 @@ static int omap2_reprogram_dpll(struct c
 		omap2_init_memory_params(omap2_dll_force_needed());
 		omap2_reprogram_sdrc(done_rate, 0);
 	}
-	omap2_clksel_recalc(&dpll_ck);
+	omap2_dpll_recalc(&dpll_ck);
 	ret = 0;
 
 dpll_exit:
@@ -1093,7 +1094,7 @@ static int omap2_select_table_rate(struc
 
 		local_irq_restore(flags);
 	}
-	omap2_clksel_recalc(&dpll_ck);
+	omap2_dpll_recalc(&dpll_ck);
 
 	return 0;
 }
Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -33,6 +33,7 @@ static void omap2_clk_disable(struct clk
 static void omap2_sys_clk_recalc(struct clk * clk);
 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
 static u32 omap2_clksel_get_divisor(struct clk *clk);
+static void omap2_dpll_recalc(struct clk *clk);
 
 #define RATE_IN_242X	(1 << 0)
 #define RATE_IN_243X	(1 << 1)
@@ -632,7 +633,7 @@ static struct clk dpll_ck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1 |
 				ALWAYS_ENABLED,
-	.recalc		= &omap2_clksel_recalc,
+	.recalc		= &omap2_dpll_recalc,
 };
 
 static struct clk apll96_ck = {

-- 

[PATCH 20/22] omap2 clock: add fixed divisor clock code

[Paul Walmsley]

[-- Attachment #1: add-parent-div-to-struct-clk.patch --]
[-- Type: text/plain, Size: 7022 bytes --]

The rates of some clocks are equal to their parents' rates, divided by some
fixed integer.  This contrasts with the existing 'followparent' clocks, 
which follow their parents' rates strictly; and the existing 'clksel' clocks,
which follow their parents' rates divided by a runtime-selectable divisor.
Add code to implement these clocks without resorting to specifying a 
fixed rate.  

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c       |   79 ++++++++++++++++++++------------------
 arch/arm/mach-omap2/clock.h       |   11 ++---
 include/asm-arm/arch-omap/clock.h |    3 +
 3 files changed, 52 insertions(+), 41 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -134,6 +134,20 @@ static void omap2_followparent_recalc(st
 	followparent_recalc(clk);
 }
 
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+static void omap2_fixed_divisor_recalc(struct clk *clk)
+{
+	WARN_ON(!clk->fixed_div);
+
+	clk->rate = clk->parent->rate / clk->fixed_div;
+
+	if (clk->flags & RATE_PROPAGATES)
+		propagate_rate(clk);
+}
+
 static void omap2_propagate_rate(struct clk * clk)
 {
 	if (!(clk->flags & RATE_FIXED))
@@ -400,39 +414,27 @@ static void omap2_dpll_recalc(struct clk
  */
 static void omap2_clksel_recalc(struct clk * clk)
 {
-	u32 fixed = 0, div = 0;
-	u32 clksel1_core;
-
-	if (clk == &iva1_mpu_int_ifck) {
-		div = 2;
-		fixed = 1;
-	}
+	u32 clksel1_core, div = 0;
 
 	clksel1_core = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1);
 
 	if ((clk == &dss1_fck) &&
 	    (clksel1_core & OMAP24XX_CLKSEL_DSS1_MASK) == 0) {
-		clk->rate = sys_ck.rate;
-		return;
+		div = 1;
 	}
 
 	if ((clk == &vlynq_fck) && cpu_is_omap2420() &&
 	    (clksel1_core & OMAP2420_CLKSEL_VLYNQ_MASK) == CLKSEL_VLYNQ_96MHZ) {
-		clk->rate = func_96m_ck.rate;
-		return;
+		div = 1;
 	}
 
-	if (!fixed) {
-		div = omap2_clksel_get_divisor(clk);
-		if (div == 0)
-			return;
-	}
+	div = omap2_clksel_get_divisor(clk);
+	if (div == 0)
+		return;
 
-	if (div != 0) {
-		if (unlikely(clk->rate == clk->parent->rate / div))
-			return;
-		clk->rate = clk->parent->rate / div;
-	}
+	if (unlikely(clk->rate == clk->parent->rate / div))
+		return;
+	clk->rate = clk->parent->rate / div;
 
 	if (unlikely(clk->flags & RATE_PROPAGATES))
 		propagate_rate(clk);
@@ -832,12 +834,13 @@ static int omap2_clk_set_rate(struct clk
 /* Converts encoded control register address into a full address */
 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
 				      struct clk *src_clk, u32 *field_mask,
-				      struct clk *clk)
+				      struct clk *clk, u32 *parent_div)
 {
 	u32 val = ~0, mask = 0;
 	void __iomem *src_reg_addr = 0;
 	u32 reg_offset;
 
+	*parent_div = 0;
 	reg_offset = clk->src_offset;
 
 	/* Find target control register.*/
@@ -854,21 +857,25 @@ static u32 omap2_clksel_get_src_field(vo
 				WARN_ON(1); /* unknown src_clk */
 		} else if (reg_offset == OMAP24XX_CLKSEL_DSS1_SHIFT) {
 			mask = OMAP24XX_CLKSEL_DSS1_MASK;
-			if (src_clk == &sys_ck)
+			if (src_clk == &sys_ck) {
 				val = CLKSEL_DSS1_SYSCLK;
-			else if (src_clk == &core_ck)	/* divided clock */
-				val = CLKSEL_DSS1_CORECLK_16;	/* rate needs fixing */
-			else
+			} else if (src_clk == &core_ck) {
+				val = CLKSEL_DSS1_CORECLK_16;
+				*parent_div = 16;
+			} else {
 				WARN_ON(1); /* unknown src clk */
+			}
 		} else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
 			   cpu_is_omap2420()) {
 			mask = OMAP2420_CLKSEL_VLYNQ_MASK;
-			if (src_clk == &func_96m_ck)
+			if (src_clk == &func_96m_ck) {
 				val = CLKSEL_VLYNQ_96MHZ;
-			else if (src_clk == &core_ck)
+			} else if (src_clk == &core_ck) {
 				val = CLKSEL_VLYNQ_CORECLK_16;
-			else
+				*parent_div = 16;
+			} else {
 				WARN_ON(1); /* unknown src_clk */
+			}
 		} else {
 			WARN_ON(1); /* unknown reg_offset */
 		}
@@ -974,7 +981,7 @@ static u32 omap2_clksel_get_src_field(vo
 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
 	void __iomem *src_addr;
-	u32 field_val, field_mask, reg_val;
+	u32 field_val, field_mask, reg_val, parent_div;
 
 	if (unlikely(clk->flags & CONFIG_PARTICIPANT))
 		return -EINVAL;
@@ -983,7 +990,7 @@ static int omap2_clk_set_parent(struct c
 		return -EINVAL;
 
 	field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
-					       &field_mask, clk);
+					       &field_mask, clk, &parent_div);
 	if (src_addr == 0)
 		return -EINVAL;
 
@@ -1001,17 +1008,17 @@ static int omap2_clk_set_parent(struct c
 			      OMAP24XX_PRCM_CLKCFG_CTRL);
 		wmb();
 	}
+
 	if (clk->usecount > 0)
 		_omap2_clk_enable(clk);
 
 	clk->parent = new_parent;
 
 	/* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
-	if ((new_parent == &core_ck) &&
-	    (clk == &dss1_fck || clk == &vlynq_fck))
-		clk->rate = new_parent->rate / 0x10;
-	else
-		clk->rate = new_parent->rate;
+	clk->rate = new_parent->rate;
+
+	if (parent_div > 0)
+		clk->rate /= parent_div;
 
 	if (unlikely(clk->flags & RATE_PROPAGATES))
 		propagate_rate(clk);
Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -34,6 +34,7 @@ static void omap2_sys_clk_recalc(struct 
 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
 static u32 omap2_clksel_get_divisor(struct clk *clk);
 static void omap2_dpll_recalc(struct clk *clk);
+static void omap2_fixed_divisor_recalc(struct clk *clk);
 
 #define RATE_IN_242X	(1 << 0)
 #define RATE_IN_243X	(1 << 1)
@@ -704,11 +705,10 @@ static struct clk func_48m_ck = {
 static struct clk func_12m_ck = {
 	.name		= "func_12m_ck",
 	.parent		= &func_48m_ck,
-	.rate		= 12000000,
+	.fixed_div	= 4,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-				RATE_FIXED | RATE_PROPAGATES |
-				PARENT_CONTROLS_CLOCK,
-	.recalc		= &omap2_propagate_rate,
+				RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+	.recalc		= &omap2_fixed_divisor_recalc,
 };
 
 /* Secure timer, only available in secure mode */
@@ -848,7 +848,8 @@ static struct clk iva1_mpu_int_ifck = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP2420_EN_IVA_MPU_SHIFT,
-	.recalc		= &omap2_clksel_recalc,
+	.fixed_div	= 2,
+	.recalc		= &omap2_fixed_divisor_recalc,
 };
 
 /*
Index: linux-omap/include/asm-arm/arch-omap/clock.h
===================================================================
--- linux-omap.orig/include/asm-arm/arch-omap/clock.h
+++ linux-omap/include/asm-arm/arch-omap/clock.h
@@ -34,6 +34,9 @@ struct clk {
 	void			(*init)(struct clk *);
 	int			(*enable)(struct clk *);
 	void			(*disable)(struct clk *);
+#if defined(CONFIG_ARCH_OMAP2420)
+	u8			fixed_div;
+#endif
 };
 
 struct clk_functions {

-- 

[PATCH 21/22] omap2 clock: remove fixed rate from mdm_osc_ck

[Paul Walmsley]

[-- Attachment #1: convert_mdm_osc_ck_to_omap2_propagate_rate.patch --]
[-- Type: text/plain, Size: 1382 bytes --]

mdm_osc_ck has a preinitialized rate and is marked as RATE_FIXED, but rather
than using omap2_propagate_rate() as its recalc function, which accounts
for RATE_FIXED clocks, it uses omap2_followparent_recalc(), which sets the 
rate to the parent clock's rate.  After reviewing the 2430 TRM, fix this
inconsistency by removing the fixed rate declarations (TRM says that this 
clock is 'typically' 26MHz).

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -960,6 +960,7 @@ static struct clk gfx_ick = {
  *	CLOCKS:
  *		MDM_OSC_CLK
  *		MDM_ICLK
+ * These clocks are usable in chassis mode only.
  */
 static struct clk mdm_ick = {		/* used both as a ick and fck */
 	.name		= "mdm_ick",
@@ -974,9 +975,8 @@ static struct clk mdm_ick = {		/* used b
 
 static struct clk mdm_osc_ck = {
 	.name		= "mdm_osc_ck",
-	.rate		= 26000000,
 	.parent		= &osc_ck,
-	.flags		= CLOCK_IN_OMAP243X | RATE_FIXED,
+	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP2430_EN_OSC_SHIFT,
 	.recalc		= &omap2_followparent_recalc,

-- 

[PATCH 22/22] omap2 clock: get rid of omap2_followparent_recalc()

[Paul Walmsley]

[-- Attachment #1: nuke_omap2_followparent_recalc.patch --]
[-- Type: text/plain, Size: 33081 bytes --]

omap2_followparent_recalc() just calls followparent_recalc(), so,
get rid of omap2_followparent_recalc().

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/clock.c |    5 -
 arch/arm/mach-omap2/clock.h |  205 +++++++++++++++++++++-----------------------
 2 files changed, 102 insertions(+), 108 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/clock.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.c
+++ linux-omap/arch/arm/mach-omap2/clock.c
@@ -129,11 +129,6 @@ static u32 omap2_get_dpll_rate(struct cl
 	return dpll_clk;
 }
 
-static void omap2_followparent_recalc(struct clk *clk)
-{
-	followparent_recalc(clk);
-}
-
 /*
  * Used for clocks that have the same value as the parent clock,
  * divided by some factor
Index: linux-omap/arch/arm/mach-omap2/clock.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock.h
+++ linux-omap/arch/arm/mach-omap2/clock.h
@@ -24,7 +24,6 @@
 
 static void omap2_sys_clk_recalc(struct clk * clk);
 static void omap2_clksel_recalc(struct clk * clk);
-static void omap2_followparent_recalc(struct clk * clk);
 static void omap2_propagate_rate(struct clk * clk);
 static void omap2_mpu_recalc(struct clk * clk);
 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
@@ -716,7 +715,7 @@ static struct clk wdt1_osc_ck = {
 	.name		= "ck_wdt1_osc",
 	.parent		= &osc_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk sys_clkout = {
@@ -952,7 +951,7 @@ static struct clk gfx_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),	/* bit 0 */
 	.enable_bit	= OMAP_EN_GFX_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 /*
@@ -979,7 +978,7 @@ static struct clk mdm_osc_ck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP2430_EN_OSC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 /*
@@ -1005,7 +1004,7 @@ static struct clk ssi_l4_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),	/* bit 1 */
 	.enable_bit	= OMAP24XX_EN_SSI_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 /*
@@ -1022,7 +1021,7 @@ static struct clk dss_ick = {		/* Enable
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_DSS1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk dss1_fck = {
@@ -1046,7 +1045,7 @@ static struct clk dss2_fck = {		/* Alt c
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_DSS2_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_DSS2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk dss_54m_fck = {	/* Alt clk used in power management */
@@ -1055,7 +1054,7 @@ static struct clk dss_54m_fck = {	/* Alt
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_TV_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 /*
@@ -1070,7 +1069,7 @@ static struct clk gpt1_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),	/* Bit0 */
 	.enable_bit	= OMAP24XX_EN_GPT1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt1_fck = {
@@ -1081,7 +1080,7 @@ static struct clk gpt1_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),	/* Bit0 */
 	.enable_bit	= OMAP24XX_EN_GPT1_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt2_ick = {
@@ -1090,7 +1089,7 @@ static struct clk gpt2_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	/* Bit4 */
 	.enable_bit	= OMAP24XX_EN_GPT2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt2_fck = {
@@ -1101,7 +1100,7 @@ static struct clk gpt2_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT2_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt3_ick = {
@@ -1110,7 +1109,7 @@ static struct clk gpt3_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	/* Bit5 */
 	.enable_bit	= OMAP24XX_EN_GPT3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt3_fck = {
@@ -1121,7 +1120,7 @@ static struct clk gpt3_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT3_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt4_ick = {
@@ -1130,7 +1129,7 @@ static struct clk gpt4_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	/* Bit6 */
 	.enable_bit	= OMAP24XX_EN_GPT4_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt4_fck = {
@@ -1141,7 +1140,7 @@ static struct clk gpt4_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT4_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT4_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt5_ick = {
@@ -1150,7 +1149,7 @@ static struct clk gpt5_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* Bit7 */
 	.enable_bit	= OMAP24XX_EN_GPT5_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt5_fck = {
@@ -1161,7 +1160,7 @@ static struct clk gpt5_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT5_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT5_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt6_ick = {
@@ -1170,7 +1169,7 @@ static struct clk gpt6_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_bit	= OMAP24XX_EN_GPT6_SHIFT,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit8 */
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt6_fck = {
@@ -1181,7 +1180,7 @@ static struct clk gpt6_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT6_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT6_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt7_ick = {
@@ -1190,7 +1189,7 @@ static struct clk gpt7_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit9 */
 	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt7_fck = {
@@ -1201,7 +1200,7 @@ static struct clk gpt7_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT7_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt8_ick = {
@@ -1210,7 +1209,7 @@ static struct clk gpt8_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit10 */
 	.enable_bit	= OMAP24XX_EN_GPT8_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt8_fck = {
@@ -1221,7 +1220,7 @@ static struct clk gpt8_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT8_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT8_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt9_ick = {
@@ -1230,7 +1229,7 @@ static struct clk gpt9_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT9_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt9_fck = {
@@ -1241,7 +1240,7 @@ static struct clk gpt9_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT9_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT9_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt10_ick = {
@@ -1250,7 +1249,7 @@ static struct clk gpt10_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT10_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt10_fck = {
@@ -1261,7 +1260,7 @@ static struct clk gpt10_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT10_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT10_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt11_ick = {
@@ -1270,7 +1269,7 @@ static struct clk gpt11_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT11_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt11_fck = {
@@ -1281,7 +1280,7 @@ static struct clk gpt11_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT11_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT11_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt12_ick = {
@@ -1290,7 +1289,7 @@ static struct clk gpt12_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit14 */
 	.enable_bit	= OMAP24XX_EN_GPT12_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpt12_fck = {
@@ -1301,7 +1300,7 @@ static struct clk gpt12_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT12_SHIFT,
 	.src_offset	= OMAP24XX_CLKSEL_GPT12_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 /* REVISIT: bit comment below wrong? */
@@ -1311,7 +1310,7 @@ static struct clk mcbsp1_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit16 */
 	.enable_bit	= OMAP24XX_EN_MCBSP1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp1_fck = {
@@ -1320,7 +1319,7 @@ static struct clk mcbsp1_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_MCBSP1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp2_ick = {
@@ -1329,7 +1328,7 @@ static struct clk mcbsp2_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_MCBSP2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp2_fck = {
@@ -1338,7 +1337,7 @@ static struct clk mcbsp2_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_MCBSP2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp3_ick = {
@@ -1347,7 +1346,7 @@ static struct clk mcbsp3_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_MCBSP3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp3_fck = {
@@ -1356,7 +1355,7 @@ static struct clk mcbsp3_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_MCBSP3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp4_ick = {
@@ -1365,7 +1364,7 @@ static struct clk mcbsp4_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_MCBSP4_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp4_fck = {
@@ -1374,7 +1373,7 @@ static struct clk mcbsp4_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_MCBSP4_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp5_ick = {
@@ -1383,7 +1382,7 @@ static struct clk mcbsp5_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_MCBSP5_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcbsp5_fck = {
@@ -1392,7 +1391,7 @@ static struct clk mcbsp5_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_MCBSP5_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcspi1_ick = {
@@ -1402,7 +1401,7 @@ static struct clk mcspi1_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_MCSPI1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcspi1_fck = {
@@ -1412,7 +1411,7 @@ static struct clk mcspi1_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_MCSPI1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcspi2_ick = {
@@ -1422,7 +1421,7 @@ static struct clk mcspi2_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_MCSPI2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcspi2_fck = {
@@ -1432,7 +1431,7 @@ static struct clk mcspi2_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_MCSPI2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcspi3_ick = {
@@ -1442,7 +1441,7 @@ static struct clk mcspi3_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_MCSPI3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mcspi3_fck = {
@@ -1452,7 +1451,7 @@ static struct clk mcspi3_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_MCSPI3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk uart1_ick = {
@@ -1461,7 +1460,7 @@ static struct clk uart1_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_UART1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk uart1_fck = {
@@ -1470,7 +1469,7 @@ static struct clk uart1_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_UART1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk uart2_ick = {
@@ -1479,7 +1478,7 @@ static struct clk uart2_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_UART2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk uart2_fck = {
@@ -1488,7 +1487,7 @@ static struct clk uart2_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_UART2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk uart3_ick = {
@@ -1497,7 +1496,7 @@ static struct clk uart3_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP24XX_EN_UART3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk uart3_fck = {
@@ -1506,7 +1505,7 @@ static struct clk uart3_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP24XX_EN_UART3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpios_ick = {
@@ -1515,7 +1514,7 @@ static struct clk gpios_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP24XX_EN_GPIOS_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpios_fck = {
@@ -1524,7 +1523,7 @@ static struct clk gpios_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP24XX_EN_GPIOS_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mpu_wdt_ick = {
@@ -1533,7 +1532,7 @@ static struct clk mpu_wdt_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP24XX_EN_MPU_WDT_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mpu_wdt_fck = {
@@ -1542,7 +1541,7 @@ static struct clk mpu_wdt_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= OMAP24XX_EN_MPU_WDT_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk sync_32k_ick = {
@@ -1551,7 +1550,7 @@ static struct clk sync_32k_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP24XX_EN_32KSYNC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 static struct clk wdt1_ick = {
 	.name		= "wdt1_ick",
@@ -1559,7 +1558,7 @@ static struct clk wdt1_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP24XX_EN_WDT1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 static struct clk omapctrl_ick = {
 	.name		= "omapctrl_ick",
@@ -1567,7 +1566,7 @@ static struct clk omapctrl_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP24XX_EN_OMAPCTRL_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 static struct clk icr_ick = {
 	.name		= "icr_ick",
@@ -1575,7 +1574,7 @@ static struct clk icr_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP2430_EN_ICR_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk cam_ick = {
@@ -1584,7 +1583,7 @@ static struct clk cam_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_CAM_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk cam_fck = {
@@ -1593,7 +1592,7 @@ static struct clk cam_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_CAM_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mailboxes_ick = {
@@ -1602,7 +1601,7 @@ static struct clk mailboxes_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_MAILBOXES_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk wdt4_ick = {
@@ -1611,7 +1610,7 @@ static struct clk wdt4_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_WDT4_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk wdt4_fck = {
@@ -1620,7 +1619,7 @@ static struct clk wdt4_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_WDT4_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk wdt3_ick = {
@@ -1629,7 +1628,7 @@ static struct clk wdt3_ick = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP2420_EN_WDT3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk wdt3_fck = {
@@ -1638,7 +1637,7 @@ static struct clk wdt3_fck = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_WDT3_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mspro_ick = {
@@ -1647,7 +1646,7 @@ static struct clk mspro_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_MSPRO_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mspro_fck = {
@@ -1656,7 +1655,7 @@ static struct clk mspro_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_MSPRO_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mmc_ick = {
@@ -1665,7 +1664,7 @@ static struct clk mmc_ick = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP2420_EN_MMC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mmc_fck = {
@@ -1674,7 +1673,7 @@ static struct clk mmc_fck = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_MMC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk fac_ick = {
@@ -1683,7 +1682,7 @@ static struct clk fac_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_FAC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk fac_fck = {
@@ -1692,7 +1691,7 @@ static struct clk fac_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_FAC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk eac_ick = {
@@ -1701,7 +1700,7 @@ static struct clk eac_ick = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP2420_EN_EAC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk eac_fck = {
@@ -1710,7 +1709,7 @@ static struct clk eac_fck = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_EAC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk hdq_ick = {
@@ -1719,7 +1718,7 @@ static struct clk hdq_ick = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_HDQ_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk hdq_fck = {
@@ -1728,7 +1727,7 @@ static struct clk hdq_fck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP24XX_EN_HDQ_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk i2c2_ick = {
@@ -1738,7 +1737,7 @@ static struct clk i2c2_ick = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk i2c2_fck = {
@@ -1748,7 +1747,7 @@ static struct clk i2c2_fck = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk i2chs2_fck = {
@@ -1758,7 +1757,7 @@ static struct clk i2chs2_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_I2CHS2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk i2c1_ick = {
@@ -1768,7 +1767,7 @@ static struct clk i2c1_ick = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk i2c1_fck = {
@@ -1778,7 +1777,7 @@ static struct clk i2c1_fck = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk i2chs1_fck = {
@@ -1788,7 +1787,7 @@ static struct clk i2chs1_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_I2CHS1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk vlynq_ick = {
@@ -1797,7 +1796,7 @@ static struct clk vlynq_ick = {
 	.flags		= CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP2420_EN_VLYNQ_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk vlynq_fck = {
@@ -1816,7 +1815,7 @@ static struct clk sdrc_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
 	.enable_bit	= OMAP2430_EN_SDRC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk des_ick = {
@@ -1825,7 +1824,7 @@ static struct clk des_ick = {
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= OMAP24XX_EN_DES_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk sha_ick = {
@@ -1834,7 +1833,7 @@ static struct clk sha_ick = {
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= OMAP24XX_EN_SHA_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk rng_ick = {
@@ -1843,7 +1842,7 @@ static struct clk rng_ick = {
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= OMAP24XX_EN_RNG_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk aes_ick = {
@@ -1852,7 +1851,7 @@ static struct clk aes_ick = {
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= OMAP24XX_EN_AES_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk pka_ick = {
@@ -1861,7 +1860,7 @@ static struct clk pka_ick = {
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= OMAP24XX_EN_PKA_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk usb_fck = {
@@ -1870,7 +1869,7 @@ static struct clk usb_fck = {
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP24XX_EN_USB_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk usbhs_ick = {
@@ -1879,7 +1878,7 @@ static struct clk usbhs_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_USBHS_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mmchs1_ick = {
@@ -1888,7 +1887,7 @@ static struct clk mmchs1_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_MMCHS1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mmchs1_fck = {
@@ -1897,7 +1896,7 @@ static struct clk mmchs1_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_MMCHS1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mmchs2_ick = {
@@ -1906,7 +1905,7 @@ static struct clk mmchs2_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_MMCHS2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mmchs2_fck = {
@@ -1915,7 +1914,7 @@ static struct clk mmchs2_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_MMCHS2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpio5_ick = {
@@ -1924,7 +1923,7 @@ static struct clk gpio5_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_GPIO5_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk gpio5_fck = {
@@ -1933,7 +1932,7 @@ static struct clk gpio5_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_GPIO5_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mdm_intc_ick = {
@@ -1942,7 +1941,7 @@ static struct clk mdm_intc_ick = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP2430_EN_MDM_INTC_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mmchsdb1_fck = {
@@ -1951,7 +1950,7 @@ static struct clk mmchsdb1_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_MMCHSDB1_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 static struct clk mmchsdb2_fck = {
@@ -1960,7 +1959,7 @@ static struct clk mmchsdb2_fck = {
 	.flags		= CLOCK_IN_OMAP243X,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= OMAP2430_EN_MMCHSDB2_SHIFT,
-	.recalc		= &omap2_followparent_recalc,
+	.recalc		= &followparent_recalc,
 };
 
 /*

-- 

RE: [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked aspresent on OMAP2430

[Woodruff, Richard]

Hi Paul,

Looks like you have gone the next level into the clock code.  So far the fixes and cleanups I've looked at seem good.  This is nice.

As for the below I think this matches the current TRM.  The bits were removed from the TRM a while back.  The clocks are actually there it's just not recommended.  Previously there was a kind of messy description about how to use one or the other clock source.  Early on seems we used the first version while some bugs were being fixed.  Later it switched or should have.

In particular on the 2430 it is very important to not set undefined bits.  Its design was such that it was meant to be used in combination with several chips.  Non-documented bits can turn on things which silently can kill your ability to hit chip retention.  Long ago this bit me as some NAND xloader code set some 2420 clocks then cleared them.

Regards,
Richard W.


> Several clocks are marked as present on OMAP2430, even though they are
> 2420-only.  Drop CLOCK_IN_OMAP243X from those clocks' flags.
> 
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> 
> ---
>  arch/arm/mach-omap2/clock.h |   11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
> 
> Index: linux-omap/arch/arm/mach-omap2/clock.h
> ===================================================================
> --- linux-omap.orig/arch/arm/mach-omap2/clock.h
> +++ linux-omap/arch/arm/mach-omap2/clock.h
> @@ -742,8 +742,7 @@ static struct clk sys_clkout2 = {
>  	.name		= "sys_clkout2",
>  	.parent		= &func_54m_ck,
>  	.rate		= 54000000,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
> -				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
> +	.flags		= CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 |
> RATE_CKCTL,
>  	.src_offset	= OMAP2420_CLKOUT2_SOURCE_SHIFT,
>  	.enable_reg	= OMAP24XX_PRCM_CLKOUT_CTRL,
>  	.enable_bit	= OMAP2420_CLKOUT2_EN_SHIFT,
> @@ -1740,7 +1739,7 @@ static struct clk i2c2_ick = {
>  	.name		= "i2c_ick",
>  	.id		= 2,
>  	.parent		= &l4_ck,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
> +	.flags		= CLOCK_IN_OMAP242X,
>  	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
>  	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
>  	.recalc		= &omap2_followparent_recalc,
> @@ -1750,7 +1749,7 @@ static struct clk i2c2_fck = {
>  	.name		= "i2c_fck",
>  	.id		= 2,
>  	.parent		= &func_12m_ck,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
> +	.flags		= CLOCK_IN_OMAP242X,
>  	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
>  	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
>  	.recalc		= &omap2_followparent_recalc,
> @@ -1770,7 +1769,7 @@ static struct clk i2c1_ick = {
>  	.name		= "i2c_ick",
>  	.id		= 1,
>  	.parent		= &l4_ck,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
> +	.flags		= CLOCK_IN_OMAP242X,
>  	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
>  	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
>  	.recalc		= &omap2_followparent_recalc,
> @@ -1780,7 +1779,7 @@ static struct clk i2c1_fck = {
>  	.name		= "i2c_fck",
>  	.id		= 1,
>  	.parent		= &func_12m_ck,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
> +	.flags		= CLOCK_IN_OMAP242X,
>  	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
>  	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
>  	.recalc		= &omap2_followparent_recalc,
> 
> --
> 
> _______________________________________________
> Linux-omap-open-source mailing list
> Linux-omap-open-source@linux.omap.com
> http://linux.omap.com/mailman/listinfo/linux-omap-open-source

RE: [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked aspresent on OMAP2430

[Woodruff, Richard]

Hi Paul,

CLOCKOUT2 is in the latest functional spec.  This might be a TRM error or the removed the ball for later ES versions.

In 2420ES1 there was no clockout2 it was added for ES2 and beyond.

Need to see if it can be mux'ed to a ball.

Regards,
Richard W.

> Several clocks are marked as present on OMAP2430, even though they are
> 2420-only.  Drop CLOCK_IN_OMAP243X from those clocks' flags.
> 
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> 
> ---
>  arch/arm/mach-omap2/clock.h |   11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
> 
> Index: linux-omap/arch/arm/mach-omap2/clock.h
> ===================================================================
> --- linux-omap.orig/arch/arm/mach-omap2/clock.h
> +++ linux-omap/arch/arm/mach-omap2/clock.h
> @@ -742,8 +742,7 @@ static struct clk sys_clkout2 = {
>  	.name		= "sys_clkout2",
>  	.parent		= &func_54m_ck,
>  	.rate		= 54000000,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
> -				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
> +	.flags		= CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 |
> RATE_CKCTL,
>  	.src_offset	= OMAP2420_CLKOUT2_SOURCE_SHIFT,
>  	.enable_reg	= OMAP24XX_PRCM_CLKOUT_CTRL,
>  	.enable_bit	= OMAP2420_CLKOUT2_EN_SHIFT,
> @@ -1740,7 +1739,7 @@ static struct clk i2c2_ick = {
>  	.name		= "i2c_ick",
>  	.id		= 2,
>  	.parent		= &l4_ck,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
> +	.flags		= CLOCK_IN_OMAP242X,
>  	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
>  	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
>  	.recalc		= &omap2_followparent_recalc,
> @@ -1750,7 +1749,7 @@ static struct clk i2c2_fck = {
>  	.name		= "i2c_fck",
>  	.id		= 2,
>  	.parent		= &func_12m_ck,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
> +	.flags		= CLOCK_IN_OMAP242X,
>  	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
>  	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
>  	.recalc		= &omap2_followparent_recalc,
> @@ -1770,7 +1769,7 @@ static struct clk i2c1_ick = {
>  	.name		= "i2c_ick",
>  	.id		= 1,
>  	.parent		= &l4_ck,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
> +	.flags		= CLOCK_IN_OMAP242X,
>  	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
>  	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
>  	.recalc		= &omap2_followparent_recalc,
> @@ -1780,7 +1779,7 @@ static struct clk i2c1_fck = {
>  	.name		= "i2c_fck",
>  	.id		= 1,
>  	.parent		= &func_12m_ck,
> -	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
> +	.flags		= CLOCK_IN_OMAP242X,
>  	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
>  	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
>  	.recalc		= &omap2_followparent_recalc,
> 
> --
> 
> _______________________________________________
> Linux-omap-open-source mailing list
> Linux-omap-open-source@linux.omap.com
> http://linux.omap.com/mailman/listinfo/linux-omap-open-source

RE: [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked aspresent on OMAP2430

[Paul Walmsley]

hi Richard,

On Thu, 2 Aug 2007, Woodruff, Richard wrote:

> CLOCKOUT2 is in the latest functional spec.  This might be a TRM error 
> or the removed the ball for later ES versions.

looking at 2430 ES2.1 TRM rev G, I can't find any mention of it - maybe 
this TRM is out-of-date?


> In 2420ES1 there was no clockout2 it was added for ES2 and beyond.

hmm, wonder if we should add some clock flags for ES revisions...


- Paul

RE: [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked aspresent on OMAP2430

[Woodruff, Richard]

Hi Paul,

> On Thu, 2 Aug 2007, Woodruff, Richard wrote:
> 
> > CLOCKOUT2 is in the latest functional spec.  This might be a TRM error
> > or the removed the ball for later ES versions.
> 
> looking at 2430 ES2.1 TRM rev G, I can't find any mention of it - maybe
> this TRM is out-of-date?

The current TRM for both 243x and 242x is version Q as of July 07.

So you need h, i, j, k, l, m, n, o, p, and q :).  The documentation just keeps getting better.

> > In 2420ES1 there was no clockout2 it was added for ES2 and beyond.
> 
> hmm, wonder if we should add some clock flags for ES revisions...

Well, the difference between ES1 and ES2 can be noticeable (especially for 242x).  But no one has gone to production on an ES1 either.  There shouldn't be so many to warrant a flag.  In the past we have tracked this to keep the pain down in transition from ES1 to ES2 but as time goes on most everyone gets updated.

Regards,
Richard W.

RE: [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked aspresent on OMAP2430

[Paul Walmsley]

On Fri, 3 Aug 2007, Woodruff, Richard wrote:

> The current TRM for both 243x and 242x is version Q as of July 07.

That would explain it.  I will pick up the more recent revisions.  In the 
meantime, I will fix the patch to preserve sys_clkout2 for 2430, and also 
to fix the register bits to indicate that they are not 2420-only.

> So you need h, i, j, k, l, m, n, o, p, and q :).  The documentation just keeps getting better.

Does TI publish revision histories?  Might be easier than diff'ing 11 
3500-page PDFs :-)

>>> In 2420ES1 there was no clockout2 it was added for ES2 and beyond.
>>
>> hmm, wonder if we should add some clock flags for ES revisions...
>
> Well, the difference between ES1 and ES2 can be noticeable (especially 
> for 242x).  But no one has gone to production on an ES1 either.  There 
> shouldn't be so many to warrant a flag.  In the past we have tracked 
> this to keep the pain down in transition from ES1 to ES2 but as time 
> goes on most everyone gets updated.

Ok, thanks, sounds like we can do without it for the time being.


- Paul

RE: [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked aspresent on OMAP2430

[Woodruff, Richard]

> > The current TRM for both 243x and 242x is version Q as of July 07.
> 
> That would explain it.  I will pick up the more recent revisions.  In
the
> meantime, I will fix the patch to preserve sys_clkout2 for 2430, and
also
> to fix the register bits to indicate that they are not 2420-only.

You might just hold off.  I didn't see it in rev Q either.  It was added
into the basic functional spec. The F-spec's are the original document
from designers, started a couple years before TRMs and are built up
along with the chips.  Later, TRMs are spun off.

> > So you need h, i, j, k, l, m, n, o, p, and q :).  The documentation
just
> keeps getting better.
> 
> Does TI publish revision histories?  Might be easier than diff'ing 11
> 3500-page PDFs :-)

Yes they do for OMAP2/3.  I tend to keep 3 back.  I don't have my main
computer handy otherwise I'll send you a document number.

Regards,
Richard W.

Re: [PATCH 11/22] omap2 clock: fix some clocks incorrectly marked aspresent on OMAP2430

[Tony Lindgren]

* Woodruff, Richard <r-woodruff2@ti.com> [070804 15:02]:
> > > The current TRM for both 243x and 242x is version Q as of July 07.
> > 
> > That would explain it.  I will pick up the more recent revisions.  In
> the
> > meantime, I will fix the patch to preserve sys_clkout2 for 2430, and
> also
> > to fix the register bits to indicate that they are not 2420-only.
> 
> You might just hold off.  I didn't see it in rev Q either.  It was added
> into the basic functional spec. The F-spec's are the original document
> from designers, started a couple years before TRMs and are built up
> along with the chips.  Later, TRMs are spun off.

Nice job with the clocks Paul :) Pushing the whole series today.

Regards,

Tony

[PATCH 02/22 - Reverse] omap2 osc & sys clock calculation.

[Woodruff, Richard]

Tony,

Can you reverse this patch?  Or should a fixed one be submitted?

With this the system gets the wrong osc speed and ends up setting the system speed wrongly.  This results in OMAP running to slow, can't have that.

As explained in another mail the APLLS tuning speed is used to set the rate of these clocks with out having to do gauging again.  The boot loader should use the 32KHz clock and a gptimer to figure out the input speed and set the APLL properly.  You then use the APLL multipled with the divider to get the osc clocks speed.  The divider is only 1 or 2.

1 step back with 22 ones forward is still pretty good ;)

Regards,
Richard W.

> Subject: [PATCH 02/22] omap2 clock: fix incorrect rate calculation
> forosc_ck, sys_ck
> 
> omap2_get_crystal_rate() calculates osc_ck and sys_ck rates
> incorrectly.  osc_ck runs at the same rate as the external clock
> source.  Also, sys_ck's rate derives from osc_ck's rate, divided (not
> multiplied) by PRCM_CLKSRC_CTRL:SYSCLKDIV.
> 
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> 
> ---
>  arch/arm/mach-omap2/clock.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> Index: linux-omap/arch/arm/mach-omap2/clock.c
> ===================================================================
> --- linux-omap.orig/arch/arm/mach-omap2/clock.c
> +++ linux-omap/arch/arm/mach-omap2/clock.c
> @@ -1126,8 +1126,8 @@ static void __init omap2_get_crystal_rat
>  	div &= OMAP_SYSCLKDIV_MASK;
>  	div >>= sys->rate_offset;
> 
> -	osc->rate = sclk * div;
> -	sys->rate = sclk;
> +	osc->rate = sclk;
> +	sys->rate = osc->rate / div;
>  }
> 
>  /*
> 
> --
> 
> _______________________________________________
> Linux-omap-open-source mailing list
> Linux-omap-open-source@linux.omap.com
> http://linux.omap.com/mailman/listinfo/linux-omap-open-source

Re: [PATCH 02/22 - Reverse] omap2 osc & sys clock calculation.

[Tony Lindgren]

Hi,

* Woodruff, Richard <r-woodruff2@ti.com> [070810 14:09]:
> Tony,
> 
> Can you reverse this patch?  Or should a fixed one be submitted?

Yeah, I'll revert it, thanks for debugging it.

> With this the system gets the wrong osc speed and ends up setting the system speed wrongly.  This results in OMAP running to slow, can't have that.
> 
> As explained in another mail the APLLS tuning speed is used to set the rate of these clocks with out having to do gauging again.  The boot loader should use the 32KHz clock and a gptimer to figure out the input speed and set the APLL properly.  You then use the APLL multipled with the divider to get the osc clocks speed.  The divider is only 1 or 2.
> 
> 1 step back with 22 ones forward is still pretty good ;)

Yeah :)

Tony



> Regards,
> Richard W.
> 
> > Subject: [PATCH 02/22] omap2 clock: fix incorrect rate calculation
> > forosc_ck, sys_ck
> > 
> > omap2_get_crystal_rate() calculates osc_ck and sys_ck rates
> > incorrectly.  osc_ck runs at the same rate as the external clock
> > source.  Also, sys_ck's rate derives from osc_ck's rate, divided (not
> > multiplied) by PRCM_CLKSRC_CTRL:SYSCLKDIV.
> > 
> > Signed-off-by: Paul Walmsley <paul@pwsan.com>
> > 
> > ---
> >  arch/arm/mach-omap2/clock.c |    4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > Index: linux-omap/arch/arm/mach-omap2/clock.c
> > ===================================================================
> > --- linux-omap.orig/arch/arm/mach-omap2/clock.c
> > +++ linux-omap/arch/arm/mach-omap2/clock.c
> > @@ -1126,8 +1126,8 @@ static void __init omap2_get_crystal_rat
> >  	div &= OMAP_SYSCLKDIV_MASK;
> >  	div >>= sys->rate_offset;
> > 
> > -	osc->rate = sclk * div;
> > -	sys->rate = sclk;
> > +	osc->rate = sclk;
> > +	sys->rate = osc->rate / div;
> >  }
> > 
> >  /*
> > 
> > --
> > 
> > _______________________________________________
> > Linux-omap-open-source mailing list
> > Linux-omap-open-source@linux.omap.com
> > http://linux.omap.com/mailman/listinfo/linux-omap-open-source