From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Walmsley Subject: [PATCH 1/2] 3430 clock: revise SmartReflex clocks Date: Mon, 12 Nov 2007 03:57:27 -0700 Message-ID: <20071112110147.779860304@pwsan.com> References: <20071112105726.514186925@pwsan.com> Return-path: Content-Disposition: inline; filename=add_sr_clocks.patch List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-omap-open-source-bounces@linux.omap.com Errors-To: linux-omap-open-source-bounces@linux.omap.com To: linux-omap-open-source@linux.omap.com List-Id: linux-omap@vger.kernel.org The two SmartReflex voltage controllers on OMAP3430 have one functional clock each. These clocks appear to be independent of each other. Encode them appropriately, replacing the previous 'sr_alwon_fck' clock. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx.h | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) Index: linux-omap/arch/arm/mach-omap2/clock34xx.h =================================================================== --- linux-omap.orig/arch/arm/mach-omap2/clock34xx.h 2007-11-08 13:05:40.000000000 -0700 +++ linux-omap/arch/arm/mach-omap2/clock34xx.h 2007-11-08 13:05:47.000000000 -0700 @@ -2003,11 +2003,23 @@ /* SR clocks */ -/* REVISIT: dependent on en_sr1 && en_sr2 - use custom enable/disable? */ -static struct clk sr_alwon_fck = { - .name = "sr_alwon_fck", +/* SmartReflex fclk (VDD1) */ +static struct clk sr1_fck = { + .name = "sr1_fck", .parent = &sys_ck, - .flags = CLOCK_IN_OMAP343X, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR1_SHIFT, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .recalc = &followparent_recalc, +}; + +/* SmartReflex fclk (VDD2) */ +static struct clk sr2_fck = { + .name = "sr2_fck", + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR2_SHIFT, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -2204,7 +2216,8 @@ &mcbsp2_fck, &mcbsp3_fck, &mcbsp4_fck, - &sr_alwon_fck, + &sr1_fck, + &sr2_fck, &sr_l4_ick, &secure_32k_fck, &gpt12_fck, --