[PATCH 0/5] SRAM patcher: patch register addresses in SRAM code at runtime

[PATCH 0/5] SRAM patcher: patch register addresses in SRAM code at runtime

[Paul Walmsley]

Several SRAM-based assembly-language routines in the Linux OMAP kernel
use hardcoded virtual addresses to access system registers.  These
addresses were defined at compile-time by the preprocessor, since the
same registers often appeared at different virtual addresses
depending upon the target OMAP architecture.  Hardcoding the addresses
is efficient and convenient to implement; but precludes a single kernel
binary image from supporting multiple OMAP architectures.

This patches implement a different approach.  They patch in the
correct register addresses at runtime into the SRAM, just after the
code is copied there.  While the current code simply writes in the
preprocessor-defined address bases, a forthcoming patch series uses
this code to write runtime-computed address bases.

The code that does the patching is quite paranoid by default, and will
refuse to overwrite any address that does not contain a magic number,
SRAM_VA_MAGIC.  It also contains debugging printks which can be
activated by defining the DEBUG symbol in sram.c and compiling with
CONFIG_DEBUG_LL enabled.

Boot-tested on N800 and 3430SDP.  If someone out there with a 2430SDP
can give these a whirl, that would be appreciated.  Comments welcome,


- Paul

---

diffstat: 

 arch/arm/mach-omap2/pm.c         |   13 +++
 arch/arm/mach-omap2/sdrc.h       |    2
 arch/arm/mach-omap2/sleep.S      |   21 +++---
 arch/arm/mach-omap2/sram-fn.S    |  125 +++++++++++++++++++-----------------
 arch/arm/plat-omap/Kconfig       |   10 ++
 arch/arm/plat-omap/sram.c        |  135 +++++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-omap/sram.h |    3
 include/linux/poison.h           |    6 +
 8 files changed, 245 insertions(+), 70 deletions(-)

size:

   text    data     bss     dec     hex filename
2924328  152944   85112 3162384  304110 vmlinux.orig.n800
2924504  152944   85112 3162560  3041c0 vmlinux.patched.nodebug.n800
2924928  152944   85112 3162984  304368 vmlinux.patched.debug.n800

[PATCH 1/5] SRAM patcher: add SRAM virtual address patcher

[Paul Walmsley]

[-- Attachment #1: sp-add-sram-patch-code.patch --]
[-- Type: text/plain, Size: 5317 bytes --]

Add omap_sram_patch_va(), which patches a virtual address into SRAM 
code at runtime.  This will be used in a future patch series to implement
part of multiboot support for OMAP2/3.

If CONFIG_OMAP_DEBUG_SRAM_PATCH is defined (the default), the code
will be very careful to ensure that the target location to patch is
valid.  It will only overwrite a location if the location contains a
32-bit magic number, defined as SRAM_VA_MAGIC.  Also, defining DEBUG
at the top of the file and enabling CONFIG_DEBUG_LL will log patch
locations and data via printk.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/plat-omap/Kconfig       |   10 ++++++
 arch/arm/plat-omap/sram.c        |   61 +++++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-omap/sram.h |    3 +
 include/linux/poison.h           |    6 +++
 4 files changed, 80 insertions(+)

Index: linux-omap/arch/arm/plat-omap/sram.c
===================================================================
--- linux-omap.orig/arch/arm/plat-omap/sram.c	2007-11-14 01:02:26.000000000 -0700
+++ linux-omap/arch/arm/plat-omap/sram.c	2007-11-14 01:02:28.000000000 -0700
@@ -10,6 +10,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#undef DEBUG
 
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -195,6 +196,66 @@
 	return (void *)omap_sram_ceil;
 }
 
+/**
+ * omap_sram_patch_va - patch a virtual address into SRAM code
+ * @srcfn: original start address (in DRAM) of function to patch
+ * @srcd: original address (in DRAM) of location to patch
+ * @sramfn: start address (in SRAM) of function to patch
+ * @d: virtual address to insert
+ *
+ * Replace a location in SRAM containing a magic number
+ * (SRAM_VA_MAGIC) with a caller-specified virtual address.  Used to
+ * dynamically patch SRAM code at runtime for multiboot, since some
+ * register addresses change depending on the OMAP chip in use.
+ * Returns 1 upon success, 0 upon failure.
+ */
+int omap_sram_patch_va(void *srcfn, void *srcd, void *sramfn, void __iomem *d)
+{
+	unsigned long sram_addr;
+	long offs;
+
+	offs = (unsigned long)srcd - (unsigned long)srcfn;
+	sram_addr = (unsigned long)sramfn + offs;
+
+#ifdef CONFIG_OMAP_DEBUG_SRAM_PATCH
+	if (offs < 0) {
+		printk(KERN_ERR "sram: patch address 0x%0lx < function start "
+		       "address 0x%0lx\n", (unsigned long)srcd,
+		       (unsigned long)srcfn);
+		WARN_ON(1);
+		return 0;
+	}
+
+	/*
+	 * REVISIT: We should probably pass in the function's size also,
+	 * so we can verify that the address to patch exists within
+	 * the function
+	 */
+	if (sram_addr > omap_sram_base + omap_sram_size ||
+	    sram_addr < omap_sram_base + SRAM_BOOTLOADER_SZ) {
+		printk(KERN_ERR "sram: invalid patch address 0x%0lx\n",
+		       sram_addr);
+		WARN_ON(1);
+		return 0;
+	}
+
+	if (*(typeof(SRAM_VA_MAGIC) *)sram_addr != SRAM_VA_MAGIC) {
+		printk(KERN_ERR "sram: will not patch address 0x%0lx: "
+		       "no magic\n", sram_addr);
+		WARN_ON(1);
+		return 0;
+	}
+#endif /* CONFIG_OMAP_DEBUG_SRAM_PATCH */
+
+	pr_debug("sram: patching 0x%0lx with 0x%0lx\n", sram_addr,
+		 (unsigned long)d);
+
+	*(unsigned long *)sram_addr = (unsigned long)d;
+
+	return 1;
+}
+
+
 static void omap_sram_error(void)
 {
 	panic("Uninitialized SRAM function\n");
Index: linux-omap/include/asm-arm/arch-omap/sram.h
===================================================================
--- linux-omap.orig/include/asm-arm/arch-omap/sram.h	2007-11-14 01:02:26.000000000 -0700
+++ linux-omap/include/asm-arm/arch-omap/sram.h	2007-11-14 01:02:28.000000000 -0700
@@ -11,7 +11,10 @@
 #ifndef __ARCH_ARM_OMAP_SRAM_H
 #define __ARCH_ARM_OMAP_SRAM_H
 
+#include <linux/poison.h>    /* for SRAM_VA_MAGIC */
+
 extern void * omap_sram_push(void * start, unsigned long size);
+extern int omap_sram_patch_va(void *srcfn, void *srcd, void *sramfn, void __iomem *d);
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
 
 extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
Index: linux-omap/include/linux/poison.h
===================================================================
--- linux-omap.orig/include/linux/poison.h	2007-11-14 01:02:26.000000000 -0700
+++ linux-omap/include/linux/poison.h	2007-11-14 01:02:28.000000000 -0700
@@ -61,4 +61,10 @@
 /********** sound/oss/ **********/
 #define OSS_POISON_FREE		0xAB
 
+/*
+ * Used in arch/arm/plat-omap/sram.h to mark SRAM addresses that
+ * will be patched at runtime
+ */
+#define SRAM_VA_MAGIC		0xbadfeed1
+
 #endif
Index: linux-omap/arch/arm/plat-omap/Kconfig
===================================================================
--- linux-omap.orig/arch/arm/plat-omap/Kconfig	2007-11-14 01:02:26.000000000 -0700
+++ linux-omap/arch/arm/plat-omap/Kconfig	2007-11-14 01:03:57.000000000 -0700
@@ -32,6 +32,16 @@
 	depends on OMAP_DEBUG_DEVICES
 	default y if LEDS || LEDS_OMAP_DEBUG
 
+config OMAP_DEBUG_SRAM_PATCH
+	bool "Extra sanity checking for SRAM patch code"
+	depends on ARCH_OMAP
+	default y
+	help
+	  Say Y here if you want the kernel to use extra caution
+	  in patching SRAM virtual addresses.  If you are
+	  confident in your SRAM code, disabling this will save
+	  about 600 bytes.
+
 config OMAP_RESET_CLOCKS
 	bool "Reset unused clocks during boot"
 	depends on ARCH_OMAP

-- 

[PATCH 2/5] SRAM patcher: convert omap24xx_sram_suspend to use runtime SRAM patcher

[Paul Walmsley]

[-- Attachment #1: sp-patch-omap24xx-sram-suspend.patch --]
[-- Type: text/plain, Size: 3669 bytes --]

Use the runtime SRAM patcher to set register addresses in
omap24xx_sram_suspend.  The long symbol names are intended to help
disambiguate the symbols, now that they are global.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/pm.c    |   13 +++++++++++++
 arch/arm/mach-omap2/sleep.S |   21 +++++++++++----------
 2 files changed, 24 insertions(+), 10 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/pm.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/pm.c	2007-11-14 01:28:52.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/pm.c	2007-11-14 01:29:02.000000000 -0700
@@ -52,6 +52,10 @@
 #include "cm_regbits_24xx.h"
 #include "sdrc.h"
 
+/* These addrs are in assembly language code to be patched at runtime */
+extern void *omap2_ocs_sdrc_power;
+extern void *omap2_ocs_sdrc_dlla_ctrl;
+
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
 static void (*saved_idle)(void);
@@ -803,9 +807,18 @@
 	 */
 	omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 					 omap24xx_idle_loop_suspend_sz);
+
 	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 					    omap24xx_cpu_suspend_sz);
 
+	/* Patch in the correct register addresses for multiboot */
+	omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
+			   omap2_sram_suspend,
+			   OMAP_SDRC_REGADDR(SDRC_POWER));
+	omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
+			   omap2_sram_suspend,
+			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
+
 	suspend_set_ops(&omap_pm_ops);
 	pm_idle = omap2_pm_idle;
 
Index: linux-omap/arch/arm/mach-omap2/sleep.S
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/sleep.S	2007-11-14 01:28:52.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/sleep.S	2007-11-14 01:29:33.000000000 -0700
@@ -26,17 +26,15 @@
  */
 
 #include <linux/linkage.h>
+#include <linux/poison.h>	/* for SRAM_VA_MAGIC */
 #include <asm/assembler.h>
 #include <asm/arch/io.h>
 #include <asm/arch/pm.h>
 
 #include <asm/arch/omap24xx.h>
 
-#define A_SDRC_DLLA_CTRL_V	IO_ADDRESS(OMAP2_SDRC_BASE + 0x60)
-#define	A_SDRC_POWER_V		IO_ADDRESS(OMAP2_SDRC_BASE + 0x70)
-#define A_SDRC_RFR_CTRL_V	IO_ADDRESS(OMAP2_SDRC_BASE + 0xA4)
+/* First address of reserved address space?  apparently valid for OMAP2 & 3 */
 #define A_SDRC0_V		(0xC0000000)
-#define A_SDRC_MANUAL_V		IO_ADDRESS(OMAP2_SDRC_BASE + 0xA8)
 
 	.text
 
@@ -88,7 +86,7 @@
 	mcr	p15, 0, r3, c7, c10, 4	@ memory barrier, hope SDR/DDR finished
 	nop
 	nop
-	ldr	r3, A_SDRC_POWER	@ addr of sdrc power
+	ldr	r3, omap2_ocs_sdrc_power	@ addr of sdrc power
 	ldr	r4, [r3]		@ value of sdrc power
 	orr	r4, r4, #0x40		@ enable self refresh on idle req
 	mov	r5, #0x2000		@ set delay (DPLL relock + DLL relock)
@@ -108,7 +106,7 @@
 	ldr	r4, [r4]
 	nop				@ start auto refresh only after clk ok
 	movs	r0, r0			@ see if DDR or SDR
-	ldrne	r1, A_SDRC_DLLA_CTRL_S	@ get addr of DLL ctrl
+	ldrne	r1, omap2_ocs_sdrc_dlla_ctrl	@ get addr of DLL ctrl
 	strne	r0, [r1]		@ rewrite DLLA to force DLL reload
 	addne	r1, r1, #0x8		@ move to DLLB
 	strne	r0, [r1]		@ rewrite DLLB to force DLL reload
@@ -120,12 +118,15 @@
 	/* resume*/
 	ldmfd	sp!, {r0 - r12, pc}	@ restore regs and return
 
-A_SDRC_POWER:
-	.word A_SDRC_POWER_V
+	.globl	omap2_ocs_sdrc_power
+	.globl	omap2_ocs_sdrc_dlla_ctrl
+
+omap2_ocs_sdrc_power:
+	.word SRAM_VA_MAGIC
 A_SDRC0:
 	.word A_SDRC0_V
-A_SDRC_DLLA_CTRL_S:
-	.word A_SDRC_DLLA_CTRL_V
+omap2_ocs_sdrc_dlla_ctrl:
+	.word SRAM_VA_MAGIC
 
 ENTRY(omap24xx_cpu_suspend_sz)
 	.word	. - omap24xx_cpu_suspend

-- 

[PATCH 3/5] SRAM patcher: convert sram_ddr_init to use runtime SRAM patcher

[Paul Walmsley]

[-- Attachment #1: sp-patch-sram-ddr-init.patch --]
[-- Type: text/plain, Size: 4819 bytes --]

Use the runtime SRAM patcher to set register addresses in
sram_ddr_init.  The long symbol names are intended to help
disambiguate the symbols, now that they are global.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/sram-fn.S |   30 ++++++++++++++++++------------
 arch/arm/plat-omap/sram.c     |   26 ++++++++++++++++++++++++++
 2 files changed, 44 insertions(+), 12 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/sram-fn.S
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/sram-fn.S	2007-11-14 00:34:56.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/sram-fn.S	2007-11-14 00:37:08.000000000 -0700
@@ -26,6 +26,7 @@
 #include <asm/assembler.h>
 #include <asm/arch/io.h>
 #include <asm/hardware.h>
+#include <linux/poison.h>
 
 #define TIMER_32KSYNCT_CR_V	IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
 
@@ -48,7 +49,7 @@
 	mov	r8, r3			@ capture force parameter
 
 	/* frequency shift down */
-	ldr	r2, cm_clksel2_pll	@ get address of dpllout reg
+	ldr	r2, omap2_sdi_cm_clksel2_pll	@ get address of dpllout reg
 	mov	r3, #0x1		@ value for 1x operation
 	str	r3, [r2]		@ go to L1-freq operation
 
@@ -57,7 +58,7 @@
 	bl voltage_shift		@ go drop voltage
 
 	/* dll lock mode */
-	ldr	r11, sdrc_dlla_ctrl	@ addr of dlla ctrl
+	ldr	r11, omap2_sdi_sdrc_dlla_ctrl	@ addr of dlla ctrl
 	ldr	r10, [r11]		@ get current val
 	cmp	r12, #0x1		@ cs1 base (2422 es2.05/1)
 	addeq	r11, r11, #0x8		@ if cs1 base, move to DLLB
@@ -108,7 +109,7 @@
 	 * wait for it to finish, use 32k sync counter, 1tick=31uS.
 	 */
 voltage_shift:
-	ldr	r4, prcm_voltctrl	@ get addr of volt ctrl.
+	ldr	r4, omap2_sdi_prcm_voltctrl	@ get addr of volt ctrl.
 	ldr	r5, [r4]		@ get value.
 	ldr	r6, prcm_mask_val	@ get value of mask
 	and	r5, r5, r6		@ apply mask to clear bits
@@ -118,7 +119,7 @@
 	orr	r5, r5, r3		@ build value for force
 	str	r5, [r4]		@ Force transition to L1
 
-	ldr	r3, timer_32ksynct_cr	@ get addr of counter
+	ldr	r3, omap2_sdi_timer_32ksynct_cr	@ get addr of counter
 	ldr	r5, [r3]		@ get value
 	add	r5, r5, #0x3		@ give it at most 93uS
 volt_delay:
@@ -128,16 +129,21 @@
 	mov	pc, lr			@ back to caller.
 
 /* relative load constants */
-cm_clksel2_pll:
-	.word CM_CLKSEL2_PLL_V
-sdrc_dlla_ctrl:
-	.word SDRC_DLLA_CTRL_V
-prcm_voltctrl:
-	.word PRCM_VOLTCTRL_V
+	.globl omap2_sdi_cm_clksel2_pll
+	.globl omap2_sdi_sdrc_dlla_ctrl
+	.globl omap2_sdi_prcm_voltctrl
+	.globl omap2_sdi_timer_32ksynct_cr
+
+omap2_sdi_cm_clksel2_pll:
+	.word SRAM_VA_MAGIC
+omap2_sdi_sdrc_dlla_ctrl:
+	.word SRAM_VA_MAGIC
+omap2_sdi_prcm_voltctrl:
+	.word SRAM_VA_MAGIC
 prcm_mask_val:
 	.word 0xFFFF3FFC
-timer_32ksynct_cr:
-	.word TIMER_32KSYNCT_CR_V
+omap2_sdi_timer_32ksynct_cr:
+	.word SRAM_VA_MAGIC
 ENTRY(sram_ddr_init_sz)
 	.word	. - sram_ddr_init
 
Index: linux-omap/arch/arm/plat-omap/sram.c
===================================================================
--- linux-omap.orig/arch/arm/plat-omap/sram.c	2007-11-14 00:34:56.000000000 -0700
+++ linux-omap/arch/arm/plat-omap/sram.c	2007-11-14 00:37:26.000000000 -0700
@@ -25,6 +25,12 @@
 #include <asm/arch/sram.h>
 #include <asm/arch/board.h>
 
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+# include "../mach-omap2/prm.h"
+# include "../mach-omap2/cm.h"
+# include "../mach-omap2/sdrc.h"
+#endif
+
 #define OMAP1_SRAM_PA		0x20000000
 #define OMAP1_SRAM_VA		0xd0000000
 #define OMAP2_SRAM_PA		0x40200000
@@ -58,6 +64,13 @@
 					 unsigned long pstart_avail,
 					 unsigned long size_avail);
 
+/* Global symbols in sram-fn.S to be patched with omap_sram_patch_va() */
+extern void *omap2_sdi_cm_clksel2_pll;
+extern void *omap2_sdi_sdrc_dlla_ctrl;
+extern void *omap2_sdi_prcm_voltctrl;
+extern void *omap2_sdi_timer_32ksynct_cr;
+
+
 /*
  * Depending on the target RAMFS firewall setup, the public usable amount of
  * SRAM varies.  The default accessible size for all device types is 2k. A GP
@@ -325,6 +338,19 @@
 {
 	_omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz);
 
+	/* Patch in the correct register addresses for multiboot */
+	omap_sram_patch_va(sram_ddr_init, &omap2_sdi_cm_clksel2_pll,
+			   _omap2_sram_ddr_init,
+			   OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2));
+	omap_sram_patch_va(sram_ddr_init, &omap2_sdi_sdrc_dlla_ctrl,
+			   _omap2_sram_ddr_init,
+			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
+	omap_sram_patch_va(sram_ddr_init, &omap2_sdi_prcm_voltctrl,
+			   _omap2_sram_ddr_init, OMAP24XX_PRCM_VOLTCTRL);
+	omap_sram_patch_va(sram_ddr_init, &omap2_sdi_timer_32ksynct_cr,
+			   _omap2_sram_ddr_init,
+			   (void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010));
+
 	_omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
 						    sram_reprogram_sdrc_sz);
 	_omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);

-- 

[PATCH 4/5] SRAM patcher: convert sram_reprogram_sdrc to use runtime SRAM patcher

[Paul Walmsley]

[-- Attachment #1: sp-patch-sram-reprogram-sdrc.patch --]
[-- Type: text/plain, Size: 5778 bytes --]

Use the runtime SRAM patcher to set register addresses in
sram_reprogram_sdrc.  The long symbol names are intended to help
disambiguate the symbols, now that they are global.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/sdrc.h    |    2 +-
 arch/arm/mach-omap2/sram-fn.S |   40 +++++++++++++++++++++-------------------
 arch/arm/plat-omap/sram.c     |   22 ++++++++++++++++++++++
 3 files changed, 44 insertions(+), 20 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/sram-fn.S
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/sram-fn.S	2007-11-14 00:37:08.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/sram-fn.S	2007-11-14 00:41:21.000000000 -0700
@@ -28,10 +28,6 @@
 #include <asm/hardware.h>
 #include <linux/poison.h>
 
-#define TIMER_32KSYNCT_CR_V	IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
-
-#define CM_CLKSEL2_PLL_V	IO_ADDRESS(OMAP2_CM_BASE + 0x544)
-#define PRCM_VOLTCTRL_V		IO_ADDRESS(OMAP2_PRM_BASE + 0x050)
 #define PRCM_CLKCFG_CTRL_V	IO_ADDRESS(OMAP2_PRM_BASE + 0x080)
 #define CM_CLKEN_PLL_V		IO_ADDRESS(OMAP2_CM_BASE + 0x500)
 #define CM_IDLEST_CKGEN_V	IO_ADDRESS(OMAP2_CM_BASE + 0x520)
@@ -158,7 +154,7 @@
 	mcr	p15, 0, r3, c7, c10, 4	@ memory barrier, finish ARM SDR/DDR
 	nop
 	nop
-	ldr	r6, ddr_sdrc_rfr_ctrl	@ get addr of refresh reg
+	ldr	r6, omap2_srs_sdrc_rfr_ctrl	@ get addr of refresh reg
 	ldr	r5, [r6]		@ get value
 	mov	r5, r5, lsr #8		@ isolate rfr field and drop burst
 
@@ -172,7 +168,7 @@
 	movne	r5, r5, lsl #1		@ mult by 2 if to full
 	mov	r5, r5, lsl #8		@ put rfr field back into place
 	add	r5, r5, #0x1		@ turn on burst of 1
-	ldr	r4, ddr_cm_clksel2_pll	@ get address of out reg
+	ldr	r4, omap2_srs_cm_clksel2_pll	@ get address of out reg
 	ldr	r3, [r4]		@ get curr value
 	orr	r3, r3, #0x3
 	bic	r3, r3, #0x3		@ clear lower bits
@@ -193,7 +189,7 @@
 	bne	freq_out		@ leave if SDR, no DLL function
 
 	/* With DDR, we need to take care of the DLL for the frequency change */
-	ldr	r2, ddr_sdrc_dlla_ctrl	@ addr of dlla ctrl
+	ldr	r2, omap2_srs_sdrc_dlla_ctrl	@ addr of dlla ctrl
 	str	r1, [r2]		@ write out new SDRC_DLLA_CTRL
 	add	r2, r2, #0x8		@ addr to SDRC_DLLB_CTRL
 	str	r1, [r2]		@ commit to SDRC_DLLB_CTRL
@@ -209,7 +205,7 @@
      *	wait for it to finish, use 32k sync counter, 1tick=31uS.
      */
 voltage_shift_c:
-	ldr	r10, ddr_prcm_voltctrl	@ get addr of volt ctrl
+	ldr	r10, omap2_srs_prcm_voltctrl	@ get addr of volt ctrl
 	ldr	r8, [r10]		@ get value
 	ldr	r7, ddr_prcm_mask_val	@ get value of mask
 	and	r8, r8, r7		@ apply mask to clear bits
@@ -219,7 +215,7 @@
 	orr	r8, r8, r7		@ build value for force
 	str	r8, [r10]		@ Force transition to L1
 
-	ldr	r10, ddr_timer_32ksynct	@ get addr of counter
+	ldr	r10, omap2_srs_timer_32ksynct	@ get addr of counter
 	ldr	r8, [r10]		@ get value
 	add	r8, r8, #0x2		@ give it at most 62uS (min 31+)
 volt_delay_c:
@@ -228,18 +224,24 @@
 	bhi	volt_delay_c		@ not yet->branch
 	mov	pc, lr			@ back to caller
 
-ddr_cm_clksel2_pll:
-	.word CM_CLKSEL2_PLL_V
-ddr_sdrc_dlla_ctrl:
-	.word SDRC_DLLA_CTRL_V
-ddr_sdrc_rfr_ctrl:
-	.word SDRC_RFR_CTRL_V
-ddr_prcm_voltctrl:
-	.word PRCM_VOLTCTRL_V
+	.globl omap2_srs_cm_clksel2_pll
+	.globl omap2_srs_sdrc_dlla_ctrl
+	.globl omap2_srs_sdrc_rfr_ctrl
+	.globl omap2_srs_prcm_voltctrl
+	.globl omap2_srs_timer_32ksynct
+
+omap2_srs_cm_clksel2_pll:
+	.word SRAM_VA_MAGIC
+omap2_srs_sdrc_dlla_ctrl:
+	.word SRAM_VA_MAGIC
+omap2_srs_sdrc_rfr_ctrl:
+	.word SRAM_VA_MAGIC
+omap2_srs_prcm_voltctrl:
+	.word SRAM_VA_MAGIC
 ddr_prcm_mask_val:
 	.word 0xFFFF3FFC
-ddr_timer_32ksynct:
-	.word TIMER_32KSYNCT_CR_V
+omap2_srs_timer_32ksynct:
+	.word SRAM_VA_MAGIC
 
 ENTRY(sram_reprogram_sdrc_sz)
 	.word	. - sram_reprogram_sdrc
Index: linux-omap/arch/arm/plat-omap/sram.c
===================================================================
--- linux-omap.orig/arch/arm/plat-omap/sram.c	2007-11-14 00:37:26.000000000 -0700
+++ linux-omap/arch/arm/plat-omap/sram.c	2007-11-14 00:41:42.000000000 -0700
@@ -69,6 +69,11 @@
 extern void *omap2_sdi_sdrc_dlla_ctrl;
 extern void *omap2_sdi_prcm_voltctrl;
 extern void *omap2_sdi_timer_32ksynct_cr;
+extern void *omap2_srs_cm_clksel2_pll;
+extern void *omap2_srs_sdrc_dlla_ctrl;
+extern void *omap2_srs_sdrc_rfr_ctrl;
+extern void *omap2_srs_prcm_voltctrl;
+extern void *omap2_srs_timer_32ksynct;
 
 
 /*
@@ -353,6 +358,23 @@
 
 	_omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
 						    sram_reprogram_sdrc_sz);
+
+	omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_cm_clksel2_pll,
+			   _omap2_sram_reprogram_sdrc,
+			   OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2));
+	omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_sdrc_dlla_ctrl,
+			   _omap2_sram_reprogram_sdrc,
+			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
+	omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_sdrc_rfr_ctrl,
+			   _omap2_sram_reprogram_sdrc,
+			   OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0));
+	omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_prcm_voltctrl,
+			   _omap2_sram_reprogram_sdrc,
+			   OMAP24XX_PRCM_VOLTCTRL);
+	omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_timer_32ksynct,
+			   _omap2_sram_reprogram_sdrc,
+			   (void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010));
+
 	_omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
 
 	return 0;
Index: linux-omap/arch/arm/mach-omap2/sdrc.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/sdrc.h	2007-11-14 00:26:05.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/sdrc.h	2007-11-14 00:37:34.000000000 -0700
@@ -29,7 +29,7 @@
 #define SDRC_DLLB_STATUS	0x06C
 #define SDRC_POWER		0x070
 #define SDRC_MR_0		0x084
-
+#define SDRC_RFR_CTRL_0		0x0a4
 
 /* SDRC global register get/set */
 

-- 

[PATCH 5/5] SRAM patcher: convert omap2_set_prcm to use runtime SRAM patcher

[Paul Walmsley]

[-- Attachment #1: sp-patch-omap2-set-prcm.patch --]
[-- Type: text/plain, Size: 5120 bytes --]

Use the runtime SRAM patcher to set register addresses in
omap2_set_prcm.  The long symbol names are intended to help
disambiguate the symbols, now that they are global.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/mach-omap2/sram-fn.S |   55 ++++++++++++++++++++----------------------
 arch/arm/plat-omap/sram.c     |   26 +++++++++++++++++++
 2 files changed, 53 insertions(+), 28 deletions(-)

Index: linux-omap/arch/arm/mach-omap2/sram-fn.S
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/sram-fn.S	2007-11-14 00:41:21.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/sram-fn.S	2007-11-14 00:41:46.000000000 -0700
@@ -28,14 +28,6 @@
 #include <asm/hardware.h>
 #include <linux/poison.h>
 
-#define PRCM_CLKCFG_CTRL_V	IO_ADDRESS(OMAP2_PRM_BASE + 0x080)
-#define CM_CLKEN_PLL_V		IO_ADDRESS(OMAP2_CM_BASE + 0x500)
-#define CM_IDLEST_CKGEN_V	IO_ADDRESS(OMAP2_CM_BASE + 0x520)
-#define CM_CLKSEL1_PLL_V	IO_ADDRESS(OMAP2_CM_BASE + 0x540)
-
-#define SDRC_DLLA_CTRL_V	IO_ADDRESS(OMAP2_SDRC_BASE + 0x060)
-#define SDRC_RFR_CTRL_V		IO_ADDRESS(OMAP2_SDRC_BASE + 0x0a4)
-
 	.text
 
 ENTRY(sram_ddr_init)
@@ -256,13 +248,13 @@
 	mcrr	p15, 1, r8, r4, c12	@ preload into icache
 pbegin:
 	/* move into fast relock bypass */
-	ldr	r8, pll_ctl		@ get addr
+	ldr	r8, omap2_ssp_pll_ctl	@ get addr
 	ldr	r5, [r8]		@ get val
 	mvn	r6, #0x3		@ clear mask
 	and	r5, r5, r6		@ clear field
 	orr	r7, r5, #0x2		@ fast relock val
 	str	r7, [r8]		@ go to fast relock
-	ldr	r4, pll_stat		@ addr of stat
+	ldr	r4, omap2_ssp_pll_stat	@ addr of stat
 block:
 	/* wait for bypass */
 	ldr	r8, [r4]		@ stat value
@@ -271,10 +263,10 @@
 	bne	block			@ loop if not
 
 	/* set new dpll dividers _after_ in bypass */
-	ldr	r4, pll_div		@ get addr
+	ldr	r4, omap2_ssp_pll_div	@ get addr
 	str	r0, [r4]		@ set dpll ctrl val
 
-	ldr	r4, set_config		@ get addr
+	ldr	r4, omap2_ssp_set_config	@ get addr
 	mov	r8, #1			@ valid cfg msk
 	str	r8, [r4]		@ make dividers take
 
@@ -288,8 +280,8 @@
 	beq	pend			@ jump over dpll relock
 
 	/* relock DPLL with new vals */
-	ldr	r5, pll_stat		@ get addr
-	ldr	r4, pll_ctl		@ get addr
+	ldr	r5, omap2_ssp_pll_stat	@ get addr
+	ldr	r4, omap2_ssp_pll_ctl	@ get addr
 	orr	r8, r7, #0x3		@ val for lock dpll
 	str	r8, [r4]		@ set val
 	mov	r0, #1000		@ dead spin a bit
@@ -303,9 +295,9 @@
 	bne	wait_lock		@ wait if not
 pend:
 	/* update memory timings & briefly lock dll */
-	ldr	r4, sdrc_rfr		@ get addr
+	ldr	r4, omap2_ssp_sdrc_rfr	@ get addr
 	str	r1, [r4]		@ update refresh timing
-	ldr	r11, dlla_ctrl		@ get addr of DLLA ctrl
+	ldr	r11, omap2_ssp_dlla_ctrl	@ get addr of DLLA ctrl
 	ldr	r10, [r11]		@ get current val
 	mvn	r9, #0x4		@ mask to get clear bit2
 	and	r10, r10, r9		@ clear bit2 for lock mode
@@ -321,18 +313,25 @@
 	nop
 	ldmfd	sp!, {r0-r12, pc}	@ restore regs and return
 
-set_config:
-	.word PRCM_CLKCFG_CTRL_V
-pll_ctl:
-	.word CM_CLKEN_PLL_V
-pll_stat:
-	.word CM_IDLEST_CKGEN_V
-pll_div:
-	.word CM_CLKSEL1_PLL_V
-sdrc_rfr:
-	.word SDRC_RFR_CTRL_V
-dlla_ctrl:
-	.word SDRC_DLLA_CTRL_V
+	.globl omap2_ssp_set_config
+	.globl omap2_ssp_pll_ctl
+	.globl omap2_ssp_pll_stat
+	.globl omap2_ssp_pll_div
+	.globl omap2_ssp_sdrc_rfr
+	.globl omap2_ssp_dlla_ctrl
+
+omap2_ssp_set_config:
+	.word SRAM_VA_MAGIC
+omap2_ssp_pll_ctl:
+	.word SRAM_VA_MAGIC
+omap2_ssp_pll_stat:
+	.word SRAM_VA_MAGIC
+omap2_ssp_pll_div:
+	.word SRAM_VA_MAGIC
+omap2_ssp_sdrc_rfr:
+	.word SRAM_VA_MAGIC
+omap2_ssp_dlla_ctrl:
+	.word SRAM_VA_MAGIC
 
 ENTRY(sram_set_prcm_sz)
 	.word	. - sram_set_prcm
Index: linux-omap/arch/arm/plat-omap/sram.c
===================================================================
--- linux-omap.orig/arch/arm/plat-omap/sram.c	2007-11-14 00:41:42.000000000 -0700
+++ linux-omap/arch/arm/plat-omap/sram.c	2007-11-14 00:42:20.000000000 -0700
@@ -74,6 +74,12 @@
 extern void *omap2_srs_sdrc_rfr_ctrl;
 extern void *omap2_srs_prcm_voltctrl;
 extern void *omap2_srs_timer_32ksynct;
+extern void *omap2_ssp_set_config;
+extern void *omap2_ssp_pll_ctl;
+extern void *omap2_ssp_pll_stat;
+extern void *omap2_ssp_pll_div;
+extern void *omap2_ssp_sdrc_rfr;
+extern void *omap2_ssp_dlla_ctrl;
 
 
 /*
@@ -377,6 +383,26 @@
 
 	_omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
 
+	/* REVISIT: prefix all these symbols with omap2_sram_ */
+	omap_sram_patch_va(sram_set_prcm, &omap2_ssp_set_config,
+			   _omap2_set_prcm,
+			   OMAP24XX_PRCM_CLKCFG_CTRL);
+	omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_ctl,
+			   _omap2_set_prcm,
+			   OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN));
+	omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_stat,
+			   _omap2_set_prcm,
+			   OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST));
+	omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_div,
+			   _omap2_set_prcm,
+			   OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1));
+	omap_sram_patch_va(sram_set_prcm, &omap2_ssp_sdrc_rfr,
+			   _omap2_set_prcm,
+			   OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0));
+	omap_sram_patch_va(sram_set_prcm, &omap2_ssp_dlla_ctrl,
+			   _omap2_set_prcm,
+			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
+
 	return 0;
 }
 #else

-- 

Re: [PATCH 0/5] SRAM patcher: patch register addresses in SRAM code at runtime

[Kevin Hilman]

On Wed, 2007-11-14 at 01:30 -0700, Paul Walmsley wrote:
> Several SRAM-based assembly-language routines in the Linux OMAP kernel
> use hardcoded virtual addresses to access system registers.  These
> addresses were defined at compile-time by the preprocessor, since the
> same registers often appeared at different virtual addresses
> depending upon the target OMAP architecture.  Hardcoding the addresses
> is efficient and convenient to implement; but precludes a single kernel
> binary image from supporting multiple OMAP architectures.
> 
> This patches implement a different approach.  They patch in the
> correct register addresses at runtime into the SRAM, just after the
> code is copied there.  While the current code simply writes in the
> preprocessor-defined address bases, a forthcoming patch series uses
> this code to write runtime-computed address bases.
> 
> The code that does the patching is quite paranoid by default, and will
> refuse to overwrite any address that does not contain a magic number,
> SRAM_VA_MAGIC.  It also contains debugging printks which can be
> activated by defining the DEBUG symbol in sram.c and compiling with
> CONFIG_DEBUG_LL enabled.
> 
> Boot-tested on N800 and 3430SDP.  If someone out there with a 2430SDP
> can give these a whirl, that would be appreciated.  Comments welcome,

Looks good for 2430DSP.

I tested suspend, and sleep-when-idle (both of which can hit full
retention BTW.)

Kevin

RE: [PATCH 0/5] SRAM patcher: patch register addresses in SRAM code atruntime

[Woodruff, Richard]

Hi Paul,

> This patches implement a different approach.  They patch in the
> correct register addresses at runtime into the SRAM, just after the
> code is copied there.  While the current code simply writes in the
> preprocessor-defined address bases, a forthcoming patch series uses
> this code to write runtime-computed address bases.

- Well that does look fine.  It kind of feels like a gratuitous cache range flush should be added.  But as its all data side patches it probably can live with out it.  The initial code copy should probably have this.  Caches are VIPT, which means you almost don't have to flush, but you still do, but it can be in a more optimal way at run time.

-*- This code as written today likely won't be used on OMAP3 anyway as the DVFS procedure will be different.  The SRAM code usage can be much smaller and should also be different.

- The OMAP2420 DVFS requirements are much more restrictive than the OMAP3 ones.  In OMAP3 the SDRC_ICLK method should be used for the final VDD2 OPP change bits.  Using an OMAP2420 method on OMAP3 will result in you not being about to scale during audio play back.  The latency is too high and you will under run your mcbsp FIFO during the pause.  I think N800 today is not affected here today based on some of the DSP side effects which require it to be running faster than needed.  Other code bases don't have these restrictions and the 3430 one shouldn't either.  If you are playing audio you only need to be at the low OPP.  Something else can happen and require a speed up while the audio is playing.  We shouldn't depend on being at the high OPP while audio is active.  To achieve this the low latency 3430 specific method should be used.  Later 2430's versions can today use a similar procedure as 3430.

The aim of making it single kernel for OMAP2 to OMAP3 in this case is just using the SRAM function for pushing the correct SRAM routine.

Regards,
Richard W.

RE: [PATCH 0/5] SRAM patcher: patch register addresses in SRAM code atruntime

[Paul Walmsley]

Hi Richard,

On Wed, 14 Nov 2007, Woodruff, Richard wrote:

> -*- This code as written today likely won't be used on OMAP3 anyway as 
> the DVFS procedure will be different.  The SRAM code usage can be much 
> smaller and should also be different.
> The aim of making it single kernel for OMAP2 to OMAP3 in this case is 
> just using the SRAM function for pushing the correct SRAM routine.

Yeah, agreed.  The main motivation was to share 2420/2430 code here.  I'm 
hoping that there may be some 3430 sharing that can be done also, perhaps 
some of the SDRAM timing change code, but there's probably other code that 
won't be sharable without contortions.

> - Well that does look fine.  It kind of feels like a gratuitous cache 
> range flush should be added.  But as its all data side patches it 
> probably can live with out it.  The initial code copy should probably 
> have this.  Caches are VIPT, which means you almost don't have to flush, 
> but you still do, but it can be in a more optimal way at run time.

Want to do a patch for omap_sram_push()?  I suppose we're getting away 
without it now because nothing is running from SRAM before 
omap_sram_push(), and therefore isn't in I$?  sounds like it should be 
there, though.

Thanks for the review.

- Paul

RE: [PATCH 0/5] SRAM patcher: patch register addresses in SRAM code atruntime

[Woodruff, Richard]

Hi Paul,

> On Wed, 14 Nov 2007, Woodruff, Richard wrote:
> 
> > -*- This code as written today likely won't be used on OMAP3 anyway as
> > the DVFS procedure will be different.  The SRAM code usage can be much
> > smaller and should also be different.
> > The aim of making it single kernel for OMAP2 to OMAP3 in this case is
> > just using the SRAM function for pushing the correct SRAM routine.
> 
> Yeah, agreed.  The main motivation was to share 2420/2430 code here.  I'm
> hoping that there may be some 3430 sharing that can be done also, perhaps
> some of the SDRAM timing change code, but there's probably other code that
> won't be sharable without contortions.

Yes it would work here.  However, like I was hinting there is another method which 2430's which have been characterized, could try.  But that is something else.

> > - Well that does look fine.  It kind of feels like a gratuitous cache
> > range flush should be added.  But as its all data side patches it
> > probably can live with out it.  The initial code copy should probably
> > have this.  Caches are VIPT, which means you almost don't have to flush,
> > but you still do, but it can be in a more optimal way at run time.
> 
> Want to do a patch for omap_sram_push()?  I suppose we're getting away
> without it now because nothing is running from SRAM before
> omap_sram_push(), and therefore isn't in I$?  sounds like it should be
> there, though.

It probably needs to be there.  The reason for getting away is this is init time stuff not so dynamic, and VIPT means there is only a chance of a conflict.  On say an OMAP1 with a VIVT cache it would be a bigger possible problem.

I think in our older images it was non-cached also.  In current GIT its MT_MEMORY so it will be.

Its kind of low in things to do today but I might file it away to do.  Right now sram only has a push and no pop so its not so dynamic either.

Regards,
Richard W.

Re: [PATCH 0/5] SRAM patcher: patch register addresses in SRAM code atruntime

[Tony Lindgren]

* Woodruff, Richard <r-woodruff2@ti.com> [071116 11:48]:
> Hi Paul,
> 
> > On Wed, 14 Nov 2007, Woodruff, Richard wrote:
> > 
> > > -*- This code as written today likely won't be used on OMAP3 anyway as
> > > the DVFS procedure will be different.  The SRAM code usage can be much
> > > smaller and should also be different.
> > > The aim of making it single kernel for OMAP2 to OMAP3 in this case is
> > > just using the SRAM function for pushing the correct SRAM routine.
> > 
> > Yeah, agreed.  The main motivation was to share 2420/2430 code here.  I'm
> > hoping that there may be some 3430 sharing that can be done also, perhaps
> > some of the SDRAM timing change code, but there's probably other code that
> > won't be sharable without contortions.
> 
> Yes it would work here.  However, like I was hinting there is another method which 2430's which have been characterized, could try.  But that is something else.
> 
> > > - Well that does look fine.  It kind of feels like a gratuitous cache
> > > range flush should be added.  But as its all data side patches it
> > > probably can live with out it.  The initial code copy should probably
> > > have this.  Caches are VIPT, which means you almost don't have to flush,
> > > but you still do, but it can be in a more optimal way at run time.
> > 
> > Want to do a patch for omap_sram_push()?  I suppose we're getting away
> > without it now because nothing is running from SRAM before
> > omap_sram_push(), and therefore isn't in I$?  sounds like it should be
> > there, though.
> 
> It probably needs to be there.  The reason for getting away is this is init time stuff not so dynamic, and VIPT means there is only a chance of a conflict.  On say an OMAP1 with a VIVT cache it would be a bigger possible problem.
> 
> I think in our older images it was non-cached also.  In current GIT its MT_MEMORY so it will be.
> 
> Its kind of low in things to do today but I might file it away to do.  Right now sram only has a push and no pop so its not so dynamic either.

Yeah and we may want to start using SRAM dynamically too at some
point. Pushing Paul's patches today.

Tony

[PATCH] flush I-cache after omap_sram_push()

[Paul Walmsley]

On Fri, 16 Nov 2007, Woodruff, Richard wrote:

> It probably needs to be there.  The reason for getting away is this is 
> init time stuff not so dynamic, and VIPT means there is only a chance of 
> a conflict.  On say an OMAP1 with a VIVT cache it would be a bigger 
> possible problem.
> 
> I think in our older images it was non-cached also.  In current GIT its 
> MT_MEMORY so it will be.
> 
> Its kind of low in things to do today but I might file it away to do.  
> Right now sram only has a push and no pop so its not so dynamic either.

Hi Richard,

Figured we should do this now so we don't forget about it :-)  Patch below 
is boot-tested on N800.  Want to give it a quick look and add a 
Signed-off-by?


- Paul

This patch implements a suggestion by Richard Woodruff
<r-woodruff2@ti.com>.  omap_sram_push() copies executable code into
SRAM memory.  Currently this happens before Linux executes anything
from the SRAM, so we don't have to worry about evicting any SRAM lines
from the I-cache.  But at some point in the future, the SRAM might be
used more dynamically, adding and removing code while the system is
running.  So we should ensure that the I-cache is clean or at
least up-to-date after the copy.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

---
 arch/arm/plat-omap/sram.c |    1 +
 1 file changed, 1 insertion(+)

Index: linux-omap/arch/arm/plat-omap/sram.c
===================================================================
--- linux-omap.orig/arch/arm/plat-omap/sram.c	2007-11-16 17:41:42.000000000 -0700
+++ linux-omap/arch/arm/plat-omap/sram.c	2007-11-16 17:43:18.000000000 -0700
@@ -216,6 +216,7 @@
 	omap_sram_ceil -= size;
 	omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 	memcpy((void *)omap_sram_ceil, start, size);
+	flush_icache_range((unsigned long)start, (unsigned long)(start + size));
 
 	return (void *)omap_sram_ceil;
 }

RE: [PATCH] flush I-cache after omap_sram_push()

[Woodruff, Richard]

> This patch implements a suggestion by Richard Woodruff
> <r-woodruff2@ti.com>.  omap_sram_push() copies executable code into
> SRAM memory.  Currently this happens before Linux executes anything
> from the SRAM, so we don't have to worry about evicting any SRAM lines
> from the I-cache.  But at some point in the future, the SRAM might be
> used more dynamically, adding and removing code while the system is
> running.  So we should ensure that the I-cache is clean or at
> least up-to-date after the copy.
> 
> Signed-off-by: Paul Walmsley <paul@pwsan.com>

Signedoff-by: Richard Woodruff <r-woodruff2@ti.com>
 
> ---
>  arch/arm/plat-omap/sram.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> Index: linux-omap/arch/arm/plat-omap/sram.c
> ===================================================================
> --- linux-omap.orig/arch/arm/plat-omap/sram.c	2007-11-16
> 17:41:42.000000000 -0700
> +++ linux-omap/arch/arm/plat-omap/sram.c	2007-11-16 17:43:18.000000000 -
> 0700
> @@ -216,6 +216,7 @@
>  	omap_sram_ceil -= size;
>  	omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
>  	memcpy((void *)omap_sram_ceil, start, size);
> +	flush_icache_range((unsigned long)start, (unsigned long)(start +
> size));
> 
>  	return (void *)omap_sram_ceil;
>  }

Looks good.

Re: [PATCH] flush I-cache after omap_sram_push()

[Tony Lindgren]

* Woodruff, Richard <r-woodruff2@ti.com> [071120 08:16]:
> > This patch implements a suggestion by Richard Woodruff
> > <r-woodruff2@ti.com>.  omap_sram_push() copies executable code into
> > SRAM memory.  Currently this happens before Linux executes anything
> > from the SRAM, so we don't have to worry about evicting any SRAM lines
> > from the I-cache.  But at some point in the future, the SRAM might be
> > used more dynamically, adding and removing code while the system is
> > running.  So we should ensure that the I-cache is clean or at
> > least up-to-date after the copy.
> > 
> > Signed-off-by: Paul Walmsley <paul@pwsan.com>
> 
> Signedoff-by: Richard Woodruff <r-woodruff2@ti.com>
>  
> > ---
> >  arch/arm/plat-omap/sram.c |    1 +
> >  1 file changed, 1 insertion(+)
> > 
> > Index: linux-omap/arch/arm/plat-omap/sram.c
> > ===================================================================
> > --- linux-omap.orig/arch/arm/plat-omap/sram.c	2007-11-16
> > 17:41:42.000000000 -0700
> > +++ linux-omap/arch/arm/plat-omap/sram.c	2007-11-16 17:43:18.000000000 -
> > 0700
> > @@ -216,6 +216,7 @@
> >  	omap_sram_ceil -= size;
> >  	omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
> >  	memcpy((void *)omap_sram_ceil, start, size);
> > +	flush_icache_range((unsigned long)start, (unsigned long)(start +
> > size));
> > 
> >  	return (void *)omap_sram_ceil;
> >  }
> 
> Looks good.

Pushing today.

Tony