* [PATCH 0/10] Rearranging things before sending patches to mainline
@ 2008-03-12 10:45 Tony Lindgren
2008-03-12 10:45 ` [PATCH 1/10] ARM: OMAP2: Fix _REGADDR macro offset calculations and cm.h for assembly Tony Lindgren
2008-03-13 11:28 ` [PATCH 0/10] Rearranging things before sending patches to mainline Tony Lindgren
0 siblings, 2 replies; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
Hi all,
Attached series moves things around a bit to make room for 34xx PM,
renames some files to have consistent naming, and moves STI support
from plat-omap to drivers/misc.
This is all to allow us to get arch/arm/*omap* stuff in sync with
mainline. I'll be putting together a series of patches for Russell
over next few days for post 2.6.25.
Regards,
Tony
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/10] ARM: OMAP2: Fix _REGADDR macro offset calculations and cm.h for assembly
2008-03-12 10:45 [PATCH 0/10] Rearranging things before sending patches to mainline Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 2/10] ARM: OMAP2: Move sram-fn.S to sram24xx.S Tony Lindgren
2008-03-13 11:28 ` [PATCH 0/10] Rearranging things before sending patches to mainline Tony Lindgren
1 sibling, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
Make sure unexpected register offsets don't get calculated because of
(unlikely) macro parameter calculations. Also fix cm.h so it can be
included from assembly functions.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/cm.h | 21 +++++++++++++++------
arch/arm/mach-omap2/prm.h | 3 ++-
arch/arm/mach-omap2/sdrc.h | 16 ++++++++++------
include/asm-arm/arch-omap/sdrc.h | 4 ----
4 files changed, 27 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 53cacc9..1a8f289 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -14,12 +14,19 @@
* published by the Free Software Foundation.
*/
-#include <linux/kernel.h>
-#include <asm/io.h>
#include "prcm_common.h"
-
-#define OMAP_CM_REGADDR(module, reg) (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + module + reg)
+#ifndef __ASSEMBLER__
+#define OMAP_CM_REGADDR(module, reg) \
+ (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
+#else
+#define OMAP2420_CM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+#define OMAP34XX_CM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+#endif
/*
* Architecture-specific global CM registers
@@ -32,7 +39,7 @@
#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
-
+#ifndef __ASSEMBLER__
/* Clock management global register get/set */
static void __attribute__((unused)) cm_write_reg(u32 val, void __iomem *addr)
@@ -46,7 +53,7 @@ static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr)
{
return __raw_readl(addr);
}
-
+#endif
/*
* Module specific CM registers from CM_BASE + domain offset
@@ -86,6 +93,7 @@ static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr)
/* Clock management domain register get/set */
+#ifndef __ASSEMBLER__
static void __attribute__((unused)) cm_write_mod_reg(u32 val, s16 module, s16 idx)
{
cm_write_reg(val, OMAP_CM_REGADDR(module, idx));
@@ -95,6 +103,7 @@ static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx)
{
return cm_read_reg(OMAP_CM_REGADDR(module, idx));
}
+#endif
/* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index e090ab4..fd8c81d 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -19,7 +19,8 @@
#include "prcm_common.h"
-#define OMAP_PRM_REGADDR(module, reg) (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + module + reg)
+#define OMAP_PRM_REGADDR(module, reg) \
+ (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
/*
* Architecture-specific global PRM registers
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index dfc86f1..aa38621 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -15,15 +15,16 @@
*/
#undef DEBUG
-#include <linux/kernel.h>
#include <asm/arch/sdrc.h>
+#ifndef __ASSEMBLER__
extern unsigned long omap2_sdrc_base;
extern unsigned long omap2_sms_base;
-#define OMAP_SDRC_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_sdrc_base + reg)
-#define OMAP_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_sms_base + reg)
-
+#define OMAP_SDRC_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
+#define OMAP_SMS_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
/* SDRC global register get/set */
@@ -54,7 +55,10 @@ static u32 __attribute__((unused)) sms_read_reg(u16 reg)
{
return __raw_readl(OMAP_SMS_REGADDR(reg));
}
-
-
+#else
+#define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP242X_SDRC_BASE + (reg))
+#define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
+#define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+#endif /* __ASSEMBLER__ */
#endif
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
index 8f74097..673b396 100644
--- a/include/asm-arm/arch-omap/sdrc.h
+++ b/include/asm-arm/arch-omap/sdrc.h
@@ -16,10 +16,6 @@
#include <asm/arch/io.h>
-#define OMAP242X_SDRC_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP242X_SDRC_BASE + reg)
-#define OMAP243X_SDRC_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SDRC_BASE + reg)
-#define OMAP343X_SDRC_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SDRC_BASE + reg)
-
/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
#define SDRC_SYSCONFIG 0x010
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/10] ARM: OMAP2: Move sram-fn.S to sram24xx.S
2008-03-12 10:45 ` [PATCH 1/10] ARM: OMAP2: Fix _REGADDR macro offset calculations and cm.h for assembly Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 3/10] ARM: OMAP2: Rename 24xx specific SRAM functions Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
This is to make room for sram34xx.S
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/Makefile | 5 +-
arch/arm/mach-omap2/sram-fn.S | 337 ----------------------------------------
arch/arm/mach-omap2/sram24xx.S | 337 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 341 insertions(+), 338 deletions(-)
delete mode 100644 arch/arm/mach-omap2/sram-fn.S
create mode 100644 arch/arm/mach-omap2/sram24xx.S
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 842f9fb..5157ff2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,9 +3,12 @@
#
# Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
+obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
devices.o serial.o gpmc.o timer-gp.o
+# Functions loaded to SRAM
+obj-$(CONFIG_ARCH_OMAP2) += sram24xx.o
+
# Power Management
obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
deleted file mode 100644
index ba1e005..0000000
--- a/arch/arm/mach-omap2/sram-fn.S
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/sram-fn.S
- *
- * Omap2 specific functions that need to be run in internal SRAM
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/arch/io.h>
-#include <asm/hardware.h>
-#include <linux/poison.h>
-
- .text
-
-ENTRY(sram_ddr_init)
- stmfd sp!, {r0 - r12, lr} @ save registers on stack
-
- mov r12, r2 @ capture CS1 vs CS0
- mov r8, r3 @ capture force parameter
-
- /* frequency shift down */
- ldr r2, omap2_sdi_cm_clksel2_pll @ get address of dpllout reg
- mov r3, #0x1 @ value for 1x operation
- str r3, [r2] @ go to L1-freq operation
-
- /* voltage shift down */
- mov r9, #0x1 @ set up for L1 voltage call
- bl voltage_shift @ go drop voltage
-
- /* dll lock mode */
- ldr r11, omap2_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
- ldr r10, [r11] @ get current val
- cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
- addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode.
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
- str r10, [r11] @ commit to DLLA_CTRL
- bl i_dll_wait @ wait for dll to lock
-
- /* get dll value */
- add r11, r11, #0x4 @ get addr of status reg
- ldr r10, [r11] @ get locked value
-
- /* voltage shift up */
- mov r9, #0x0 @ shift back to L0-voltage
- bl voltage_shift @ go raise voltage
-
- /* frequency shift up */
- mov r3, #0x2 @ value for 2x operation
- str r3, [r2] @ go to L0-freq operation
-
- /* reset entry mode for dllctrl */
- sub r11, r11, #0x4 @ move from status to ctrl
- cmp r12, #0x1 @ normalize if cs1 based
- subeq r11, r11, #0x8 @ possibly back to DLLA
- cmp r8, #0x1 @ if forced unlock exit
- orreq r1, r1, #0x4 @ make sure exit with unlocked value
- str r1, [r11] @ restore DLLA_CTRL high value
- add r11, r11, #0x8 @ move to DLLB_CTRL addr
- str r1, [r11] @ set value DLLB_CTRL
- bl i_dll_wait @ wait for possible lock
-
- /* set up for return, DDR should be good */
- str r10, [r0] @ write dll_status and return counter
- ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-
- /* ensure the DLL has relocked */
-i_dll_wait:
- mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
-i_dll_delay:
- subs r4, r4, #0x1
- bne i_dll_delay
- mov pc, lr
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift:
- ldr r4, omap2_sdi_prcm_voltctrl @ get addr of volt ctrl.
- ldr r5, [r4] @ get value.
- ldr r6, prcm_mask_val @ get value of mask
- and r5, r5, r6 @ apply mask to clear bits
- orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
- str r5, [r4] @ set up for change.
- mov r3, #0x4000 @ get val for force
- orr r5, r5, r3 @ build value for force
- str r5, [r4] @ Force transition to L1
-
- ldr r3, omap2_sdi_timer_32ksynct_cr @ get addr of counter
- ldr r5, [r3] @ get value
- add r5, r5, #0x3 @ give it at most 93uS
-volt_delay:
- ldr r7, [r3] @ get timer value
- cmp r5, r7 @ time up?
- bhi volt_delay @ not yet->branch
- mov pc, lr @ back to caller.
-
-/* relative load constants */
- .globl omap2_sdi_cm_clksel2_pll
- .globl omap2_sdi_sdrc_dlla_ctrl
- .globl omap2_sdi_prcm_voltctrl
- .globl omap2_sdi_timer_32ksynct_cr
-
-omap2_sdi_cm_clksel2_pll:
- .word SRAM_VA_MAGIC
-omap2_sdi_sdrc_dlla_ctrl:
- .word SRAM_VA_MAGIC
-omap2_sdi_prcm_voltctrl:
- .word SRAM_VA_MAGIC
-prcm_mask_val:
- .word 0xFFFF3FFC
-omap2_sdi_timer_32ksynct_cr:
- .word SRAM_VA_MAGIC
-ENTRY(sram_ddr_init_sz)
- .word . - sram_ddr_init
-
-/*
- * Reprograms memory timings.
- * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
- * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
- */
-ENTRY(sram_reprogram_sdrc)
- stmfd sp!, {r0 - r10, lr} @ save registers on stack
- mov r3, #0x0 @ clear for mrc call
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
- nop
- nop
- ldr r6, omap2_srs_sdrc_rfr_ctrl @ get addr of refresh reg
- ldr r5, [r6] @ get value
- mov r5, r5, lsr #8 @ isolate rfr field and drop burst
-
- cmp r0, #0x1 @ going to half speed?
- movne r9, #0x0 @ if up set flag up for pre up, hi volt
-
- blne voltage_shift_c @ adjust voltage
-
- cmp r0, #0x1 @ going to half speed (post branch link)
- moveq r5, r5, lsr #1 @ divide by 2 if to half
- movne r5, r5, lsl #1 @ mult by 2 if to full
- mov r5, r5, lsl #8 @ put rfr field back into place
- add r5, r5, #0x1 @ turn on burst of 1
- ldr r4, omap2_srs_cm_clksel2_pll @ get address of out reg
- ldr r3, [r4] @ get curr value
- orr r3, r3, #0x3
- bic r3, r3, #0x3 @ clear lower bits
- orr r3, r3, r0 @ new state value
- str r3, [r4] @ set new state (pll/x, x=1 or 2)
- nop
- nop
-
- moveq r9, #0x1 @ if speed down, post down, drop volt
- bleq voltage_shift_c
-
- mcr p15, 0, r3, c7, c10, 4 @ memory barrier
- str r5, [r6] @ set new RFR_1 value
- add r6, r6, #0x30 @ get RFR_2 addr
- str r5, [r6] @ set RFR_2
- nop
- cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
- bne freq_out @ leave if SDR, no DLL function
-
- /* With DDR, we need to take care of the DLL for the frequency change */
- ldr r2, omap2_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
- str r1, [r2] @ write out new SDRC_DLLA_CTRL
- add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
- str r1, [r2] @ commit to SDRC_DLLB_CTRL
- mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
-dll_wait:
- subs r1, r1, #0x1
- bne dll_wait
-freq_out:
- ldmfd sp!, {r0 - r10, pc} @ restore regs and return
-
- /*
- * shift up or down voltage, use R9 as input to tell level.
- * wait for it to finish, use 32k sync counter, 1tick=31uS.
- */
-voltage_shift_c:
- ldr r10, omap2_srs_prcm_voltctrl @ get addr of volt ctrl
- ldr r8, [r10] @ get value
- ldr r7, ddr_prcm_mask_val @ get value of mask
- and r8, r8, r7 @ apply mask to clear bits
- orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
- str r8, [r10] @ set up for change.
- mov r7, #0x4000 @ get val for force
- orr r8, r8, r7 @ build value for force
- str r8, [r10] @ Force transition to L1
-
- ldr r10, omap2_srs_timer_32ksynct @ get addr of counter
- ldr r8, [r10] @ get value
- add r8, r8, #0x2 @ give it at most 62uS (min 31+)
-volt_delay_c:
- ldr r7, [r10] @ get timer value
- cmp r8, r7 @ time up?
- bhi volt_delay_c @ not yet->branch
- mov pc, lr @ back to caller
-
- .globl omap2_srs_cm_clksel2_pll
- .globl omap2_srs_sdrc_dlla_ctrl
- .globl omap2_srs_sdrc_rfr_ctrl
- .globl omap2_srs_prcm_voltctrl
- .globl omap2_srs_timer_32ksynct
-
-omap2_srs_cm_clksel2_pll:
- .word SRAM_VA_MAGIC
-omap2_srs_sdrc_dlla_ctrl:
- .word SRAM_VA_MAGIC
-omap2_srs_sdrc_rfr_ctrl:
- .word SRAM_VA_MAGIC
-omap2_srs_prcm_voltctrl:
- .word SRAM_VA_MAGIC
-ddr_prcm_mask_val:
- .word 0xFFFF3FFC
-omap2_srs_timer_32ksynct:
- .word SRAM_VA_MAGIC
-
-ENTRY(sram_reprogram_sdrc_sz)
- .word . - sram_reprogram_sdrc
-
-/*
- * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
- */
-ENTRY(sram_set_prcm)
- stmfd sp!, {r0-r12, lr} @ regs to stack
- adr r4, pbegin @ addr of preload start
- adr r8, pend @ addr of preload end
- mcrr p15, 1, r8, r4, c12 @ preload into icache
-pbegin:
- /* move into fast relock bypass */
- ldr r8, omap2_ssp_pll_ctl @ get addr
- ldr r5, [r8] @ get val
- mvn r6, #0x3 @ clear mask
- and r5, r5, r6 @ clear field
- orr r7, r5, #0x2 @ fast relock val
- str r7, [r8] @ go to fast relock
- ldr r4, omap2_ssp_pll_stat @ addr of stat
-block:
- /* wait for bypass */
- ldr r8, [r4] @ stat value
- and r8, r8, #0x3 @ mask for stat
- cmp r8, #0x1 @ there yet
- bne block @ loop if not
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, omap2_ssp_pll_div @ get addr
- str r0, [r4] @ set dpll ctrl val
-
- ldr r4, omap2_ssp_set_config @ get addr
- mov r8, #1 @ valid cfg msk
- str r8, [r4] @ make dividers take
-
- mov r4, #100 @ dead spin a bit
-wait_a_bit:
- subs r4, r4, #1 @ dec loop
- bne wait_a_bit @ delay done?
-
- /* check if staying in bypass */
- cmp r2, #0x1 @ stay in bypass?
- beq pend @ jump over dpll relock
-
- /* relock DPLL with new vals */
- ldr r5, omap2_ssp_pll_stat @ get addr
- ldr r4, omap2_ssp_pll_ctl @ get addr
- orr r8, r7, #0x3 @ val for lock dpll
- str r8, [r4] @ set val
- mov r0, #1000 @ dead spin a bit
-wait_more:
- subs r0, r0, #1 @ dec loop
- bne wait_more @ delay done?
-wait_lock:
- ldr r8, [r5] @ get lock val
- and r8, r8, #3 @ isolate field
- cmp r8, #2 @ locked?
- bne wait_lock @ wait if not
-pend:
- /* update memory timings & briefly lock dll */
- ldr r4, omap2_ssp_sdrc_rfr @ get addr
- str r1, [r4] @ update refresh timing
- ldr r11, omap2_ssp_dlla_ctrl @ get addr of DLLA ctrl
- ldr r10, [r11] @ get current val
- mvn r9, #0x4 @ mask to get clear bit2
- and r10, r10, r9 @ clear bit2 for lock mode
- orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
- str r10, [r11] @ commit to DLLA_CTRL
- add r11, r11, #0x8 @ move to dllb
- str r10, [r11] @ hit DLLB also
-
- mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
-wait_dll_lock:
- subs r4, r4, #0x1
- bne wait_dll_lock
- nop
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
-
- .globl omap2_ssp_set_config
- .globl omap2_ssp_pll_ctl
- .globl omap2_ssp_pll_stat
- .globl omap2_ssp_pll_div
- .globl omap2_ssp_sdrc_rfr
- .globl omap2_ssp_dlla_ctrl
-
-omap2_ssp_set_config:
- .word SRAM_VA_MAGIC
-omap2_ssp_pll_ctl:
- .word SRAM_VA_MAGIC
-omap2_ssp_pll_stat:
- .word SRAM_VA_MAGIC
-omap2_ssp_pll_div:
- .word SRAM_VA_MAGIC
-omap2_ssp_sdrc_rfr:
- .word SRAM_VA_MAGIC
-omap2_ssp_dlla_ctrl:
- .word SRAM_VA_MAGIC
-
-ENTRY(sram_set_prcm_sz)
- .word . - sram_set_prcm
diff --git a/arch/arm/mach-omap2/sram24xx.S b/arch/arm/mach-omap2/sram24xx.S
new file mode 100644
index 0000000..ba1e005
--- /dev/null
+++ b/arch/arm/mach-omap2/sram24xx.S
@@ -0,0 +1,337 @@
+/*
+ * linux/arch/arm/mach-omap2/sram-fn.S
+ *
+ * Omap2 specific functions that need to be run in internal SRAM
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/arch/io.h>
+#include <asm/hardware.h>
+#include <linux/poison.h>
+
+ .text
+
+ENTRY(sram_ddr_init)
+ stmfd sp!, {r0 - r12, lr} @ save registers on stack
+
+ mov r12, r2 @ capture CS1 vs CS0
+ mov r8, r3 @ capture force parameter
+
+ /* frequency shift down */
+ ldr r2, omap2_sdi_cm_clksel2_pll @ get address of dpllout reg
+ mov r3, #0x1 @ value for 1x operation
+ str r3, [r2] @ go to L1-freq operation
+
+ /* voltage shift down */
+ mov r9, #0x1 @ set up for L1 voltage call
+ bl voltage_shift @ go drop voltage
+
+ /* dll lock mode */
+ ldr r11, omap2_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
+ ldr r10, [r11] @ get current val
+ cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
+ addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
+ mvn r9, #0x4 @ mask to get clear bit2
+ and r10, r10, r9 @ clear bit2 for lock mode.
+ orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
+ orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
+ str r10, [r11] @ commit to DLLA_CTRL
+ bl i_dll_wait @ wait for dll to lock
+
+ /* get dll value */
+ add r11, r11, #0x4 @ get addr of status reg
+ ldr r10, [r11] @ get locked value
+
+ /* voltage shift up */
+ mov r9, #0x0 @ shift back to L0-voltage
+ bl voltage_shift @ go raise voltage
+
+ /* frequency shift up */
+ mov r3, #0x2 @ value for 2x operation
+ str r3, [r2] @ go to L0-freq operation
+
+ /* reset entry mode for dllctrl */
+ sub r11, r11, #0x4 @ move from status to ctrl
+ cmp r12, #0x1 @ normalize if cs1 based
+ subeq r11, r11, #0x8 @ possibly back to DLLA
+ cmp r8, #0x1 @ if forced unlock exit
+ orreq r1, r1, #0x4 @ make sure exit with unlocked value
+ str r1, [r11] @ restore DLLA_CTRL high value
+ add r11, r11, #0x8 @ move to DLLB_CTRL addr
+ str r1, [r11] @ set value DLLB_CTRL
+ bl i_dll_wait @ wait for possible lock
+
+ /* set up for return, DDR should be good */
+ str r10, [r0] @ write dll_status and return counter
+ ldmfd sp!, {r0 - r12, pc} @ restore regs and return
+
+ /* ensure the DLL has relocked */
+i_dll_wait:
+ mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
+i_dll_delay:
+ subs r4, r4, #0x1
+ bne i_dll_delay
+ mov pc, lr
+
+ /*
+ * shift up or down voltage, use R9 as input to tell level.
+ * wait for it to finish, use 32k sync counter, 1tick=31uS.
+ */
+voltage_shift:
+ ldr r4, omap2_sdi_prcm_voltctrl @ get addr of volt ctrl.
+ ldr r5, [r4] @ get value.
+ ldr r6, prcm_mask_val @ get value of mask
+ and r5, r5, r6 @ apply mask to clear bits
+ orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
+ str r5, [r4] @ set up for change.
+ mov r3, #0x4000 @ get val for force
+ orr r5, r5, r3 @ build value for force
+ str r5, [r4] @ Force transition to L1
+
+ ldr r3, omap2_sdi_timer_32ksynct_cr @ get addr of counter
+ ldr r5, [r3] @ get value
+ add r5, r5, #0x3 @ give it at most 93uS
+volt_delay:
+ ldr r7, [r3] @ get timer value
+ cmp r5, r7 @ time up?
+ bhi volt_delay @ not yet->branch
+ mov pc, lr @ back to caller.
+
+/* relative load constants */
+ .globl omap2_sdi_cm_clksel2_pll
+ .globl omap2_sdi_sdrc_dlla_ctrl
+ .globl omap2_sdi_prcm_voltctrl
+ .globl omap2_sdi_timer_32ksynct_cr
+
+omap2_sdi_cm_clksel2_pll:
+ .word SRAM_VA_MAGIC
+omap2_sdi_sdrc_dlla_ctrl:
+ .word SRAM_VA_MAGIC
+omap2_sdi_prcm_voltctrl:
+ .word SRAM_VA_MAGIC
+prcm_mask_val:
+ .word 0xFFFF3FFC
+omap2_sdi_timer_32ksynct_cr:
+ .word SRAM_VA_MAGIC
+ENTRY(sram_ddr_init_sz)
+ .word . - sram_ddr_init
+
+/*
+ * Reprograms memory timings.
+ * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
+ * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
+ */
+ENTRY(sram_reprogram_sdrc)
+ stmfd sp!, {r0 - r10, lr} @ save registers on stack
+ mov r3, #0x0 @ clear for mrc call
+ mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
+ nop
+ nop
+ ldr r6, omap2_srs_sdrc_rfr_ctrl @ get addr of refresh reg
+ ldr r5, [r6] @ get value
+ mov r5, r5, lsr #8 @ isolate rfr field and drop burst
+
+ cmp r0, #0x1 @ going to half speed?
+ movne r9, #0x0 @ if up set flag up for pre up, hi volt
+
+ blne voltage_shift_c @ adjust voltage
+
+ cmp r0, #0x1 @ going to half speed (post branch link)
+ moveq r5, r5, lsr #1 @ divide by 2 if to half
+ movne r5, r5, lsl #1 @ mult by 2 if to full
+ mov r5, r5, lsl #8 @ put rfr field back into place
+ add r5, r5, #0x1 @ turn on burst of 1
+ ldr r4, omap2_srs_cm_clksel2_pll @ get address of out reg
+ ldr r3, [r4] @ get curr value
+ orr r3, r3, #0x3
+ bic r3, r3, #0x3 @ clear lower bits
+ orr r3, r3, r0 @ new state value
+ str r3, [r4] @ set new state (pll/x, x=1 or 2)
+ nop
+ nop
+
+ moveq r9, #0x1 @ if speed down, post down, drop volt
+ bleq voltage_shift_c
+
+ mcr p15, 0, r3, c7, c10, 4 @ memory barrier
+ str r5, [r6] @ set new RFR_1 value
+ add r6, r6, #0x30 @ get RFR_2 addr
+ str r5, [r6] @ set RFR_2
+ nop
+ cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
+ bne freq_out @ leave if SDR, no DLL function
+
+ /* With DDR, we need to take care of the DLL for the frequency change */
+ ldr r2, omap2_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
+ str r1, [r2] @ write out new SDRC_DLLA_CTRL
+ add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
+ str r1, [r2] @ commit to SDRC_DLLB_CTRL
+ mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
+dll_wait:
+ subs r1, r1, #0x1
+ bne dll_wait
+freq_out:
+ ldmfd sp!, {r0 - r10, pc} @ restore regs and return
+
+ /*
+ * shift up or down voltage, use R9 as input to tell level.
+ * wait for it to finish, use 32k sync counter, 1tick=31uS.
+ */
+voltage_shift_c:
+ ldr r10, omap2_srs_prcm_voltctrl @ get addr of volt ctrl
+ ldr r8, [r10] @ get value
+ ldr r7, ddr_prcm_mask_val @ get value of mask
+ and r8, r8, r7 @ apply mask to clear bits
+ orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
+ str r8, [r10] @ set up for change.
+ mov r7, #0x4000 @ get val for force
+ orr r8, r8, r7 @ build value for force
+ str r8, [r10] @ Force transition to L1
+
+ ldr r10, omap2_srs_timer_32ksynct @ get addr of counter
+ ldr r8, [r10] @ get value
+ add r8, r8, #0x2 @ give it at most 62uS (min 31+)
+volt_delay_c:
+ ldr r7, [r10] @ get timer value
+ cmp r8, r7 @ time up?
+ bhi volt_delay_c @ not yet->branch
+ mov pc, lr @ back to caller
+
+ .globl omap2_srs_cm_clksel2_pll
+ .globl omap2_srs_sdrc_dlla_ctrl
+ .globl omap2_srs_sdrc_rfr_ctrl
+ .globl omap2_srs_prcm_voltctrl
+ .globl omap2_srs_timer_32ksynct
+
+omap2_srs_cm_clksel2_pll:
+ .word SRAM_VA_MAGIC
+omap2_srs_sdrc_dlla_ctrl:
+ .word SRAM_VA_MAGIC
+omap2_srs_sdrc_rfr_ctrl:
+ .word SRAM_VA_MAGIC
+omap2_srs_prcm_voltctrl:
+ .word SRAM_VA_MAGIC
+ddr_prcm_mask_val:
+ .word 0xFFFF3FFC
+omap2_srs_timer_32ksynct:
+ .word SRAM_VA_MAGIC
+
+ENTRY(sram_reprogram_sdrc_sz)
+ .word . - sram_reprogram_sdrc
+
+/*
+ * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
+ */
+ENTRY(sram_set_prcm)
+ stmfd sp!, {r0-r12, lr} @ regs to stack
+ adr r4, pbegin @ addr of preload start
+ adr r8, pend @ addr of preload end
+ mcrr p15, 1, r8, r4, c12 @ preload into icache
+pbegin:
+ /* move into fast relock bypass */
+ ldr r8, omap2_ssp_pll_ctl @ get addr
+ ldr r5, [r8] @ get val
+ mvn r6, #0x3 @ clear mask
+ and r5, r5, r6 @ clear field
+ orr r7, r5, #0x2 @ fast relock val
+ str r7, [r8] @ go to fast relock
+ ldr r4, omap2_ssp_pll_stat @ addr of stat
+block:
+ /* wait for bypass */
+ ldr r8, [r4] @ stat value
+ and r8, r8, #0x3 @ mask for stat
+ cmp r8, #0x1 @ there yet
+ bne block @ loop if not
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r4, omap2_ssp_pll_div @ get addr
+ str r0, [r4] @ set dpll ctrl val
+
+ ldr r4, omap2_ssp_set_config @ get addr
+ mov r8, #1 @ valid cfg msk
+ str r8, [r4] @ make dividers take
+
+ mov r4, #100 @ dead spin a bit
+wait_a_bit:
+ subs r4, r4, #1 @ dec loop
+ bne wait_a_bit @ delay done?
+
+ /* check if staying in bypass */
+ cmp r2, #0x1 @ stay in bypass?
+ beq pend @ jump over dpll relock
+
+ /* relock DPLL with new vals */
+ ldr r5, omap2_ssp_pll_stat @ get addr
+ ldr r4, omap2_ssp_pll_ctl @ get addr
+ orr r8, r7, #0x3 @ val for lock dpll
+ str r8, [r4] @ set val
+ mov r0, #1000 @ dead spin a bit
+wait_more:
+ subs r0, r0, #1 @ dec loop
+ bne wait_more @ delay done?
+wait_lock:
+ ldr r8, [r5] @ get lock val
+ and r8, r8, #3 @ isolate field
+ cmp r8, #2 @ locked?
+ bne wait_lock @ wait if not
+pend:
+ /* update memory timings & briefly lock dll */
+ ldr r4, omap2_ssp_sdrc_rfr @ get addr
+ str r1, [r4] @ update refresh timing
+ ldr r11, omap2_ssp_dlla_ctrl @ get addr of DLLA ctrl
+ ldr r10, [r11] @ get current val
+ mvn r9, #0x4 @ mask to get clear bit2
+ and r10, r10, r9 @ clear bit2 for lock mode
+ orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
+ str r10, [r11] @ commit to DLLA_CTRL
+ add r11, r11, #0x8 @ move to dllb
+ str r10, [r11] @ hit DLLB also
+
+ mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
+wait_dll_lock:
+ subs r4, r4, #0x1
+ bne wait_dll_lock
+ nop
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
+
+ .globl omap2_ssp_set_config
+ .globl omap2_ssp_pll_ctl
+ .globl omap2_ssp_pll_stat
+ .globl omap2_ssp_pll_div
+ .globl omap2_ssp_sdrc_rfr
+ .globl omap2_ssp_dlla_ctrl
+
+omap2_ssp_set_config:
+ .word SRAM_VA_MAGIC
+omap2_ssp_pll_ctl:
+ .word SRAM_VA_MAGIC
+omap2_ssp_pll_stat:
+ .word SRAM_VA_MAGIC
+omap2_ssp_pll_div:
+ .word SRAM_VA_MAGIC
+omap2_ssp_sdrc_rfr:
+ .word SRAM_VA_MAGIC
+omap2_ssp_dlla_ctrl:
+ .word SRAM_VA_MAGIC
+
+ENTRY(sram_set_prcm_sz)
+ .word . - sram_set_prcm
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/10] ARM: OMAP2: Rename 24xx specific SRAM functions
2008-03-12 10:45 ` [PATCH 2/10] ARM: OMAP2: Move sram-fn.S to sram24xx.S Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 4/10] ARM: OMAP3: Add SRAM support for 3430 Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
This is needed to make room for 34xx specific SRAM functions.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/sram24xx.S | 112 +++++++++++++++++++-------------------
arch/arm/plat-omap/sram.c | 102 +++++++++++++++++++---------------
include/asm-arm/arch-omap/sram.h | 20 ++++---
3 files changed, 124 insertions(+), 110 deletions(-)
diff --git a/arch/arm/mach-omap2/sram24xx.S b/arch/arm/mach-omap2/sram24xx.S
index ba1e005..5f1a305 100644
--- a/arch/arm/mach-omap2/sram24xx.S
+++ b/arch/arm/mach-omap2/sram24xx.S
@@ -30,14 +30,14 @@
.text
-ENTRY(sram_ddr_init)
+ENTRY(omap24xx_sram_ddr_init)
stmfd sp!, {r0 - r12, lr} @ save registers on stack
mov r12, r2 @ capture CS1 vs CS0
mov r8, r3 @ capture force parameter
/* frequency shift down */
- ldr r2, omap2_sdi_cm_clksel2_pll @ get address of dpllout reg
+ ldr r2, omap24xx_sdi_cm_clksel2_pll @ get address of dpllout reg
mov r3, #0x1 @ value for 1x operation
str r3, [r2] @ go to L1-freq operation
@@ -46,7 +46,7 @@ ENTRY(sram_ddr_init)
bl voltage_shift @ go drop voltage
/* dll lock mode */
- ldr r11, omap2_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
+ ldr r11, omap24xx_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
ldr r10, [r11] @ get current val
cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
@@ -97,7 +97,7 @@ i_dll_delay:
* wait for it to finish, use 32k sync counter, 1tick=31uS.
*/
voltage_shift:
- ldr r4, omap2_sdi_prcm_voltctrl @ get addr of volt ctrl.
+ ldr r4, omap24xx_sdi_prcm_voltctrl @ get addr of volt ctrl.
ldr r5, [r4] @ get value.
ldr r6, prcm_mask_val @ get value of mask
and r5, r5, r6 @ apply mask to clear bits
@@ -107,7 +107,7 @@ voltage_shift:
orr r5, r5, r3 @ build value for force
str r5, [r4] @ Force transition to L1
- ldr r3, omap2_sdi_timer_32ksynct_cr @ get addr of counter
+ ldr r3, omap24xx_sdi_timer_32ksynct_cr @ get addr of counter
ldr r5, [r3] @ get value
add r5, r5, #0x3 @ give it at most 93uS
volt_delay:
@@ -117,36 +117,36 @@ volt_delay:
mov pc, lr @ back to caller.
/* relative load constants */
- .globl omap2_sdi_cm_clksel2_pll
- .globl omap2_sdi_sdrc_dlla_ctrl
- .globl omap2_sdi_prcm_voltctrl
- .globl omap2_sdi_timer_32ksynct_cr
+ .globl omap24xx_sdi_cm_clksel2_pll
+ .globl omap24xx_sdi_sdrc_dlla_ctrl
+ .globl omap24xx_sdi_prcm_voltctrl
+ .globl omap24xx_sdi_timer_32ksynct_cr
-omap2_sdi_cm_clksel2_pll:
+omap24xx_sdi_cm_clksel2_pll:
.word SRAM_VA_MAGIC
-omap2_sdi_sdrc_dlla_ctrl:
+omap24xx_sdi_sdrc_dlla_ctrl:
.word SRAM_VA_MAGIC
-omap2_sdi_prcm_voltctrl:
+omap24xx_sdi_prcm_voltctrl:
.word SRAM_VA_MAGIC
prcm_mask_val:
.word 0xFFFF3FFC
-omap2_sdi_timer_32ksynct_cr:
+omap24xx_sdi_timer_32ksynct_cr:
.word SRAM_VA_MAGIC
-ENTRY(sram_ddr_init_sz)
- .word . - sram_ddr_init
+ENTRY(omap24xx_sram_ddr_init_sz)
+ .word . - omap24xx_sram_ddr_init
/*
* Reprograms memory timings.
* r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
* PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
*/
-ENTRY(sram_reprogram_sdrc)
+ENTRY(omap24xx_sram_reprogram_sdrc)
stmfd sp!, {r0 - r10, lr} @ save registers on stack
mov r3, #0x0 @ clear for mrc call
mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
nop
nop
- ldr r6, omap2_srs_sdrc_rfr_ctrl @ get addr of refresh reg
+ ldr r6, omap24xx_srs_sdrc_rfr_ctrl @ get addr of refresh reg
ldr r5, [r6] @ get value
mov r5, r5, lsr #8 @ isolate rfr field and drop burst
@@ -160,7 +160,7 @@ ENTRY(sram_reprogram_sdrc)
movne r5, r5, lsl #1 @ mult by 2 if to full
mov r5, r5, lsl #8 @ put rfr field back into place
add r5, r5, #0x1 @ turn on burst of 1
- ldr r4, omap2_srs_cm_clksel2_pll @ get address of out reg
+ ldr r4, omap24xx_srs_cm_clksel2_pll @ get address of out reg
ldr r3, [r4] @ get curr value
orr r3, r3, #0x3
bic r3, r3, #0x3 @ clear lower bits
@@ -181,7 +181,7 @@ ENTRY(sram_reprogram_sdrc)
bne freq_out @ leave if SDR, no DLL function
/* With DDR, we need to take care of the DLL for the frequency change */
- ldr r2, omap2_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
+ ldr r2, omap24xx_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
str r1, [r2] @ write out new SDRC_DLLA_CTRL
add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
str r1, [r2] @ commit to SDRC_DLLB_CTRL
@@ -197,7 +197,7 @@ freq_out:
* wait for it to finish, use 32k sync counter, 1tick=31uS.
*/
voltage_shift_c:
- ldr r10, omap2_srs_prcm_voltctrl @ get addr of volt ctrl
+ ldr r10, omap24xx_srs_prcm_voltctrl @ get addr of volt ctrl
ldr r8, [r10] @ get value
ldr r7, ddr_prcm_mask_val @ get value of mask
and r8, r8, r7 @ apply mask to clear bits
@@ -207,7 +207,7 @@ voltage_shift_c:
orr r8, r8, r7 @ build value for force
str r8, [r10] @ Force transition to L1
- ldr r10, omap2_srs_timer_32ksynct @ get addr of counter
+ ldr r10, omap24xx_srs_timer_32ksynct @ get addr of counter
ldr r8, [r10] @ get value
add r8, r8, #0x2 @ give it at most 62uS (min 31+)
volt_delay_c:
@@ -216,45 +216,45 @@ volt_delay_c:
bhi volt_delay_c @ not yet->branch
mov pc, lr @ back to caller
- .globl omap2_srs_cm_clksel2_pll
- .globl omap2_srs_sdrc_dlla_ctrl
- .globl omap2_srs_sdrc_rfr_ctrl
- .globl omap2_srs_prcm_voltctrl
- .globl omap2_srs_timer_32ksynct
+ .globl omap24xx_srs_cm_clksel2_pll
+ .globl omap24xx_srs_sdrc_dlla_ctrl
+ .globl omap24xx_srs_sdrc_rfr_ctrl
+ .globl omap24xx_srs_prcm_voltctrl
+ .globl omap24xx_srs_timer_32ksynct
-omap2_srs_cm_clksel2_pll:
+omap24xx_srs_cm_clksel2_pll:
.word SRAM_VA_MAGIC
-omap2_srs_sdrc_dlla_ctrl:
+omap24xx_srs_sdrc_dlla_ctrl:
.word SRAM_VA_MAGIC
-omap2_srs_sdrc_rfr_ctrl:
+omap24xx_srs_sdrc_rfr_ctrl:
.word SRAM_VA_MAGIC
-omap2_srs_prcm_voltctrl:
+omap24xx_srs_prcm_voltctrl:
.word SRAM_VA_MAGIC
ddr_prcm_mask_val:
.word 0xFFFF3FFC
-omap2_srs_timer_32ksynct:
+omap24xx_srs_timer_32ksynct:
.word SRAM_VA_MAGIC
-ENTRY(sram_reprogram_sdrc_sz)
- .word . - sram_reprogram_sdrc
+ENTRY(omap24xx_sram_reprogram_sdrc_sz)
+ .word . - omap24xx_sram_reprogram_sdrc
/*
* Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
*/
-ENTRY(sram_set_prcm)
+ENTRY(omap24xx_sram_set_prcm)
stmfd sp!, {r0-r12, lr} @ regs to stack
adr r4, pbegin @ addr of preload start
adr r8, pend @ addr of preload end
mcrr p15, 1, r8, r4, c12 @ preload into icache
pbegin:
/* move into fast relock bypass */
- ldr r8, omap2_ssp_pll_ctl @ get addr
+ ldr r8, omap24xx_ssp_pll_ctl @ get addr
ldr r5, [r8] @ get val
mvn r6, #0x3 @ clear mask
and r5, r5, r6 @ clear field
orr r7, r5, #0x2 @ fast relock val
str r7, [r8] @ go to fast relock
- ldr r4, omap2_ssp_pll_stat @ addr of stat
+ ldr r4, omap24xx_ssp_pll_stat @ addr of stat
block:
/* wait for bypass */
ldr r8, [r4] @ stat value
@@ -263,10 +263,10 @@ block:
bne block @ loop if not
/* set new dpll dividers _after_ in bypass */
- ldr r4, omap2_ssp_pll_div @ get addr
+ ldr r4, omap24xx_ssp_pll_div @ get addr
str r0, [r4] @ set dpll ctrl val
- ldr r4, omap2_ssp_set_config @ get addr
+ ldr r4, omap24xx_ssp_set_config @ get addr
mov r8, #1 @ valid cfg msk
str r8, [r4] @ make dividers take
@@ -280,8 +280,8 @@ wait_a_bit:
beq pend @ jump over dpll relock
/* relock DPLL with new vals */
- ldr r5, omap2_ssp_pll_stat @ get addr
- ldr r4, omap2_ssp_pll_ctl @ get addr
+ ldr r5, omap24xx_ssp_pll_stat @ get addr
+ ldr r4, omap24xx_ssp_pll_ctl @ get addr
orr r8, r7, #0x3 @ val for lock dpll
str r8, [r4] @ set val
mov r0, #1000 @ dead spin a bit
@@ -295,9 +295,9 @@ wait_lock:
bne wait_lock @ wait if not
pend:
/* update memory timings & briefly lock dll */
- ldr r4, omap2_ssp_sdrc_rfr @ get addr
+ ldr r4, omap24xx_ssp_sdrc_rfr @ get addr
str r1, [r4] @ update refresh timing
- ldr r11, omap2_ssp_dlla_ctrl @ get addr of DLLA ctrl
+ ldr r11, omap24xx_ssp_dlla_ctrl @ get addr of DLLA ctrl
ldr r10, [r11] @ get current val
mvn r9, #0x4 @ mask to get clear bit2
and r10, r10, r9 @ clear bit2 for lock mode
@@ -313,25 +313,25 @@ wait_dll_lock:
nop
ldmfd sp!, {r0-r12, pc} @ restore regs and return
- .globl omap2_ssp_set_config
- .globl omap2_ssp_pll_ctl
- .globl omap2_ssp_pll_stat
- .globl omap2_ssp_pll_div
- .globl omap2_ssp_sdrc_rfr
- .globl omap2_ssp_dlla_ctrl
+ .globl omap24xx_ssp_set_config
+ .globl omap24xx_ssp_pll_ctl
+ .globl omap24xx_ssp_pll_stat
+ .globl omap24xx_ssp_pll_div
+ .globl omap24xx_ssp_sdrc_rfr
+ .globl omap24xx_ssp_dlla_ctrl
-omap2_ssp_set_config:
+omap24xx_ssp_set_config:
.word SRAM_VA_MAGIC
-omap2_ssp_pll_ctl:
+omap24xx_ssp_pll_ctl:
.word SRAM_VA_MAGIC
-omap2_ssp_pll_stat:
+omap24xx_ssp_pll_stat:
.word SRAM_VA_MAGIC
-omap2_ssp_pll_div:
+omap24xx_ssp_pll_div:
.word SRAM_VA_MAGIC
-omap2_ssp_sdrc_rfr:
+omap24xx_ssp_sdrc_rfr:
.word SRAM_VA_MAGIC
-omap2_ssp_dlla_ctrl:
+omap24xx_ssp_dlla_ctrl:
.word SRAM_VA_MAGIC
-ENTRY(sram_set_prcm_sz)
- .word . - sram_set_prcm
+ENTRY(omap24xx_sram_set_prcm_sz)
+ .word . - omap24xx_sram_set_prcm
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 204cd81..6b1ce47 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -46,9 +46,9 @@
#define SRAM_BOOTLOADER_SZ 0x80
#endif
-#define VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
-#define VA_READPERM0 IO_ADDRESS(0x68005050)
-#define VA_WRITEPERM0 IO_ADDRESS(0x68005058)
+#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
#define GP_DEVICE 0x300
#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
@@ -65,21 +65,21 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
unsigned long size_avail);
/* Global symbols in sram-fn.S to be patched with omap_sram_patch_va() */
-extern void *omap2_sdi_cm_clksel2_pll;
-extern void *omap2_sdi_sdrc_dlla_ctrl;
-extern void *omap2_sdi_prcm_voltctrl;
-extern void *omap2_sdi_timer_32ksynct_cr;
-extern void *omap2_srs_cm_clksel2_pll;
-extern void *omap2_srs_sdrc_dlla_ctrl;
-extern void *omap2_srs_sdrc_rfr_ctrl;
-extern void *omap2_srs_prcm_voltctrl;
-extern void *omap2_srs_timer_32ksynct;
-extern void *omap2_ssp_set_config;
-extern void *omap2_ssp_pll_ctl;
-extern void *omap2_ssp_pll_stat;
-extern void *omap2_ssp_pll_div;
-extern void *omap2_ssp_sdrc_rfr;
-extern void *omap2_ssp_dlla_ctrl;
+extern void *omap24xx_sdi_cm_clksel2_pll;
+extern void *omap24xx_sdi_sdrc_dlla_ctrl;
+extern void *omap24xx_sdi_prcm_voltctrl;
+extern void *omap24xx_sdi_timer_32ksynct_cr;
+extern void *omap24xx_srs_cm_clksel2_pll;
+extern void *omap24xx_srs_sdrc_dlla_ctrl;
+extern void *omap24xx_srs_sdrc_rfr_ctrl;
+extern void *omap24xx_srs_prcm_voltctrl;
+extern void *omap24xx_srs_timer_32ksynct;
+extern void *omap24xx_ssp_set_config;
+extern void *omap24xx_ssp_pll_ctl;
+extern void *omap24xx_ssp_pll_stat;
+extern void *omap24xx_ssp_pll_div;
+extern void *omap24xx_ssp_sdrc_rfr;
+extern void *omap24xx_ssp_dlla_ctrl;
/*
@@ -98,9 +98,9 @@ static int is_sram_locked(void)
if (type == GP_DEVICE) {
/* RAMFW: R/W access to all initiators for all qualifier sets */
if (cpu_is_omap242x()) {
- __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
- __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */
- __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */
+ __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
+ __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
+ __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
}
return 0;
} else
@@ -345,69 +345,81 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
}
+#endif
-int __init omap2_sram_init(void)
+#ifdef CONFIG_ARCH_OMAP2
+int __init omap24xx_sram_init(void)
{
- _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz);
+ _omap2_sram_ddr_init = omap_sram_push(omap24xx_sram_ddr_init,
+ omap24xx_sram_ddr_init_sz);
/* Patch in the correct register addresses for multiboot */
- omap_sram_patch_va(sram_ddr_init, &omap2_sdi_cm_clksel2_pll,
+ omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_cm_clksel2_pll,
_omap2_sram_ddr_init,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2));
- omap_sram_patch_va(sram_ddr_init, &omap2_sdi_sdrc_dlla_ctrl,
+ omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_sdrc_dlla_ctrl,
_omap2_sram_ddr_init,
OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
- omap_sram_patch_va(sram_ddr_init, &omap2_sdi_prcm_voltctrl,
+ omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_prcm_voltctrl,
_omap2_sram_ddr_init, OMAP24XX_PRCM_VOLTCTRL);
- omap_sram_patch_va(sram_ddr_init, &omap2_sdi_timer_32ksynct_cr,
+ omap_sram_patch_va(omap24xx_sram_ddr_init,
+ &omap24xx_sdi_timer_32ksynct_cr,
_omap2_sram_ddr_init,
(void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010));
- _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
- sram_reprogram_sdrc_sz);
+ _omap2_sram_reprogram_sdrc = omap_sram_push(omap24xx_sram_reprogram_sdrc,
+ omap24xx_sram_reprogram_sdrc_sz);
- omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_cm_clksel2_pll,
+ omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
+ &omap24xx_srs_cm_clksel2_pll,
_omap2_sram_reprogram_sdrc,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2));
- omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_sdrc_dlla_ctrl,
+ omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
+ &omap24xx_srs_sdrc_dlla_ctrl,
_omap2_sram_reprogram_sdrc,
OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
- omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_sdrc_rfr_ctrl,
+ omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
+ &omap24xx_srs_sdrc_rfr_ctrl,
_omap2_sram_reprogram_sdrc,
OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0));
- omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_prcm_voltctrl,
+ omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
+ &omap24xx_srs_prcm_voltctrl,
_omap2_sram_reprogram_sdrc,
OMAP24XX_PRCM_VOLTCTRL);
- omap_sram_patch_va(sram_reprogram_sdrc, &omap2_srs_timer_32ksynct,
+ omap_sram_patch_va(omap24xx_sram_reprogram_sdrc,
+ &omap24xx_srs_timer_32ksynct,
_omap2_sram_reprogram_sdrc,
(void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010));
- _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
+ _omap2_set_prcm = omap_sram_push(omap24xx_sram_set_prcm,
+ omap24xx_sram_set_prcm_sz);
- /* REVISIT: prefix all these symbols with omap2_sram_ */
- omap_sram_patch_va(sram_set_prcm, &omap2_ssp_set_config,
+ omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_set_config,
_omap2_set_prcm,
OMAP24XX_PRCM_CLKCFG_CTRL);
- omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_ctl,
+ omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_ctl,
_omap2_set_prcm,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN));
- omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_stat,
+ omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_stat,
_omap2_set_prcm,
OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST));
- omap_sram_patch_va(sram_set_prcm, &omap2_ssp_pll_div,
+ omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_div,
_omap2_set_prcm,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1));
- omap_sram_patch_va(sram_set_prcm, &omap2_ssp_sdrc_rfr,
+ omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_sdrc_rfr,
_omap2_set_prcm,
OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0));
- omap_sram_patch_va(sram_set_prcm, &omap2_ssp_dlla_ctrl,
+ omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_dlla_ctrl,
_omap2_set_prcm,
OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
return 0;
}
#else
-#define omap2_sram_init() do {} while (0)
+static inline int omap24xx_sram_init(void)
+{
+ return 0;
+}
#endif
int __init omap_sram_init(void)
@@ -417,8 +429,8 @@ int __init omap_sram_init(void)
if (!(cpu_class_is_omap2()))
omap1_sram_init();
- else
- omap2_sram_init();
+ else if (cpu_is_omap24xx())
+ omap24xx_sram_init();
return 0;
}
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index 5bfbe37..2b7f103 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -24,17 +24,19 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
/* Do not use these */
-extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long sram_reprogram_clock_sz;
+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap24xx_sram_reprogram_clock_sz;
-extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-extern unsigned long sram_ddr_init_sz;
+extern void omap24xx_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+ u32 base_cs, u32 force_unlock);
+extern unsigned long omap24xx_sram_ddr_init_sz;
-extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-extern unsigned long sram_set_prcm_sz;
+extern u32 omap24xx_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+ int bypass);
+extern unsigned long omap24xx_sram_set_prcm_sz;
-extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type);
-extern unsigned long sram_reprogram_sdrc_sz;
+extern void omap24xx_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+ u32 mem_type);
+extern unsigned long omap24xx_sram_reprogram_sdrc_sz;
#endif
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/10] ARM: OMAP3: Add SRAM support for 3430
2008-03-12 10:45 ` [PATCH 3/10] ARM: OMAP2: Rename 24xx specific SRAM functions Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 5/10] ARM: OMAP2: Rename cm_regbits_24xx.h to cm-regbits-24xx.h Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Dasu, Karthik P, Tony Lindgren
From: Dasu, Karthik P <karthik-dp@ti.com>
Add SRAM support for 3430
Patch modified by Tony to leave out new functions,
they will be added later in a separate patch.
Signed-off-by: Karthik Dasu<karthik-dp@ti.com>
Acked-by: Richard Woodruff <r-woodruff2@ti.com>
Acked-by: Vikram Pandita <vikram.pandita@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/plat-omap/sram.c | 56 +++++++++++++++++++++++++++++++++++++-------
1 files changed, 47 insertions(+), 9 deletions(-)
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 6b1ce47..1186d2b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -39,6 +39,10 @@
#define OMAP2_SRAM_PUB_PA 0x4020f800
#define OMAP2_SRAM_VA VMALLOC_END
#define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800)
+#define OMAP3_SRAM_PA 0x40200000
+#define OMAP3_SRAM_VA 0xd7000000
+#define OMAP3_SRAM_PUB_PA 0x40208000
+#define OMAP3_SRAM_PUB_VA 0xd7008000
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#define SRAM_BOOTLOADER_SZ 0x00
@@ -49,6 +53,14 @@
#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
+
+#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048)
+#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0)
+
#define GP_DEVICE 0x300
#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
@@ -102,6 +114,13 @@ static int is_sram_locked(void)
__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
}
+ if (cpu_is_omap34xx()) {
+ __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+ __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
+ __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+ __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
+ __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
+ }
return 0;
} else
return 1; /* assume locked with no PPA or security driver */
@@ -119,16 +138,28 @@ void __init omap_detect_sram(void)
if (cpu_class_is_omap2()) {
if (is_sram_locked()) {
- omap_sram_base = OMAP2_SRAM_PUB_VA;
- omap_sram_start = OMAP2_SRAM_PUB_PA;
- omap_sram_size = 0x800; /* 2K */
+ if (cpu_is_omap34xx()) {
+ omap_sram_base = OMAP3_SRAM_PUB_VA;
+ omap_sram_start = OMAP3_SRAM_PUB_PA;
+ omap_sram_size = 0x8000; /* 32K */
+ } else {
+ omap_sram_base = OMAP2_SRAM_PUB_VA;
+ omap_sram_start = OMAP2_SRAM_PUB_PA;
+ omap_sram_size = 0x800; /* 2K */
+ }
} else {
- omap_sram_base = OMAP2_SRAM_VA;
- omap_sram_start = OMAP2_SRAM_PA;
- if (cpu_is_omap242x())
- omap_sram_size = 0xa0000; /* 640K */
- else if (cpu_is_omap243x() || cpu_is_omap34xx())
+ if (cpu_is_omap34xx()) {
+ omap_sram_base = OMAP3_SRAM_VA;
+ omap_sram_start = OMAP3_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
+ } else {
+ omap_sram_base = OMAP2_SRAM_VA;
+ omap_sram_start = OMAP2_SRAM_PA;
+ if (cpu_is_omap242x())
+ omap_sram_size = 0xa0000; /* 640K */
+ else if (cpu_is_omap243x())
+ omap_sram_size = 0x10000; /* 64K */
+ }
}
} else {
omap_sram_base = OMAP1_SRAM_VA;
@@ -174,7 +205,7 @@ void __init omap_map_sram(void)
if (omap_sram_size == 0)
return;
- if (cpu_class_is_omap2()) {
+ if (cpu_is_omap24xx()) {
omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
base = OMAP2_SRAM_PA;
@@ -182,6 +213,13 @@ void __init omap_map_sram(void)
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
}
+ if (cpu_is_omap34xx()) {
+ omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
+ base = OMAP3_SRAM_PA;
+ base = ROUND_DOWN(base, PAGE_SIZE);
+ omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+ }
+
omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/10] ARM: OMAP2: Rename cm_regbits_24xx.h to cm-regbits-24xx.h
2008-03-12 10:45 ` [PATCH 4/10] ARM: OMAP3: Add SRAM support for 3430 Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 6/10] ARM: OMAP3: Rename cm_regbits_34xx.h to cm-regbits-34xx.h Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
This is to follow current naming before sending files upstream.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock.c | 2 +-
arch/arm/mach-omap2/clock24xx.c | 2 +-
arch/arm/mach-omap2/clock24xx.h | 2 +-
arch/arm/mach-omap2/cm-regbits-24xx.h | 401 +++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/cm_regbits_24xx.h | 401 ---------------------------------
arch/arm/mach-omap2/pm.c | 2 +-
drivers/dsp/dspgateway/dsp.h | 2 +-
7 files changed, 406 insertions(+), 406 deletions(-)
create mode 100644 arch/arm/mach-omap2/cm-regbits-24xx.h
delete mode 100644 arch/arm/mach-omap2/cm_regbits_24xx.h
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 314ac57..3f41144 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -42,7 +42,7 @@
#include "prm.h"
#include "prm_regbits_24xx.h"
#include "cm.h"
-#include "cm_regbits_24xx.h"
+#include "cm-regbits-24xx.h"
#include "cm_regbits_34xx.h"
#define MAX_CLOCK_ENABLE_WAIT 100000
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 1053fc9..e8d0fe3 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -38,7 +38,7 @@
#include "prm.h"
#include "prm_regbits_24xx.h"
#include "cm.h"
-#include "cm_regbits_24xx.h"
+#include "cm-regbits-24xx.h"
/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
#define EN_APLL_STOPPED 0
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 6ea0c1b..2b4a6a6 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -26,7 +26,7 @@
#include "prm.h"
#include "cm.h"
#include "prm_regbits_24xx.h"
-#include "cm_regbits_24xx.h"
+#include "cm-regbits-24xx.h"
#include "sdrc.h"
static void omap2_table_mpu_recalc(struct clk *clk);
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
new file mode 100644
index 0000000..20ac381
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -0,0 +1,401 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Clock Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP24XX_EN_CAM_SHIFT 31
+#define OMAP24XX_EN_CAM (1 << 31)
+#define OMAP24XX_EN_WDT4_SHIFT 29
+#define OMAP24XX_EN_WDT4 (1 << 29)
+#define OMAP2420_EN_WDT3_SHIFT 28
+#define OMAP2420_EN_WDT3 (1 << 28)
+#define OMAP24XX_EN_MSPRO_SHIFT 27
+#define OMAP24XX_EN_MSPRO (1 << 27)
+#define OMAP24XX_EN_FAC_SHIFT 25
+#define OMAP24XX_EN_FAC (1 << 25)
+#define OMAP2420_EN_EAC_SHIFT 24
+#define OMAP2420_EN_EAC (1 << 24)
+#define OMAP24XX_EN_HDQ_SHIFT 23
+#define OMAP24XX_EN_HDQ (1 << 23)
+#define OMAP2420_EN_I2C2_SHIFT 20
+#define OMAP2420_EN_I2C2 (1 << 20)
+#define OMAP2420_EN_I2C1_SHIFT 19
+#define OMAP2420_EN_I2C1 (1 << 19)
+
+/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
+#define OMAP2430_EN_MCBSP5_SHIFT 5
+#define OMAP2430_EN_MCBSP5 (1 << 5)
+#define OMAP2430_EN_MCBSP4_SHIFT 4
+#define OMAP2430_EN_MCBSP4 (1 << 4)
+#define OMAP2430_EN_MCBSP3_SHIFT 3
+#define OMAP2430_EN_MCBSP3 (1 << 3)
+#define OMAP24XX_EN_SSI_SHIFT 1
+#define OMAP24XX_EN_SSI (1 << 1)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP24XX_EN_MPU_WDT_SHIFT 3
+#define OMAP24XX_EN_MPU_WDT (1 << 3)
+
+/* Bits specific to each register */
+
+/* CM_IDLEST_MPU */
+/* 2430 only */
+#define OMAP2430_ST_MPU (1 << 0)
+
+/* CM_CLKSEL_MPU */
+#define OMAP24XX_CLKSEL_MPU_SHIFT 0
+#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP24XX_AUTOSTATE_MPU (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits*/
+#define OMAP24XX_EN_TV_SHIFT 2
+#define OMAP24XX_EN_TV (1 << 2)
+#define OMAP24XX_EN_DSS2_SHIFT 1
+#define OMAP24XX_EN_DSS2 (1 << 1)
+#define OMAP24XX_EN_DSS1_SHIFT 0
+#define OMAP24XX_EN_DSS1 (1 << 0)
+
+/* CM_FCLKEN2_CORE specific bits */
+#define OMAP2430_EN_I2CHS2_SHIFT 20
+#define OMAP2430_EN_I2CHS2 (1 << 20)
+#define OMAP2430_EN_I2CHS1_SHIFT 19
+#define OMAP2430_EN_I2CHS1 (1 << 19)
+#define OMAP2430_EN_MMCHSDB2_SHIFT 17
+#define OMAP2430_EN_MMCHSDB2 (1 << 17)
+#define OMAP2430_EN_MMCHSDB1_SHIFT 16
+#define OMAP2430_EN_MMCHSDB1 (1 << 16)
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP24XX_EN_MAILBOXES_SHIFT 30
+#define OMAP24XX_EN_MAILBOXES (1 << 30)
+#define OMAP24XX_EN_DSS_SHIFT 0
+#define OMAP24XX_EN_DSS (1 << 0)
+
+/* CM_ICLKEN2_CORE specific bits */
+
+/* CM_ICLKEN3_CORE */
+/* 2430 only */
+#define OMAP2430_EN_SDRC_SHIFT 2
+#define OMAP2430_EN_SDRC (1 << 2)
+
+/* CM_ICLKEN4_CORE */
+#define OMAP24XX_EN_PKA_SHIFT 4
+#define OMAP24XX_EN_PKA (1 << 4)
+#define OMAP24XX_EN_AES_SHIFT 3
+#define OMAP24XX_EN_AES (1 << 3)
+#define OMAP24XX_EN_RNG_SHIFT 2
+#define OMAP24XX_EN_RNG (1 << 2)
+#define OMAP24XX_EN_SHA_SHIFT 1
+#define OMAP24XX_EN_SHA (1 << 1)
+#define OMAP24XX_EN_DES_SHIFT 0
+#define OMAP24XX_EN_DES (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP24XX_ST_MAILBOXES (1 << 30)
+#define OMAP24XX_ST_WDT4 (1 << 29)
+#define OMAP2420_ST_WDT3 (1 << 28)
+#define OMAP24XX_ST_MSPRO (1 << 27)
+#define OMAP24XX_ST_FAC (1 << 25)
+#define OMAP2420_ST_EAC (1 << 24)
+#define OMAP24XX_ST_HDQ (1 << 23)
+#define OMAP24XX_ST_I2C2 (1 << 20)
+#define OMAP24XX_ST_I2C1 (1 << 19)
+#define OMAP24XX_ST_MCBSP2 (1 << 16)
+#define OMAP24XX_ST_MCBSP1 (1 << 15)
+#define OMAP24XX_ST_DSS (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP2430_ST_MCBSP5 (1 << 5)
+#define OMAP2430_ST_MCBSP4 (1 << 4)
+#define OMAP2430_ST_MCBSP3 (1 << 3)
+#define OMAP24XX_ST_SSI (1 << 1)
+
+/* CM_IDLEST3_CORE */
+/* 2430 only */
+#define OMAP2430_ST_SDRC (1 << 2)
+
+/* CM_IDLEST4_CORE */
+#define OMAP24XX_ST_PKA (1 << 4)
+#define OMAP24XX_ST_AES (1 << 3)
+#define OMAP24XX_ST_RNG (1 << 2)
+#define OMAP24XX_ST_SHA (1 << 1)
+#define OMAP24XX_ST_DES (1 << 0)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP24XX_AUTO_CAM (1 << 31)
+#define OMAP24XX_AUTO_MAILBOXES (1 << 30)
+#define OMAP24XX_AUTO_WDT4 (1 << 29)
+#define OMAP2420_AUTO_WDT3 (1 << 28)
+#define OMAP24XX_AUTO_MSPRO (1 << 27)
+#define OMAP2420_AUTO_MMC (1 << 26)
+#define OMAP24XX_AUTO_FAC (1 << 25)
+#define OMAP2420_AUTO_EAC (1 << 24)
+#define OMAP24XX_AUTO_HDQ (1 << 23)
+#define OMAP24XX_AUTO_UART2 (1 << 22)
+#define OMAP24XX_AUTO_UART1 (1 << 21)
+#define OMAP24XX_AUTO_I2C2 (1 << 20)
+#define OMAP24XX_AUTO_I2C1 (1 << 19)
+#define OMAP24XX_AUTO_MCSPI2 (1 << 18)
+#define OMAP24XX_AUTO_MCSPI1 (1 << 17)
+#define OMAP24XX_AUTO_MCBSP2 (1 << 16)
+#define OMAP24XX_AUTO_MCBSP1 (1 << 15)
+#define OMAP24XX_AUTO_GPT12 (1 << 14)
+#define OMAP24XX_AUTO_GPT11 (1 << 13)
+#define OMAP24XX_AUTO_GPT10 (1 << 12)
+#define OMAP24XX_AUTO_GPT9 (1 << 11)
+#define OMAP24XX_AUTO_GPT8 (1 << 10)
+#define OMAP24XX_AUTO_GPT7 (1 << 9)
+#define OMAP24XX_AUTO_GPT6 (1 << 8)
+#define OMAP24XX_AUTO_GPT5 (1 << 7)
+#define OMAP24XX_AUTO_GPT4 (1 << 6)
+#define OMAP24XX_AUTO_GPT3 (1 << 5)
+#define OMAP24XX_AUTO_GPT2 (1 << 4)
+#define OMAP2420_AUTO_VLYNQ (1 << 3)
+#define OMAP24XX_AUTO_DSS (1 << 0)
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP2430_AUTO_MDM_INTC (1 << 11)
+#define OMAP2430_AUTO_GPIO5 (1 << 10)
+#define OMAP2430_AUTO_MCSPI3 (1 << 9)
+#define OMAP2430_AUTO_MMCHS2 (1 << 8)
+#define OMAP2430_AUTO_MMCHS1 (1 << 7)
+#define OMAP2430_AUTO_USBHS (1 << 6)
+#define OMAP2430_AUTO_MCBSP5 (1 << 5)
+#define OMAP2430_AUTO_MCBSP4 (1 << 4)
+#define OMAP2430_AUTO_MCBSP3 (1 << 3)
+#define OMAP24XX_AUTO_UART3 (1 << 2)
+#define OMAP24XX_AUTO_SSI (1 << 1)
+#define OMAP24XX_AUTO_USB (1 << 0)
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC (1 << 2)
+#define OMAP24XX_AUTO_GPMC (1 << 1)
+#define OMAP24XX_AUTO_SDMA (1 << 0)
+
+/* CM_AUTOIDLE4_CORE */
+#define OMAP24XX_AUTO_PKA (1 << 4)
+#define OMAP24XX_AUTO_AES (1 << 3)
+#define OMAP24XX_AUTO_RNG (1 << 2)
+#define OMAP24XX_AUTO_SHA (1 << 1)
+#define OMAP24XX_AUTO_DES (1 << 0)
+
+/* CM_CLKSEL1_CORE */
+#define OMAP24XX_CLKSEL_USB_SHIFT 25
+#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
+#define OMAP24XX_CLKSEL_SSI_SHIFT 20
+#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
+#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
+#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
+#define OMAP24XX_CLKSEL_DSS2_SHIFT 13
+#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
+#define OMAP24XX_CLKSEL_DSS1_SHIFT 8
+#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
+#define OMAP24XX_CLKSEL_L4_SHIFT 5
+#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
+#define OMAP24XX_CLKSEL_L3_SHIFT 0
+#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
+
+/* CM_CLKSEL2_CORE */
+#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
+#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
+#define OMAP24XX_CLKSEL_GPT11_SHIFT 20
+#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
+#define OMAP24XX_CLKSEL_GPT10_SHIFT 18
+#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
+#define OMAP24XX_CLKSEL_GPT9_SHIFT 16
+#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
+#define OMAP24XX_CLKSEL_GPT8_SHIFT 14
+#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
+#define OMAP24XX_CLKSEL_GPT7_SHIFT 12
+#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
+#define OMAP24XX_CLKSEL_GPT6_SHIFT 10
+#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
+#define OMAP24XX_CLKSEL_GPT5_SHIFT 8
+#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
+#define OMAP24XX_CLKSEL_GPT4_SHIFT 6
+#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
+#define OMAP24XX_CLKSEL_GPT3_SHIFT 4
+#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
+#define OMAP24XX_CLKSEL_GPT2_SHIFT 2
+#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP24XX_AUTOSTATE_DSS (1 << 2)
+#define OMAP24XX_AUTOSTATE_L4 (1 << 1)
+#define OMAP24XX_AUTOSTATE_L3 (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP24XX_EN_3D_SHIFT 2
+#define OMAP24XX_EN_3D (1 << 2)
+#define OMAP24XX_EN_2D_SHIFT 1
+#define OMAP24XX_EN_2D (1 << 1)
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP24XX_AUTOSTATE_GFX (1 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP2430_EN_ICR_SHIFT 6
+#define OMAP2430_EN_ICR (1 << 6)
+#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
+#define OMAP24XX_EN_OMAPCTRL (1 << 5)
+#define OMAP24XX_EN_WDT1_SHIFT 4
+#define OMAP24XX_EN_WDT1 (1 << 4)
+#define OMAP24XX_EN_32KSYNC_SHIFT 1
+#define OMAP24XX_EN_32KSYNC (1 << 1)
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP2430_ST_ICR (1 << 6)
+#define OMAP24XX_ST_OMAPCTRL (1 << 5)
+#define OMAP24XX_ST_WDT1 (1 << 4)
+#define OMAP24XX_ST_MPU_WDT (1 << 3)
+#define OMAP24XX_ST_32KSYNC (1 << 1)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP24XX_AUTO_OMAPCTRL (1 << 5)
+#define OMAP24XX_AUTO_WDT1 (1 << 4)
+#define OMAP24XX_AUTO_MPU_WDT (1 << 3)
+#define OMAP24XX_AUTO_GPIOS (1 << 2)
+#define OMAP24XX_AUTO_32KSYNC (1 << 1)
+#define OMAP24XX_AUTO_GPT1 (1 << 0)
+
+/* CM_CLKSEL_WKUP */
+#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
+#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP24XX_EN_54M_PLL_SHIFT 6
+#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
+#define OMAP24XX_EN_96M_PLL_SHIFT 2
+#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
+#define OMAP24XX_EN_DPLL_SHIFT 0
+#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP24XX_ST_54M_APLL (1 << 9)
+#define OMAP24XX_ST_96M_APLL (1 << 8)
+#define OMAP24XX_ST_54M_CLK (1 << 6)
+#define OMAP24XX_ST_12M_CLK (1 << 5)
+#define OMAP24XX_ST_48M_CLK (1 << 4)
+#define OMAP24XX_ST_96M_CLK (1 << 2)
+#define OMAP24XX_ST_CORE_CLK_SHIFT 0
+#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP24XX_AUTO_54M_SHIFT 6
+#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
+#define OMAP24XX_AUTO_96M_SHIFT 2
+#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
+#define OMAP24XX_AUTO_DPLL_SHIFT 0
+#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
+
+/* CM_CLKSEL1_PLL */
+#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
+#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
+#define OMAP24XX_APLLS_CLKIN_SHIFT 23
+#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
+#define OMAP24XX_DPLL_MULT_SHIFT 12
+#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
+#define OMAP24XX_DPLL_DIV_SHIFT 8
+#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
+#define OMAP24XX_54M_SOURCE_SHIFT 5
+#define OMAP24XX_54M_SOURCE (1 << 5)
+#define OMAP2430_96M_SOURCE_SHIFT 4
+#define OMAP2430_96M_SOURCE (1 << 4)
+#define OMAP24XX_48M_SOURCE_SHIFT 3
+#define OMAP24XX_48M_SOURCE (1 << 3)
+#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
+#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP24XX_CORE_CLK_SRC_SHIFT 0
+#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
+
+/* CM_FCLKEN_DSP */
+#define OMAP2420_EN_IVA_COP_SHIFT 10
+#define OMAP2420_EN_IVA_COP (1 << 10)
+#define OMAP2420_EN_IVA_MPU_SHIFT 8
+#define OMAP2420_EN_IVA_MPU (1 << 8)
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0)
+
+/* CM_ICLKEN_DSP */
+#define OMAP2420_EN_DSP_IPI_SHIFT 1
+#define OMAP2420_EN_DSP_IPI (1 << 1)
+
+/* CM_IDLEST_DSP */
+#define OMAP2420_ST_IVA (1 << 8)
+#define OMAP2420_ST_IPI (1 << 1)
+#define OMAP24XX_ST_DSP (1 << 0)
+
+/* CM_AUTOIDLE_DSP */
+#define OMAP2420_AUTO_DSP_IPI (1 << 1)
+
+/* CM_CLKSEL_DSP */
+#define OMAP2420_SYNC_IVA (1 << 13)
+#define OMAP2420_CLKSEL_IVA_SHIFT 8
+#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
+#define OMAP24XX_SYNC_DSP (1 << 7)
+#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
+#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
+#define OMAP24XX_CLKSEL_DSP_SHIFT 0
+#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_DSP */
+#define OMAP2420_AUTOSTATE_IVA (1 << 8)
+#define OMAP24XX_AUTOSTATE_DSP (1 << 0)
+
+/* CM_FCLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_EN_OSC_SHIFT 1
+#define OMAP2430_EN_OSC (1 << 1)
+
+/* CM_ICLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0)
+
+/* CM_IDLEST_MDM specific bits */
+/* 2430 only */
+
+/* CM_AUTOIDLE_MDM */
+/* 2430 only */
+#define OMAP2430_AUTO_OSC (1 << 1)
+#define OMAP2430_AUTO_MDM (1 << 0)
+
+/* CM_CLKSEL_MDM */
+/* 2430 only */
+#define OMAP2430_SYNC_MDM (1 << 4)
+#define OMAP2430_CLKSEL_MDM_SHIFT 0
+#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
+
+/* CM_CLKSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_AUTOSTATE_MDM (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm_regbits_24xx.h b/arch/arm/mach-omap2/cm_regbits_24xx.h
deleted file mode 100644
index 20ac381..0000000
--- a/arch/arm/mach-omap2/cm_regbits_24xx.h
+++ /dev/null
@@ -1,401 +0,0 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
-
-/*
- * OMAP24XX Clock Management register bits
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include "cm.h"
-
-/* Bits shared between registers */
-
-/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
-#define OMAP24XX_EN_CAM_SHIFT 31
-#define OMAP24XX_EN_CAM (1 << 31)
-#define OMAP24XX_EN_WDT4_SHIFT 29
-#define OMAP24XX_EN_WDT4 (1 << 29)
-#define OMAP2420_EN_WDT3_SHIFT 28
-#define OMAP2420_EN_WDT3 (1 << 28)
-#define OMAP24XX_EN_MSPRO_SHIFT 27
-#define OMAP24XX_EN_MSPRO (1 << 27)
-#define OMAP24XX_EN_FAC_SHIFT 25
-#define OMAP24XX_EN_FAC (1 << 25)
-#define OMAP2420_EN_EAC_SHIFT 24
-#define OMAP2420_EN_EAC (1 << 24)
-#define OMAP24XX_EN_HDQ_SHIFT 23
-#define OMAP24XX_EN_HDQ (1 << 23)
-#define OMAP2420_EN_I2C2_SHIFT 20
-#define OMAP2420_EN_I2C2 (1 << 20)
-#define OMAP2420_EN_I2C1_SHIFT 19
-#define OMAP2420_EN_I2C1 (1 << 19)
-
-/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
-#define OMAP2430_EN_MCBSP5_SHIFT 5
-#define OMAP2430_EN_MCBSP5 (1 << 5)
-#define OMAP2430_EN_MCBSP4_SHIFT 4
-#define OMAP2430_EN_MCBSP4 (1 << 4)
-#define OMAP2430_EN_MCBSP3_SHIFT 3
-#define OMAP2430_EN_MCBSP3 (1 << 3)
-#define OMAP24XX_EN_SSI_SHIFT 1
-#define OMAP24XX_EN_SSI (1 << 1)
-
-/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
-#define OMAP24XX_EN_MPU_WDT_SHIFT 3
-#define OMAP24XX_EN_MPU_WDT (1 << 3)
-
-/* Bits specific to each register */
-
-/* CM_IDLEST_MPU */
-/* 2430 only */
-#define OMAP2430_ST_MPU (1 << 0)
-
-/* CM_CLKSEL_MPU */
-#define OMAP24XX_CLKSEL_MPU_SHIFT 0
-#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
-
-/* CM_CLKSTCTRL_MPU */
-#define OMAP24XX_AUTOSTATE_MPU (1 << 0)
-
-/* CM_FCLKEN1_CORE specific bits*/
-#define OMAP24XX_EN_TV_SHIFT 2
-#define OMAP24XX_EN_TV (1 << 2)
-#define OMAP24XX_EN_DSS2_SHIFT 1
-#define OMAP24XX_EN_DSS2 (1 << 1)
-#define OMAP24XX_EN_DSS1_SHIFT 0
-#define OMAP24XX_EN_DSS1 (1 << 0)
-
-/* CM_FCLKEN2_CORE specific bits */
-#define OMAP2430_EN_I2CHS2_SHIFT 20
-#define OMAP2430_EN_I2CHS2 (1 << 20)
-#define OMAP2430_EN_I2CHS1_SHIFT 19
-#define OMAP2430_EN_I2CHS1 (1 << 19)
-#define OMAP2430_EN_MMCHSDB2_SHIFT 17
-#define OMAP2430_EN_MMCHSDB2 (1 << 17)
-#define OMAP2430_EN_MMCHSDB1_SHIFT 16
-#define OMAP2430_EN_MMCHSDB1 (1 << 16)
-
-/* CM_ICLKEN1_CORE specific bits */
-#define OMAP24XX_EN_MAILBOXES_SHIFT 30
-#define OMAP24XX_EN_MAILBOXES (1 << 30)
-#define OMAP24XX_EN_DSS_SHIFT 0
-#define OMAP24XX_EN_DSS (1 << 0)
-
-/* CM_ICLKEN2_CORE specific bits */
-
-/* CM_ICLKEN3_CORE */
-/* 2430 only */
-#define OMAP2430_EN_SDRC_SHIFT 2
-#define OMAP2430_EN_SDRC (1 << 2)
-
-/* CM_ICLKEN4_CORE */
-#define OMAP24XX_EN_PKA_SHIFT 4
-#define OMAP24XX_EN_PKA (1 << 4)
-#define OMAP24XX_EN_AES_SHIFT 3
-#define OMAP24XX_EN_AES (1 << 3)
-#define OMAP24XX_EN_RNG_SHIFT 2
-#define OMAP24XX_EN_RNG (1 << 2)
-#define OMAP24XX_EN_SHA_SHIFT 1
-#define OMAP24XX_EN_SHA (1 << 1)
-#define OMAP24XX_EN_DES_SHIFT 0
-#define OMAP24XX_EN_DES (1 << 0)
-
-/* CM_IDLEST1_CORE specific bits */
-#define OMAP24XX_ST_MAILBOXES (1 << 30)
-#define OMAP24XX_ST_WDT4 (1 << 29)
-#define OMAP2420_ST_WDT3 (1 << 28)
-#define OMAP24XX_ST_MSPRO (1 << 27)
-#define OMAP24XX_ST_FAC (1 << 25)
-#define OMAP2420_ST_EAC (1 << 24)
-#define OMAP24XX_ST_HDQ (1 << 23)
-#define OMAP24XX_ST_I2C2 (1 << 20)
-#define OMAP24XX_ST_I2C1 (1 << 19)
-#define OMAP24XX_ST_MCBSP2 (1 << 16)
-#define OMAP24XX_ST_MCBSP1 (1 << 15)
-#define OMAP24XX_ST_DSS (1 << 0)
-
-/* CM_IDLEST2_CORE */
-#define OMAP2430_ST_MCBSP5 (1 << 5)
-#define OMAP2430_ST_MCBSP4 (1 << 4)
-#define OMAP2430_ST_MCBSP3 (1 << 3)
-#define OMAP24XX_ST_SSI (1 << 1)
-
-/* CM_IDLEST3_CORE */
-/* 2430 only */
-#define OMAP2430_ST_SDRC (1 << 2)
-
-/* CM_IDLEST4_CORE */
-#define OMAP24XX_ST_PKA (1 << 4)
-#define OMAP24XX_ST_AES (1 << 3)
-#define OMAP24XX_ST_RNG (1 << 2)
-#define OMAP24XX_ST_SHA (1 << 1)
-#define OMAP24XX_ST_DES (1 << 0)
-
-/* CM_AUTOIDLE1_CORE */
-#define OMAP24XX_AUTO_CAM (1 << 31)
-#define OMAP24XX_AUTO_MAILBOXES (1 << 30)
-#define OMAP24XX_AUTO_WDT4 (1 << 29)
-#define OMAP2420_AUTO_WDT3 (1 << 28)
-#define OMAP24XX_AUTO_MSPRO (1 << 27)
-#define OMAP2420_AUTO_MMC (1 << 26)
-#define OMAP24XX_AUTO_FAC (1 << 25)
-#define OMAP2420_AUTO_EAC (1 << 24)
-#define OMAP24XX_AUTO_HDQ (1 << 23)
-#define OMAP24XX_AUTO_UART2 (1 << 22)
-#define OMAP24XX_AUTO_UART1 (1 << 21)
-#define OMAP24XX_AUTO_I2C2 (1 << 20)
-#define OMAP24XX_AUTO_I2C1 (1 << 19)
-#define OMAP24XX_AUTO_MCSPI2 (1 << 18)
-#define OMAP24XX_AUTO_MCSPI1 (1 << 17)
-#define OMAP24XX_AUTO_MCBSP2 (1 << 16)
-#define OMAP24XX_AUTO_MCBSP1 (1 << 15)
-#define OMAP24XX_AUTO_GPT12 (1 << 14)
-#define OMAP24XX_AUTO_GPT11 (1 << 13)
-#define OMAP24XX_AUTO_GPT10 (1 << 12)
-#define OMAP24XX_AUTO_GPT9 (1 << 11)
-#define OMAP24XX_AUTO_GPT8 (1 << 10)
-#define OMAP24XX_AUTO_GPT7 (1 << 9)
-#define OMAP24XX_AUTO_GPT6 (1 << 8)
-#define OMAP24XX_AUTO_GPT5 (1 << 7)
-#define OMAP24XX_AUTO_GPT4 (1 << 6)
-#define OMAP24XX_AUTO_GPT3 (1 << 5)
-#define OMAP24XX_AUTO_GPT2 (1 << 4)
-#define OMAP2420_AUTO_VLYNQ (1 << 3)
-#define OMAP24XX_AUTO_DSS (1 << 0)
-
-/* CM_AUTOIDLE2_CORE */
-#define OMAP2430_AUTO_MDM_INTC (1 << 11)
-#define OMAP2430_AUTO_GPIO5 (1 << 10)
-#define OMAP2430_AUTO_MCSPI3 (1 << 9)
-#define OMAP2430_AUTO_MMCHS2 (1 << 8)
-#define OMAP2430_AUTO_MMCHS1 (1 << 7)
-#define OMAP2430_AUTO_USBHS (1 << 6)
-#define OMAP2430_AUTO_MCBSP5 (1 << 5)
-#define OMAP2430_AUTO_MCBSP4 (1 << 4)
-#define OMAP2430_AUTO_MCBSP3 (1 << 3)
-#define OMAP24XX_AUTO_UART3 (1 << 2)
-#define OMAP24XX_AUTO_SSI (1 << 1)
-#define OMAP24XX_AUTO_USB (1 << 0)
-
-/* CM_AUTOIDLE3_CORE */
-#define OMAP24XX_AUTO_SDRC (1 << 2)
-#define OMAP24XX_AUTO_GPMC (1 << 1)
-#define OMAP24XX_AUTO_SDMA (1 << 0)
-
-/* CM_AUTOIDLE4_CORE */
-#define OMAP24XX_AUTO_PKA (1 << 4)
-#define OMAP24XX_AUTO_AES (1 << 3)
-#define OMAP24XX_AUTO_RNG (1 << 2)
-#define OMAP24XX_AUTO_SHA (1 << 1)
-#define OMAP24XX_AUTO_DES (1 << 0)
-
-/* CM_CLKSEL1_CORE */
-#define OMAP24XX_CLKSEL_USB_SHIFT 25
-#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
-#define OMAP24XX_CLKSEL_SSI_SHIFT 20
-#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
-#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
-#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
-#define OMAP24XX_CLKSEL_DSS2_SHIFT 13
-#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
-#define OMAP24XX_CLKSEL_DSS1_SHIFT 8
-#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
-#define OMAP24XX_CLKSEL_L4_SHIFT 5
-#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
-#define OMAP24XX_CLKSEL_L3_SHIFT 0
-#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
-
-/* CM_CLKSEL2_CORE */
-#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
-#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
-#define OMAP24XX_CLKSEL_GPT11_SHIFT 20
-#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
-#define OMAP24XX_CLKSEL_GPT10_SHIFT 18
-#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
-#define OMAP24XX_CLKSEL_GPT9_SHIFT 16
-#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
-#define OMAP24XX_CLKSEL_GPT8_SHIFT 14
-#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
-#define OMAP24XX_CLKSEL_GPT7_SHIFT 12
-#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
-#define OMAP24XX_CLKSEL_GPT6_SHIFT 10
-#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
-#define OMAP24XX_CLKSEL_GPT5_SHIFT 8
-#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
-#define OMAP24XX_CLKSEL_GPT4_SHIFT 6
-#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
-#define OMAP24XX_CLKSEL_GPT3_SHIFT 4
-#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
-#define OMAP24XX_CLKSEL_GPT2_SHIFT 2
-#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
-
-/* CM_CLKSTCTRL_CORE */
-#define OMAP24XX_AUTOSTATE_DSS (1 << 2)
-#define OMAP24XX_AUTOSTATE_L4 (1 << 1)
-#define OMAP24XX_AUTOSTATE_L3 (1 << 0)
-
-/* CM_FCLKEN_GFX */
-#define OMAP24XX_EN_3D_SHIFT 2
-#define OMAP24XX_EN_3D (1 << 2)
-#define OMAP24XX_EN_2D_SHIFT 1
-#define OMAP24XX_EN_2D (1 << 1)
-
-/* CM_ICLKEN_GFX specific bits */
-
-/* CM_IDLEST_GFX specific bits */
-
-/* CM_CLKSEL_GFX specific bits */
-
-/* CM_CLKSTCTRL_GFX */
-#define OMAP24XX_AUTOSTATE_GFX (1 << 0)
-
-/* CM_FCLKEN_WKUP specific bits */
-
-/* CM_ICLKEN_WKUP specific bits */
-#define OMAP2430_EN_ICR_SHIFT 6
-#define OMAP2430_EN_ICR (1 << 6)
-#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
-#define OMAP24XX_EN_OMAPCTRL (1 << 5)
-#define OMAP24XX_EN_WDT1_SHIFT 4
-#define OMAP24XX_EN_WDT1 (1 << 4)
-#define OMAP24XX_EN_32KSYNC_SHIFT 1
-#define OMAP24XX_EN_32KSYNC (1 << 1)
-
-/* CM_IDLEST_WKUP specific bits */
-#define OMAP2430_ST_ICR (1 << 6)
-#define OMAP24XX_ST_OMAPCTRL (1 << 5)
-#define OMAP24XX_ST_WDT1 (1 << 4)
-#define OMAP24XX_ST_MPU_WDT (1 << 3)
-#define OMAP24XX_ST_32KSYNC (1 << 1)
-
-/* CM_AUTOIDLE_WKUP */
-#define OMAP24XX_AUTO_OMAPCTRL (1 << 5)
-#define OMAP24XX_AUTO_WDT1 (1 << 4)
-#define OMAP24XX_AUTO_MPU_WDT (1 << 3)
-#define OMAP24XX_AUTO_GPIOS (1 << 2)
-#define OMAP24XX_AUTO_32KSYNC (1 << 1)
-#define OMAP24XX_AUTO_GPT1 (1 << 0)
-
-/* CM_CLKSEL_WKUP */
-#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
-#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
-
-/* CM_CLKEN_PLL */
-#define OMAP24XX_EN_54M_PLL_SHIFT 6
-#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
-#define OMAP24XX_EN_96M_PLL_SHIFT 2
-#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
-#define OMAP24XX_EN_DPLL_SHIFT 0
-#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
-
-/* CM_IDLEST_CKGEN */
-#define OMAP24XX_ST_54M_APLL (1 << 9)
-#define OMAP24XX_ST_96M_APLL (1 << 8)
-#define OMAP24XX_ST_54M_CLK (1 << 6)
-#define OMAP24XX_ST_12M_CLK (1 << 5)
-#define OMAP24XX_ST_48M_CLK (1 << 4)
-#define OMAP24XX_ST_96M_CLK (1 << 2)
-#define OMAP24XX_ST_CORE_CLK_SHIFT 0
-#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
-
-/* CM_AUTOIDLE_PLL */
-#define OMAP24XX_AUTO_54M_SHIFT 6
-#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
-#define OMAP24XX_AUTO_96M_SHIFT 2
-#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
-#define OMAP24XX_AUTO_DPLL_SHIFT 0
-#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
-
-/* CM_CLKSEL1_PLL */
-#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
-#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
-#define OMAP24XX_APLLS_CLKIN_SHIFT 23
-#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
-#define OMAP24XX_DPLL_MULT_SHIFT 12
-#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
-#define OMAP24XX_DPLL_DIV_SHIFT 8
-#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
-#define OMAP24XX_54M_SOURCE_SHIFT 5
-#define OMAP24XX_54M_SOURCE (1 << 5)
-#define OMAP2430_96M_SOURCE_SHIFT 4
-#define OMAP2430_96M_SOURCE (1 << 4)
-#define OMAP24XX_48M_SOURCE_SHIFT 3
-#define OMAP24XX_48M_SOURCE (1 << 3)
-#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
-#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
-
-/* CM_CLKSEL2_PLL */
-#define OMAP24XX_CORE_CLK_SRC_SHIFT 0
-#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
-
-/* CM_FCLKEN_DSP */
-#define OMAP2420_EN_IVA_COP_SHIFT 10
-#define OMAP2420_EN_IVA_COP (1 << 10)
-#define OMAP2420_EN_IVA_MPU_SHIFT 8
-#define OMAP2420_EN_IVA_MPU (1 << 8)
-#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
-#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0)
-
-/* CM_ICLKEN_DSP */
-#define OMAP2420_EN_DSP_IPI_SHIFT 1
-#define OMAP2420_EN_DSP_IPI (1 << 1)
-
-/* CM_IDLEST_DSP */
-#define OMAP2420_ST_IVA (1 << 8)
-#define OMAP2420_ST_IPI (1 << 1)
-#define OMAP24XX_ST_DSP (1 << 0)
-
-/* CM_AUTOIDLE_DSP */
-#define OMAP2420_AUTO_DSP_IPI (1 << 1)
-
-/* CM_CLKSEL_DSP */
-#define OMAP2420_SYNC_IVA (1 << 13)
-#define OMAP2420_CLKSEL_IVA_SHIFT 8
-#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
-#define OMAP24XX_SYNC_DSP (1 << 7)
-#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
-#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
-#define OMAP24XX_CLKSEL_DSP_SHIFT 0
-#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
-
-/* CM_CLKSTCTRL_DSP */
-#define OMAP2420_AUTOSTATE_IVA (1 << 8)
-#define OMAP24XX_AUTOSTATE_DSP (1 << 0)
-
-/* CM_FCLKEN_MDM */
-/* 2430 only */
-#define OMAP2430_EN_OSC_SHIFT 1
-#define OMAP2430_EN_OSC (1 << 1)
-
-/* CM_ICLKEN_MDM */
-/* 2430 only */
-#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
-#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0)
-
-/* CM_IDLEST_MDM specific bits */
-/* 2430 only */
-
-/* CM_AUTOIDLE_MDM */
-/* 2430 only */
-#define OMAP2430_AUTO_OSC (1 << 1)
-#define OMAP2430_AUTO_MDM (1 << 0)
-
-/* CM_CLKSEL_MDM */
-/* 2430 only */
-#define OMAP2430_SYNC_MDM (1 << 4)
-#define OMAP2430_CLKSEL_MDM_SHIFT 0
-#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
-
-/* CM_CLKSTCTRL_MDM */
-/* 2430 only */
-#define OMAP2430_AUTOSTATE_MDM (1 << 0)
-
-#endif
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index a1fe348..095b910 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -49,7 +49,7 @@
#include "prm.h"
#include "prm_regbits_24xx.h"
#include "cm.h"
-#include "cm_regbits_24xx.h"
+#include "cm-regbits-24xx.h"
#include "sdrc.h"
/* These addrs are in assembly language code to be patched at runtime */
diff --git a/drivers/dsp/dspgateway/dsp.h b/drivers/dsp/dspgateway/dsp.h
index 23321be..7d238e5 100644
--- a/drivers/dsp/dspgateway/dsp.h
+++ b/drivers/dsp/dspgateway/dsp.h
@@ -33,7 +33,7 @@
#include "../../../arch/arm/mach-omap2/prm.h"
#include "../../../arch/arm/mach-omap2/prm_regbits_24xx.h"
#include "../../../arch/arm/mach-omap2/cm.h"
-#include "../../../arch/arm/mach-omap2/cm_regbits_24xx.h"
+#include "../../../arch/arm/mach-omap2/cm-regbits-24xx.h"
#endif
/*
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/10] ARM: OMAP3: Rename cm_regbits_34xx.h to cm-regbits-34xx.h
2008-03-12 10:45 ` [PATCH 5/10] ARM: OMAP2: Rename cm_regbits_24xx.h to cm-regbits-24xx.h Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 7/10] ARM: OMAP2: Rename prcm_common.h to prcm-common.h Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
Rename cm_regbits_34xx.h to cm-regbits-34xx.h
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock.c | 2 +-
arch/arm/mach-omap2/clock34xx.c | 2 +-
arch/arm/mach-omap2/clock34xx.h | 2 +-
arch/arm/mach-omap2/cm-regbits-34xx.h | 667 +++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/cm_regbits_34xx.h | 667 ---------------------------------
drivers/usb/host/ehci-omap.h | 2 +-
6 files changed, 671 insertions(+), 671 deletions(-)
create mode 100644 arch/arm/mach-omap2/cm-regbits-34xx.h
delete mode 100644 arch/arm/mach-omap2/cm_regbits_34xx.h
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 3f41144..3f107d4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -43,7 +43,7 @@
#include "prm_regbits_24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
-#include "cm_regbits_34xx.h"
+#include "cm-regbits-34xx.h"
#define MAX_CLOCK_ENABLE_WAIT 100000
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 2558a23..616e071 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -35,7 +35,7 @@
#include "prm.h"
#include "prm_regbits_34xx.h"
#include "cm.h"
-#include "cm_regbits_34xx.h"
+#include "cm-regbits-34xx.h"
/* CM_CLKEN_PLL*.EN* bit values */
#define DPLL_LOCKED 0x7
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 99cb536..9f61352 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -14,7 +14,7 @@
#include "clock.h"
#include "cm.h"
-#include "cm_regbits_34xx.h"
+#include "cm-regbits-34xx.h"
#include "prm.h"
#include "prm_regbits_34xx.h"
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
new file mode 100644
index 0000000..fcb7c12
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -0,0 +1,667 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Clock Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
+#define OMAP3430ES2_EN_MMC3_SHIFT 30
+#define OMAP3430_EN_MSPRO (1 << 23)
+#define OMAP3430_EN_MSPRO_SHIFT 23
+#define OMAP3430_EN_HDQ (1 << 22)
+#define OMAP3430_EN_HDQ_SHIFT 22
+#define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)
+#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
+#define OMAP3430ES1_EN_D2D (1 << 3)
+#define OMAP3430ES1_EN_D2D_SHIFT 3
+#define OMAP3430_EN_SSI (1 << 0)
+#define OMAP3430_EN_SSI_SHIFT 0
+
+/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
+#define OMAP3430ES2_EN_USBTLL_SHIFT 2
+#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP3430_EN_WDT2 (1 << 5)
+#define OMAP3430_EN_WDT2_SHIFT 5
+
+/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
+#define OMAP3430_EN_CAM (1 << 0)
+#define OMAP3430_EN_CAM_SHIFT 0
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
+#define OMAP3430_EN_WDT3 (1 << 12)
+#define OMAP3430_EN_WDT3_SHIFT 12
+
+/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
+#define OMAP3430_OVERRIDE_ENABLE (1 << 19)
+
+
+/* Bits specific to each register */
+
+/* CM_FCLKEN_IVA2 */
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
+
+/* CM_CLKEN_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
+#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_IVA2 */
+#define OMAP3430_ST_IVA2 (1 << 0)
+
+/* CM_IDLEST_PLL_IVA2 */
+#define OMAP3430_ST_IVA2_CLK (1 << 0)
+
+/* CM_AUTOIDLE_PLL_IVA2 */
+#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
+#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_IVA2 */
+#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
+#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
+#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
+#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
+#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_IVA2 */
+#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
+#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
+
+/* CM_CLKSTST_IVA2 */
+#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0)
+
+/* CM_REVISION specific bits */
+
+/* CM_SYSCONFIG specific bits */
+
+/* CM_CLKEN_PLL_MPU */
+#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_MPU_DPLL_SHIFT 0
+#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_MPU */
+#define OMAP3430_ST_MPU (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK (1 << 0)
+
+/* CM_AUTOIDLE_PLL_MPU */
+#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
+#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_MPU */
+#define OMAP3430_MPU_CLK_SRC_SHIFT 19
+#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
+#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
+#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
+#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_MPU */
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
+#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
+
+/* CM_CLKSTST_MPU */
+#define OMAP3430_CLKACTIVITY_MPU (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits */
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP3430_EN_ICR (1 << 29)
+#define OMAP3430_EN_ICR_SHIFT 29
+#define OMAP3430_EN_AES2 (1 << 28)
+#define OMAP3430_EN_AES2_SHIFT 28
+#define OMAP3430_EN_SHA12 (1 << 27)
+#define OMAP3430_EN_SHA12_SHIFT 27
+#define OMAP3430_EN_DES2 (1 << 26)
+#define OMAP3430_EN_DES2_SHIFT 26
+#define OMAP3430ES1_EN_FAC (1 << 8)
+#define OMAP3430ES1_EN_FAC_SHIFT 8
+#define OMAP3430_EN_MAILBOXES (1 << 7)
+#define OMAP3430_EN_MAILBOXES_SHIFT 7
+#define OMAP3430_EN_OMAPCTRL (1 << 6)
+#define OMAP3430_EN_OMAPCTRL_SHIFT 6
+#define OMAP3430_EN_SDRC (1 << 1)
+#define OMAP3430_EN_SDRC_SHIFT 1
+
+/* CM_ICLKEN2_CORE */
+#define OMAP3430_EN_PKA (1 << 4)
+#define OMAP3430_EN_PKA_SHIFT 4
+#define OMAP3430_EN_AES1 (1 << 3)
+#define OMAP3430_EN_AES1_SHIFT 3
+#define OMAP3430_EN_RNG (1 << 2)
+#define OMAP3430_EN_RNG_SHIFT 2
+#define OMAP3430_EN_SHA11 (1 << 1)
+#define OMAP3430_EN_SHA11_SHIFT 1
+#define OMAP3430_EN_DES1 (1 << 0)
+#define OMAP3430_EN_DES1_SHIFT 0
+
+/* CM_FCLKEN3_CORE specific bits */
+#define OMAP3430ES2_EN_TS_SHIFT 1
+#define OMAP3430ES2_EN_TS_MASK (1 << 1)
+#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
+#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP3430_ST_ICR (1 << 29)
+#define OMAP3430_ST_AES2 (1 << 28)
+#define OMAP3430_ST_SHA12 (1 << 27)
+#define OMAP3430_ST_DES2 (1 << 26)
+#define OMAP3430_ST_MSPRO (1 << 23)
+#define OMAP3430_ST_HDQ (1 << 22)
+#define OMAP3430ES1_ST_FAC (1 << 8)
+#define OMAP3430ES1_ST_MAILBOXES (1 << 7)
+#define OMAP3430_ST_OMAPCTRL (1 << 6)
+#define OMAP3430_ST_SDMA (1 << 2)
+#define OMAP3430_ST_SDRC (1 << 1)
+#define OMAP3430_ST_SSI (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP3430_ST_PKA (1 << 4)
+#define OMAP3430_ST_AES1 (1 << 3)
+#define OMAP3430_ST_RNG (1 << 2)
+#define OMAP3430_ST_SHA11 (1 << 1)
+#define OMAP3430_ST_DES1 (1 << 0)
+
+/* CM_IDLEST3_CORE */
+#define OMAP3430_ST_USBTLL (1 << 2)
+#define OMAP3430_ST_USBTLL_SHIFT 2
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_AES2 (1 << 28)
+#define OMAP3430_AUTO_AES2_SHIFT 28
+#define OMAP3430_AUTO_SHA12 (1 << 27)
+#define OMAP3430_AUTO_SHA12_SHIFT 27
+#define OMAP3430_AUTO_DES2 (1 << 26)
+#define OMAP3430_AUTO_DES2_SHIFT 26
+#define OMAP3430_AUTO_MMC2 (1 << 25)
+#define OMAP3430_AUTO_MMC2_SHIFT 25
+#define OMAP3430_AUTO_MMC1 (1 << 24)
+#define OMAP3430_AUTO_MMC1_SHIFT 24
+#define OMAP3430_AUTO_MSPRO (1 << 23)
+#define OMAP3430_AUTO_MSPRO_SHIFT 23
+#define OMAP3430_AUTO_HDQ (1 << 22)
+#define OMAP3430_AUTO_HDQ_SHIFT 22
+#define OMAP3430_AUTO_MCSPI4 (1 << 21)
+#define OMAP3430_AUTO_MCSPI4_SHIFT 21
+#define OMAP3430_AUTO_MCSPI3 (1 << 20)
+#define OMAP3430_AUTO_MCSPI3_SHIFT 20
+#define OMAP3430_AUTO_MCSPI2 (1 << 19)
+#define OMAP3430_AUTO_MCSPI2_SHIFT 19
+#define OMAP3430_AUTO_MCSPI1 (1 << 18)
+#define OMAP3430_AUTO_MCSPI1_SHIFT 18
+#define OMAP3430_AUTO_I2C3 (1 << 17)
+#define OMAP3430_AUTO_I2C3_SHIFT 17
+#define OMAP3430_AUTO_I2C2 (1 << 16)
+#define OMAP3430_AUTO_I2C2_SHIFT 16
+#define OMAP3430_AUTO_I2C1 (1 << 15)
+#define OMAP3430_AUTO_I2C1_SHIFT 15
+#define OMAP3430_AUTO_UART2 (1 << 14)
+#define OMAP3430_AUTO_UART2_SHIFT 14
+#define OMAP3430_AUTO_UART1 (1 << 13)
+#define OMAP3430_AUTO_UART1_SHIFT 13
+#define OMAP3430_AUTO_GPT11 (1 << 12)
+#define OMAP3430_AUTO_GPT11_SHIFT 12
+#define OMAP3430_AUTO_GPT10 (1 << 11)
+#define OMAP3430_AUTO_GPT10_SHIFT 11
+#define OMAP3430_AUTO_MCBSP5 (1 << 10)
+#define OMAP3430_AUTO_MCBSP5_SHIFT 10
+#define OMAP3430_AUTO_MCBSP1 (1 << 9)
+#define OMAP3430_AUTO_MCBSP1_SHIFT 9
+#define OMAP3430ES1_AUTO_FAC (1 << 8)
+#define OMAP3430ES1_AUTO_FAC_SHIFT 8
+#define OMAP3430_AUTO_MAILBOXES (1 << 7)
+#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
+#define OMAP3430_AUTO_OMAPCTRL (1 << 6)
+#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
+#define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)
+#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
+#define OMAP3430_AUTO_HSOTGUSB (1 << 4)
+#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
+#define OMAP3430ES1_AUTO_D2D (1 << 3)
+#define OMAP3430ES1_AUTO_D2D_SHIFT 3
+#define OMAP3430_AUTO_SSI (1 << 0)
+#define OMAP3430_AUTO_SSI_SHIFT 0
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP3430_AUTO_PKA (1 << 4)
+#define OMAP3430_AUTO_PKA_SHIFT 4
+#define OMAP3430_AUTO_AES1 (1 << 3)
+#define OMAP3430_AUTO_AES1_SHIFT 3
+#define OMAP3430_AUTO_RNG (1 << 2)
+#define OMAP3430_AUTO_RNG_SHIFT 2
+#define OMAP3430_AUTO_SHA11 (1 << 1)
+#define OMAP3430_AUTO_SHA11_SHIFT 1
+#define OMAP3430_AUTO_DES1 (1 << 0)
+#define OMAP3430_AUTO_DES1_SHIFT 0
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP3430_AUTO_USBTLL (1 << 2)
+#define OMAP3430_AUTO_USBTLL_SHIFT 2
+
+/* CM_CLKSEL_CORE */
+#define OMAP3430_CLKSEL_SSI_SHIFT 8
+#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
+#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
+#define OMAP3430_CLKSEL_GPT11_SHIFT 7
+#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
+#define OMAP3430_CLKSEL_GPT10_SHIFT 6
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
+#define OMAP3430_CLKSEL_L4_SHIFT 2
+#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
+#define OMAP3430_CLKSEL_L3_SHIFT 0
+#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
+#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
+#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
+#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
+#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
+#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
+
+/* CM_CLKSTST_CORE */
+#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2)
+#define OMAP3430_CLKACTIVITY_L4 (1 << 1)
+#define OMAP3430_CLKACTIVITY_L3 (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP3430ES1_EN_3D (1 << 2)
+#define OMAP3430ES1_EN_3D_SHIFT 2
+#define OMAP3430ES1_EN_2D (1 << 1)
+#define OMAP3430ES1_EN_2D_SHIFT 1
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_SLEEPDEP_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
+#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
+
+/* CM_CLKSTST_GFX */
+#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0)
+
+/* CM_FCLKEN_SGX */
+#define OMAP3430ES2_EN_SGX_SHIFT 1
+#define OMAP3430ES2_EN_SGX_MASK (1 << 1)
+
+/* CM_CLKSEL_SGX */
+#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
+#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP3430_EN_WDT1 (1 << 4)
+#define OMAP3430_EN_WDT1_SHIFT 4
+#define OMAP3430_EN_32KSYNC (1 << 2)
+#define OMAP3430_EN_32KSYNC_SHIFT 2
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP3430_ST_WDT2 (1 << 5)
+#define OMAP3430_ST_WDT1 (1 << 4)
+#define OMAP3430_ST_32KSYNC (1 << 2)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP3430_AUTO_WDT2 (1 << 5)
+#define OMAP3430_AUTO_WDT2_SHIFT 5
+#define OMAP3430_AUTO_WDT1 (1 << 4)
+#define OMAP3430_AUTO_WDT1_SHIFT 4
+#define OMAP3430_AUTO_GPIO1 (1 << 3)
+#define OMAP3430_AUTO_GPIO1_SHIFT 3
+#define OMAP3430_AUTO_32KSYNC (1 << 2)
+#define OMAP3430_AUTO_32KSYNC_SHIFT 2
+#define OMAP3430_AUTO_GPT12 (1 << 1)
+#define OMAP3430_AUTO_GPT12_SHIFT 1
+#define OMAP3430_AUTO_GPT1 (1 << 0)
+#define OMAP3430_AUTO_GPT1_SHIFT 0
+
+/* CM_CLKSEL_WKUP */
+#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
+#define OMAP3430_CLKSEL_RM_SHIFT 1
+#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
+#define OMAP3430_CLKSEL_GPT1_SHIFT 0
+#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
+#define OMAP3430_PWRDN_CAM_SHIFT 30
+#define OMAP3430_PWRDN_DSS1_SHIFT 29
+#define OMAP3430_PWRDN_TV_SHIFT 28
+#define OMAP3430_PWRDN_96M_SHIFT 27
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
+#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
+#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
+#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
+#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
+#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
+#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_CORE_DPLL_SHIFT 0
+#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKEN2_PLL */
+#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
+#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
+#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP3430_ST_54M_CLK (1 << 5)
+#define OMAP3430_ST_12M_CLK (1 << 4)
+#define OMAP3430_ST_48M_CLK (1 << 3)
+#define OMAP3430_ST_96M_CLK (1 << 2)
+#define OMAP3430_ST_PERIPH_CLK (1 << 1)
+#define OMAP3430_ST_CORE_CLK (1 << 0)
+
+/* CM_IDLEST2_CKGEN */
+#define OMAP3430_ST_120M_CLK (1 << 1)
+#define OMAP3430_ST_PERIPH2_CLK (1 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
+#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
+#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
+#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL */
+/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
+#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
+#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
+#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
+#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
+#define OMAP3430_SOURCE_54M (1 << 5)
+#define OMAP3430_SOURCE_48M (1 << 3)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
+#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
+#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL3_PLL */
+#define OMAP3430_DIV_96M_SHIFT 0
+#define OMAP3430_DIV_96M_MASK (0x1f << 0)
+
+/* CM_CLKSEL4_PLL */
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL5_PLL */
+#define OMAP3430ES2_DIV_120M_SHIFT 0
+#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
+
+/* CM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT2_EN_SHIFT 7
+#define OMAP3430_CLKOUT2_EN (1 << 7)
+#define OMAP3430_CLKOUT2_DIV_SHIFT 3
+#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
+#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
+#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
+
+/* CM_FCLKEN_DSS */
+#define OMAP3430_EN_TV (1 << 2)
+#define OMAP3430_EN_TV_SHIFT 2
+#define OMAP3430_EN_DSS2 (1 << 1)
+#define OMAP3430_EN_DSS2_SHIFT 1
+#define OMAP3430_EN_DSS1 (1 << 0)
+#define OMAP3430_EN_DSS1_SHIFT 0
+
+/* CM_ICLKEN_DSS */
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0)
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
+
+/* CM_IDLEST_DSS */
+#define OMAP3430_ST_DSS (1 << 0)
+
+/* CM_AUTOIDLE_DSS */
+#define OMAP3430_AUTO_DSS (1 << 0)
+#define OMAP3430_AUTO_DSS_SHIFT 0
+
+/* CM_CLKSEL_DSS */
+#define OMAP3430_CLKSEL_TV_SHIFT 8
+#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
+#define OMAP3430_CLKSEL_DSS1_SHIFT 0
+#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
+
+/* CM_SLEEPDEP_DSS specific bits */
+
+/* CM_CLKSTCTRL_DSS */
+#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
+#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
+
+/* CM_CLKSTST_DSS */
+#define OMAP3430_CLKACTIVITY_DSS (1 << 0)
+
+/* CM_FCLKEN_CAM specific bits */
+
+/* CM_ICLKEN_CAM specific bits */
+
+/* CM_IDLEST_CAM */
+#define OMAP3430_ST_CAM (1 << 0)
+
+/* CM_AUTOIDLE_CAM */
+#define OMAP3430_AUTO_CAM (1 << 0)
+#define OMAP3430_AUTO_CAM_SHIFT 0
+
+/* CM_CLKSEL_CAM */
+#define OMAP3430_CLKSEL_CAM_SHIFT 0
+#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
+
+/* CM_SLEEPDEP_CAM specific bits */
+
+/* CM_CLKSTCTRL_CAM */
+#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
+#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
+
+/* CM_CLKSTST_CAM */
+#define OMAP3430_CLKACTIVITY_CAM (1 << 0)
+
+/* CM_FCLKEN_PER specific bits */
+
+/* CM_ICLKEN_PER specific bits */
+
+/* CM_IDLEST_PER */
+#define OMAP3430_ST_WDT3 (1 << 12)
+#define OMAP3430_ST_MCBSP4 (1 << 2)
+#define OMAP3430_ST_MCBSP3 (1 << 1)
+#define OMAP3430_ST_MCBSP2 (1 << 0)
+
+/* CM_AUTOIDLE_PER */
+#define OMAP3430_AUTO_GPIO6 (1 << 17)
+#define OMAP3430_AUTO_GPIO6_SHIFT 17
+#define OMAP3430_AUTO_GPIO5 (1 << 16)
+#define OMAP3430_AUTO_GPIO5_SHIFT 16
+#define OMAP3430_AUTO_GPIO4 (1 << 15)
+#define OMAP3430_AUTO_GPIO4_SHIFT 15
+#define OMAP3430_AUTO_GPIO3 (1 << 14)
+#define OMAP3430_AUTO_GPIO3_SHIFT 14
+#define OMAP3430_AUTO_GPIO2 (1 << 13)
+#define OMAP3430_AUTO_GPIO2_SHIFT 13
+#define OMAP3430_AUTO_WDT3 (1 << 12)
+#define OMAP3430_AUTO_WDT3_SHIFT 12
+#define OMAP3430_AUTO_UART3 (1 << 11)
+#define OMAP3430_AUTO_UART3_SHIFT 11
+#define OMAP3430_AUTO_GPT9 (1 << 10)
+#define OMAP3430_AUTO_GPT9_SHIFT 10
+#define OMAP3430_AUTO_GPT8 (1 << 9)
+#define OMAP3430_AUTO_GPT8_SHIFT 9
+#define OMAP3430_AUTO_GPT7 (1 << 8)
+#define OMAP3430_AUTO_GPT7_SHIFT 8
+#define OMAP3430_AUTO_GPT6 (1 << 7)
+#define OMAP3430_AUTO_GPT6_SHIFT 7
+#define OMAP3430_AUTO_GPT5 (1 << 6)
+#define OMAP3430_AUTO_GPT5_SHIFT 6
+#define OMAP3430_AUTO_GPT4 (1 << 5)
+#define OMAP3430_AUTO_GPT4_SHIFT 5
+#define OMAP3430_AUTO_GPT3 (1 << 4)
+#define OMAP3430_AUTO_GPT3_SHIFT 4
+#define OMAP3430_AUTO_GPT2 (1 << 3)
+#define OMAP3430_AUTO_GPT2_SHIFT 3
+#define OMAP3430_AUTO_MCBSP4 (1 << 2)
+#define OMAP3430_AUTO_MCBSP4_SHIFT 2
+#define OMAP3430_AUTO_MCBSP3 (1 << 1)
+#define OMAP3430_AUTO_MCBSP3_SHIFT 1
+#define OMAP3430_AUTO_MCBSP2 (1 << 0)
+#define OMAP3430_AUTO_MCBSP2_SHIFT 0
+
+/* CM_CLKSEL_PER */
+#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
+#define OMAP3430_CLKSEL_GPT9_SHIFT 7
+#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
+#define OMAP3430_CLKSEL_GPT8_SHIFT 6
+#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
+#define OMAP3430_CLKSEL_GPT7_SHIFT 5
+#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
+#define OMAP3430_CLKSEL_GPT6_SHIFT 4
+#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
+#define OMAP3430_CLKSEL_GPT5_SHIFT 3
+#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
+#define OMAP3430_CLKSEL_GPT4_SHIFT 2
+#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
+#define OMAP3430_CLKSEL_GPT3_SHIFT 1
+#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
+#define OMAP3430_CLKSEL_GPT2_SHIFT 0
+
+/* CM_SLEEPDEP_PER specific bits */
+#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)
+
+/* CM_CLKSTCTRL_PER */
+#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
+#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
+
+/* CM_CLKSTST_PER */
+#define OMAP3430_CLKACTIVITY_PER (1 << 0)
+
+/* CM_CLKSEL1_EMU */
+#define OMAP3430_DIV_DPLL4_SHIFT 24
+#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
+#define OMAP3430_DIV_DPLL3_SHIFT 16
+#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
+#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
+#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
+#define OMAP3430_CLKSEL_PCLK_SHIFT 8
+#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
+#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
+#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
+#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
+#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
+#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
+#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
+#define OMAP3430_MUX_CTRL_SHIFT 0
+#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
+
+/* CM_CLKSTCTRL_EMU */
+#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
+#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
+
+/* CM_CLKSTST_EMU */
+#define OMAP3430_CLKACTIVITY_EMU (1 << 0)
+
+/* CM_CLKSEL2_EMU specific bits */
+#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
+#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
+#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
+#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL3_EMU specific bits */
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
+
+/* CM_POLCTRL */
+#define OMAP3430_CLKOUT2_POL (1 << 0)
+
+/* CM_IDLEST_NEON */
+#define OMAP3430_ST_NEON (1 << 0)
+
+/* CM_CLKSTCTRL_NEON */
+#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
+#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
+
+/* CM_FCLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
+#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
+#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
+#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
+
+/* CM_ICLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST_SHIFT 0
+#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
+
+/* CM_IDLEST_USBHOST */
+
+/* CM_AUTOIDLE_USBHOST */
+#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
+#define OMAP3430ES2_AUTO_USBHOST_MASK (1<<0)
+
+/* CM_SLEEPDEP_USBHOST */
+#define OMAP3430ES2_EN_MPU_SHIFT 1
+#define OMAP3430ES2_EN_MPU_MASK (1<<1)
+#define OMAP3430ES2_EN_IVA2_SHIFT 2
+#define OMAP3430ES2_EN_IVA2_MASK (1<<2)
+
+/* CM_CLKSTCTRL_USBHOST */
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3<<0)
+
+
+
+#endif
diff --git a/arch/arm/mach-omap2/cm_regbits_34xx.h b/arch/arm/mach-omap2/cm_regbits_34xx.h
deleted file mode 100644
index fcb7c12..0000000
--- a/arch/arm/mach-omap2/cm_regbits_34xx.h
+++ /dev/null
@@ -1,667 +0,0 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
-
-/*
- * OMAP3430 Clock Management register bits
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include "cm.h"
-
-/* Bits shared between registers */
-
-/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
-#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
-#define OMAP3430ES2_EN_MMC3_SHIFT 30
-#define OMAP3430_EN_MSPRO (1 << 23)
-#define OMAP3430_EN_MSPRO_SHIFT 23
-#define OMAP3430_EN_HDQ (1 << 22)
-#define OMAP3430_EN_HDQ_SHIFT 22
-#define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)
-#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
-#define OMAP3430ES1_EN_D2D (1 << 3)
-#define OMAP3430ES1_EN_D2D_SHIFT 3
-#define OMAP3430_EN_SSI (1 << 0)
-#define OMAP3430_EN_SSI_SHIFT 0
-
-/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
-#define OMAP3430ES2_EN_USBTLL_SHIFT 2
-#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
-
-/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
-#define OMAP3430_EN_WDT2 (1 << 5)
-#define OMAP3430_EN_WDT2_SHIFT 5
-
-/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
-#define OMAP3430_EN_CAM (1 << 0)
-#define OMAP3430_EN_CAM_SHIFT 0
-
-/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
-#define OMAP3430_EN_WDT3 (1 << 12)
-#define OMAP3430_EN_WDT3_SHIFT 12
-
-/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
-#define OMAP3430_OVERRIDE_ENABLE (1 << 19)
-
-
-/* Bits specific to each register */
-
-/* CM_FCLKEN_IVA2 */
-#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
-
-/* CM_CLKEN_PLL_IVA2 */
-#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
-#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
-#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
-#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
-#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
-#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
-#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
-#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
-
-/* CM_IDLEST_IVA2 */
-#define OMAP3430_ST_IVA2 (1 << 0)
-
-/* CM_IDLEST_PLL_IVA2 */
-#define OMAP3430_ST_IVA2_CLK (1 << 0)
-
-/* CM_AUTOIDLE_PLL_IVA2 */
-#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
-#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
-
-/* CM_CLKSEL1_PLL_IVA2 */
-#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
-#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
-#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
-#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
-#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
-#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
-
-/* CM_CLKSEL2_PLL_IVA2 */
-#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
-#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
-
-/* CM_CLKSTCTRL_IVA2 */
-#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
-#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
-
-/* CM_CLKSTST_IVA2 */
-#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0)
-
-/* CM_REVISION specific bits */
-
-/* CM_SYSCONFIG specific bits */
-
-/* CM_CLKEN_PLL_MPU */
-#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
-#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
-#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
-#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
-#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
-#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
-#define OMAP3430_EN_MPU_DPLL_SHIFT 0
-#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
-
-/* CM_IDLEST_MPU */
-#define OMAP3430_ST_MPU (1 << 0)
-
-/* CM_IDLEST_PLL_MPU */
-#define OMAP3430_ST_MPU_CLK (1 << 0)
-
-/* CM_AUTOIDLE_PLL_MPU */
-#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
-#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
-
-/* CM_CLKSEL1_PLL_MPU */
-#define OMAP3430_MPU_CLK_SRC_SHIFT 19
-#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
-#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
-#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
-#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
-#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
-
-/* CM_CLKSEL2_PLL_MPU */
-#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
-#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
-
-/* CM_CLKSTCTRL_MPU */
-#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
-#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
-
-/* CM_CLKSTST_MPU */
-#define OMAP3430_CLKACTIVITY_MPU (1 << 0)
-
-/* CM_FCLKEN1_CORE specific bits */
-
-/* CM_ICLKEN1_CORE specific bits */
-#define OMAP3430_EN_ICR (1 << 29)
-#define OMAP3430_EN_ICR_SHIFT 29
-#define OMAP3430_EN_AES2 (1 << 28)
-#define OMAP3430_EN_AES2_SHIFT 28
-#define OMAP3430_EN_SHA12 (1 << 27)
-#define OMAP3430_EN_SHA12_SHIFT 27
-#define OMAP3430_EN_DES2 (1 << 26)
-#define OMAP3430_EN_DES2_SHIFT 26
-#define OMAP3430ES1_EN_FAC (1 << 8)
-#define OMAP3430ES1_EN_FAC_SHIFT 8
-#define OMAP3430_EN_MAILBOXES (1 << 7)
-#define OMAP3430_EN_MAILBOXES_SHIFT 7
-#define OMAP3430_EN_OMAPCTRL (1 << 6)
-#define OMAP3430_EN_OMAPCTRL_SHIFT 6
-#define OMAP3430_EN_SDRC (1 << 1)
-#define OMAP3430_EN_SDRC_SHIFT 1
-
-/* CM_ICLKEN2_CORE */
-#define OMAP3430_EN_PKA (1 << 4)
-#define OMAP3430_EN_PKA_SHIFT 4
-#define OMAP3430_EN_AES1 (1 << 3)
-#define OMAP3430_EN_AES1_SHIFT 3
-#define OMAP3430_EN_RNG (1 << 2)
-#define OMAP3430_EN_RNG_SHIFT 2
-#define OMAP3430_EN_SHA11 (1 << 1)
-#define OMAP3430_EN_SHA11_SHIFT 1
-#define OMAP3430_EN_DES1 (1 << 0)
-#define OMAP3430_EN_DES1_SHIFT 0
-
-/* CM_FCLKEN3_CORE specific bits */
-#define OMAP3430ES2_EN_TS_SHIFT 1
-#define OMAP3430ES2_EN_TS_MASK (1 << 1)
-#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
-#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
-
-/* CM_IDLEST1_CORE specific bits */
-#define OMAP3430_ST_ICR (1 << 29)
-#define OMAP3430_ST_AES2 (1 << 28)
-#define OMAP3430_ST_SHA12 (1 << 27)
-#define OMAP3430_ST_DES2 (1 << 26)
-#define OMAP3430_ST_MSPRO (1 << 23)
-#define OMAP3430_ST_HDQ (1 << 22)
-#define OMAP3430ES1_ST_FAC (1 << 8)
-#define OMAP3430ES1_ST_MAILBOXES (1 << 7)
-#define OMAP3430_ST_OMAPCTRL (1 << 6)
-#define OMAP3430_ST_SDMA (1 << 2)
-#define OMAP3430_ST_SDRC (1 << 1)
-#define OMAP3430_ST_SSI (1 << 0)
-
-/* CM_IDLEST2_CORE */
-#define OMAP3430_ST_PKA (1 << 4)
-#define OMAP3430_ST_AES1 (1 << 3)
-#define OMAP3430_ST_RNG (1 << 2)
-#define OMAP3430_ST_SHA11 (1 << 1)
-#define OMAP3430_ST_DES1 (1 << 0)
-
-/* CM_IDLEST3_CORE */
-#define OMAP3430_ST_USBTLL (1 << 2)
-#define OMAP3430_ST_USBTLL_SHIFT 2
-
-/* CM_AUTOIDLE1_CORE */
-#define OMAP3430_AUTO_AES2 (1 << 28)
-#define OMAP3430_AUTO_AES2_SHIFT 28
-#define OMAP3430_AUTO_SHA12 (1 << 27)
-#define OMAP3430_AUTO_SHA12_SHIFT 27
-#define OMAP3430_AUTO_DES2 (1 << 26)
-#define OMAP3430_AUTO_DES2_SHIFT 26
-#define OMAP3430_AUTO_MMC2 (1 << 25)
-#define OMAP3430_AUTO_MMC2_SHIFT 25
-#define OMAP3430_AUTO_MMC1 (1 << 24)
-#define OMAP3430_AUTO_MMC1_SHIFT 24
-#define OMAP3430_AUTO_MSPRO (1 << 23)
-#define OMAP3430_AUTO_MSPRO_SHIFT 23
-#define OMAP3430_AUTO_HDQ (1 << 22)
-#define OMAP3430_AUTO_HDQ_SHIFT 22
-#define OMAP3430_AUTO_MCSPI4 (1 << 21)
-#define OMAP3430_AUTO_MCSPI4_SHIFT 21
-#define OMAP3430_AUTO_MCSPI3 (1 << 20)
-#define OMAP3430_AUTO_MCSPI3_SHIFT 20
-#define OMAP3430_AUTO_MCSPI2 (1 << 19)
-#define OMAP3430_AUTO_MCSPI2_SHIFT 19
-#define OMAP3430_AUTO_MCSPI1 (1 << 18)
-#define OMAP3430_AUTO_MCSPI1_SHIFT 18
-#define OMAP3430_AUTO_I2C3 (1 << 17)
-#define OMAP3430_AUTO_I2C3_SHIFT 17
-#define OMAP3430_AUTO_I2C2 (1 << 16)
-#define OMAP3430_AUTO_I2C2_SHIFT 16
-#define OMAP3430_AUTO_I2C1 (1 << 15)
-#define OMAP3430_AUTO_I2C1_SHIFT 15
-#define OMAP3430_AUTO_UART2 (1 << 14)
-#define OMAP3430_AUTO_UART2_SHIFT 14
-#define OMAP3430_AUTO_UART1 (1 << 13)
-#define OMAP3430_AUTO_UART1_SHIFT 13
-#define OMAP3430_AUTO_GPT11 (1 << 12)
-#define OMAP3430_AUTO_GPT11_SHIFT 12
-#define OMAP3430_AUTO_GPT10 (1 << 11)
-#define OMAP3430_AUTO_GPT10_SHIFT 11
-#define OMAP3430_AUTO_MCBSP5 (1 << 10)
-#define OMAP3430_AUTO_MCBSP5_SHIFT 10
-#define OMAP3430_AUTO_MCBSP1 (1 << 9)
-#define OMAP3430_AUTO_MCBSP1_SHIFT 9
-#define OMAP3430ES1_AUTO_FAC (1 << 8)
-#define OMAP3430ES1_AUTO_FAC_SHIFT 8
-#define OMAP3430_AUTO_MAILBOXES (1 << 7)
-#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
-#define OMAP3430_AUTO_OMAPCTRL (1 << 6)
-#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
-#define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)
-#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
-#define OMAP3430_AUTO_HSOTGUSB (1 << 4)
-#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
-#define OMAP3430ES1_AUTO_D2D (1 << 3)
-#define OMAP3430ES1_AUTO_D2D_SHIFT 3
-#define OMAP3430_AUTO_SSI (1 << 0)
-#define OMAP3430_AUTO_SSI_SHIFT 0
-
-/* CM_AUTOIDLE2_CORE */
-#define OMAP3430_AUTO_PKA (1 << 4)
-#define OMAP3430_AUTO_PKA_SHIFT 4
-#define OMAP3430_AUTO_AES1 (1 << 3)
-#define OMAP3430_AUTO_AES1_SHIFT 3
-#define OMAP3430_AUTO_RNG (1 << 2)
-#define OMAP3430_AUTO_RNG_SHIFT 2
-#define OMAP3430_AUTO_SHA11 (1 << 1)
-#define OMAP3430_AUTO_SHA11_SHIFT 1
-#define OMAP3430_AUTO_DES1 (1 << 0)
-#define OMAP3430_AUTO_DES1_SHIFT 0
-
-/* CM_AUTOIDLE3_CORE */
-#define OMAP3430_AUTO_USBTLL (1 << 2)
-#define OMAP3430_AUTO_USBTLL_SHIFT 2
-
-/* CM_CLKSEL_CORE */
-#define OMAP3430_CLKSEL_SSI_SHIFT 8
-#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
-#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
-#define OMAP3430_CLKSEL_GPT11_SHIFT 7
-#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
-#define OMAP3430_CLKSEL_GPT10_SHIFT 6
-#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
-#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
-#define OMAP3430_CLKSEL_L4_SHIFT 2
-#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
-#define OMAP3430_CLKSEL_L3_SHIFT 0
-#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
-
-/* CM_CLKSTCTRL_CORE */
-#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
-#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
-#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
-#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
-#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
-#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
-
-/* CM_CLKSTST_CORE */
-#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2)
-#define OMAP3430_CLKACTIVITY_L4 (1 << 1)
-#define OMAP3430_CLKACTIVITY_L3 (1 << 0)
-
-/* CM_FCLKEN_GFX */
-#define OMAP3430ES1_EN_3D (1 << 2)
-#define OMAP3430ES1_EN_3D_SHIFT 2
-#define OMAP3430ES1_EN_2D (1 << 1)
-#define OMAP3430ES1_EN_2D_SHIFT 1
-
-/* CM_ICLKEN_GFX specific bits */
-
-/* CM_IDLEST_GFX specific bits */
-
-/* CM_CLKSEL_GFX specific bits */
-
-/* CM_SLEEPDEP_GFX specific bits */
-
-/* CM_CLKSTCTRL_GFX */
-#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
-#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
-
-/* CM_CLKSTST_GFX */
-#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0)
-
-/* CM_FCLKEN_SGX */
-#define OMAP3430ES2_EN_SGX_SHIFT 1
-#define OMAP3430ES2_EN_SGX_MASK (1 << 1)
-
-/* CM_CLKSEL_SGX */
-#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
-#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
-
-/* CM_FCLKEN_WKUP specific bits */
-#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
-
-/* CM_ICLKEN_WKUP specific bits */
-#define OMAP3430_EN_WDT1 (1 << 4)
-#define OMAP3430_EN_WDT1_SHIFT 4
-#define OMAP3430_EN_32KSYNC (1 << 2)
-#define OMAP3430_EN_32KSYNC_SHIFT 2
-
-/* CM_IDLEST_WKUP specific bits */
-#define OMAP3430_ST_WDT2 (1 << 5)
-#define OMAP3430_ST_WDT1 (1 << 4)
-#define OMAP3430_ST_32KSYNC (1 << 2)
-
-/* CM_AUTOIDLE_WKUP */
-#define OMAP3430_AUTO_WDT2 (1 << 5)
-#define OMAP3430_AUTO_WDT2_SHIFT 5
-#define OMAP3430_AUTO_WDT1 (1 << 4)
-#define OMAP3430_AUTO_WDT1_SHIFT 4
-#define OMAP3430_AUTO_GPIO1 (1 << 3)
-#define OMAP3430_AUTO_GPIO1_SHIFT 3
-#define OMAP3430_AUTO_32KSYNC (1 << 2)
-#define OMAP3430_AUTO_32KSYNC_SHIFT 2
-#define OMAP3430_AUTO_GPT12 (1 << 1)
-#define OMAP3430_AUTO_GPT12_SHIFT 1
-#define OMAP3430_AUTO_GPT1 (1 << 0)
-#define OMAP3430_AUTO_GPT1_SHIFT 0
-
-/* CM_CLKSEL_WKUP */
-#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
-#define OMAP3430_CLKSEL_RM_SHIFT 1
-#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
-#define OMAP3430_CLKSEL_GPT1_SHIFT 0
-#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
-
-/* CM_CLKEN_PLL */
-#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
-#define OMAP3430_PWRDN_CAM_SHIFT 30
-#define OMAP3430_PWRDN_DSS1_SHIFT 29
-#define OMAP3430_PWRDN_TV_SHIFT 28
-#define OMAP3430_PWRDN_96M_SHIFT 27
-#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
-#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
-#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
-#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
-#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
-#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
-#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
-#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
-#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
-#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
-#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
-#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
-#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
-#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
-#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
-#define OMAP3430_EN_CORE_DPLL_SHIFT 0
-#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
-
-/* CM_CLKEN2_PLL */
-#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
-#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
-#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
-#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
-#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
-#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
-#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
-
-/* CM_IDLEST_CKGEN */
-#define OMAP3430_ST_54M_CLK (1 << 5)
-#define OMAP3430_ST_12M_CLK (1 << 4)
-#define OMAP3430_ST_48M_CLK (1 << 3)
-#define OMAP3430_ST_96M_CLK (1 << 2)
-#define OMAP3430_ST_PERIPH_CLK (1 << 1)
-#define OMAP3430_ST_CORE_CLK (1 << 0)
-
-/* CM_IDLEST2_CKGEN */
-#define OMAP3430_ST_120M_CLK (1 << 1)
-#define OMAP3430_ST_PERIPH2_CLK (1 << 0)
-
-/* CM_AUTOIDLE_PLL */
-#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
-#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
-#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
-#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
-
-/* CM_CLKSEL1_PLL */
-/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
-#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
-#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
-#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
-#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
-#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
-#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
-#define OMAP3430_SOURCE_54M (1 << 5)
-#define OMAP3430_SOURCE_48M (1 << 3)
-
-/* CM_CLKSEL2_PLL */
-#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
-#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
-#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
-#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
-
-/* CM_CLKSEL3_PLL */
-#define OMAP3430_DIV_96M_SHIFT 0
-#define OMAP3430_DIV_96M_MASK (0x1f << 0)
-
-/* CM_CLKSEL4_PLL */
-#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
-#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
-#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
-#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
-
-/* CM_CLKSEL5_PLL */
-#define OMAP3430ES2_DIV_120M_SHIFT 0
-#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
-
-/* CM_CLKOUT_CTRL */
-#define OMAP3430_CLKOUT2_EN_SHIFT 7
-#define OMAP3430_CLKOUT2_EN (1 << 7)
-#define OMAP3430_CLKOUT2_DIV_SHIFT 3
-#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
-#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
-#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
-
-/* CM_FCLKEN_DSS */
-#define OMAP3430_EN_TV (1 << 2)
-#define OMAP3430_EN_TV_SHIFT 2
-#define OMAP3430_EN_DSS2 (1 << 1)
-#define OMAP3430_EN_DSS2_SHIFT 1
-#define OMAP3430_EN_DSS1 (1 << 0)
-#define OMAP3430_EN_DSS1_SHIFT 0
-
-/* CM_ICLKEN_DSS */
-#define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0)
-#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
-
-/* CM_IDLEST_DSS */
-#define OMAP3430_ST_DSS (1 << 0)
-
-/* CM_AUTOIDLE_DSS */
-#define OMAP3430_AUTO_DSS (1 << 0)
-#define OMAP3430_AUTO_DSS_SHIFT 0
-
-/* CM_CLKSEL_DSS */
-#define OMAP3430_CLKSEL_TV_SHIFT 8
-#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
-#define OMAP3430_CLKSEL_DSS1_SHIFT 0
-#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
-
-/* CM_SLEEPDEP_DSS specific bits */
-
-/* CM_CLKSTCTRL_DSS */
-#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
-#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
-
-/* CM_CLKSTST_DSS */
-#define OMAP3430_CLKACTIVITY_DSS (1 << 0)
-
-/* CM_FCLKEN_CAM specific bits */
-
-/* CM_ICLKEN_CAM specific bits */
-
-/* CM_IDLEST_CAM */
-#define OMAP3430_ST_CAM (1 << 0)
-
-/* CM_AUTOIDLE_CAM */
-#define OMAP3430_AUTO_CAM (1 << 0)
-#define OMAP3430_AUTO_CAM_SHIFT 0
-
-/* CM_CLKSEL_CAM */
-#define OMAP3430_CLKSEL_CAM_SHIFT 0
-#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
-
-/* CM_SLEEPDEP_CAM specific bits */
-
-/* CM_CLKSTCTRL_CAM */
-#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
-#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
-
-/* CM_CLKSTST_CAM */
-#define OMAP3430_CLKACTIVITY_CAM (1 << 0)
-
-/* CM_FCLKEN_PER specific bits */
-
-/* CM_ICLKEN_PER specific bits */
-
-/* CM_IDLEST_PER */
-#define OMAP3430_ST_WDT3 (1 << 12)
-#define OMAP3430_ST_MCBSP4 (1 << 2)
-#define OMAP3430_ST_MCBSP3 (1 << 1)
-#define OMAP3430_ST_MCBSP2 (1 << 0)
-
-/* CM_AUTOIDLE_PER */
-#define OMAP3430_AUTO_GPIO6 (1 << 17)
-#define OMAP3430_AUTO_GPIO6_SHIFT 17
-#define OMAP3430_AUTO_GPIO5 (1 << 16)
-#define OMAP3430_AUTO_GPIO5_SHIFT 16
-#define OMAP3430_AUTO_GPIO4 (1 << 15)
-#define OMAP3430_AUTO_GPIO4_SHIFT 15
-#define OMAP3430_AUTO_GPIO3 (1 << 14)
-#define OMAP3430_AUTO_GPIO3_SHIFT 14
-#define OMAP3430_AUTO_GPIO2 (1 << 13)
-#define OMAP3430_AUTO_GPIO2_SHIFT 13
-#define OMAP3430_AUTO_WDT3 (1 << 12)
-#define OMAP3430_AUTO_WDT3_SHIFT 12
-#define OMAP3430_AUTO_UART3 (1 << 11)
-#define OMAP3430_AUTO_UART3_SHIFT 11
-#define OMAP3430_AUTO_GPT9 (1 << 10)
-#define OMAP3430_AUTO_GPT9_SHIFT 10
-#define OMAP3430_AUTO_GPT8 (1 << 9)
-#define OMAP3430_AUTO_GPT8_SHIFT 9
-#define OMAP3430_AUTO_GPT7 (1 << 8)
-#define OMAP3430_AUTO_GPT7_SHIFT 8
-#define OMAP3430_AUTO_GPT6 (1 << 7)
-#define OMAP3430_AUTO_GPT6_SHIFT 7
-#define OMAP3430_AUTO_GPT5 (1 << 6)
-#define OMAP3430_AUTO_GPT5_SHIFT 6
-#define OMAP3430_AUTO_GPT4 (1 << 5)
-#define OMAP3430_AUTO_GPT4_SHIFT 5
-#define OMAP3430_AUTO_GPT3 (1 << 4)
-#define OMAP3430_AUTO_GPT3_SHIFT 4
-#define OMAP3430_AUTO_GPT2 (1 << 3)
-#define OMAP3430_AUTO_GPT2_SHIFT 3
-#define OMAP3430_AUTO_MCBSP4 (1 << 2)
-#define OMAP3430_AUTO_MCBSP4_SHIFT 2
-#define OMAP3430_AUTO_MCBSP3 (1 << 1)
-#define OMAP3430_AUTO_MCBSP3_SHIFT 1
-#define OMAP3430_AUTO_MCBSP2 (1 << 0)
-#define OMAP3430_AUTO_MCBSP2_SHIFT 0
-
-/* CM_CLKSEL_PER */
-#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
-#define OMAP3430_CLKSEL_GPT9_SHIFT 7
-#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
-#define OMAP3430_CLKSEL_GPT8_SHIFT 6
-#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
-#define OMAP3430_CLKSEL_GPT7_SHIFT 5
-#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
-#define OMAP3430_CLKSEL_GPT6_SHIFT 4
-#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
-#define OMAP3430_CLKSEL_GPT5_SHIFT 3
-#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
-#define OMAP3430_CLKSEL_GPT4_SHIFT 2
-#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
-#define OMAP3430_CLKSEL_GPT3_SHIFT 1
-#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
-#define OMAP3430_CLKSEL_GPT2_SHIFT 0
-
-/* CM_SLEEPDEP_PER specific bits */
-#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)
-
-/* CM_CLKSTCTRL_PER */
-#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
-#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
-
-/* CM_CLKSTST_PER */
-#define OMAP3430_CLKACTIVITY_PER (1 << 0)
-
-/* CM_CLKSEL1_EMU */
-#define OMAP3430_DIV_DPLL4_SHIFT 24
-#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
-#define OMAP3430_DIV_DPLL3_SHIFT 16
-#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
-#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
-#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
-#define OMAP3430_CLKSEL_PCLK_SHIFT 8
-#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
-#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
-#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
-#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
-#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
-#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
-#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
-#define OMAP3430_MUX_CTRL_SHIFT 0
-#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
-
-/* CM_CLKSTCTRL_EMU */
-#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
-#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
-
-/* CM_CLKSTST_EMU */
-#define OMAP3430_CLKACTIVITY_EMU (1 << 0)
-
-/* CM_CLKSEL2_EMU specific bits */
-#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
-#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
-#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
-#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
-
-/* CM_CLKSEL3_EMU specific bits */
-#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
-#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
-#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
-#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
-
-/* CM_POLCTRL */
-#define OMAP3430_CLKOUT2_POL (1 << 0)
-
-/* CM_IDLEST_NEON */
-#define OMAP3430_ST_NEON (1 << 0)
-
-/* CM_CLKSTCTRL_NEON */
-#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
-#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
-
-/* CM_FCLKEN_USBHOST */
-#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
-#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
-#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
-#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
-
-/* CM_ICLKEN_USBHOST */
-#define OMAP3430ES2_EN_USBHOST_SHIFT 0
-#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
-
-/* CM_IDLEST_USBHOST */
-
-/* CM_AUTOIDLE_USBHOST */
-#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
-#define OMAP3430ES2_AUTO_USBHOST_MASK (1<<0)
-
-/* CM_SLEEPDEP_USBHOST */
-#define OMAP3430ES2_EN_MPU_SHIFT 1
-#define OMAP3430ES2_EN_MPU_MASK (1<<1)
-#define OMAP3430ES2_EN_IVA2_SHIFT 2
-#define OMAP3430ES2_EN_IVA2_MASK (1<<2)
-
-/* CM_CLKSTCTRL_USBHOST */
-#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
-#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3<<0)
-
-
-
-#endif
diff --git a/drivers/usb/host/ehci-omap.h b/drivers/usb/host/ehci-omap.h
index 86cd962..f75eda7 100644
--- a/drivers/usb/host/ehci-omap.h
+++ b/drivers/usb/host/ehci-omap.h
@@ -25,7 +25,7 @@
#include <asm/hardware.h>
#include "../../../arch/arm/mach-omap2/cm.h"
-#include "../../../arch/arm/mach-omap2/cm_regbits_34xx.h"
+#include "../../../arch/arm/mach-omap2/cm-regbits-34xx.h"
/*
* OMAP USBHOST Register addresses: PHYSICAL ADDRESSES
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 7/10] ARM: OMAP2: Rename prcm_common.h to prcm-common.h
2008-03-12 10:45 ` [PATCH 6/10] ARM: OMAP3: Rename cm_regbits_34xx.h to cm-regbits-34xx.h Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 8/10] ARM: OMAP2: Rename prm_regbits_24xx.h to prm-regbits-24xx.h Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
Rename prcm_common.h to prcm-common.h
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/cm.h | 2 +-
arch/arm/mach-omap2/prcm-common.h | 317 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm_common.h | 317 -------------------------------------
arch/arm/mach-omap2/prm.h | 2 +-
4 files changed, 319 insertions(+), 319 deletions(-)
create mode 100644 arch/arm/mach-omap2/prcm-common.h
delete mode 100644 arch/arm/mach-omap2/prcm_common.h
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 1a8f289..8310e18 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -14,7 +14,7 @@
* published by the Free Software Foundation.
*/
-#include "prcm_common.h"
+#include "prcm-common.h"
#ifndef __ASSEMBLER__
#define OMAP_CM_REGADDR(module, reg) \
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
new file mode 100644
index 0000000..cacb340
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -0,0 +1,317 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+
+/*
+ * OMAP2/3 PRCM base and module definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* Module offsets from both CM_BASE & PRM_BASE */
+
+/*
+ * Offsets that are the same on 24xx and 34xx
+ *
+ * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ */
+#define OCP_MOD 0x000
+#define MPU_MOD 0x100
+#define CORE_MOD 0x200
+#define GFX_MOD 0x300
+#define WKUP_MOD 0x400
+#define PLL_MOD 0x500
+
+
+/* Chip-specific module offsets */
+#define OMAP24XX_DSP_MOD 0x800
+
+#define OMAP2430_MDM_MOD 0xc00
+
+/* IVA2 module is < base on 3430 */
+#define OMAP3430_IVA2_MOD -0x800
+#define OMAP3430ES2_SGX_MOD GFX_MOD
+#define OMAP3430_CCR_MOD PLL_MOD
+#define OMAP3430_DSS_MOD 0x600
+#define OMAP3430_CAM_MOD 0x700
+#define OMAP3430_PER_MOD 0x800
+#define OMAP3430_EMU_MOD 0x900
+#define OMAP3430_GR_MOD 0xa00
+#define OMAP3430_NEON_MOD 0xb00
+#define OMAP3430ES2_USBHOST_MOD 0xc00
+
+
+/* 24XX register bits shared between CM & PRM registers */
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP2420_EN_MMC_SHIFT 26
+#define OMAP2420_EN_MMC (1 << 26)
+#define OMAP24XX_EN_UART2_SHIFT 22
+#define OMAP24XX_EN_UART2 (1 << 22)
+#define OMAP24XX_EN_UART1_SHIFT 21
+#define OMAP24XX_EN_UART1 (1 << 21)
+#define OMAP24XX_EN_MCSPI2_SHIFT 18
+#define OMAP24XX_EN_MCSPI2 (1 << 18)
+#define OMAP24XX_EN_MCSPI1_SHIFT 17
+#define OMAP24XX_EN_MCSPI1 (1 << 17)
+#define OMAP24XX_EN_MCBSP2_SHIFT 16
+#define OMAP24XX_EN_MCBSP2 (1 << 16)
+#define OMAP24XX_EN_MCBSP1_SHIFT 15
+#define OMAP24XX_EN_MCBSP1 (1 << 15)
+#define OMAP24XX_EN_GPT12_SHIFT 14
+#define OMAP24XX_EN_GPT12 (1 << 14)
+#define OMAP24XX_EN_GPT11_SHIFT 13
+#define OMAP24XX_EN_GPT11 (1 << 13)
+#define OMAP24XX_EN_GPT10_SHIFT 12
+#define OMAP24XX_EN_GPT10 (1 << 12)
+#define OMAP24XX_EN_GPT9_SHIFT 11
+#define OMAP24XX_EN_GPT9 (1 << 11)
+#define OMAP24XX_EN_GPT8_SHIFT 10
+#define OMAP24XX_EN_GPT8 (1 << 10)
+#define OMAP24XX_EN_GPT7_SHIFT 9
+#define OMAP24XX_EN_GPT7 (1 << 9)
+#define OMAP24XX_EN_GPT6_SHIFT 8
+#define OMAP24XX_EN_GPT6 (1 << 8)
+#define OMAP24XX_EN_GPT5_SHIFT 7
+#define OMAP24XX_EN_GPT5 (1 << 7)
+#define OMAP24XX_EN_GPT4_SHIFT 6
+#define OMAP24XX_EN_GPT4 (1 << 6)
+#define OMAP24XX_EN_GPT3_SHIFT 5
+#define OMAP24XX_EN_GPT3 (1 << 5)
+#define OMAP24XX_EN_GPT2_SHIFT 4
+#define OMAP24XX_EN_GPT2 (1 << 4)
+#define OMAP2420_EN_VLYNQ_SHIFT 3
+#define OMAP2420_EN_VLYNQ (1 << 3)
+
+/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_GPIO5_SHIFT 10
+#define OMAP2430_EN_GPIO5 (1 << 10)
+#define OMAP2430_EN_MCSPI3_SHIFT 9
+#define OMAP2430_EN_MCSPI3 (1 << 9)
+#define OMAP2430_EN_MMCHS2_SHIFT 8
+#define OMAP2430_EN_MMCHS2 (1 << 8)
+#define OMAP2430_EN_MMCHS1_SHIFT 7
+#define OMAP2430_EN_MMCHS1 (1 << 7)
+#define OMAP24XX_EN_UART3_SHIFT 2
+#define OMAP24XX_EN_UART3 (1 << 2)
+#define OMAP24XX_EN_USB_SHIFT 0
+#define OMAP24XX_EN_USB (1 << 0)
+
+/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_MDM_INTC_SHIFT 11
+#define OMAP2430_EN_MDM_INTC (1 << 11)
+#define OMAP2430_EN_USBHS_SHIFT 6
+#define OMAP2430_EN_USBHS (1 << 6)
+
+/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+#define OMAP2420_ST_MMC (1 << 26)
+#define OMAP24XX_ST_UART2 (1 << 22)
+#define OMAP24XX_ST_UART1 (1 << 21)
+#define OMAP24XX_ST_MCSPI2 (1 << 18)
+#define OMAP24XX_ST_MCSPI1 (1 << 17)
+#define OMAP24XX_ST_GPT12 (1 << 14)
+#define OMAP24XX_ST_GPT11 (1 << 13)
+#define OMAP24XX_ST_GPT10 (1 << 12)
+#define OMAP24XX_ST_GPT9 (1 << 11)
+#define OMAP24XX_ST_GPT8 (1 << 10)
+#define OMAP24XX_ST_GPT7 (1 << 9)
+#define OMAP24XX_ST_GPT6 (1 << 8)
+#define OMAP24XX_ST_GPT5 (1 << 7)
+#define OMAP24XX_ST_GPT4 (1 << 6)
+#define OMAP24XX_ST_GPT3 (1 << 5)
+#define OMAP24XX_ST_GPT2 (1 << 4)
+#define OMAP2420_ST_VLYNQ (1 << 3)
+
+/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+#define OMAP2430_ST_MDM_INTC (1 << 11)
+#define OMAP2430_ST_GPIO5 (1 << 10)
+#define OMAP2430_ST_MCSPI3 (1 << 9)
+#define OMAP2430_ST_MMCHS2 (1 << 8)
+#define OMAP2430_ST_MMCHS1 (1 << 7)
+#define OMAP2430_ST_USBHS (1 << 6)
+#define OMAP24XX_ST_UART3 (1 << 2)
+#define OMAP24XX_ST_USB (1 << 0)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP24XX_EN_GPIOS_SHIFT 2
+#define OMAP24XX_EN_GPIOS (1 << 2)
+#define OMAP24XX_EN_GPT1_SHIFT 0
+#define OMAP24XX_EN_GPT1 (1 << 0)
+
+/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+#define OMAP24XX_ST_GPIOS (1 << 2)
+#define OMAP24XX_ST_GPT1 (1 << 0)
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM (1 << 0)
+
+
+/* 3430 register bits shared between CM & PRM registers */
+
+/* CM_REVISION, PRM_REVISION shared bits */
+#define OMAP3430_REV_SHIFT 0
+#define OMAP3430_REV_MASK (0xff << 0)
+
+/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+#define OMAP3430_AUTOIDLE (1 << 0)
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC2 (1 << 25)
+#define OMAP3430_EN_MMC2_SHIFT 25
+#define OMAP3430_EN_MMC1 (1 << 24)
+#define OMAP3430_EN_MMC1_SHIFT 24
+#define OMAP3430_EN_MCSPI4 (1 << 21)
+#define OMAP3430_EN_MCSPI4_SHIFT 21
+#define OMAP3430_EN_MCSPI3 (1 << 20)
+#define OMAP3430_EN_MCSPI3_SHIFT 20
+#define OMAP3430_EN_MCSPI2 (1 << 19)
+#define OMAP3430_EN_MCSPI2_SHIFT 19
+#define OMAP3430_EN_MCSPI1 (1 << 18)
+#define OMAP3430_EN_MCSPI1_SHIFT 18
+#define OMAP3430_EN_I2C3 (1 << 17)
+#define OMAP3430_EN_I2C3_SHIFT 17
+#define OMAP3430_EN_I2C2 (1 << 16)
+#define OMAP3430_EN_I2C2_SHIFT 16
+#define OMAP3430_EN_I2C1 (1 << 15)
+#define OMAP3430_EN_I2C1_SHIFT 15
+#define OMAP3430_EN_UART2 (1 << 14)
+#define OMAP3430_EN_UART2_SHIFT 14
+#define OMAP3430_EN_UART1 (1 << 13)
+#define OMAP3430_EN_UART1_SHIFT 13
+#define OMAP3430_EN_GPT11 (1 << 12)
+#define OMAP3430_EN_GPT11_SHIFT 12
+#define OMAP3430_EN_GPT10 (1 << 11)
+#define OMAP3430_EN_GPT10_SHIFT 11
+#define OMAP3430_EN_MCBSP5 (1 << 10)
+#define OMAP3430_EN_MCBSP5_SHIFT 10
+#define OMAP3430_EN_MCBSP1 (1 << 9)
+#define OMAP3430_EN_MCBSP1_SHIFT 9
+#define OMAP3430_EN_FSHOSTUSB (1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
+#define OMAP3430_EN_D2D (1 << 3)
+#define OMAP3430_EN_D2D_SHIFT 3
+
+/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_HSOTGUSB (1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT 4
+
+/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC2 (1 << 25)
+#define OMAP3430_ST_MMC1 (1 << 24)
+#define OMAP3430_ST_MCSPI4 (1 << 21)
+#define OMAP3430_ST_MCSPI3 (1 << 20)
+#define OMAP3430_ST_MCSPI2 (1 << 19)
+#define OMAP3430_ST_MCSPI1 (1 << 18)
+#define OMAP3430_ST_I2C3 (1 << 17)
+#define OMAP3430_ST_I2C2 (1 << 16)
+#define OMAP3430_ST_I2C1 (1 << 15)
+#define OMAP3430_ST_UART2 (1 << 14)
+#define OMAP3430_ST_UART1 (1 << 13)
+#define OMAP3430_ST_GPT11 (1 << 12)
+#define OMAP3430_ST_GPT10 (1 << 11)
+#define OMAP3430_ST_MCBSP5 (1 << 10)
+#define OMAP3430_ST_MCBSP1 (1 << 9)
+#define OMAP3430_ST_FSHOSTUSB (1 << 5)
+#define OMAP3430_ST_HSOTGUSB (1 << 4)
+#define OMAP3430_ST_D2D (1 << 3)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPIO1 (1 << 3)
+#define OMAP3430_EN_GPIO1_SHIFT 3
+#define OMAP3430_EN_GPT1 (1 << 0)
+#define OMAP3430_EN_GPT1_SHIFT 0
+
+/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_SR2 (1 << 7)
+#define OMAP3430_EN_SR2_SHIFT 7
+#define OMAP3430_EN_SR1 (1 << 6)
+#define OMAP3430_EN_SR1_SHIFT 6
+
+/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPT12 (1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT 1
+
+/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
+#define OMAP3430_ST_SR2 (1 << 7)
+#define OMAP3430_ST_SR1 (1 << 6)
+#define OMAP3430_ST_GPIO1 (1 << 3)
+#define OMAP3430_ST_GPT12 (1 << 1)
+#define OMAP3430_ST_GPT1 (1 << 0)
+
+/*
+ * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
+ * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
+ * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
+ */
+#define OMAP3430_EN_MPU (1 << 1)
+#define OMAP3430_EN_MPU_SHIFT 1
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+#define OMAP3430_EN_GPIO6 (1 << 17)
+#define OMAP3430_EN_GPIO6_SHIFT 17
+#define OMAP3430_EN_GPIO5 (1 << 16)
+#define OMAP3430_EN_GPIO5_SHIFT 16
+#define OMAP3430_EN_GPIO4 (1 << 15)
+#define OMAP3430_EN_GPIO4_SHIFT 15
+#define OMAP3430_EN_GPIO3 (1 << 14)
+#define OMAP3430_EN_GPIO3_SHIFT 14
+#define OMAP3430_EN_GPIO2 (1 << 13)
+#define OMAP3430_EN_GPIO2_SHIFT 13
+#define OMAP3430_EN_UART3 (1 << 11)
+#define OMAP3430_EN_UART3_SHIFT 11
+#define OMAP3430_EN_GPT9 (1 << 10)
+#define OMAP3430_EN_GPT9_SHIFT 10
+#define OMAP3430_EN_GPT8 (1 << 9)
+#define OMAP3430_EN_GPT8_SHIFT 9
+#define OMAP3430_EN_GPT7 (1 << 8)
+#define OMAP3430_EN_GPT7_SHIFT 8
+#define OMAP3430_EN_GPT6 (1 << 7)
+#define OMAP3430_EN_GPT6_SHIFT 7
+#define OMAP3430_EN_GPT5 (1 << 6)
+#define OMAP3430_EN_GPT5_SHIFT 6
+#define OMAP3430_EN_GPT4 (1 << 5)
+#define OMAP3430_EN_GPT4_SHIFT 5
+#define OMAP3430_EN_GPT3 (1 << 4)
+#define OMAP3430_EN_GPT3_SHIFT 4
+#define OMAP3430_EN_GPT2 (1 << 3)
+#define OMAP3430_EN_GPT2_SHIFT 3
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
+/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
+ * be ST_* bits instead? */
+#define OMAP3430_EN_MCBSP4 (1 << 2)
+#define OMAP3430_EN_MCBSP4_SHIFT 2
+#define OMAP3430_EN_MCBSP3 (1 << 1)
+#define OMAP3430_EN_MCBSP3_SHIFT 1
+#define OMAP3430_EN_MCBSP2 (1 << 0)
+#define OMAP3430_EN_MCBSP2_SHIFT 0
+
+/* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3430_ST_GPIO6 (1 << 17)
+#define OMAP3430_ST_GPIO5 (1 << 16)
+#define OMAP3430_ST_GPIO4 (1 << 15)
+#define OMAP3430_ST_GPIO3 (1 << 14)
+#define OMAP3430_ST_GPIO2 (1 << 13)
+#define OMAP3430_ST_UART3 (1 << 11)
+#define OMAP3430_ST_GPT9 (1 << 10)
+#define OMAP3430_ST_GPT8 (1 << 9)
+#define OMAP3430_ST_GPT7 (1 << 8)
+#define OMAP3430_ST_GPT6 (1 << 7)
+#define OMAP3430_ST_GPT5 (1 << 6)
+#define OMAP3430_ST_GPT4 (1 << 5)
+#define OMAP3430_ST_GPT3 (1 << 4)
+#define OMAP3430_ST_GPT2 (1 << 3)
+
+/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
+#define OMAP3430_EN_CORE (1 << 0)
+
+#endif
+
diff --git a/arch/arm/mach-omap2/prcm_common.h b/arch/arm/mach-omap2/prcm_common.h
deleted file mode 100644
index cacb340..0000000
--- a/arch/arm/mach-omap2/prcm_common.h
+++ /dev/null
@@ -1,317 +0,0 @@
-#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
-#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
-
-/*
- * OMAP2/3 PRCM base and module definitions
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-/* Module offsets from both CM_BASE & PRM_BASE */
-
-/*
- * Offsets that are the same on 24xx and 34xx
- *
- * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
- * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
- */
-#define OCP_MOD 0x000
-#define MPU_MOD 0x100
-#define CORE_MOD 0x200
-#define GFX_MOD 0x300
-#define WKUP_MOD 0x400
-#define PLL_MOD 0x500
-
-
-/* Chip-specific module offsets */
-#define OMAP24XX_DSP_MOD 0x800
-
-#define OMAP2430_MDM_MOD 0xc00
-
-/* IVA2 module is < base on 3430 */
-#define OMAP3430_IVA2_MOD -0x800
-#define OMAP3430ES2_SGX_MOD GFX_MOD
-#define OMAP3430_CCR_MOD PLL_MOD
-#define OMAP3430_DSS_MOD 0x600
-#define OMAP3430_CAM_MOD 0x700
-#define OMAP3430_PER_MOD 0x800
-#define OMAP3430_EMU_MOD 0x900
-#define OMAP3430_GR_MOD 0xa00
-#define OMAP3430_NEON_MOD 0xb00
-#define OMAP3430ES2_USBHOST_MOD 0xc00
-
-
-/* 24XX register bits shared between CM & PRM registers */
-
-/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP2420_EN_MMC_SHIFT 26
-#define OMAP2420_EN_MMC (1 << 26)
-#define OMAP24XX_EN_UART2_SHIFT 22
-#define OMAP24XX_EN_UART2 (1 << 22)
-#define OMAP24XX_EN_UART1_SHIFT 21
-#define OMAP24XX_EN_UART1 (1 << 21)
-#define OMAP24XX_EN_MCSPI2_SHIFT 18
-#define OMAP24XX_EN_MCSPI2 (1 << 18)
-#define OMAP24XX_EN_MCSPI1_SHIFT 17
-#define OMAP24XX_EN_MCSPI1 (1 << 17)
-#define OMAP24XX_EN_MCBSP2_SHIFT 16
-#define OMAP24XX_EN_MCBSP2 (1 << 16)
-#define OMAP24XX_EN_MCBSP1_SHIFT 15
-#define OMAP24XX_EN_MCBSP1 (1 << 15)
-#define OMAP24XX_EN_GPT12_SHIFT 14
-#define OMAP24XX_EN_GPT12 (1 << 14)
-#define OMAP24XX_EN_GPT11_SHIFT 13
-#define OMAP24XX_EN_GPT11 (1 << 13)
-#define OMAP24XX_EN_GPT10_SHIFT 12
-#define OMAP24XX_EN_GPT10 (1 << 12)
-#define OMAP24XX_EN_GPT9_SHIFT 11
-#define OMAP24XX_EN_GPT9 (1 << 11)
-#define OMAP24XX_EN_GPT8_SHIFT 10
-#define OMAP24XX_EN_GPT8 (1 << 10)
-#define OMAP24XX_EN_GPT7_SHIFT 9
-#define OMAP24XX_EN_GPT7 (1 << 9)
-#define OMAP24XX_EN_GPT6_SHIFT 8
-#define OMAP24XX_EN_GPT6 (1 << 8)
-#define OMAP24XX_EN_GPT5_SHIFT 7
-#define OMAP24XX_EN_GPT5 (1 << 7)
-#define OMAP24XX_EN_GPT4_SHIFT 6
-#define OMAP24XX_EN_GPT4 (1 << 6)
-#define OMAP24XX_EN_GPT3_SHIFT 5
-#define OMAP24XX_EN_GPT3 (1 << 5)
-#define OMAP24XX_EN_GPT2_SHIFT 4
-#define OMAP24XX_EN_GPT2 (1 << 4)
-#define OMAP2420_EN_VLYNQ_SHIFT 3
-#define OMAP2420_EN_VLYNQ (1 << 3)
-
-/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
-#define OMAP2430_EN_GPIO5_SHIFT 10
-#define OMAP2430_EN_GPIO5 (1 << 10)
-#define OMAP2430_EN_MCSPI3_SHIFT 9
-#define OMAP2430_EN_MCSPI3 (1 << 9)
-#define OMAP2430_EN_MMCHS2_SHIFT 8
-#define OMAP2430_EN_MMCHS2 (1 << 8)
-#define OMAP2430_EN_MMCHS1_SHIFT 7
-#define OMAP2430_EN_MMCHS1 (1 << 7)
-#define OMAP24XX_EN_UART3_SHIFT 2
-#define OMAP24XX_EN_UART3 (1 << 2)
-#define OMAP24XX_EN_USB_SHIFT 0
-#define OMAP24XX_EN_USB (1 << 0)
-
-/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
-#define OMAP2430_EN_MDM_INTC_SHIFT 11
-#define OMAP2430_EN_MDM_INTC (1 << 11)
-#define OMAP2430_EN_USBHS_SHIFT 6
-#define OMAP2430_EN_USBHS (1 << 6)
-
-/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
-#define OMAP2420_ST_MMC (1 << 26)
-#define OMAP24XX_ST_UART2 (1 << 22)
-#define OMAP24XX_ST_UART1 (1 << 21)
-#define OMAP24XX_ST_MCSPI2 (1 << 18)
-#define OMAP24XX_ST_MCSPI1 (1 << 17)
-#define OMAP24XX_ST_GPT12 (1 << 14)
-#define OMAP24XX_ST_GPT11 (1 << 13)
-#define OMAP24XX_ST_GPT10 (1 << 12)
-#define OMAP24XX_ST_GPT9 (1 << 11)
-#define OMAP24XX_ST_GPT8 (1 << 10)
-#define OMAP24XX_ST_GPT7 (1 << 9)
-#define OMAP24XX_ST_GPT6 (1 << 8)
-#define OMAP24XX_ST_GPT5 (1 << 7)
-#define OMAP24XX_ST_GPT4 (1 << 6)
-#define OMAP24XX_ST_GPT3 (1 << 5)
-#define OMAP24XX_ST_GPT2 (1 << 4)
-#define OMAP2420_ST_VLYNQ (1 << 3)
-
-/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
-#define OMAP2430_ST_MDM_INTC (1 << 11)
-#define OMAP2430_ST_GPIO5 (1 << 10)
-#define OMAP2430_ST_MCSPI3 (1 << 9)
-#define OMAP2430_ST_MMCHS2 (1 << 8)
-#define OMAP2430_ST_MMCHS1 (1 << 7)
-#define OMAP2430_ST_USBHS (1 << 6)
-#define OMAP24XX_ST_UART3 (1 << 2)
-#define OMAP24XX_ST_USB (1 << 0)
-
-/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP24XX_EN_GPIOS_SHIFT 2
-#define OMAP24XX_EN_GPIOS (1 << 2)
-#define OMAP24XX_EN_GPT1_SHIFT 0
-#define OMAP24XX_EN_GPT1 (1 << 0)
-
-/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS (1 << 2)
-#define OMAP24XX_ST_GPT1 (1 << 0)
-
-/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM (1 << 0)
-
-
-/* 3430 register bits shared between CM & PRM registers */
-
-/* CM_REVISION, PRM_REVISION shared bits */
-#define OMAP3430_REV_SHIFT 0
-#define OMAP3430_REV_MASK (0xff << 0)
-
-/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
-#define OMAP3430_AUTOIDLE (1 << 0)
-
-/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP3430_EN_MMC2 (1 << 25)
-#define OMAP3430_EN_MMC2_SHIFT 25
-#define OMAP3430_EN_MMC1 (1 << 24)
-#define OMAP3430_EN_MMC1_SHIFT 24
-#define OMAP3430_EN_MCSPI4 (1 << 21)
-#define OMAP3430_EN_MCSPI4_SHIFT 21
-#define OMAP3430_EN_MCSPI3 (1 << 20)
-#define OMAP3430_EN_MCSPI3_SHIFT 20
-#define OMAP3430_EN_MCSPI2 (1 << 19)
-#define OMAP3430_EN_MCSPI2_SHIFT 19
-#define OMAP3430_EN_MCSPI1 (1 << 18)
-#define OMAP3430_EN_MCSPI1_SHIFT 18
-#define OMAP3430_EN_I2C3 (1 << 17)
-#define OMAP3430_EN_I2C3_SHIFT 17
-#define OMAP3430_EN_I2C2 (1 << 16)
-#define OMAP3430_EN_I2C2_SHIFT 16
-#define OMAP3430_EN_I2C1 (1 << 15)
-#define OMAP3430_EN_I2C1_SHIFT 15
-#define OMAP3430_EN_UART2 (1 << 14)
-#define OMAP3430_EN_UART2_SHIFT 14
-#define OMAP3430_EN_UART1 (1 << 13)
-#define OMAP3430_EN_UART1_SHIFT 13
-#define OMAP3430_EN_GPT11 (1 << 12)
-#define OMAP3430_EN_GPT11_SHIFT 12
-#define OMAP3430_EN_GPT10 (1 << 11)
-#define OMAP3430_EN_GPT10_SHIFT 11
-#define OMAP3430_EN_MCBSP5 (1 << 10)
-#define OMAP3430_EN_MCBSP5_SHIFT 10
-#define OMAP3430_EN_MCBSP1 (1 << 9)
-#define OMAP3430_EN_MCBSP1_SHIFT 9
-#define OMAP3430_EN_FSHOSTUSB (1 << 5)
-#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
-#define OMAP3430_EN_D2D (1 << 3)
-#define OMAP3430_EN_D2D_SHIFT 3
-
-/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
-#define OMAP3430_EN_HSOTGUSB (1 << 4)
-#define OMAP3430_EN_HSOTGUSB_SHIFT 4
-
-/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
-#define OMAP3430_ST_MMC2 (1 << 25)
-#define OMAP3430_ST_MMC1 (1 << 24)
-#define OMAP3430_ST_MCSPI4 (1 << 21)
-#define OMAP3430_ST_MCSPI3 (1 << 20)
-#define OMAP3430_ST_MCSPI2 (1 << 19)
-#define OMAP3430_ST_MCSPI1 (1 << 18)
-#define OMAP3430_ST_I2C3 (1 << 17)
-#define OMAP3430_ST_I2C2 (1 << 16)
-#define OMAP3430_ST_I2C1 (1 << 15)
-#define OMAP3430_ST_UART2 (1 << 14)
-#define OMAP3430_ST_UART1 (1 << 13)
-#define OMAP3430_ST_GPT11 (1 << 12)
-#define OMAP3430_ST_GPT10 (1 << 11)
-#define OMAP3430_ST_MCBSP5 (1 << 10)
-#define OMAP3430_ST_MCBSP1 (1 << 9)
-#define OMAP3430_ST_FSHOSTUSB (1 << 5)
-#define OMAP3430_ST_HSOTGUSB (1 << 4)
-#define OMAP3430_ST_D2D (1 << 3)
-
-/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_GPIO1 (1 << 3)
-#define OMAP3430_EN_GPIO1_SHIFT 3
-#define OMAP3430_EN_GPT1 (1 << 0)
-#define OMAP3430_EN_GPT1_SHIFT 0
-
-/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_SR2 (1 << 7)
-#define OMAP3430_EN_SR2_SHIFT 7
-#define OMAP3430_EN_SR1 (1 << 6)
-#define OMAP3430_EN_SR1_SHIFT 6
-
-/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
-#define OMAP3430_EN_GPT12 (1 << 1)
-#define OMAP3430_EN_GPT12_SHIFT 1
-
-/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
-#define OMAP3430_ST_SR2 (1 << 7)
-#define OMAP3430_ST_SR1 (1 << 6)
-#define OMAP3430_ST_GPIO1 (1 << 3)
-#define OMAP3430_ST_GPT12 (1 << 1)
-#define OMAP3430_ST_GPT1 (1 << 0)
-
-/*
- * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
- * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
- * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
- */
-#define OMAP3430_EN_MPU (1 << 1)
-#define OMAP3430_EN_MPU_SHIFT 1
-
-/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
-#define OMAP3430_EN_GPIO6 (1 << 17)
-#define OMAP3430_EN_GPIO6_SHIFT 17
-#define OMAP3430_EN_GPIO5 (1 << 16)
-#define OMAP3430_EN_GPIO5_SHIFT 16
-#define OMAP3430_EN_GPIO4 (1 << 15)
-#define OMAP3430_EN_GPIO4_SHIFT 15
-#define OMAP3430_EN_GPIO3 (1 << 14)
-#define OMAP3430_EN_GPIO3_SHIFT 14
-#define OMAP3430_EN_GPIO2 (1 << 13)
-#define OMAP3430_EN_GPIO2_SHIFT 13
-#define OMAP3430_EN_UART3 (1 << 11)
-#define OMAP3430_EN_UART3_SHIFT 11
-#define OMAP3430_EN_GPT9 (1 << 10)
-#define OMAP3430_EN_GPT9_SHIFT 10
-#define OMAP3430_EN_GPT8 (1 << 9)
-#define OMAP3430_EN_GPT8_SHIFT 9
-#define OMAP3430_EN_GPT7 (1 << 8)
-#define OMAP3430_EN_GPT7_SHIFT 8
-#define OMAP3430_EN_GPT6 (1 << 7)
-#define OMAP3430_EN_GPT6_SHIFT 7
-#define OMAP3430_EN_GPT5 (1 << 6)
-#define OMAP3430_EN_GPT5_SHIFT 6
-#define OMAP3430_EN_GPT4 (1 << 5)
-#define OMAP3430_EN_GPT4_SHIFT 5
-#define OMAP3430_EN_GPT3 (1 << 4)
-#define OMAP3430_EN_GPT3_SHIFT 4
-#define OMAP3430_EN_GPT2 (1 << 3)
-#define OMAP3430_EN_GPT2_SHIFT 3
-
-/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
-/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
- * be ST_* bits instead? */
-#define OMAP3430_EN_MCBSP4 (1 << 2)
-#define OMAP3430_EN_MCBSP4_SHIFT 2
-#define OMAP3430_EN_MCBSP3 (1 << 1)
-#define OMAP3430_EN_MCBSP3_SHIFT 1
-#define OMAP3430_EN_MCBSP2 (1 << 0)
-#define OMAP3430_EN_MCBSP2_SHIFT 0
-
-/* CM_IDLEST_PER, PM_WKST_PER shared bits */
-#define OMAP3430_ST_GPIO6 (1 << 17)
-#define OMAP3430_ST_GPIO5 (1 << 16)
-#define OMAP3430_ST_GPIO4 (1 << 15)
-#define OMAP3430_ST_GPIO3 (1 << 14)
-#define OMAP3430_ST_GPIO2 (1 << 13)
-#define OMAP3430_ST_UART3 (1 << 11)
-#define OMAP3430_ST_GPT9 (1 << 10)
-#define OMAP3430_ST_GPT8 (1 << 9)
-#define OMAP3430_ST_GPT7 (1 << 8)
-#define OMAP3430_ST_GPT6 (1 << 7)
-#define OMAP3430_ST_GPT5 (1 << 6)
-#define OMAP3430_ST_GPT4 (1 << 5)
-#define OMAP3430_ST_GPT3 (1 << 4)
-#define OMAP3430_ST_GPT2 (1 << 3)
-
-/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
-#define OMAP3430_EN_CORE (1 << 0)
-
-#endif
-
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index fd8c81d..fcc1aa0 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -16,7 +16,7 @@
#include <linux/kernel.h>
#include <asm/io.h>
-#include "prcm_common.h"
+#include "prcm-common.h"
#define OMAP_PRM_REGADDR(module, reg) \
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 8/10] ARM: OMAP2: Rename prm_regbits_24xx.h to prm-regbits-24xx.h
2008-03-12 10:45 ` [PATCH 7/10] ARM: OMAP2: Rename prcm_common.h to prcm-common.h Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 9/10] ARM: OMAP3: Rename prm_regbits_34xx.h to prm-regbits-34xx.h Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
Rename prm_regbits_24xx.h to prm-regbits-24xx.h
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock.c | 2 +-
arch/arm/mach-omap2/clock24xx.c | 2 +-
arch/arm/mach-omap2/clock24xx.h | 2 +-
arch/arm/mach-omap2/pm.c | 2 +-
arch/arm/mach-omap2/prcm.c | 2 +-
arch/arm/mach-omap2/prm-regbits-24xx.h | 279 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prm_regbits_24xx.h | 279 --------------------------------
drivers/dsp/dspgateway/dsp.h | 2 +-
8 files changed, 285 insertions(+), 285 deletions(-)
create mode 100644 arch/arm/mach-omap2/prm-regbits-24xx.h
delete mode 100644 arch/arm/mach-omap2/prm_regbits_24xx.h
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 3f107d4..5cf88b7 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -40,7 +40,7 @@
#include "sdrc.h"
#include "clock.h"
#include "prm.h"
-#include "prm_regbits_24xx.h"
+#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index e8d0fe3..35a255d 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -36,7 +36,7 @@
#include "clock.h"
#include "clock24xx.h"
#include "prm.h"
-#include "prm_regbits_24xx.h"
+#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 2b4a6a6..be95bf7 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -25,7 +25,7 @@
#include "prm.h"
#include "cm.h"
-#include "prm_regbits_24xx.h"
+#include "prm-regbits-24xx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 095b910..3a455e8 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -47,7 +47,7 @@
#include <asm/arch/board.h>
#include "prm.h"
-#include "prm_regbits_24xx.h"
+#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 9857ba7..9ff918a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -18,7 +18,7 @@
#include <linux/clk.h>
#include "prm.h"
-#include "prm_regbits_24xx.h"
+#include "prm-regbits-24xx.h"
extern void omap2_clk_prepare_for_reboot(void);
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
new file mode 100644
index 0000000..c6d17a3
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -0,0 +1,279 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Power/Reset Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Bits shared between registers */
+
+/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_ST (1 << 2)
+#define OMAP24XX_WKUP2_ST (1 << 1)
+#define OMAP24XX_WKUP1_ST (1 << 0)
+
+/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_EN (1 << 2)
+#define OMAP24XX_WKUP2_EN (1 << 1)
+#define OMAP24XX_WKUP1_EN (1 << 0)
+
+/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
+#define OMAP24XX_EN_MPU (1 << 1)
+#define OMAP24XX_EN_CORE (1 << 0)
+
+/*
+ * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
+ * shared bits
+ */
+#define OMAP24XX_MEMONSTATE_SHIFT 10
+#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
+#define OMAP24XX_MEMRETSTATE (1 << 3)
+
+/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
+#define OMAP24XX_FORCESTATE (1 << 18)
+
+/*
+ * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
+ * PM_PWSTST_MDM shared bits
+ */
+#define OMAP24XX_CLKACTIVITY (1 << 19)
+
+/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
+#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
+#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
+
+/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
+#define OMAP2430_MEMSTATEST_SHIFT 10
+#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
+
+/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
+#define OMAP24XX_POWERSTATEST_SHIFT 0
+#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
+
+
+/* Bits specific to each register */
+
+/* PRCM_REVISION */
+#define OMAP24XX_REV_SHIFT 0
+#define OMAP24XX_REV_MASK (0xff << 0)
+
+/* PRCM_SYSCONFIG */
+#define OMAP24XX_AUTOIDLE (1 << 0)
+
+/* PRCM_IRQSTATUS_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_ST (1 << 6)
+#define OMAP24XX_TRANSITION_ST (1 << 5)
+#define OMAP24XX_EVGENOFF_ST (1 << 4)
+#define OMAP24XX_EVGENON_ST (1 << 3)
+
+/* PRCM_IRQENABLE_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_EN (1 << 6)
+#define OMAP24XX_TRANSITION_EN (1 << 5)
+#define OMAP24XX_EVGENOFF_EN (1 << 4)
+#define OMAP24XX_EVGENON_EN (1 << 3)
+
+/* PRCM_VOLTCTRL */
+#define OMAP24XX_AUTO_EXTVOLT (1 << 15)
+#define OMAP24XX_FORCE_EXTVOLT (1 << 14)
+#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
+#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
+#define OMAP24XX_MEMRETCTRL (1 << 8)
+#define OMAP24XX_SETRET_LEVEL_SHIFT 6
+#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
+#define OMAP24XX_VOLT_LEVEL_SHIFT 0
+#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
+
+/* PRCM_VOLTST */
+#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
+#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
+
+/* PRCM_CLKSRC_CTRL specific bits */
+
+/* PRCM_CLKOUT_CTRL */
+#define OMAP2420_CLKOUT2_EN_SHIFT 15
+#define OMAP2420_CLKOUT2_EN (1 << 15)
+#define OMAP2420_CLKOUT2_DIV_SHIFT 11
+#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
+#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
+#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
+#define OMAP24XX_CLKOUT_EN_SHIFT 7
+#define OMAP24XX_CLKOUT_EN (1 << 7)
+#define OMAP24XX_CLKOUT_DIV_SHIFT 3
+#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
+#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
+#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
+
+/* PRCM_CLKEMUL_CTRL */
+#define OMAP24XX_EMULATION_EN_SHIFT 0
+#define OMAP24XX_EMULATION_EN (1 << 0)
+
+/* PRCM_CLKCFG_CTRL */
+#define OMAP24XX_VALID_CONFIG (1 << 0)
+
+/* PRCM_CLKCFG_STATUS */
+#define OMAP24XX_CONFIG_STATUS (1 << 0)
+
+/* PRCM_VOLTSETUP specific bits */
+
+/* PRCM_CLKSSETUP specific bits */
+
+/* PRCM_POLCTRL */
+#define OMAP2420_CLKOUT2_POL (1 << 10)
+#define OMAP24XX_CLKOUT_POL (1 << 9)
+#define OMAP24XX_CLKREQ_POL (1 << 8)
+#define OMAP2430_USE_POWEROK (1 << 2)
+#define OMAP2430_POWEROK_POL (1 << 1)
+#define OMAP24XX_EXTVOL_POL (1 << 0)
+
+/* RM_RSTST_MPU specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5)
+#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2)
+
+/* PM_EVGENCTRL_MPU specific bits */
+
+/* PM_EVEGENONTIM_MPU specific bits */
+
+/* PM_EVEGENOFFTIM_MPU specific bits */
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP2430_FORCESTATE (1 << 18)
+
+/* PM_PWSTST_MPU specific bits */
+/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_WKEN2_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits*/
+
+/* PM_WKST2_CORE specific bits */
+
+/* PM_WKDEP_CORE specific bits*/
+#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5)
+#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3)
+#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2)
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP24XX_MEMORYCHANGE (1 << 20)
+#define OMAP24XX_MEM3ONSTATE_SHIFT 14
+#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
+#define OMAP24XX_MEM2ONSTATE_SHIFT 12
+#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
+#define OMAP24XX_MEM1ONSTATE_SHIFT 10
+#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
+#define OMAP24XX_MEM3RETSTATE (1 << 5)
+#define OMAP24XX_MEM2RETSTATE (1 << 4)
+#define OMAP24XX_MEM1RETSTATE (1 << 3)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP24XX_MEM3STATEST_SHIFT 14
+#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
+#define OMAP24XX_MEM2STATEST_SHIFT 12
+#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
+#define OMAP24XX_MEM1STATEST_SHIFT 10
+#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
+
+/* RM_RSTCTRL_GFX */
+#define OMAP24XX_GFX_RST (1 << 0)
+
+/* RM_RSTST_GFX specific bits */
+#define OMAP24XX_GFX_SW_RST (1 << 4)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+/* 2430 often calls EN_WAKEUP "EN_WKUP" */
+
+/* RM_RSTCTRL_WKUP specific bits */
+
+/* RM_RSTTIME_WKUP specific bits */
+
+/* RM_RSTST_WKUP specific bits */
+/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP24XX_EXTWMPU_RST (1 << 6)
+#define OMAP24XX_SECU_WD_RST (1 << 5)
+#define OMAP24XX_MPU_WD_RST (1 << 4)
+#define OMAP24XX_SECU_VIOL_RST (1 << 3)
+
+/* PM_WKEN_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+
+/* RM_RSTCTRL_DSP */
+#define OMAP2420_RST_IVA (1 << 8)
+#define OMAP24XX_RST2_DSP (1 << 1)
+#define OMAP24XX_RST1_DSP (1 << 0)
+
+/* RM_RSTST_DSP specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP2420_IVA_SW_RST (1 << 8)
+#define OMAP24XX_DSP_SW_RST2 (1 << 5)
+#define OMAP24XX_DSP_SW_RST1 (1 << 4)
+
+/* PM_WKDEP_DSP specific bits */
+
+/* PM_PWSTCTRL_DSP specific bits */
+/* 2430 only: MEMONSTATE, MEMRETSTATE */
+#define OMAP2420_MEMIONSTATE_SHIFT 12
+#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
+#define OMAP2420_MEMIRETSTATE (1 << 4)
+
+/* PM_PWSTST_DSP specific bits */
+/* MEMSTATEST is 2430 only */
+#define OMAP2420_MEMISTATEST_SHIFT 12
+#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
+
+/* PRCM_IRQSTATUS_DSP specific bits */
+
+/* PRCM_IRQENABLE_DSP specific bits */
+
+/* RM_RSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_PWRON1_MDM (1 << 1)
+#define OMAP2430_RST1_MDM (1 << 0)
+
+/* RM_RSTST_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_MDM_SECU_VIOL (1 << 6)
+#define OMAP2430_MDM_SW_PWRON1 (1 << 5)
+#define OMAP2430_MDM_SW_RST1 (1 << 4)
+
+/* PM_WKEN_MDM */
+/* 2430 only */
+#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0)
+
+/* PM_WKST_MDM specific bits */
+/* 2430 only */
+
+/* PM_WKDEP_MDM specific bits */
+/* 2430 only */
+
+/* PM_PWSTCTRL_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_KILLDOMAINWKUP (1 << 19)
+
+/* PM_PWSTST_MDM specific bits */
+/* 2430 only */
+
+/* PRCM_IRQSTATUS_IVA */
+/* 2420 only */
+
+/* PRCM_IRQENABLE_IVA */
+/* 2420 only */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm_regbits_24xx.h b/arch/arm/mach-omap2/prm_regbits_24xx.h
deleted file mode 100644
index c6d17a3..0000000
--- a/arch/arm/mach-omap2/prm_regbits_24xx.h
+++ /dev/null
@@ -1,279 +0,0 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
-
-/*
- * OMAP24XX Power/Reset Management register bits
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include "prm.h"
-
-/* Bits shared between registers */
-
-/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
-#define OMAP24XX_VOLTTRANS_ST (1 << 2)
-#define OMAP24XX_WKUP2_ST (1 << 1)
-#define OMAP24XX_WKUP1_ST (1 << 0)
-
-/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
-#define OMAP24XX_VOLTTRANS_EN (1 << 2)
-#define OMAP24XX_WKUP2_EN (1 << 1)
-#define OMAP24XX_WKUP1_EN (1 << 0)
-
-/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
-#define OMAP24XX_EN_MPU (1 << 1)
-#define OMAP24XX_EN_CORE (1 << 0)
-
-/*
- * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
- * shared bits
- */
-#define OMAP24XX_MEMONSTATE_SHIFT 10
-#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
-#define OMAP24XX_MEMRETSTATE (1 << 3)
-
-/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
-#define OMAP24XX_FORCESTATE (1 << 18)
-
-/*
- * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
- * PM_PWSTST_MDM shared bits
- */
-#define OMAP24XX_CLKACTIVITY (1 << 19)
-
-/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
-#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
-#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
-
-/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
-#define OMAP2430_MEMSTATEST_SHIFT 10
-#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
-
-/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
-#define OMAP24XX_POWERSTATEST_SHIFT 0
-#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
-
-
-/* Bits specific to each register */
-
-/* PRCM_REVISION */
-#define OMAP24XX_REV_SHIFT 0
-#define OMAP24XX_REV_MASK (0xff << 0)
-
-/* PRCM_SYSCONFIG */
-#define OMAP24XX_AUTOIDLE (1 << 0)
-
-/* PRCM_IRQSTATUS_MPU specific bits */
-#define OMAP2430_DPLL_RECAL_ST (1 << 6)
-#define OMAP24XX_TRANSITION_ST (1 << 5)
-#define OMAP24XX_EVGENOFF_ST (1 << 4)
-#define OMAP24XX_EVGENON_ST (1 << 3)
-
-/* PRCM_IRQENABLE_MPU specific bits */
-#define OMAP2430_DPLL_RECAL_EN (1 << 6)
-#define OMAP24XX_TRANSITION_EN (1 << 5)
-#define OMAP24XX_EVGENOFF_EN (1 << 4)
-#define OMAP24XX_EVGENON_EN (1 << 3)
-
-/* PRCM_VOLTCTRL */
-#define OMAP24XX_AUTO_EXTVOLT (1 << 15)
-#define OMAP24XX_FORCE_EXTVOLT (1 << 14)
-#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
-#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
-#define OMAP24XX_MEMRETCTRL (1 << 8)
-#define OMAP24XX_SETRET_LEVEL_SHIFT 6
-#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
-#define OMAP24XX_VOLT_LEVEL_SHIFT 0
-#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
-
-/* PRCM_VOLTST */
-#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
-#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
-
-/* PRCM_CLKSRC_CTRL specific bits */
-
-/* PRCM_CLKOUT_CTRL */
-#define OMAP2420_CLKOUT2_EN_SHIFT 15
-#define OMAP2420_CLKOUT2_EN (1 << 15)
-#define OMAP2420_CLKOUT2_DIV_SHIFT 11
-#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
-#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
-#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
-#define OMAP24XX_CLKOUT_EN_SHIFT 7
-#define OMAP24XX_CLKOUT_EN (1 << 7)
-#define OMAP24XX_CLKOUT_DIV_SHIFT 3
-#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
-#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
-#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
-
-/* PRCM_CLKEMUL_CTRL */
-#define OMAP24XX_EMULATION_EN_SHIFT 0
-#define OMAP24XX_EMULATION_EN (1 << 0)
-
-/* PRCM_CLKCFG_CTRL */
-#define OMAP24XX_VALID_CONFIG (1 << 0)
-
-/* PRCM_CLKCFG_STATUS */
-#define OMAP24XX_CONFIG_STATUS (1 << 0)
-
-/* PRCM_VOLTSETUP specific bits */
-
-/* PRCM_CLKSSETUP specific bits */
-
-/* PRCM_POLCTRL */
-#define OMAP2420_CLKOUT2_POL (1 << 10)
-#define OMAP24XX_CLKOUT_POL (1 << 9)
-#define OMAP24XX_CLKREQ_POL (1 << 8)
-#define OMAP2430_USE_POWEROK (1 << 2)
-#define OMAP2430_POWEROK_POL (1 << 1)
-#define OMAP24XX_EXTVOL_POL (1 << 0)
-
-/* RM_RSTST_MPU specific bits */
-/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
-
-/* PM_WKDEP_MPU specific bits */
-#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5)
-#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2)
-
-/* PM_EVGENCTRL_MPU specific bits */
-
-/* PM_EVEGENONTIM_MPU specific bits */
-
-/* PM_EVEGENOFFTIM_MPU specific bits */
-
-/* PM_PWSTCTRL_MPU specific bits */
-#define OMAP2430_FORCESTATE (1 << 18)
-
-/* PM_PWSTST_MPU specific bits */
-/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
-
-/* PM_WKEN1_CORE specific bits */
-
-/* PM_WKEN2_CORE specific bits */
-
-/* PM_WKST1_CORE specific bits*/
-
-/* PM_WKST2_CORE specific bits */
-
-/* PM_WKDEP_CORE specific bits*/
-#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5)
-#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3)
-#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2)
-
-/* PM_PWSTCTRL_CORE specific bits */
-#define OMAP24XX_MEMORYCHANGE (1 << 20)
-#define OMAP24XX_MEM3ONSTATE_SHIFT 14
-#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
-#define OMAP24XX_MEM2ONSTATE_SHIFT 12
-#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
-#define OMAP24XX_MEM1ONSTATE_SHIFT 10
-#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
-#define OMAP24XX_MEM3RETSTATE (1 << 5)
-#define OMAP24XX_MEM2RETSTATE (1 << 4)
-#define OMAP24XX_MEM1RETSTATE (1 << 3)
-
-/* PM_PWSTST_CORE specific bits */
-#define OMAP24XX_MEM3STATEST_SHIFT 14
-#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
-#define OMAP24XX_MEM2STATEST_SHIFT 12
-#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
-#define OMAP24XX_MEM1STATEST_SHIFT 10
-#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
-
-/* RM_RSTCTRL_GFX */
-#define OMAP24XX_GFX_RST (1 << 0)
-
-/* RM_RSTST_GFX specific bits */
-#define OMAP24XX_GFX_SW_RST (1 << 4)
-
-/* PM_PWSTCTRL_GFX specific bits */
-
-/* PM_WKDEP_GFX specific bits */
-/* 2430 often calls EN_WAKEUP "EN_WKUP" */
-
-/* RM_RSTCTRL_WKUP specific bits */
-
-/* RM_RSTTIME_WKUP specific bits */
-
-/* RM_RSTST_WKUP specific bits */
-/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
-#define OMAP24XX_EXTWMPU_RST (1 << 6)
-#define OMAP24XX_SECU_WD_RST (1 << 5)
-#define OMAP24XX_MPU_WD_RST (1 << 4)
-#define OMAP24XX_SECU_VIOL_RST (1 << 3)
-
-/* PM_WKEN_WKUP specific bits */
-
-/* PM_WKST_WKUP specific bits */
-
-/* RM_RSTCTRL_DSP */
-#define OMAP2420_RST_IVA (1 << 8)
-#define OMAP24XX_RST2_DSP (1 << 1)
-#define OMAP24XX_RST1_DSP (1 << 0)
-
-/* RM_RSTST_DSP specific bits */
-/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
-#define OMAP2420_IVA_SW_RST (1 << 8)
-#define OMAP24XX_DSP_SW_RST2 (1 << 5)
-#define OMAP24XX_DSP_SW_RST1 (1 << 4)
-
-/* PM_WKDEP_DSP specific bits */
-
-/* PM_PWSTCTRL_DSP specific bits */
-/* 2430 only: MEMONSTATE, MEMRETSTATE */
-#define OMAP2420_MEMIONSTATE_SHIFT 12
-#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
-#define OMAP2420_MEMIRETSTATE (1 << 4)
-
-/* PM_PWSTST_DSP specific bits */
-/* MEMSTATEST is 2430 only */
-#define OMAP2420_MEMISTATEST_SHIFT 12
-#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
-
-/* PRCM_IRQSTATUS_DSP specific bits */
-
-/* PRCM_IRQENABLE_DSP specific bits */
-
-/* RM_RSTCTRL_MDM */
-/* 2430 only */
-#define OMAP2430_PWRON1_MDM (1 << 1)
-#define OMAP2430_RST1_MDM (1 << 0)
-
-/* RM_RSTST_MDM specific bits */
-/* 2430 only */
-#define OMAP2430_MDM_SECU_VIOL (1 << 6)
-#define OMAP2430_MDM_SW_PWRON1 (1 << 5)
-#define OMAP2430_MDM_SW_RST1 (1 << 4)
-
-/* PM_WKEN_MDM */
-/* 2430 only */
-#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0)
-
-/* PM_WKST_MDM specific bits */
-/* 2430 only */
-
-/* PM_WKDEP_MDM specific bits */
-/* 2430 only */
-
-/* PM_PWSTCTRL_MDM specific bits */
-/* 2430 only */
-#define OMAP2430_KILLDOMAINWKUP (1 << 19)
-
-/* PM_PWSTST_MDM specific bits */
-/* 2430 only */
-
-/* PRCM_IRQSTATUS_IVA */
-/* 2420 only */
-
-/* PRCM_IRQENABLE_IVA */
-/* 2420 only */
-
-#endif
diff --git a/drivers/dsp/dspgateway/dsp.h b/drivers/dsp/dspgateway/dsp.h
index 7d238e5..2a3dc24 100644
--- a/drivers/dsp/dspgateway/dsp.h
+++ b/drivers/dsp/dspgateway/dsp.h
@@ -31,7 +31,7 @@
#ifdef CONFIG_ARCH_OMAP2
#include "../../../arch/arm/mach-omap2/prm.h"
-#include "../../../arch/arm/mach-omap2/prm_regbits_24xx.h"
+#include "../../../arch/arm/mach-omap2/prm-regbits-24xx.h"
#include "../../../arch/arm/mach-omap2/cm.h"
#include "../../../arch/arm/mach-omap2/cm-regbits-24xx.h"
#endif
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 9/10] ARM: OMAP3: Rename prm_regbits_34xx.h to prm-regbits-34xx.h
2008-03-12 10:45 ` [PATCH 8/10] ARM: OMAP2: Rename prm_regbits_24xx.h to prm-regbits-24xx.h Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
2008-03-12 10:45 ` [PATCH 10/10] ARM: OMAP: Move STI support to drivers/misc Tony Lindgren
0 siblings, 1 reply; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
Rename prm_regbits_34xx.h to prm-regbits-34xx.h
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/clock34xx.c | 2 +-
arch/arm/mach-omap2/clock34xx.h | 2 +-
arch/arm/mach-omap2/prm-regbits-34xx.h | 582 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prm_regbits_34xx.h | 582 --------------------------------
4 files changed, 584 insertions(+), 584 deletions(-)
create mode 100644 arch/arm/mach-omap2/prm-regbits-34xx.h
delete mode 100644 arch/arm/mach-omap2/prm_regbits_34xx.h
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 616e071..f05dd2e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -33,7 +33,7 @@
#include "clock.h"
#include "clock34xx.h"
#include "prm.h"
-#include "prm_regbits_34xx.h"
+#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 9f61352..64f108d 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -16,7 +16,7 @@
#include "cm.h"
#include "cm-regbits-34xx.h"
#include "prm.h"
-#include "prm_regbits_34xx.h"
+#include "prm-regbits-34xx.h"
static void omap3_dpll_recalc(struct clk *clk);
static void omap3_clkoutx2_recalc(struct clk *clk);
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
new file mode 100644
index 0000000..b4686bc
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -0,0 +1,582 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Power/Reset Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Shared register bits */
+
+/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
+#define OMAP3430_ON_SHIFT 24
+#define OMAP3430_ON_MASK (0xff << 24)
+#define OMAP3430_ONLP_SHIFT 16
+#define OMAP3430_ONLP_MASK (0xff << 16)
+#define OMAP3430_RET_SHIFT 8
+#define OMAP3430_RET_MASK (0xff << 8)
+#define OMAP3430_OFF_SHIFT 0
+#define OMAP3430_OFF_MASK (0xff << 0)
+
+/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
+#define OMAP3430_ERROROFFSET_SHIFT 24
+#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
+#define OMAP3430_ERRORGAIN_SHIFT 16
+#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
+#define OMAP3430_INITVOLTAGE_SHIFT 8
+#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
+#define OMAP3430_TIMEOUTEN (1 << 3)
+#define OMAP3430_INITVDD (1 << 2)
+#define OMAP3430_FORCEUPDATE (1 << 1)
+#define OMAP3430_VPENABLE (1 << 0)
+
+/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
+#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
+#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
+#define OMAP3430_VSTEPMIN_SHIFT 0
+#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
+
+/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
+#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
+#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
+#define OMAP3430_VSTEPMAX_SHIFT 0
+#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
+
+/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
+#define OMAP3430_VDDMAX_SHIFT 24
+#define OMAP3430_VDDMAX_MASK (0xff << 24)
+#define OMAP3430_VDDMIN_SHIFT 16
+#define OMAP3430_VDDMIN_MASK (0xff << 16)
+#define OMAP3430_TIMEOUT_SHIFT 0
+#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
+
+/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
+#define OMAP3430_VPVOLTAGE_SHIFT 0
+#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
+
+/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
+#define OMAP3430_VPINIDLE (1 << 0)
+
+/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
+#define OMAP3430_EN_PER (1 << 7)
+
+/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
+#define OMAP3430_MEMORYCHANGE (1 << 3)
+
+/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
+#define OMAP3430_LOGICSTATEST (1 << 2)
+
+/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
+#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
+
+/*
+ * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
+ * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
+ * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
+ */
+#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
+#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
+
+/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
+#define OMAP3430_WKUP_ST (1 << 0)
+
+/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
+#define OMAP3430_WKUP_EN (1 << 0)
+
+/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
+#define OMAP3430_GRPSEL_MMC2 (1 << 25)
+#define OMAP3430_GRPSEL_MMC1 (1 << 24)
+#define OMAP3430_GRPSEL_MCSPI4 (1 << 21)
+#define OMAP3430_GRPSEL_MCSPI3 (1 << 20)
+#define OMAP3430_GRPSEL_MCSPI2 (1 << 19)
+#define OMAP3430_GRPSEL_MCSPI1 (1 << 18)
+#define OMAP3430_GRPSEL_I2C3 (1 << 17)
+#define OMAP3430_GRPSEL_I2C2 (1 << 16)
+#define OMAP3430_GRPSEL_I2C1 (1 << 15)
+#define OMAP3430_GRPSEL_UART2 (1 << 14)
+#define OMAP3430_GRPSEL_UART1 (1 << 13)
+#define OMAP3430_GRPSEL_GPT11 (1 << 12)
+#define OMAP3430_GRPSEL_GPT10 (1 << 11)
+#define OMAP3430_GRPSEL_MCBSP5 (1 << 10)
+#define OMAP3430_GRPSEL_MCBSP1 (1 << 9)
+#define OMAP3430_GRPSEL_HSOTGUSB (1 << 4)
+#define OMAP3430_GRPSEL_D2D (1 << 3)
+
+/*
+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
+ * PM_PWSTCTRL_PER shared bits
+ */
+#define OMAP3430_MEMONSTATE_SHIFT 16
+#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
+#define OMAP3430_MEMRETSTATE (1 << 8)
+
+/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3430_GRPSEL_GPIO6 (1 << 17)
+#define OMAP3430_GRPSEL_GPIO5 (1 << 16)
+#define OMAP3430_GRPSEL_GPIO4 (1 << 15)
+#define OMAP3430_GRPSEL_GPIO3 (1 << 14)
+#define OMAP3430_GRPSEL_GPIO2 (1 << 13)
+#define OMAP3430_GRPSEL_UART3 (1 << 11)
+#define OMAP3430_GRPSEL_GPT9 (1 << 10)
+#define OMAP3430_GRPSEL_GPT8 (1 << 9)
+#define OMAP3430_GRPSEL_GPT7 (1 << 8)
+#define OMAP3430_GRPSEL_GPT6 (1 << 7)
+#define OMAP3430_GRPSEL_GPT5 (1 << 6)
+#define OMAP3430_GRPSEL_GPT4 (1 << 5)
+#define OMAP3430_GRPSEL_GPT3 (1 << 4)
+#define OMAP3430_GRPSEL_GPT2 (1 << 3)
+#define OMAP3430_GRPSEL_MCBSP4 (1 << 2)
+#define OMAP3430_GRPSEL_MCBSP3 (1 << 1)
+#define OMAP3430_GRPSEL_MCBSP2 (1 << 0)
+
+/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
+#define OMAP3430_GRPSEL_IO (1 << 8)
+#define OMAP3430_GRPSEL_SR2 (1 << 7)
+#define OMAP3430_GRPSEL_SR1 (1 << 6)
+#define OMAP3430_GRPSEL_GPIO1 (1 << 3)
+#define OMAP3430_GRPSEL_GPT12 (1 << 1)
+#define OMAP3430_GRPSEL_GPT1 (1 << 0)
+
+/* Bits specific to each register */
+
+/* RM_RSTCTRL_IVA2 */
+#define OMAP3430_RST3_IVA2 (1 << 2)
+#define OMAP3430_RST2_IVA2 (1 << 1)
+#define OMAP3430_RST1_IVA2 (1 << 0)
+
+/* RM_RSTST_IVA2 specific bits */
+#define OMAP3430_EMULATION_VSEQ_RST (1 << 13)
+#define OMAP3430_EMULATION_VHWA_RST (1 << 12)
+#define OMAP3430_EMULATION_IVA2_RST (1 << 11)
+#define OMAP3430_IVA2_SW_RST3 (1 << 10)
+#define OMAP3430_IVA2_SW_RST2 (1 << 9)
+#define OMAP3430_IVA2_SW_RST1 (1 << 8)
+
+/* PM_WKDEP_IVA2 specific bits */
+
+/* PM_PWSTCTRL_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
+#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
+#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
+#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
+#define OMAP3430_L2FLATMEMRETSTATE (1 << 11)
+#define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10)
+#define OMAP3430_L1FLATMEMRETSTATE (1 << 9)
+#define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8)
+
+/* PM_PWSTST_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
+#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
+#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
+#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
+
+/* PM_PREPWSTST_IVA2 specific bits */
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
+
+/* PRM_IRQSTATUS_IVA2 specific bits */
+#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2)
+#define OMAP3430_FORCEWKUP_ST (1 << 1)
+
+/* PRM_IRQENABLE_IVA2 specific bits */
+#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2)
+#define OMAP3430_FORCEWKUP_EN (1 << 1)
+
+/* PRM_REVISION specific bits */
+
+/* PRM_SYSCONFIG specific bits */
+
+/* PRM_IRQSTATUS_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_ST (1 << 24)
+#define OMAP3430_VC_RAERR_ST (1 << 23)
+#define OMAP3430_VC_SAERR_ST (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_ST (1 << 21)
+#define OMAP3430_VP2_EQVALUE_ST (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_ST (1 << 19)
+#define OMAP3430_VP2_MAXVDD_ST (1 << 18)
+#define OMAP3430_VP2_MINVDD_ST (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_ST (1 << 15)
+#define OMAP3430_VP1_EQVALUE_ST (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_ST (1 << 13)
+#define OMAP3430_VP1_MAXVDD_ST (1 << 12)
+#define OMAP3430_VP1_MINVDD_ST (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10)
+#define OMAP3430_IO_ST (1 << 9)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
+#define OMAP3430_MPU_DPLL_ST (1 << 7)
+#define OMAP3430_MPU_DPLL_ST_SHIFT 7
+#define OMAP3430_PERIPH_DPLL_ST (1 << 6)
+#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
+#define OMAP3430_CORE_DPLL_ST (1 << 5)
+#define OMAP3430_CORE_DPLL_ST_SHIFT 5
+#define OMAP3430_TRANSITION_ST (1 << 4)
+#define OMAP3430_EVGENOFF_ST (1 << 3)
+#define OMAP3430_EVGENON_ST (1 << 2)
+#define OMAP3430_FS_USB_WKUP_ST (1 << 1)
+
+/* PRM_IRQENABLE_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_EN (1 << 24)
+#define OMAP3430_VC_RAERR_EN (1 << 23)
+#define OMAP3430_VC_SAERR_EN (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_EN (1 << 21)
+#define OMAP3430_VP2_EQVALUE_EN (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_EN (1 << 19)
+#define OMAP3430_VP2_MAXVDD_EN (1 << 18)
+#define OMAP3430_VP2_MINVDD_EN (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_EN (1 << 15)
+#define OMAP3430_VP1_EQVALUE_EN (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_EN (1 << 13)
+#define OMAP3430_VP1_MAXVDD_EN (1 << 12)
+#define OMAP3430_VP1_MINVDD_EN (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10)
+#define OMAP3430_IO_EN (1 << 9)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
+#define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7)
+#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
+#define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6)
+#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
+#define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5)
+#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
+#define OMAP3430_TRANSITION_EN (1 << 4)
+#define OMAP3430_EVGENOFF_EN (1 << 3)
+#define OMAP3430_EVGENON_EN (1 << 2)
+#define OMAP3430_FS_USB_WKUP_EN (1 << 1)
+
+/* RM_RSTST_MPU specific bits */
+#define OMAP3430_EMULATION_MPU_RST (1 << 11)
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5)
+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP3430_OFFLOADMODE_SHIFT 3
+#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
+#define OMAP3430_ONLOADMODE_SHIFT 1
+#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
+#define OMAP3430_ENABLE (1 << 0)
+
+/* PM_EVGENONTIM_MPU */
+#define OMAP3430_ONTIMEVAL_SHIFT 0
+#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+#define OMAP3430_OFFTIMEVAL_SHIFT 0
+#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP3430_L2CACHEONSTATE_SHIFT 16
+#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
+#define OMAP3430_L2CACHERETSTATE (1 << 8)
+#define OMAP3430_LOGICL1CACHERETSTATE (1 << 2)
+
+/* PM_PWSTST_MPU specific bits */
+#define OMAP3430_L2CACHESTATEST_SHIFT 6
+#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
+#define OMAP3430_LOGICL1CACHESTATEST (1 << 2)
+
+/* PM_PREPWSTST_MPU specific bits */
+#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
+#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2)
+
+/* RM_RSTCTRL_CORE */
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0)
+
+/* RM_RSTST_CORE specific bits */
+#define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8)
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_MPUGRPSEL1_CORE specific bits */
+#define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5)
+
+/* PM_IVA2GRPSEL1_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits */
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP3430_MEM2ONSTATE_SHIFT 18
+#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
+#define OMAP3430_MEM1ONSTATE_SHIFT 16
+#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
+#define OMAP3430_MEM2RETSTATE (1 << 9)
+#define OMAP3430_MEM1RETSTATE (1 << 8)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP3430_MEM2STATEST_SHIFT 6
+#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
+#define OMAP3430_MEM1STATEST_SHIFT 4
+#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
+
+/* PM_PREPWSTST_CORE specific bits */
+#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
+#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
+#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
+
+/* RM_RSTST_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+#define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_PWSTST_GFX specific bits */
+
+/* PM_PREPWSTST_GFX specific bits */
+
+/* PM_WKEN_WKUP specific bits */
+#define OMAP3430_EN_IO (1 << 8)
+
+/* PM_MPUGRPSEL_WKUP specific bits */
+
+/* PM_IVA2GRPSEL_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+#define OMAP3430_ST_IO (1 << 8)
+
+/* PRM_CLKSEL */
+#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
+#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
+
+/* PRM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT_EN (1 << 7)
+#define OMAP3430_CLKOUT_EN_SHIFT 7
+
+/* RM_RSTST_DSS specific bits */
+
+/* PM_WKEN_DSS */
+#define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0)
+
+/* PM_WKDEP_DSS specific bits */
+#define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_DSS specific bits */
+
+/* PM_PWSTST_DSS specific bits */
+
+/* PM_PREPWSTST_DSS specific bits */
+
+/* RM_RSTST_CAM specific bits */
+
+/* PM_WKDEP_CAM specific bits */
+#define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_CAM specific bits */
+
+/* PM_PWSTST_CAM specific bits */
+
+/* PM_PREPWSTST_CAM specific bits */
+
+/* PM_PWSTCTRL_USBHOST specific bits */
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4)
+
+/* RM_RSTST_PER specific bits */
+
+/* PM_WKEN_PER specific bits */
+
+/* PM_MPUGRPSEL_PER specific bits */
+
+/* PM_IVA2GRPSEL_PER specific bits */
+
+/* PM_WKST_PER specific bits */
+
+/* PM_WKDEP_PER specific bits */
+#define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_PER specific bits */
+
+/* PM_PWSTST_PER specific bits */
+
+/* PM_PREPWSTST_PER specific bits */
+
+/* RM_RSTST_EMU specific bits */
+
+/* PM_PWSTST_EMU specific bits */
+
+/* PRM_VC_SMPS_SA */
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
+
+/* PRM_VC_SMPS_VOL_RA */
+#define OMAP3430_VOLRA1_SHIFT 16
+#define OMAP3430_VOLRA1_MASK (0xff << 16)
+#define OMAP3430_VOLRA0_SHIFT 0
+#define OMAP3430_VOLRA0_MASK (0xff << 0)
+
+/* PRM_VC_SMPS_CMD_RA */
+#define OMAP3430_CMDRA1_SHIFT 16
+#define OMAP3430_CMDRA1_MASK (0xff << 16)
+#define OMAP3430_CMDRA0_SHIFT 0
+#define OMAP3430_CMDRA0_MASK (0xff << 0)
+
+/* PRM_VC_CMD_VAL_0 specific bits */
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+
+/* PRM_VC_CH_CONF */
+#define OMAP3430_CMD1 (1 << 20)
+#define OMAP3430_RACEN1 (1 << 19)
+#define OMAP3430_RAC1 (1 << 18)
+#define OMAP3430_RAV1 (1 << 17)
+#define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16)
+#define OMAP3430_CMD0 (1 << 4)
+#define OMAP3430_RACEN0 (1 << 3)
+#define OMAP3430_RAC0 (1 << 2)
+#define OMAP3430_RAV0 (1 << 1)
+#define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0)
+
+/* PRM_VC_I2C_CFG */
+#define OMAP3430_HSMASTER (1 << 5)
+#define OMAP3430_SREN (1 << 4)
+#define OMAP3430_HSEN (1 << 3)
+#define OMAP3430_MCODE_SHIFT 0
+#define OMAP3430_MCODE_MASK (0x7 << 0)
+
+/* PRM_VC_BYPASS_VAL */
+#define OMAP3430_VALID (1 << 24)
+#define OMAP3430_DATA_SHIFT 16
+#define OMAP3430_DATA_MASK (0xff << 16)
+#define OMAP3430_REGADDR_SHIFT 8
+#define OMAP3430_REGADDR_MASK (0xff << 8)
+#define OMAP3430_SLAVEADDR_SHIFT 0
+#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
+
+/* PRM_RSTCTRL */
+#define OMAP3430_RST_DPLL3 (1 << 2)
+#define OMAP3430_RST_GS (1 << 1)
+
+/* PRM_RSTTIME */
+#define OMAP3430_RSTTIME2_SHIFT 8
+#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
+#define OMAP3430_RSTTIME1_SHIFT 0
+#define OMAP3430_RSTTIME1_MASK (0xff << 0)
+
+/* PRM_RSTST */
+#define OMAP3430_ICECRUSHER_RST (1 << 10)
+#define OMAP3430_ICEPICK_RST (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST (1 << 6)
+#define OMAP3430_SECURE_WD_RST (1 << 5)
+#define OMAP3430_MPU_WD_RST (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST (1 << 0)
+
+/* PRM_VOLTCTRL */
+#define OMAP3430_SEL_VMODE (1 << 4)
+#define OMAP3430_SEL_OFF (1 << 3)
+#define OMAP3430_AUTO_OFF (1 << 2)
+#define OMAP3430_AUTO_RET (1 << 1)
+#define OMAP3430_AUTO_SLEEP (1 << 0)
+
+/* PRM_SRAM_PCHARGE */
+#define OMAP3430_PCHARGE_TIME_SHIFT 0
+#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
+
+/* PRM_CLKSRC_CTRL */
+#define OMAP3430_SYSCLKDIV_SHIFT 6
+#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
+#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
+#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
+#define OMAP3430_SYSCLKSEL_SHIFT 0
+#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
+
+/* PRM_VOLTSETUP1 */
+#define OMAP3430_SETUP_TIME2_SHIFT 16
+#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
+#define OMAP3430_SETUP_TIME1_SHIFT 0
+#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
+
+/* PRM_VOLTOFFSET */
+#define OMAP3430_OFFSET_TIME_SHIFT 0
+#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
+
+/* PRM_CLKSETUP */
+#define OMAP3430_SETUP_TIME_SHIFT 0
+#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
+
+/* PRM_POLCTRL */
+#define OMAP3430_OFFMODE_POL (1 << 3)
+#define OMAP3430_CLKOUT_POL (1 << 2)
+#define OMAP3430_CLKREQ_POL (1 << 1)
+#define OMAP3430_EXTVOL_POL (1 << 0)
+
+/* PRM_VOLTSETUP2 */
+#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
+#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
+
+/* PRM_VP1_CONFIG specific bits */
+
+/* PRM_VP1_VSTEPMIN specific bits */
+
+/* PRM_VP1_VSTEPMAX specific bits */
+
+/* PRM_VP1_VLIMITTO specific bits */
+
+/* PRM_VP1_VOLTAGE specific bits */
+
+/* PRM_VP1_STATUS specific bits */
+
+/* PRM_VP2_CONFIG specific bits */
+
+/* PRM_VP2_VSTEPMIN specific bits */
+
+/* PRM_VP2_VSTEPMAX specific bits */
+
+/* PRM_VP2_VLIMITTO specific bits */
+
+/* PRM_VP2_VOLTAGE specific bits */
+
+/* PRM_VP2_STATUS specific bits */
+
+/* RM_RSTST_NEON specific bits */
+
+/* PM_WKDEP_NEON specific bits */
+
+/* PM_PWSTCTRL_NEON specific bits */
+
+/* PM_PWSTST_NEON specific bits */
+
+/* PM_PREPWSTST_NEON specific bits */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm_regbits_34xx.h b/arch/arm/mach-omap2/prm_regbits_34xx.h
deleted file mode 100644
index b4686bc..0000000
--- a/arch/arm/mach-omap2/prm_regbits_34xx.h
+++ /dev/null
@@ -1,582 +0,0 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
-
-/*
- * OMAP3430 Power/Reset Management register bits
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include "prm.h"
-
-/* Shared register bits */
-
-/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
-#define OMAP3430_ON_SHIFT 24
-#define OMAP3430_ON_MASK (0xff << 24)
-#define OMAP3430_ONLP_SHIFT 16
-#define OMAP3430_ONLP_MASK (0xff << 16)
-#define OMAP3430_RET_SHIFT 8
-#define OMAP3430_RET_MASK (0xff << 8)
-#define OMAP3430_OFF_SHIFT 0
-#define OMAP3430_OFF_MASK (0xff << 0)
-
-/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
-#define OMAP3430_ERROROFFSET_SHIFT 24
-#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
-#define OMAP3430_ERRORGAIN_SHIFT 16
-#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
-#define OMAP3430_INITVOLTAGE_SHIFT 8
-#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
-#define OMAP3430_TIMEOUTEN (1 << 3)
-#define OMAP3430_INITVDD (1 << 2)
-#define OMAP3430_FORCEUPDATE (1 << 1)
-#define OMAP3430_VPENABLE (1 << 0)
-
-/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
-#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
-#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
-#define OMAP3430_VSTEPMIN_SHIFT 0
-#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
-
-/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
-#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
-#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
-#define OMAP3430_VSTEPMAX_SHIFT 0
-#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
-
-/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
-#define OMAP3430_VDDMAX_SHIFT 24
-#define OMAP3430_VDDMAX_MASK (0xff << 24)
-#define OMAP3430_VDDMIN_SHIFT 16
-#define OMAP3430_VDDMIN_MASK (0xff << 16)
-#define OMAP3430_TIMEOUT_SHIFT 0
-#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
-
-/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
-#define OMAP3430_VPVOLTAGE_SHIFT 0
-#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
-
-/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
-#define OMAP3430_VPINIDLE (1 << 0)
-
-/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
-#define OMAP3430_EN_PER (1 << 7)
-
-/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
-#define OMAP3430_MEMORYCHANGE (1 << 3)
-
-/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
-#define OMAP3430_LOGICSTATEST (1 << 2)
-
-/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
-#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
-
-/*
- * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
- * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
- * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
- */
-#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
-#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
-
-/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
-#define OMAP3430_WKUP_ST (1 << 0)
-
-/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
-#define OMAP3430_WKUP_EN (1 << 0)
-
-/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
-#define OMAP3430_GRPSEL_MMC2 (1 << 25)
-#define OMAP3430_GRPSEL_MMC1 (1 << 24)
-#define OMAP3430_GRPSEL_MCSPI4 (1 << 21)
-#define OMAP3430_GRPSEL_MCSPI3 (1 << 20)
-#define OMAP3430_GRPSEL_MCSPI2 (1 << 19)
-#define OMAP3430_GRPSEL_MCSPI1 (1 << 18)
-#define OMAP3430_GRPSEL_I2C3 (1 << 17)
-#define OMAP3430_GRPSEL_I2C2 (1 << 16)
-#define OMAP3430_GRPSEL_I2C1 (1 << 15)
-#define OMAP3430_GRPSEL_UART2 (1 << 14)
-#define OMAP3430_GRPSEL_UART1 (1 << 13)
-#define OMAP3430_GRPSEL_GPT11 (1 << 12)
-#define OMAP3430_GRPSEL_GPT10 (1 << 11)
-#define OMAP3430_GRPSEL_MCBSP5 (1 << 10)
-#define OMAP3430_GRPSEL_MCBSP1 (1 << 9)
-#define OMAP3430_GRPSEL_HSOTGUSB (1 << 4)
-#define OMAP3430_GRPSEL_D2D (1 << 3)
-
-/*
- * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
- * PM_PWSTCTRL_PER shared bits
- */
-#define OMAP3430_MEMONSTATE_SHIFT 16
-#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
-#define OMAP3430_MEMRETSTATE (1 << 8)
-
-/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
-#define OMAP3430_GRPSEL_GPIO6 (1 << 17)
-#define OMAP3430_GRPSEL_GPIO5 (1 << 16)
-#define OMAP3430_GRPSEL_GPIO4 (1 << 15)
-#define OMAP3430_GRPSEL_GPIO3 (1 << 14)
-#define OMAP3430_GRPSEL_GPIO2 (1 << 13)
-#define OMAP3430_GRPSEL_UART3 (1 << 11)
-#define OMAP3430_GRPSEL_GPT9 (1 << 10)
-#define OMAP3430_GRPSEL_GPT8 (1 << 9)
-#define OMAP3430_GRPSEL_GPT7 (1 << 8)
-#define OMAP3430_GRPSEL_GPT6 (1 << 7)
-#define OMAP3430_GRPSEL_GPT5 (1 << 6)
-#define OMAP3430_GRPSEL_GPT4 (1 << 5)
-#define OMAP3430_GRPSEL_GPT3 (1 << 4)
-#define OMAP3430_GRPSEL_GPT2 (1 << 3)
-#define OMAP3430_GRPSEL_MCBSP4 (1 << 2)
-#define OMAP3430_GRPSEL_MCBSP3 (1 << 1)
-#define OMAP3430_GRPSEL_MCBSP2 (1 << 0)
-
-/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
-#define OMAP3430_GRPSEL_IO (1 << 8)
-#define OMAP3430_GRPSEL_SR2 (1 << 7)
-#define OMAP3430_GRPSEL_SR1 (1 << 6)
-#define OMAP3430_GRPSEL_GPIO1 (1 << 3)
-#define OMAP3430_GRPSEL_GPT12 (1 << 1)
-#define OMAP3430_GRPSEL_GPT1 (1 << 0)
-
-/* Bits specific to each register */
-
-/* RM_RSTCTRL_IVA2 */
-#define OMAP3430_RST3_IVA2 (1 << 2)
-#define OMAP3430_RST2_IVA2 (1 << 1)
-#define OMAP3430_RST1_IVA2 (1 << 0)
-
-/* RM_RSTST_IVA2 specific bits */
-#define OMAP3430_EMULATION_VSEQ_RST (1 << 13)
-#define OMAP3430_EMULATION_VHWA_RST (1 << 12)
-#define OMAP3430_EMULATION_IVA2_RST (1 << 11)
-#define OMAP3430_IVA2_SW_RST3 (1 << 10)
-#define OMAP3430_IVA2_SW_RST2 (1 << 9)
-#define OMAP3430_IVA2_SW_RST1 (1 << 8)
-
-/* PM_WKDEP_IVA2 specific bits */
-
-/* PM_PWSTCTRL_IVA2 specific bits */
-#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
-#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
-#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
-#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
-#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
-#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
-#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
-#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
-#define OMAP3430_L2FLATMEMRETSTATE (1 << 11)
-#define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10)
-#define OMAP3430_L1FLATMEMRETSTATE (1 << 9)
-#define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8)
-
-/* PM_PWSTST_IVA2 specific bits */
-#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
-#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
-#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
-#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
-#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
-#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
-#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
-#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
-
-/* PM_PREPWSTST_IVA2 specific bits */
-#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
-#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
-#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
-#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
-#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
-#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
-#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
-#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
-
-/* PRM_IRQSTATUS_IVA2 specific bits */
-#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2)
-#define OMAP3430_FORCEWKUP_ST (1 << 1)
-
-/* PRM_IRQENABLE_IVA2 specific bits */
-#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2)
-#define OMAP3430_FORCEWKUP_EN (1 << 1)
-
-/* PRM_REVISION specific bits */
-
-/* PRM_SYSCONFIG specific bits */
-
-/* PRM_IRQSTATUS_MPU specific bits */
-#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
-#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25)
-#define OMAP3430_VC_TIMEOUTERR_ST (1 << 24)
-#define OMAP3430_VC_RAERR_ST (1 << 23)
-#define OMAP3430_VC_SAERR_ST (1 << 22)
-#define OMAP3430_VP2_TRANXDONE_ST (1 << 21)
-#define OMAP3430_VP2_EQVALUE_ST (1 << 20)
-#define OMAP3430_VP2_NOSMPSACK_ST (1 << 19)
-#define OMAP3430_VP2_MAXVDD_ST (1 << 18)
-#define OMAP3430_VP2_MINVDD_ST (1 << 17)
-#define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16)
-#define OMAP3430_VP1_TRANXDONE_ST (1 << 15)
-#define OMAP3430_VP1_EQVALUE_ST (1 << 14)
-#define OMAP3430_VP1_NOSMPSACK_ST (1 << 13)
-#define OMAP3430_VP1_MAXVDD_ST (1 << 12)
-#define OMAP3430_VP1_MINVDD_ST (1 << 11)
-#define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10)
-#define OMAP3430_IO_ST (1 << 9)
-#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8)
-#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
-#define OMAP3430_MPU_DPLL_ST (1 << 7)
-#define OMAP3430_MPU_DPLL_ST_SHIFT 7
-#define OMAP3430_PERIPH_DPLL_ST (1 << 6)
-#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
-#define OMAP3430_CORE_DPLL_ST (1 << 5)
-#define OMAP3430_CORE_DPLL_ST_SHIFT 5
-#define OMAP3430_TRANSITION_ST (1 << 4)
-#define OMAP3430_EVGENOFF_ST (1 << 3)
-#define OMAP3430_EVGENON_ST (1 << 2)
-#define OMAP3430_FS_USB_WKUP_ST (1 << 1)
-
-/* PRM_IRQENABLE_MPU specific bits */
-#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
-#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25)
-#define OMAP3430_VC_TIMEOUTERR_EN (1 << 24)
-#define OMAP3430_VC_RAERR_EN (1 << 23)
-#define OMAP3430_VC_SAERR_EN (1 << 22)
-#define OMAP3430_VP2_TRANXDONE_EN (1 << 21)
-#define OMAP3430_VP2_EQVALUE_EN (1 << 20)
-#define OMAP3430_VP2_NOSMPSACK_EN (1 << 19)
-#define OMAP3430_VP2_MAXVDD_EN (1 << 18)
-#define OMAP3430_VP2_MINVDD_EN (1 << 17)
-#define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16)
-#define OMAP3430_VP1_TRANXDONE_EN (1 << 15)
-#define OMAP3430_VP1_EQVALUE_EN (1 << 14)
-#define OMAP3430_VP1_NOSMPSACK_EN (1 << 13)
-#define OMAP3430_VP1_MAXVDD_EN (1 << 12)
-#define OMAP3430_VP1_MINVDD_EN (1 << 11)
-#define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10)
-#define OMAP3430_IO_EN (1 << 9)
-#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8)
-#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
-#define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7)
-#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
-#define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6)
-#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
-#define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5)
-#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
-#define OMAP3430_TRANSITION_EN (1 << 4)
-#define OMAP3430_EVGENOFF_EN (1 << 3)
-#define OMAP3430_EVGENON_EN (1 << 2)
-#define OMAP3430_FS_USB_WKUP_EN (1 << 1)
-
-/* RM_RSTST_MPU specific bits */
-#define OMAP3430_EMULATION_MPU_RST (1 << 11)
-
-/* PM_WKDEP_MPU specific bits */
-#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5)
-#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2)
-
-/* PM_EVGENCTRL_MPU */
-#define OMAP3430_OFFLOADMODE_SHIFT 3
-#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
-#define OMAP3430_ONLOADMODE_SHIFT 1
-#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
-#define OMAP3430_ENABLE (1 << 0)
-
-/* PM_EVGENONTIM_MPU */
-#define OMAP3430_ONTIMEVAL_SHIFT 0
-#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
-
-/* PM_EVGENOFFTIM_MPU */
-#define OMAP3430_OFFTIMEVAL_SHIFT 0
-#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
-
-/* PM_PWSTCTRL_MPU specific bits */
-#define OMAP3430_L2CACHEONSTATE_SHIFT 16
-#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
-#define OMAP3430_L2CACHERETSTATE (1 << 8)
-#define OMAP3430_LOGICL1CACHERETSTATE (1 << 2)
-
-/* PM_PWSTST_MPU specific bits */
-#define OMAP3430_L2CACHESTATEST_SHIFT 6
-#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
-#define OMAP3430_LOGICL1CACHESTATEST (1 << 2)
-
-/* PM_PREPWSTST_MPU specific bits */
-#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
-#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
-#define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2)
-
-/* RM_RSTCTRL_CORE */
-#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1)
-#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0)
-
-/* RM_RSTST_CORE specific bits */
-#define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10)
-#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9)
-#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8)
-
-/* PM_WKEN1_CORE specific bits */
-
-/* PM_MPUGRPSEL1_CORE specific bits */
-#define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5)
-
-/* PM_IVA2GRPSEL1_CORE specific bits */
-
-/* PM_WKST1_CORE specific bits */
-
-/* PM_PWSTCTRL_CORE specific bits */
-#define OMAP3430_MEM2ONSTATE_SHIFT 18
-#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
-#define OMAP3430_MEM1ONSTATE_SHIFT 16
-#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
-#define OMAP3430_MEM2RETSTATE (1 << 9)
-#define OMAP3430_MEM1RETSTATE (1 << 8)
-
-/* PM_PWSTST_CORE specific bits */
-#define OMAP3430_MEM2STATEST_SHIFT 6
-#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
-#define OMAP3430_MEM1STATEST_SHIFT 4
-#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
-
-/* PM_PREPWSTST_CORE specific bits */
-#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
-#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
-#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
-#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
-
-/* RM_RSTST_GFX specific bits */
-
-/* PM_WKDEP_GFX specific bits */
-#define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2)
-
-/* PM_PWSTCTRL_GFX specific bits */
-
-/* PM_PWSTST_GFX specific bits */
-
-/* PM_PREPWSTST_GFX specific bits */
-
-/* PM_WKEN_WKUP specific bits */
-#define OMAP3430_EN_IO (1 << 8)
-
-/* PM_MPUGRPSEL_WKUP specific bits */
-
-/* PM_IVA2GRPSEL_WKUP specific bits */
-
-/* PM_WKST_WKUP specific bits */
-#define OMAP3430_ST_IO (1 << 8)
-
-/* PRM_CLKSEL */
-#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
-#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
-
-/* PRM_CLKOUT_CTRL */
-#define OMAP3430_CLKOUT_EN (1 << 7)
-#define OMAP3430_CLKOUT_EN_SHIFT 7
-
-/* RM_RSTST_DSS specific bits */
-
-/* PM_WKEN_DSS */
-#define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0)
-
-/* PM_WKDEP_DSS specific bits */
-#define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2)
-
-/* PM_PWSTCTRL_DSS specific bits */
-
-/* PM_PWSTST_DSS specific bits */
-
-/* PM_PREPWSTST_DSS specific bits */
-
-/* RM_RSTST_CAM specific bits */
-
-/* PM_WKDEP_CAM specific bits */
-#define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2)
-
-/* PM_PWSTCTRL_CAM specific bits */
-
-/* PM_PWSTST_CAM specific bits */
-
-/* PM_PREPWSTST_CAM specific bits */
-
-/* PM_PWSTCTRL_USBHOST specific bits */
-#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4)
-
-/* RM_RSTST_PER specific bits */
-
-/* PM_WKEN_PER specific bits */
-
-/* PM_MPUGRPSEL_PER specific bits */
-
-/* PM_IVA2GRPSEL_PER specific bits */
-
-/* PM_WKST_PER specific bits */
-
-/* PM_WKDEP_PER specific bits */
-#define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2)
-
-/* PM_PWSTCTRL_PER specific bits */
-
-/* PM_PWSTST_PER specific bits */
-
-/* PM_PREPWSTST_PER specific bits */
-
-/* RM_RSTST_EMU specific bits */
-
-/* PM_PWSTST_EMU specific bits */
-
-/* PRM_VC_SMPS_SA */
-#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
-#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
-#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
-#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
-
-/* PRM_VC_SMPS_VOL_RA */
-#define OMAP3430_VOLRA1_SHIFT 16
-#define OMAP3430_VOLRA1_MASK (0xff << 16)
-#define OMAP3430_VOLRA0_SHIFT 0
-#define OMAP3430_VOLRA0_MASK (0xff << 0)
-
-/* PRM_VC_SMPS_CMD_RA */
-#define OMAP3430_CMDRA1_SHIFT 16
-#define OMAP3430_CMDRA1_MASK (0xff << 16)
-#define OMAP3430_CMDRA0_SHIFT 0
-#define OMAP3430_CMDRA0_MASK (0xff << 0)
-
-/* PRM_VC_CMD_VAL_0 specific bits */
-
-/* PRM_VC_CMD_VAL_1 specific bits */
-
-/* PRM_VC_CH_CONF */
-#define OMAP3430_CMD1 (1 << 20)
-#define OMAP3430_RACEN1 (1 << 19)
-#define OMAP3430_RAC1 (1 << 18)
-#define OMAP3430_RAV1 (1 << 17)
-#define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16)
-#define OMAP3430_CMD0 (1 << 4)
-#define OMAP3430_RACEN0 (1 << 3)
-#define OMAP3430_RAC0 (1 << 2)
-#define OMAP3430_RAV0 (1 << 1)
-#define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0)
-
-/* PRM_VC_I2C_CFG */
-#define OMAP3430_HSMASTER (1 << 5)
-#define OMAP3430_SREN (1 << 4)
-#define OMAP3430_HSEN (1 << 3)
-#define OMAP3430_MCODE_SHIFT 0
-#define OMAP3430_MCODE_MASK (0x7 << 0)
-
-/* PRM_VC_BYPASS_VAL */
-#define OMAP3430_VALID (1 << 24)
-#define OMAP3430_DATA_SHIFT 16
-#define OMAP3430_DATA_MASK (0xff << 16)
-#define OMAP3430_REGADDR_SHIFT 8
-#define OMAP3430_REGADDR_MASK (0xff << 8)
-#define OMAP3430_SLAVEADDR_SHIFT 0
-#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
-
-/* PRM_RSTCTRL */
-#define OMAP3430_RST_DPLL3 (1 << 2)
-#define OMAP3430_RST_GS (1 << 1)
-
-/* PRM_RSTTIME */
-#define OMAP3430_RSTTIME2_SHIFT 8
-#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
-#define OMAP3430_RSTTIME1_SHIFT 0
-#define OMAP3430_RSTTIME1_MASK (0xff << 0)
-
-/* PRM_RSTST */
-#define OMAP3430_ICECRUSHER_RST (1 << 10)
-#define OMAP3430_ICEPICK_RST (1 << 9)
-#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8)
-#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7)
-#define OMAP3430_EXTERNAL_WARM_RST (1 << 6)
-#define OMAP3430_SECURE_WD_RST (1 << 5)
-#define OMAP3430_MPU_WD_RST (1 << 4)
-#define OMAP3430_SECURITY_VIOL_RST (1 << 3)
-#define OMAP3430_GLOBAL_SW_RST (1 << 1)
-#define OMAP3430_GLOBAL_COLD_RST (1 << 0)
-
-/* PRM_VOLTCTRL */
-#define OMAP3430_SEL_VMODE (1 << 4)
-#define OMAP3430_SEL_OFF (1 << 3)
-#define OMAP3430_AUTO_OFF (1 << 2)
-#define OMAP3430_AUTO_RET (1 << 1)
-#define OMAP3430_AUTO_SLEEP (1 << 0)
-
-/* PRM_SRAM_PCHARGE */
-#define OMAP3430_PCHARGE_TIME_SHIFT 0
-#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
-
-/* PRM_CLKSRC_CTRL */
-#define OMAP3430_SYSCLKDIV_SHIFT 6
-#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
-#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
-#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
-#define OMAP3430_SYSCLKSEL_SHIFT 0
-#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
-
-/* PRM_VOLTSETUP1 */
-#define OMAP3430_SETUP_TIME2_SHIFT 16
-#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
-#define OMAP3430_SETUP_TIME1_SHIFT 0
-#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
-
-/* PRM_VOLTOFFSET */
-#define OMAP3430_OFFSET_TIME_SHIFT 0
-#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
-
-/* PRM_CLKSETUP */
-#define OMAP3430_SETUP_TIME_SHIFT 0
-#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
-
-/* PRM_POLCTRL */
-#define OMAP3430_OFFMODE_POL (1 << 3)
-#define OMAP3430_CLKOUT_POL (1 << 2)
-#define OMAP3430_CLKREQ_POL (1 << 1)
-#define OMAP3430_EXTVOL_POL (1 << 0)
-
-/* PRM_VOLTSETUP2 */
-#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
-#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
-
-/* PRM_VP1_CONFIG specific bits */
-
-/* PRM_VP1_VSTEPMIN specific bits */
-
-/* PRM_VP1_VSTEPMAX specific bits */
-
-/* PRM_VP1_VLIMITTO specific bits */
-
-/* PRM_VP1_VOLTAGE specific bits */
-
-/* PRM_VP1_STATUS specific bits */
-
-/* PRM_VP2_CONFIG specific bits */
-
-/* PRM_VP2_VSTEPMIN specific bits */
-
-/* PRM_VP2_VSTEPMAX specific bits */
-
-/* PRM_VP2_VLIMITTO specific bits */
-
-/* PRM_VP2_VOLTAGE specific bits */
-
-/* PRM_VP2_STATUS specific bits */
-
-/* RM_RSTST_NEON specific bits */
-
-/* PM_WKDEP_NEON specific bits */
-
-/* PM_PWSTCTRL_NEON specific bits */
-
-/* PM_PWSTST_NEON specific bits */
-
-/* PM_PREPWSTST_NEON specific bits */
-
-#endif
--
1.5.3.6
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 10/10] ARM: OMAP: Move STI support to drivers/misc
2008-03-12 10:45 ` [PATCH 9/10] ARM: OMAP3: Rename prm_regbits_34xx.h to prm-regbits-34xx.h Tony Lindgren
@ 2008-03-12 10:45 ` Tony Lindgren
0 siblings, 0 replies; 12+ messages in thread
From: Tony Lindgren @ 2008-03-12 10:45 UTC (permalink / raw)
To: linux-omap; +Cc: Tony Lindgren
This is to allow syncing plat-omap with mainline kernel.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/plat-omap/Makefile | 3 -
arch/arm/plat-omap/sti/Makefile | 4 -
arch/arm/plat-omap/sti/sti-console.c | 189 ---------------
arch/arm/plat-omap/sti/sti-fifo.c | 117 ---------
arch/arm/plat-omap/sti/sti-netlink.c | 152 ------------
arch/arm/plat-omap/sti/sti.c | 432 ----------------------------------
drivers/misc/Makefile | 1 +
drivers/misc/sti/Makefile | 4 +
drivers/misc/sti/sti-console.c | 189 +++++++++++++++
drivers/misc/sti/sti-fifo.c | 117 +++++++++
drivers/misc/sti/sti-netlink.c | 152 ++++++++++++
drivers/misc/sti/sti.c | 432 ++++++++++++++++++++++++++++++++++
12 files changed, 895 insertions(+), 897 deletions(-)
delete mode 100644 arch/arm/plat-omap/sti/Makefile
delete mode 100644 arch/arm/plat-omap/sti/sti-console.c
delete mode 100644 arch/arm/plat-omap/sti/sti-fifo.c
delete mode 100644 arch/arm/plat-omap/sti/sti-netlink.c
delete mode 100644 arch/arm/plat-omap/sti/sti.c
create mode 100644 drivers/misc/sti/Makefile
create mode 100644 drivers/misc/sti/sti-console.c
create mode 100644 drivers/misc/sti/sti-fifo.c
create mode 100644 drivers/misc/sti/sti-netlink.c
create mode 100644 drivers/misc/sti/sti.c
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index c1ada8f..a3f1f5c 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -14,9 +14,6 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
-# STI support
-obj-$(CONFIG_OMAP_STI) += sti/
-
obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_BOOT_REASON) += bootreason.o
diff --git a/arch/arm/plat-omap/sti/Makefile b/arch/arm/plat-omap/sti/Makefile
deleted file mode 100644
index 6ad9bb3..0000000
--- a/arch/arm/plat-omap/sti/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-obj-y += sti.o sti-fifo.o
-
-obj-$(CONFIG_OMAP_STI_CONSOLE) += sti-console.o
-obj-$(CONFIG_NET) += sti-netlink.o
diff --git a/arch/arm/plat-omap/sti/sti-console.c b/arch/arm/plat-omap/sti/sti-console.c
deleted file mode 100644
index 451a139..0000000
--- a/arch/arm/plat-omap/sti/sti-console.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Console support for OMAP STI/XTI
- *
- * Copyright (C) 2004, 2005, 2006 Nokia Corporation
- * Written by: Paul Mundt <paul.mundt@nokia.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/tty.h>
-#include <linux/tty_driver.h>
-#include <asm/arch/sti.h>
-#include <asm/arch/board.h>
-
-#define DRV_NAME "sticon"
-
-static struct tty_driver *tty_driver;
-static DEFINE_SPINLOCK(sti_console_lock);
-static unsigned int sti_console_channel = -1;
-static int sti_line_done = -1;
-
-/*
- * Write a string to any channel (including terminating NULL)
- * Returns number of characters written.
- */
-static int sti_channel_puts(const char *string, unsigned int channel, int len)
-{
- int count = 0;
-
- /*
- * sti_line_done is needed to determine when we have reached the
- * end of the line. write() has a tendency to hand us small
- * strings which otherwise end up creating newlines.. we need to
- * keep the channel open and in append mode until the line has
- * been terminated.
- */
- if (sti_line_done != 0) {
-#ifdef __LITTLE_ENDIAN
- sti_channel_writeb(0xc3, channel);
-#else
- sti_channel_writeb(0xc0, channel);
-#endif
- xchg(&sti_line_done, 0);
- }
-
- while (*string && count != len) {
- char c = *string++;
-
- count++;
-
- if (c == '\n') {
- xchg(&sti_line_done, 1);
- sti_channel_writeb(0, channel);
- break;
- } else
- sti_channel_writeb(c, channel);
- }
-
- if (sti_line_done)
- sti_channel_flush(channel);
-
- return count;
-}
-
-static int sti_tty_open(struct tty_struct *tty, struct file *filp)
-{
- return 0;
-}
-
-static int sti_tty_write(struct tty_struct *tty,
- const unsigned char *buf, int len)
-{
- unsigned long flags;
- int bytes;
-
- spin_lock_irqsave(&sti_console_lock, flags);
- bytes = sti_channel_puts(buf, sti_console_channel, len);
- spin_unlock_irqrestore(&sti_console_lock, flags);
-
- return bytes;
-}
-
-static int sti_tty_write_room(struct tty_struct *tty)
-{
- return 0x100000;
-}
-
-static int sti_tty_chars_in_buffer(struct tty_struct *tty)
-{
- return 0;
-}
-
-static struct tty_operations sti_tty_ops = {
- .open = sti_tty_open,
- .write = sti_tty_write,
- .write_room = sti_tty_write_room,
- .chars_in_buffer = sti_tty_chars_in_buffer,
-};
-
-static void sti_console_write(struct console *c, const char *s, unsigned n)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&sti_console_lock, flags);
- sti_channel_puts(s, sti_console_channel, n);
- spin_unlock_irqrestore(&sti_console_lock, flags);
-}
-
-static struct tty_driver *sti_console_device(struct console *c, int *index)
-{
- *index = c->index;
- return tty_driver;
-}
-
-static int sti_console_setup(struct console *c, char *opts)
-{
- return 0;
-}
-
-static struct console sti_console = {
- .name = DRV_NAME,
- .write = sti_console_write,
- .device = sti_console_device,
- .setup = sti_console_setup,
- .flags = CON_PRINTBUFFER | CON_ENABLED,
- .index = -1,
-};
-
-static int __init sti_console_init(void)
-{
- const struct omap_sti_console_config *info;
-
- info = omap_get_config(OMAP_TAG_STI_CONSOLE,
- struct omap_sti_console_config);
- if (info && info->enable) {
- add_preferred_console(DRV_NAME, 0, NULL);
-
- sti_console_channel = info->channel;
- }
-
- if (unlikely(sti_console_channel == -1))
- return -EINVAL;
-
- register_console(&sti_console);
-
- return 0;
-}
-__initcall(sti_console_init);
-
-static int __init sti_tty_init(void)
-{
- struct tty_driver *tty;
- int ret;
-
- tty = alloc_tty_driver(1);
- if (!tty)
- return -ENOMEM;
-
- tty->name = DRV_NAME;
- tty->driver_name = DRV_NAME;
- tty->major = 0; /* dynamic major */
- tty->minor_start = 0;
- tty->type = TTY_DRIVER_TYPE_SYSTEM;
- tty->subtype = SYSTEM_TYPE_SYSCONS;
- tty->init_termios = tty_std_termios;
-
- tty_set_operations(tty, &sti_tty_ops);
-
- ret = tty_register_driver(tty);
- if (ret) {
- put_tty_driver(tty);
- return ret;
- }
-
- tty_driver = tty;
- return 0;
-}
-late_initcall(sti_tty_init);
-
-module_param(sti_console_channel, uint, 0);
-MODULE_PARM_DESC(sti_console_channel, "STI console channel");
-MODULE_AUTHOR("Paul Mundt");
-MODULE_DESCRIPTION("OMAP STI console support");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-omap/sti/sti-fifo.c b/arch/arm/plat-omap/sti/sti-fifo.c
deleted file mode 100644
index 4069d9b..0000000
--- a/arch/arm/plat-omap/sti/sti-fifo.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * STI RX FIFO Support
- *
- * Copyright (C) 2005, 2006 Nokia Corporation
- * Written by: Paul Mundt <paul.mundt@nokia.com> and
- * Roman Tereshonkov <roman.tereshonkov@nokia.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <asm/arch/sti.h>
-
-#define STI_READ_BUFFER_SIZE 1024
-#define sti_buf_pos(pos) ((sti_crb->bufpos + (pos)) % \
- STI_READ_BUFFER_SIZE)
-
-static struct sti_cycle_buffer {
- int bufpos;
- int datalen;
- unsigned char *buf;
-} *sti_crb;
-
-/**
- * sti_read_packet - STI read packet (read an entire STI packet)
- * @buf: Buffer to store the packet.
- * @maxsize: Maximum size requested.
- *
- * This reads in a single completed STI packet from the RX FIFOs and
- * places it in @buf for further processing.
- *
- * The return value is < 0 on error, and >= 0 for the number of bytes
- * actually read. As per the STI specification, we require a 0xC1 to
- * indicate the end of the packet, and we don't return the packet until
- * we've read the entire thing in.
- *
- * Due to the size of the FIFOs, it's unrealistic to constantly drain
- * this for 1 or 2 bytes at a time, so we assemble it here and return
- * the whole thing.
- */
-int sti_read_packet(unsigned char *buf, int maxsize)
-{
- unsigned int pos;
-
- if (unlikely(!buf))
- return -EINVAL;
- if (!sti_crb->datalen)
- return 0;
-
- pos = sti_buf_pos(sti_crb->datalen - 1);
- /* End of packet */
- if (sti_crb->buf[pos] == 0xC1) {
- int i;
-
- for (i = 0; i < sti_crb->datalen && i < maxsize; i++) {
- pos = sti_buf_pos(i);
- buf[i] = sti_crb->buf[pos];
- }
-
- sti_crb->bufpos = sti_buf_pos(i);
- sti_crb->datalen -= i;
-
- return i;
- }
-
- return 0;
-}
-EXPORT_SYMBOL(sti_read_packet);
-
-static void sti_fifo_irq(unsigned long arg)
-{
- /* If there is data read it */
- while (!(sti_readl(STI_RX_STATUS) & STI_RXFIFO_EMPTY)) {
- unsigned int pos = sti_buf_pos(sti_crb->datalen);
-
- sti_crb->buf[pos] = sti_readl(STI_RX_DR);
- sti_crb->datalen++;
- }
-
- sti_ack_irq(STI_RX_INT);
-}
-
-static int __init sti_fifo_init(void)
-{
- unsigned int size;
- int ret;
-
- size = sizeof(struct sti_cycle_buffer) + STI_READ_BUFFER_SIZE;
- sti_crb = kmalloc(size, GFP_KERNEL);
- if (!sti_crb)
- return -ENOMEM;
-
- sti_crb->bufpos = sti_crb->datalen = 0;
- sti_crb->buf = (unsigned char *)(sti_crb + sizeof(*sti_crb));
-
- ret = sti_request_irq(STI_RX_INT, sti_fifo_irq, 0);
- if (ret != 0)
- kfree(sti_crb);
-
- return ret;
-}
-
-static void __exit sti_fifo_exit(void)
-{
- sti_free_irq(STI_RX_INT);
- kfree(sti_crb);
-}
-
-module_init(sti_fifo_init);
-module_exit(sti_fifo_exit);
-
-MODULE_AUTHOR("Paul Mundt, Roman Tereshonkov");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-omap/sti/sti-netlink.c b/arch/arm/plat-omap/sti/sti-netlink.c
deleted file mode 100644
index ca3533e..0000000
--- a/arch/arm/plat-omap/sti/sti-netlink.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * OMAP STI/XTI communications interface via netlink socket.
- *
- * Copyright (C) 2004, 2005, 2006 Nokia Corporation
- * Written by: Paul Mundt <paul.mundt@nokia.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/netlink.h>
-#include <linux/socket.h>
-#include <linux/skbuff.h>
-#include <linux/mutex.h>
-#include <net/sock.h>
-#include <asm/arch/sti.h>
-
-static struct sock *sti_sock;
-static DEFINE_MUTEX(sti_netlink_mutex);
-
-enum {
- STI_READ,
- STI_WRITE,
-};
-
-static int sti_netlink_read(int pid, int seq, void *payload, int size)
-{
- struct sk_buff *skb;
- struct nlmsghdr *nlh;
- int ret, len = NLMSG_SPACE(size);
- unsigned char *tail;
-
- skb = alloc_skb(len, GFP_KERNEL);
- if (!skb)
- return -ENOMEM;
-
- tail = skb->tail;
- nlh = NLMSG_PUT(skb, pid, seq, STI_READ,
- len - (sizeof(struct nlmsghdr)));
- nlh->nlmsg_flags = 0;
- memcpy(NLMSG_DATA(nlh), payload, size);
- nlh->nlmsg_len = skb->tail - tail;
-
- ret = netlink_unicast(sti_sock, skb, pid, MSG_DONTWAIT);
- if (ret > 0)
- ret = 0;
-
- return ret;
-
-nlmsg_failure:
- if (skb)
- kfree_skb(skb);
-
- return -EINVAL;
-}
-
-/*
- * We abuse nlmsg_type and nlmsg_flags for our purposes.
- *
- * The ID is encoded into the upper 8 bits of the nlmsg_type, while the
- * channel number is encoded into the upper 8 bits of the nlmsg_flags.
- */
-static int sti_netlink_receive_msg(struct sk_buff *skb, struct nlmsghdr *nlh)
-{
- void *data;
- u8 chan, id;
- int size, ret = 0, len = 0;
-
- data = NLMSG_DATA(nlh);
- chan = (nlh->nlmsg_flags >> 8) & 0xff;
- id = (nlh->nlmsg_type >> 8) & 0xff;
- size = (int)(nlh->nlmsg_len - ((char *)data - (char *)nlh));
-
- switch (nlh->nlmsg_type & 0xff) {
- case STI_WRITE:
- sti_channel_write_trace(size, id, data, chan);
- break;
- case STI_READ:
- data = kmalloc(size, GFP_KERNEL);
- if (!data)
- return -ENOMEM;
- memset(data, 0, size);
-
- len = sti_read_packet(data, size);
- ret = sti_netlink_read(NETLINK_CB(skb).pid, nlh->nlmsg_seq,
- data, len);
- kfree(data);
- break;
- default:
- return -ENOTTY;
- }
-
- return ret;
-}
-
-static int sti_netlink_receive_skb(struct sk_buff *skb)
-{
- while (skb->len >= NLMSG_SPACE(0)) {
- struct nlmsghdr *nlh;
- u32 rlen;
- int ret;
-
- nlh = (struct nlmsghdr *)skb->data;
- if (nlh->nlmsg_len < sizeof(struct nlmsghdr) ||
- skb->len < nlh->nlmsg_len)
- break;
-
- rlen = NLMSG_ALIGN(nlh->nlmsg_len);
- if (rlen > skb->len)
- rlen = skb->len;
-
- ret = sti_netlink_receive_msg(skb, nlh);
- if (ret)
- netlink_ack(skb, nlh, -ret);
- else if (nlh->nlmsg_flags & NLM_F_ACK)
- netlink_ack(skb, nlh, 0);
-
- skb_pull(skb, rlen);
- }
-
- return 0;
-}
-
-static void sti_netlink_receive(struct sk_buff *skb)
-{
- if (!mutex_trylock(&sti_netlink_mutex))
- return;
-
- sti_netlink_receive_skb(skb);
- mutex_unlock(&sti_netlink_mutex);
-}
-
-static int __init sti_netlink_init(void)
-{
- sti_sock = netlink_kernel_create(&init_net, NETLINK_USERSOCK, 0,
- sti_netlink_receive, NULL,
- THIS_MODULE);
- if (!sti_sock) {
- printk(KERN_ERR "STI: Failed to create netlink socket\n");
- return -ENODEV;
- }
-
- return 0;
-}
-
-module_init(sti_netlink_init);
-
-MODULE_AUTHOR("Paul Mundt");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("STI netlink-driven communications interface");
diff --git a/arch/arm/plat-omap/sti/sti.c b/arch/arm/plat-omap/sti/sti.c
deleted file mode 100644
index e828860..0000000
--- a/arch/arm/plat-omap/sti/sti.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * Support functions for OMAP STI/XTI (Serial Tracing Interface)
- *
- * Copyright (C) 2004, 2005, 2006 Nokia Corporation
- * Written by: Paul Mundt <paul.mundt@nokia.com>
- *
- * STI initialization code and channel handling
- * from Juha Yrjölä <juha.yrjola@nokia.com>.
- *
- * XTI initialization
- * from Roman Tereshonkov <roman.tereshonkov@nokia.com>.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <asm/arch/sti.h>
-#include <asm/byteorder.h>
-
-static struct clk *sti_ck;
-unsigned long sti_base, sti_channel_base;
-static unsigned long sti_kern_mask = STIEn;
-static unsigned long sti_irq_mask = STI_IRQSTATUS_MASK;
-static DEFINE_SPINLOCK(sti_lock);
-
-static struct sti_irqdesc {
- irqreturn_t (*func)(unsigned long);
- unsigned long data;
-} ____cacheline_aligned sti_irq_desc[STI_NR_IRQS];
-
-void sti_channel_write_trace(int len, int id, void *data, unsigned int channel)
-{
- const u8 *tpntr = data;
-
- sti_channel_writeb(id, channel);
-
- if (cpu_is_omap16xx())
- /* Check u32 boundary */
- if (!((u32)data & (STI_PERCHANNEL_SIZE - 1)) &&
- (len >= STI_PERCHANNEL_SIZE)) {
- const u32 *asrc = data;
-
- do {
- sti_channel_writel(cpu_to_be32(*asrc++),
- channel);
- len -= STI_PERCHANNEL_SIZE;
- } while (len >= STI_PERCHANNEL_SIZE);
-
- tpntr = (const u8 *)asrc;
- }
-
- while (len--)
- sti_channel_writeb(*tpntr++, channel);
-
- sti_channel_flush(channel);
-}
-EXPORT_SYMBOL(sti_channel_write_trace);
-
-void sti_enable_irq(unsigned int id)
-{
- spin_lock_irq(&sti_lock);
- sti_writel(1 << id, STI_IRQSETEN);
- spin_unlock_irq(&sti_lock);
-}
-EXPORT_SYMBOL(sti_enable_irq);
-
-void sti_disable_irq(unsigned int id)
-{
- spin_lock_irq(&sti_lock);
-
- if (cpu_is_omap16xx())
- sti_writel(1 << id, STI_IRQCLREN);
- else if (cpu_is_omap24xx())
- sti_writel(sti_readl(STI_IRQSETEN) & ~(1 << id), STI_IRQSETEN);
- else
- BUG();
-
- spin_unlock_irq(&sti_lock);
-}
-EXPORT_SYMBOL(sti_disable_irq);
-
-void sti_ack_irq(unsigned int id)
-{
- /* Even though the clear state is 0, we have to write 1 to clear */
- sti_writel(1 << id, STI_IRQSTATUS);
-}
-EXPORT_SYMBOL(sti_ack_irq);
-
-int sti_request_irq(unsigned int irq, void *handler, unsigned long arg)
-{
- struct sti_irqdesc *desc;
-
- if (unlikely(!handler || irq > STI_NR_IRQS))
- return -EINVAL;
-
- desc = sti_irq_desc + irq;
- if (unlikely(desc->func)) {
- printk(KERN_WARNING "STI: Attempting to request in-use IRQ "
- "%d, consider fixing your code..\n", irq);
- return -EBUSY;
- }
-
- desc->func = handler;
- desc->data = arg;
-
- sti_enable_irq(irq);
- return 0;
-}
-EXPORT_SYMBOL(sti_request_irq);
-
-void sti_free_irq(unsigned int irq)
-{
- struct sti_irqdesc *desc = sti_irq_desc + irq;
-
- if (unlikely(irq > STI_NR_IRQS))
- return;
-
- sti_disable_irq(irq);
-
- desc->func = NULL;
- desc->data = 0;
-}
-EXPORT_SYMBOL(sti_free_irq);
-
-/*
- * This is a bit heavy, so normally we would defer this to a tasklet.
- * Unfortunately tasklets are too slow for the RX FIFO interrupt (and
- * possibly some others), so we just do the irqdesc walking here.
- */
-static irqreturn_t sti_interrupt(int irq, void *dev_id)
-{
- int ret = IRQ_NONE;
- u16 status;
- int i;
-
- status = sti_readl(STI_IRQSTATUS) & sti_irq_mask;
-
- for (i = 0; status; i++) {
- struct sti_irqdesc *desc = sti_irq_desc + i;
- u16 id = 1 << i;
-
- if (!(status & id))
- continue;
-
- if (likely(desc && desc->func))
- ret |= desc->func(desc->data);
- if (unlikely(ret == IRQ_NONE)) {
- printk("STI: spurious interrupt (id %d)\n", id);
- sti_disable_irq(i);
- sti_ack_irq(i);
- ret = IRQ_HANDLED;
- }
-
- status &= ~id;
- }
-
- return IRQ_RETVAL(ret);
-}
-
-static void omap_sti_reset(void)
-{
- int i;
-
- /* Reset STI module */
- sti_writel(0x02, STI_SYSCONFIG);
-
- /* Wait a while for the STI module to complete its reset */
- for (i = 0; i < 10000; i++)
- if (sti_readl(STI_SYSSTATUS) & 1)
- break;
-}
-
-static int __init sti_init(void)
-{
- char buf[64];
- int i;
-
- if (cpu_is_omap16xx()) {
- /* Release ARM Rhea buses peripherals enable */
- sti_writel(sti_readl(ARM_RSTCT2) | 0x0001, ARM_RSTCT2);
-
- /* Enable TC1_CK (functional clock) */
- sti_ck = clk_get(NULL, "tc1_ck");
- } else if (cpu_is_omap24xx())
- /* Enable emulation tools clock */
- sti_ck = clk_get(NULL, "emul_ck");
-
- if (IS_ERR(sti_ck))
- return PTR_ERR(sti_ck);
-
- clk_enable(sti_ck);
-
- /* Reset STI module */
- omap_sti_reset();
-
- /* Enable STI */
- sti_trace_enable(MPUCmdEn);
-
- /* Change to custom serial protocol */
- sti_writel(0x01, STI_SERIAL_CFG);
-
- /* Set STI clock control register to normal mode */
- sti_writel(0x00, STI_CLK_CTRL);
-
- i = sti_readl(STI_REVISION);
- snprintf(buf, sizeof(buf), "OMAP STI support loaded (HW v%u.%u)\n",
- (i >> 4) & 0x0f, i & 0x0f);
- printk(KERN_INFO "%s", buf);
-
- sti_channel_write_trace(strlen(buf), 0xc3, buf, 239);
-
- return 0;
-}
-
-static void sti_exit(void)
-{
- u32 tmp;
-
- /*
- * This should have already been done by reset, but we switch off
- * STI entirely just for added sanity..
- */
- tmp = sti_readl(STI_ER);
- tmp &= ~STIEn;
- sti_writel(tmp, STI_ER);
-
- clk_disable(sti_ck);
- clk_put(sti_ck);
-}
-
-static void __sti_trace_enable(int event)
-{
- u32 tmp;
-
- tmp = sti_readl(STI_ER);
- tmp |= sti_kern_mask | event;
- sti_writel(tmp, STI_ER);
-}
-
-int sti_trace_enable(int event)
-{
- spin_lock_irq(&sti_lock);
- sti_kern_mask |= event;
- __sti_trace_enable(event);
- spin_unlock_irq(&sti_lock);
-
- return 0;
-}
-EXPORT_SYMBOL(sti_trace_enable);
-
-static void __sti_trace_disable(int event)
-{
- u32 tmp;
-
- tmp = sti_readl(STI_DR);
-
- if (cpu_is_omap16xx()) {
- tmp |= event;
- tmp &= ~sti_kern_mask;
- } else if (cpu_is_omap24xx()) {
- tmp &= ~event;
- tmp |= sti_kern_mask;
- } else
- BUG();
-
- sti_writel(tmp, STI_DR);
-}
-
-void sti_trace_disable(int event)
-{
- spin_lock_irq(&sti_lock);
- sti_kern_mask &= ~event;
- __sti_trace_disable(event);
- spin_unlock_irq(&sti_lock);
-}
-EXPORT_SYMBOL(sti_trace_disable);
-
-static ssize_t
-sti_trace_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- return sprintf(buf, "0x%08lx\n", sti_readl(STI_ER));
-}
-
-static ssize_t
-sti_trace_store(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t count)
-{
- int evt = simple_strtoul(buf, NULL, 0);
- int mask = ~evt;
-
- spin_lock_irq(&sti_lock);
- __sti_trace_disable(mask);
- __sti_trace_enable(evt);
- spin_unlock_irq(&sti_lock);
-
- return count;
-}
-static DEVICE_ATTR(trace, S_IRUGO | S_IWUSR, sti_trace_show, sti_trace_store);
-
-static ssize_t
-sti_imask_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- return sprintf(buf, "0x%04lx\n", sti_irq_mask);
-}
-
-static ssize_t
-sti_imask_store(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t count)
-{
- spin_lock_irq(&sti_lock);
- sti_irq_mask = simple_strtoul(buf, NULL, 0);
- spin_unlock_irq(&sti_lock);
-
- return count;
-}
-static DEVICE_ATTR(imask, S_IRUGO | S_IWUSR, sti_imask_show, sti_imask_store);
-
-static int __devinit sti_probe(struct platform_device *pdev)
-{
- struct resource *res, *cres;
- int ret;
-
- if (pdev->num_resources != 3) {
- dev_err(&pdev->dev, "invalid number of resources: %d\n",
- pdev->num_resources);
- return -ENODEV;
- }
-
- /* STI base */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (unlikely(!res)) {
- dev_err(&pdev->dev, "invalid mem resource\n");
- return -ENODEV;
- }
-
- /* Channel base */
- cres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (unlikely(!cres)) {
- dev_err(&pdev->dev, "invalid channel mem resource\n");
- return -ENODEV;
- }
-
- ret = device_create_file(&pdev->dev, &dev_attr_trace);
- if (unlikely(ret != 0))
- return ret;
-
- ret = device_create_file(&pdev->dev, &dev_attr_imask);
- if (unlikely(ret != 0))
- goto err;
-
- sti_base = res->start;
-
- /*
- * OMAP 16xx keeps channels in a relatively sane location,
- * whereas 24xx maps them much further out, and so they must be
- * remapped.
- */
- if (cpu_is_omap16xx())
- sti_channel_base = cres->start;
- else if (cpu_is_omap24xx()) {
- unsigned int size = cres->end - cres->start;
-
- sti_channel_base = (unsigned long)ioremap(cres->start, size);
- if (unlikely(!sti_channel_base)) {
- ret = -ENODEV;
- goto err_badremap;
- }
- }
-
- ret = request_irq(platform_get_irq(pdev, 0), sti_interrupt,
- IRQF_DISABLED, "sti", NULL);
- if (unlikely(ret != 0))
- goto err_badirq;
-
- return sti_init();
-
-err_badirq:
- iounmap((void *)sti_channel_base);
-err_badremap:
- device_remove_file(&pdev->dev, &dev_attr_imask);
-err:
- device_remove_file(&pdev->dev, &dev_attr_trace);
-
- return ret;
-}
-
-static int __devexit sti_remove(struct platform_device *pdev)
-{
- unsigned int irq = platform_get_irq(pdev, 0);
-
- if (cpu_is_omap24xx())
- iounmap((void *)sti_channel_base);
-
- device_remove_file(&pdev->dev, &dev_attr_trace);
- device_remove_file(&pdev->dev, &dev_attr_imask);
- free_irq(irq, NULL);
- sti_exit();
-
- return 0;
-}
-
-static struct platform_driver sti_driver = {
- .probe = sti_probe,
- .remove = __devexit_p(sti_remove),
- .driver = {
- .name = "sti",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init sti_module_init(void)
-{
- return platform_driver_register(&sti_driver);
-}
-
-static void __exit sti_module_exit(void)
-{
- platform_driver_unregister(&sti_driver);
-}
-subsys_initcall(sti_module_init);
-module_exit(sti_module_exit);
-
-MODULE_AUTHOR("Paul Mundt, Juha Yrjölä, Roman Tereshonkov");
-MODULE_LICENSE("GPL");
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3b12f5d..d65b43d 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -5,6 +5,7 @@ obj- := misc.o # Dummy rule to force built-in.o to be made
obj-$(CONFIG_IBM_ASM) += ibmasm/
obj-$(CONFIG_HDPU_FEATURES) += hdpuftrs/
+obj-$(CONFIG_OMAP_STI) += sti/
obj-$(CONFIG_MSI_LAPTOP) += msi-laptop.o
obj-$(CONFIG_ACER_WMI) += acer-wmi.o
obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
diff --git a/drivers/misc/sti/Makefile b/drivers/misc/sti/Makefile
new file mode 100644
index 0000000..6ad9bb3
--- /dev/null
+++ b/drivers/misc/sti/Makefile
@@ -0,0 +1,4 @@
+obj-y += sti.o sti-fifo.o
+
+obj-$(CONFIG_OMAP_STI_CONSOLE) += sti-console.o
+obj-$(CONFIG_NET) += sti-netlink.o
diff --git a/drivers/misc/sti/sti-console.c b/drivers/misc/sti/sti-console.c
new file mode 100644
index 0000000..451a139
--- /dev/null
+++ b/drivers/misc/sti/sti-console.c
@@ -0,0 +1,189 @@
+/*
+ * Console support for OMAP STI/XTI
+ *
+ * Copyright (C) 2004, 2005, 2006 Nokia Corporation
+ * Written by: Paul Mundt <paul.mundt@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <asm/arch/sti.h>
+#include <asm/arch/board.h>
+
+#define DRV_NAME "sticon"
+
+static struct tty_driver *tty_driver;
+static DEFINE_SPINLOCK(sti_console_lock);
+static unsigned int sti_console_channel = -1;
+static int sti_line_done = -1;
+
+/*
+ * Write a string to any channel (including terminating NULL)
+ * Returns number of characters written.
+ */
+static int sti_channel_puts(const char *string, unsigned int channel, int len)
+{
+ int count = 0;
+
+ /*
+ * sti_line_done is needed to determine when we have reached the
+ * end of the line. write() has a tendency to hand us small
+ * strings which otherwise end up creating newlines.. we need to
+ * keep the channel open and in append mode until the line has
+ * been terminated.
+ */
+ if (sti_line_done != 0) {
+#ifdef __LITTLE_ENDIAN
+ sti_channel_writeb(0xc3, channel);
+#else
+ sti_channel_writeb(0xc0, channel);
+#endif
+ xchg(&sti_line_done, 0);
+ }
+
+ while (*string && count != len) {
+ char c = *string++;
+
+ count++;
+
+ if (c == '\n') {
+ xchg(&sti_line_done, 1);
+ sti_channel_writeb(0, channel);
+ break;
+ } else
+ sti_channel_writeb(c, channel);
+ }
+
+ if (sti_line_done)
+ sti_channel_flush(channel);
+
+ return count;
+}
+
+static int sti_tty_open(struct tty_struct *tty, struct file *filp)
+{
+ return 0;
+}
+
+static int sti_tty_write(struct tty_struct *tty,
+ const unsigned char *buf, int len)
+{
+ unsigned long flags;
+ int bytes;
+
+ spin_lock_irqsave(&sti_console_lock, flags);
+ bytes = sti_channel_puts(buf, sti_console_channel, len);
+ spin_unlock_irqrestore(&sti_console_lock, flags);
+
+ return bytes;
+}
+
+static int sti_tty_write_room(struct tty_struct *tty)
+{
+ return 0x100000;
+}
+
+static int sti_tty_chars_in_buffer(struct tty_struct *tty)
+{
+ return 0;
+}
+
+static struct tty_operations sti_tty_ops = {
+ .open = sti_tty_open,
+ .write = sti_tty_write,
+ .write_room = sti_tty_write_room,
+ .chars_in_buffer = sti_tty_chars_in_buffer,
+};
+
+static void sti_console_write(struct console *c, const char *s, unsigned n)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&sti_console_lock, flags);
+ sti_channel_puts(s, sti_console_channel, n);
+ spin_unlock_irqrestore(&sti_console_lock, flags);
+}
+
+static struct tty_driver *sti_console_device(struct console *c, int *index)
+{
+ *index = c->index;
+ return tty_driver;
+}
+
+static int sti_console_setup(struct console *c, char *opts)
+{
+ return 0;
+}
+
+static struct console sti_console = {
+ .name = DRV_NAME,
+ .write = sti_console_write,
+ .device = sti_console_device,
+ .setup = sti_console_setup,
+ .flags = CON_PRINTBUFFER | CON_ENABLED,
+ .index = -1,
+};
+
+static int __init sti_console_init(void)
+{
+ const struct omap_sti_console_config *info;
+
+ info = omap_get_config(OMAP_TAG_STI_CONSOLE,
+ struct omap_sti_console_config);
+ if (info && info->enable) {
+ add_preferred_console(DRV_NAME, 0, NULL);
+
+ sti_console_channel = info->channel;
+ }
+
+ if (unlikely(sti_console_channel == -1))
+ return -EINVAL;
+
+ register_console(&sti_console);
+
+ return 0;
+}
+__initcall(sti_console_init);
+
+static int __init sti_tty_init(void)
+{
+ struct tty_driver *tty;
+ int ret;
+
+ tty = alloc_tty_driver(1);
+ if (!tty)
+ return -ENOMEM;
+
+ tty->name = DRV_NAME;
+ tty->driver_name = DRV_NAME;
+ tty->major = 0; /* dynamic major */
+ tty->minor_start = 0;
+ tty->type = TTY_DRIVER_TYPE_SYSTEM;
+ tty->subtype = SYSTEM_TYPE_SYSCONS;
+ tty->init_termios = tty_std_termios;
+
+ tty_set_operations(tty, &sti_tty_ops);
+
+ ret = tty_register_driver(tty);
+ if (ret) {
+ put_tty_driver(tty);
+ return ret;
+ }
+
+ tty_driver = tty;
+ return 0;
+}
+late_initcall(sti_tty_init);
+
+module_param(sti_console_channel, uint, 0);
+MODULE_PARM_DESC(sti_console_channel, "STI console channel");
+MODULE_AUTHOR("Paul Mundt");
+MODULE_DESCRIPTION("OMAP STI console support");
+MODULE_LICENSE("GPL");
diff --git a/drivers/misc/sti/sti-fifo.c b/drivers/misc/sti/sti-fifo.c
new file mode 100644
index 0000000..4069d9b
--- /dev/null
+++ b/drivers/misc/sti/sti-fifo.c
@@ -0,0 +1,117 @@
+/*
+ * STI RX FIFO Support
+ *
+ * Copyright (C) 2005, 2006 Nokia Corporation
+ * Written by: Paul Mundt <paul.mundt@nokia.com> and
+ * Roman Tereshonkov <roman.tereshonkov@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <asm/arch/sti.h>
+
+#define STI_READ_BUFFER_SIZE 1024
+#define sti_buf_pos(pos) ((sti_crb->bufpos + (pos)) % \
+ STI_READ_BUFFER_SIZE)
+
+static struct sti_cycle_buffer {
+ int bufpos;
+ int datalen;
+ unsigned char *buf;
+} *sti_crb;
+
+/**
+ * sti_read_packet - STI read packet (read an entire STI packet)
+ * @buf: Buffer to store the packet.
+ * @maxsize: Maximum size requested.
+ *
+ * This reads in a single completed STI packet from the RX FIFOs and
+ * places it in @buf for further processing.
+ *
+ * The return value is < 0 on error, and >= 0 for the number of bytes
+ * actually read. As per the STI specification, we require a 0xC1 to
+ * indicate the end of the packet, and we don't return the packet until
+ * we've read the entire thing in.
+ *
+ * Due to the size of the FIFOs, it's unrealistic to constantly drain
+ * this for 1 or 2 bytes at a time, so we assemble it here and return
+ * the whole thing.
+ */
+int sti_read_packet(unsigned char *buf, int maxsize)
+{
+ unsigned int pos;
+
+ if (unlikely(!buf))
+ return -EINVAL;
+ if (!sti_crb->datalen)
+ return 0;
+
+ pos = sti_buf_pos(sti_crb->datalen - 1);
+ /* End of packet */
+ if (sti_crb->buf[pos] == 0xC1) {
+ int i;
+
+ for (i = 0; i < sti_crb->datalen && i < maxsize; i++) {
+ pos = sti_buf_pos(i);
+ buf[i] = sti_crb->buf[pos];
+ }
+
+ sti_crb->bufpos = sti_buf_pos(i);
+ sti_crb->datalen -= i;
+
+ return i;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(sti_read_packet);
+
+static void sti_fifo_irq(unsigned long arg)
+{
+ /* If there is data read it */
+ while (!(sti_readl(STI_RX_STATUS) & STI_RXFIFO_EMPTY)) {
+ unsigned int pos = sti_buf_pos(sti_crb->datalen);
+
+ sti_crb->buf[pos] = sti_readl(STI_RX_DR);
+ sti_crb->datalen++;
+ }
+
+ sti_ack_irq(STI_RX_INT);
+}
+
+static int __init sti_fifo_init(void)
+{
+ unsigned int size;
+ int ret;
+
+ size = sizeof(struct sti_cycle_buffer) + STI_READ_BUFFER_SIZE;
+ sti_crb = kmalloc(size, GFP_KERNEL);
+ if (!sti_crb)
+ return -ENOMEM;
+
+ sti_crb->bufpos = sti_crb->datalen = 0;
+ sti_crb->buf = (unsigned char *)(sti_crb + sizeof(*sti_crb));
+
+ ret = sti_request_irq(STI_RX_INT, sti_fifo_irq, 0);
+ if (ret != 0)
+ kfree(sti_crb);
+
+ return ret;
+}
+
+static void __exit sti_fifo_exit(void)
+{
+ sti_free_irq(STI_RX_INT);
+ kfree(sti_crb);
+}
+
+module_init(sti_fifo_init);
+module_exit(sti_fifo_exit);
+
+MODULE_AUTHOR("Paul Mundt, Roman Tereshonkov");
+MODULE_LICENSE("GPL");
diff --git a/drivers/misc/sti/sti-netlink.c b/drivers/misc/sti/sti-netlink.c
new file mode 100644
index 0000000..ca3533e
--- /dev/null
+++ b/drivers/misc/sti/sti-netlink.c
@@ -0,0 +1,152 @@
+/*
+ * OMAP STI/XTI communications interface via netlink socket.
+ *
+ * Copyright (C) 2004, 2005, 2006 Nokia Corporation
+ * Written by: Paul Mundt <paul.mundt@nokia.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/netlink.h>
+#include <linux/socket.h>
+#include <linux/skbuff.h>
+#include <linux/mutex.h>
+#include <net/sock.h>
+#include <asm/arch/sti.h>
+
+static struct sock *sti_sock;
+static DEFINE_MUTEX(sti_netlink_mutex);
+
+enum {
+ STI_READ,
+ STI_WRITE,
+};
+
+static int sti_netlink_read(int pid, int seq, void *payload, int size)
+{
+ struct sk_buff *skb;
+ struct nlmsghdr *nlh;
+ int ret, len = NLMSG_SPACE(size);
+ unsigned char *tail;
+
+ skb = alloc_skb(len, GFP_KERNEL);
+ if (!skb)
+ return -ENOMEM;
+
+ tail = skb->tail;
+ nlh = NLMSG_PUT(skb, pid, seq, STI_READ,
+ len - (sizeof(struct nlmsghdr)));
+ nlh->nlmsg_flags = 0;
+ memcpy(NLMSG_DATA(nlh), payload, size);
+ nlh->nlmsg_len = skb->tail - tail;
+
+ ret = netlink_unicast(sti_sock, skb, pid, MSG_DONTWAIT);
+ if (ret > 0)
+ ret = 0;
+
+ return ret;
+
+nlmsg_failure:
+ if (skb)
+ kfree_skb(skb);
+
+ return -EINVAL;
+}
+
+/*
+ * We abuse nlmsg_type and nlmsg_flags for our purposes.
+ *
+ * The ID is encoded into the upper 8 bits of the nlmsg_type, while the
+ * channel number is encoded into the upper 8 bits of the nlmsg_flags.
+ */
+static int sti_netlink_receive_msg(struct sk_buff *skb, struct nlmsghdr *nlh)
+{
+ void *data;
+ u8 chan, id;
+ int size, ret = 0, len = 0;
+
+ data = NLMSG_DATA(nlh);
+ chan = (nlh->nlmsg_flags >> 8) & 0xff;
+ id = (nlh->nlmsg_type >> 8) & 0xff;
+ size = (int)(nlh->nlmsg_len - ((char *)data - (char *)nlh));
+
+ switch (nlh->nlmsg_type & 0xff) {
+ case STI_WRITE:
+ sti_channel_write_trace(size, id, data, chan);
+ break;
+ case STI_READ:
+ data = kmalloc(size, GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+ memset(data, 0, size);
+
+ len = sti_read_packet(data, size);
+ ret = sti_netlink_read(NETLINK_CB(skb).pid, nlh->nlmsg_seq,
+ data, len);
+ kfree(data);
+ break;
+ default:
+ return -ENOTTY;
+ }
+
+ return ret;
+}
+
+static int sti_netlink_receive_skb(struct sk_buff *skb)
+{
+ while (skb->len >= NLMSG_SPACE(0)) {
+ struct nlmsghdr *nlh;
+ u32 rlen;
+ int ret;
+
+ nlh = (struct nlmsghdr *)skb->data;
+ if (nlh->nlmsg_len < sizeof(struct nlmsghdr) ||
+ skb->len < nlh->nlmsg_len)
+ break;
+
+ rlen = NLMSG_ALIGN(nlh->nlmsg_len);
+ if (rlen > skb->len)
+ rlen = skb->len;
+
+ ret = sti_netlink_receive_msg(skb, nlh);
+ if (ret)
+ netlink_ack(skb, nlh, -ret);
+ else if (nlh->nlmsg_flags & NLM_F_ACK)
+ netlink_ack(skb, nlh, 0);
+
+ skb_pull(skb, rlen);
+ }
+
+ return 0;
+}
+
+static void sti_netlink_receive(struct sk_buff *skb)
+{
+ if (!mutex_trylock(&sti_netlink_mutex))
+ return;
+
+ sti_netlink_receive_skb(skb);
+ mutex_unlock(&sti_netlink_mutex);
+}
+
+static int __init sti_netlink_init(void)
+{
+ sti_sock = netlink_kernel_create(&init_net, NETLINK_USERSOCK, 0,
+ sti_netlink_receive, NULL,
+ THIS_MODULE);
+ if (!sti_sock) {
+ printk(KERN_ERR "STI: Failed to create netlink socket\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+module_init(sti_netlink_init);
+
+MODULE_AUTHOR("Paul Mundt");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("STI netlink-driven communications interface");
diff --git a/drivers/misc/sti/sti.c b/drivers/misc/sti/sti.c
new file mode 100644
index 0000000..e828860
--- /dev/null
+++ b/drivers/misc/sti/sti.c
@@ -0,0 +1,432 @@
+/*
+ * Support functions for OMAP STI/XTI (Serial Tracing Interface)
+ *
+ * Copyright (C) 2004, 2005, 2006 Nokia Corporation
+ * Written by: Paul Mundt <paul.mundt@nokia.com>
+ *
+ * STI initialization code and channel handling
+ * from Juha Yrjölä <juha.yrjola@nokia.com>.
+ *
+ * XTI initialization
+ * from Roman Tereshonkov <roman.tereshonkov@nokia.com>.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <asm/arch/sti.h>
+#include <asm/byteorder.h>
+
+static struct clk *sti_ck;
+unsigned long sti_base, sti_channel_base;
+static unsigned long sti_kern_mask = STIEn;
+static unsigned long sti_irq_mask = STI_IRQSTATUS_MASK;
+static DEFINE_SPINLOCK(sti_lock);
+
+static struct sti_irqdesc {
+ irqreturn_t (*func)(unsigned long);
+ unsigned long data;
+} ____cacheline_aligned sti_irq_desc[STI_NR_IRQS];
+
+void sti_channel_write_trace(int len, int id, void *data, unsigned int channel)
+{
+ const u8 *tpntr = data;
+
+ sti_channel_writeb(id, channel);
+
+ if (cpu_is_omap16xx())
+ /* Check u32 boundary */
+ if (!((u32)data & (STI_PERCHANNEL_SIZE - 1)) &&
+ (len >= STI_PERCHANNEL_SIZE)) {
+ const u32 *asrc = data;
+
+ do {
+ sti_channel_writel(cpu_to_be32(*asrc++),
+ channel);
+ len -= STI_PERCHANNEL_SIZE;
+ } while (len >= STI_PERCHANNEL_SIZE);
+
+ tpntr = (const u8 *)asrc;
+ }
+
+ while (len--)
+ sti_channel_writeb(*tpntr++, channel);
+
+ sti_channel_flush(channel);
+}
+EXPORT_SYMBOL(sti_channel_write_trace);
+
+void sti_enable_irq(unsigned int id)
+{
+ spin_lock_irq(&sti_lock);
+ sti_writel(1 << id, STI_IRQSETEN);
+ spin_unlock_irq(&sti_lock);
+}
+EXPORT_SYMBOL(sti_enable_irq);
+
+void sti_disable_irq(unsigned int id)
+{
+ spin_lock_irq(&sti_lock);
+
+ if (cpu_is_omap16xx())
+ sti_writel(1 << id, STI_IRQCLREN);
+ else if (cpu_is_omap24xx())
+ sti_writel(sti_readl(STI_IRQSETEN) & ~(1 << id), STI_IRQSETEN);
+ else
+ BUG();
+
+ spin_unlock_irq(&sti_lock);
+}
+EXPORT_SYMBOL(sti_disable_irq);
+
+void sti_ack_irq(unsigned int id)
+{
+ /* Even though the clear state is 0, we have to write 1 to clear */
+ sti_writel(1 << id, STI_IRQSTATUS);
+}
+EXPORT_SYMBOL(sti_ack_irq);
+
+int sti_request_irq(unsigned int irq, void *handler, unsigned long arg)
+{
+ struct sti_irqdesc *desc;
+
+ if (unlikely(!handler || irq > STI_NR_IRQS))
+ return -EINVAL;
+
+ desc = sti_irq_desc + irq;
+ if (unlikely(desc->func)) {
+ printk(KERN_WARNING "STI: Attempting to request in-use IRQ "
+ "%d, consider fixing your code..\n", irq);
+ return -EBUSY;
+ }
+
+ desc->func = handler;
+ desc->data = arg;
+
+ sti_enable_irq(irq);
+ return 0;
+}
+EXPORT_SYMBOL(sti_request_irq);
+
+void sti_free_irq(unsigned int irq)
+{
+ struct sti_irqdesc *desc = sti_irq_desc + irq;
+
+ if (unlikely(irq > STI_NR_IRQS))
+ return;
+
+ sti_disable_irq(irq);
+
+ desc->func = NULL;
+ desc->data = 0;
+}
+EXPORT_SYMBOL(sti_free_irq);
+
+/*
+ * This is a bit heavy, so normally we would defer this to a tasklet.
+ * Unfortunately tasklets are too slow for the RX FIFO interrupt (and
+ * possibly some others), so we just do the irqdesc walking here.
+ */
+static irqreturn_t sti_interrupt(int irq, void *dev_id)
+{
+ int ret = IRQ_NONE;
+ u16 status;
+ int i;
+
+ status = sti_readl(STI_IRQSTATUS) & sti_irq_mask;
+
+ for (i = 0; status; i++) {
+ struct sti_irqdesc *desc = sti_irq_desc + i;
+ u16 id = 1 << i;
+
+ if (!(status & id))
+ continue;
+
+ if (likely(desc && desc->func))
+ ret |= desc->func(desc->data);
+ if (unlikely(ret == IRQ_NONE)) {
+ printk("STI: spurious interrupt (id %d)\n", id);
+ sti_disable_irq(i);
+ sti_ack_irq(i);
+ ret = IRQ_HANDLED;
+ }
+
+ status &= ~id;
+ }
+
+ return IRQ_RETVAL(ret);
+}
+
+static void omap_sti_reset(void)
+{
+ int i;
+
+ /* Reset STI module */
+ sti_writel(0x02, STI_SYSCONFIG);
+
+ /* Wait a while for the STI module to complete its reset */
+ for (i = 0; i < 10000; i++)
+ if (sti_readl(STI_SYSSTATUS) & 1)
+ break;
+}
+
+static int __init sti_init(void)
+{
+ char buf[64];
+ int i;
+
+ if (cpu_is_omap16xx()) {
+ /* Release ARM Rhea buses peripherals enable */
+ sti_writel(sti_readl(ARM_RSTCT2) | 0x0001, ARM_RSTCT2);
+
+ /* Enable TC1_CK (functional clock) */
+ sti_ck = clk_get(NULL, "tc1_ck");
+ } else if (cpu_is_omap24xx())
+ /* Enable emulation tools clock */
+ sti_ck = clk_get(NULL, "emul_ck");
+
+ if (IS_ERR(sti_ck))
+ return PTR_ERR(sti_ck);
+
+ clk_enable(sti_ck);
+
+ /* Reset STI module */
+ omap_sti_reset();
+
+ /* Enable STI */
+ sti_trace_enable(MPUCmdEn);
+
+ /* Change to custom serial protocol */
+ sti_writel(0x01, STI_SERIAL_CFG);
+
+ /* Set STI clock control register to normal mode */
+ sti_writel(0x00, STI_CLK_CTRL);
+
+ i = sti_readl(STI_REVISION);
+ snprintf(buf, sizeof(buf), "OMAP STI support loaded (HW v%u.%u)\n",
+ (i >> 4) & 0x0f, i & 0x0f);
+ printk(KERN_INFO "%s", buf);
+
+ sti_channel_write_trace(strlen(buf), 0xc3, buf, 239);
+
+ return 0;
+}
+
+static void sti_exit(void)
+{
+ u32 tmp;
+
+ /*
+ * This should have already been done by reset, but we switch off
+ * STI entirely just for added sanity..
+ */
+ tmp = sti_readl(STI_ER);
+ tmp &= ~STIEn;
+ sti_writel(tmp, STI_ER);
+
+ clk_disable(sti_ck);
+ clk_put(sti_ck);
+}
+
+static void __sti_trace_enable(int event)
+{
+ u32 tmp;
+
+ tmp = sti_readl(STI_ER);
+ tmp |= sti_kern_mask | event;
+ sti_writel(tmp, STI_ER);
+}
+
+int sti_trace_enable(int event)
+{
+ spin_lock_irq(&sti_lock);
+ sti_kern_mask |= event;
+ __sti_trace_enable(event);
+ spin_unlock_irq(&sti_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(sti_trace_enable);
+
+static void __sti_trace_disable(int event)
+{
+ u32 tmp;
+
+ tmp = sti_readl(STI_DR);
+
+ if (cpu_is_omap16xx()) {
+ tmp |= event;
+ tmp &= ~sti_kern_mask;
+ } else if (cpu_is_omap24xx()) {
+ tmp &= ~event;
+ tmp |= sti_kern_mask;
+ } else
+ BUG();
+
+ sti_writel(tmp, STI_DR);
+}
+
+void sti_trace_disable(int event)
+{
+ spin_lock_irq(&sti_lock);
+ sti_kern_mask &= ~event;
+ __sti_trace_disable(event);
+ spin_unlock_irq(&sti_lock);
+}
+EXPORT_SYMBOL(sti_trace_disable);
+
+static ssize_t
+sti_trace_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "0x%08lx\n", sti_readl(STI_ER));
+}
+
+static ssize_t
+sti_trace_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ int evt = simple_strtoul(buf, NULL, 0);
+ int mask = ~evt;
+
+ spin_lock_irq(&sti_lock);
+ __sti_trace_disable(mask);
+ __sti_trace_enable(evt);
+ spin_unlock_irq(&sti_lock);
+
+ return count;
+}
+static DEVICE_ATTR(trace, S_IRUGO | S_IWUSR, sti_trace_show, sti_trace_store);
+
+static ssize_t
+sti_imask_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "0x%04lx\n", sti_irq_mask);
+}
+
+static ssize_t
+sti_imask_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ spin_lock_irq(&sti_lock);
+ sti_irq_mask = simple_strtoul(buf, NULL, 0);
+ spin_unlock_irq(&sti_lock);
+
+ return count;
+}
+static DEVICE_ATTR(imask, S_IRUGO | S_IWUSR, sti_imask_show, sti_imask_store);
+
+static int __devinit sti_probe(struct platform_device *pdev)
+{
+ struct resource *res, *cres;
+ int ret;
+
+ if (pdev->num_resources != 3) {
+ dev_err(&pdev->dev, "invalid number of resources: %d\n",
+ pdev->num_resources);
+ return -ENODEV;
+ }
+
+ /* STI base */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!res)) {
+ dev_err(&pdev->dev, "invalid mem resource\n");
+ return -ENODEV;
+ }
+
+ /* Channel base */
+ cres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (unlikely(!cres)) {
+ dev_err(&pdev->dev, "invalid channel mem resource\n");
+ return -ENODEV;
+ }
+
+ ret = device_create_file(&pdev->dev, &dev_attr_trace);
+ if (unlikely(ret != 0))
+ return ret;
+
+ ret = device_create_file(&pdev->dev, &dev_attr_imask);
+ if (unlikely(ret != 0))
+ goto err;
+
+ sti_base = res->start;
+
+ /*
+ * OMAP 16xx keeps channels in a relatively sane location,
+ * whereas 24xx maps them much further out, and so they must be
+ * remapped.
+ */
+ if (cpu_is_omap16xx())
+ sti_channel_base = cres->start;
+ else if (cpu_is_omap24xx()) {
+ unsigned int size = cres->end - cres->start;
+
+ sti_channel_base = (unsigned long)ioremap(cres->start, size);
+ if (unlikely(!sti_channel_base)) {
+ ret = -ENODEV;
+ goto err_badremap;
+ }
+ }
+
+ ret = request_irq(platform_get_irq(pdev, 0), sti_interrupt,
+ IRQF_DISABLED, "sti", NULL);
+ if (unlikely(ret != 0))
+ goto err_badirq;
+
+ return sti_init();
+
+err_badirq:
+ iounmap((void *)sti_channel_base);
+err_badremap:
+ device_remove_file(&pdev->dev, &dev_attr_imask);
+err:
+ device_remove_file(&pdev->dev, &dev_attr_trace);
+
+ return ret;
+}
+
+static int __devexit sti_remove(struct platform_device *pdev)
+{
+ unsigned int irq = platform_get_irq(pdev, 0);
+
+ if (cpu_is_omap24xx())
+ iounmap((void *)sti_channel_base);
+
+ device_remove_file(&pdev->dev, &dev_attr_trace);
+ device_remove_file(&pdev->dev, &dev_attr_imask);
+ free_irq(irq, NULL);
+ sti_exit();
+
+ return 0;
+}
+
+static struct platform_driver sti_driver = {
+ .probe = sti_probe,
+ .remove = __devexit_p(sti_remove),
+ .driver = {
+ .name = "sti",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init sti_module_init(void)
+{
+ return platform_driver_register(&sti_driver);
+}
+
+static void __exit sti_module_exit(void)
+{
+ platform_driver_unregister(&sti_driver);
+}
+subsys_initcall(sti_module_init);
+module_exit(sti_module_exit);
+
+MODULE_AUTHOR("Paul Mundt, Juha Yrjölä, Roman Tereshonkov");
+MODULE_LICENSE("GPL");
--
1.5.3.6
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 0/10] Rearranging things before sending patches to mainline
2008-03-12 10:45 [PATCH 0/10] Rearranging things before sending patches to mainline Tony Lindgren
2008-03-12 10:45 ` [PATCH 1/10] ARM: OMAP2: Fix _REGADDR macro offset calculations and cm.h for assembly Tony Lindgren
@ 2008-03-13 11:28 ` Tony Lindgren
1 sibling, 0 replies; 12+ messages in thread
From: Tony Lindgren @ 2008-03-13 11:28 UTC (permalink / raw)
To: linux-omap
* Tony Lindgren <tony@atomide.com> [080312 12:46]:
> Hi all,
>
> Attached series moves things around a bit to make room for 34xx PM,
> renames some files to have consistent naming, and moves STI support
> from plat-omap to drivers/misc.
>
> This is all to allow us to get arch/arm/*omap* stuff in sync with
> mainline. I'll be putting together a series of patches for Russell
> over next few days for post 2.6.25.
I've pushed these changes.
Tony
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2008-03-13 11:28 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-03-12 10:45 [PATCH 0/10] Rearranging things before sending patches to mainline Tony Lindgren
2008-03-12 10:45 ` [PATCH 1/10] ARM: OMAP2: Fix _REGADDR macro offset calculations and cm.h for assembly Tony Lindgren
2008-03-12 10:45 ` [PATCH 2/10] ARM: OMAP2: Move sram-fn.S to sram24xx.S Tony Lindgren
2008-03-12 10:45 ` [PATCH 3/10] ARM: OMAP2: Rename 24xx specific SRAM functions Tony Lindgren
2008-03-12 10:45 ` [PATCH 4/10] ARM: OMAP3: Add SRAM support for 3430 Tony Lindgren
2008-03-12 10:45 ` [PATCH 5/10] ARM: OMAP2: Rename cm_regbits_24xx.h to cm-regbits-24xx.h Tony Lindgren
2008-03-12 10:45 ` [PATCH 6/10] ARM: OMAP3: Rename cm_regbits_34xx.h to cm-regbits-34xx.h Tony Lindgren
2008-03-12 10:45 ` [PATCH 7/10] ARM: OMAP2: Rename prcm_common.h to prcm-common.h Tony Lindgren
2008-03-12 10:45 ` [PATCH 8/10] ARM: OMAP2: Rename prm_regbits_24xx.h to prm-regbits-24xx.h Tony Lindgren
2008-03-12 10:45 ` [PATCH 9/10] ARM: OMAP3: Rename prm_regbits_34xx.h to prm-regbits-34xx.h Tony Lindgren
2008-03-12 10:45 ` [PATCH 10/10] ARM: OMAP: Move STI support to drivers/misc Tony Lindgren
2008-03-13 11:28 ` [PATCH 0/10] Rearranging things before sending patches to mainline Tony Lindgren
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