* Woodruff, Richard <r-woodruff2@ti.com> [080320 00:14]:
> Hi,
> 
> > > > Cool. Here's a version that gets rid of the lookup table by
> encoding
> > > the
> > > > posted write pending bit into the reg offset. This should be OK,
> as
> > > the
> > > > functions are used within dmtimer.c only.
> 
> I updated your changed patch with the couple things I mentioned below.
> 
> I don't have a board handy now to check but changes are minor.
> 
> One note is some more optimization could happen later on with
> reordering.  The current usage in gptimer has dmtimer_set_load()
> followed by a dm_timer_start().  This causes a read/write/read/write of
> the CTRL register.  Those writes could be collapsed into each other.
> With a load_start().  Others maybe elsewhere.

OK. We might also want to optimize the timer reload function. I'll post
a separate patch on that to experiment with.

> Measurements seem to show timer CPU % usage dropping by /3 using the
> original patch. Perhaps a little better with this one. However, the
> timer still shows up in the profile list.
> 
> > > Ok, that looks nice and will generate a bit better code.  I thought
> > > briefly on that it but wanted the change to be small and was a
> little
> > > worried someone might use the offset somewhere else.  But, they way
> you
> > > did it makes the 2nd aspect go away.
> > >
> > > * You have defined WPSHIFT to 8.  However, that bit is currently
> taken
> > > by WP_TOCR.  I chose 15 hoping if the register expanded it would be
> the
> > > last one in a u_int16 and still can be encoded in an op code as a
> shift
> > > value.  A 16 would be a good codegen value, but always assume
> u_int32
> > > register.  As the registers are u_int32 in current implementations,
> > > probably 16 is a better value.
> > 
> > OK, good catch.
> 
> Now WPSHIFT is 16.
> 
> I was only half getting the intent before.  Now the offset looks like:
> 	31:16[posting bit]15:0[offset].

OK

> I wonder if read/write reg check is reordered if the compiler is smart
> enough to not do the register read if first expression evaluates to 0.
> 	If( reg >> WPSHFIT) & (readl(xyz) & 0xff)

Yeah that might work.

> > > > The init of other timers into posted mode is not done yet, so I
> > > changed
> > > > the timer->posted handling too.
> > >
> > > Not inited in software, BUT the power on reset of the timer module
> is to
> > > posted mode in reset.  Its better to have someone shut it off in
> both
> > > places as its on by default.
> > 
> > OK
> 
> Now reset function does match hardware init default with posted on.

Cool

> > > I'll tweak the points mentioned and fix a typo in the description
> and
> > > send a version.
> > 
> > OK
> 
> I fixed the typo in the description.

Attached is a rev-4 with the cpu_relax() added to while loops as
suggested by Ladislav, and CTRL register defines moved to the right
location.

Regards,

Tony