[PATCH 0/2] Add D2D clockdomain on OMAP3 ES2+

[PATCH 0/2] Add D2D clockdomain on OMAP3 ES2+

[Paul Walmsley]

Hello,

This patch series adds D2D (die-to-die) clockdomain handling into
OMAP3 ES2+ builds.  It seems the D2D clockdomain logic is still
present on the chip and must be manually programmed to allow the
CORE_D2D clockdomain to go inactive.

For this to work, the pm34xx.c code also had to be modified to use the
pwrdm_for_each_clkdm() iterator, lest the existing for-loop fall off
the end of pwrdm->pwrdm_clkdms[].  This also should fix an oops with
CONFIG_PM on any 3430ES1 boards out there.

Tested on 3430SDP ES2.0.


- Paul


diffstat:
 arch/arm/mach-omap2/clockdomains.h |    9 ++++++++-
 arch/arm/mach-omap2/pm34xx.c       |   23 ++++++++++++++++++-----
 2 files changed, 26 insertions(+), 6 deletions(-)

size:
   text    data     bss     dec     hex filename
3280225  155416   98792 3534433  35ee61 vmlinux.3430sdp.orig
3280305  155416   98792 3534513  35eeb1 vmlinux.3430sdp.patched

[PATCH 1/2] OMAP3 PM: convert open-coded iterator to use pwrdm_for_each_clkdm()

[Paul Walmsley]

Convert iterators of the list of clockdomains in a powerdomain to use
pwrdm_for_each_clkdm(), rather than an open-coded for-loop.

This also fixes a bug when the D2D clockdomain is added to the 3430ES2
chip.  The open-coded for-loop tested for a NULL pointer in pwrdm_clkdms[]
to determine when to end the loop.  This causes the iterator to fall
off the end of the array when the powerdomain contains the maximum number
of clockdomains per powerdomain (currently 3).

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/pm34xx.c |   23 ++++++++++++++++++-----
 1 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a1bfb30..7e775cc 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -179,6 +179,22 @@ static int omap3_can_sleep(void)
 	return 1;
 }
 
+/* _clkdm_deny_idle - private callback function used by set_pwrdm_state() */
+static int _clkdm_deny_idle(struct powerdomain *pwrdm,
+			    struct clockdomain *clkdm)
+{
+	omap2_clkdm_deny_idle(clkdm);
+	return 0;
+}
+
+/* _clkdm_allow_idle - private callback function used by set_pwrdm_state() */
+static int _clkdm_allow_idle(struct powerdomain *pwrdm,
+			     struct clockdomain *clkdm)
+{
+	omap2_clkdm_allow_idle(clkdm);
+	return 0;
+}
+
 /* This sets pwrdm state (other than mpu & core. Currently only ON &
  * RET are supported. Function is assuming that clkdm doesn't have
  * hw_sup mode enabled. */
@@ -186,7 +202,6 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 {
 	u32 cur_state;
 	int ret = 0;
-	int i = 0;
 
 	if (pwrdm == NULL || IS_ERR(pwrdm))
 		return -EINVAL;
@@ -196,8 +211,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 	if (cur_state == state)
 		return ret;
 
-	for (i = 0; pwrdm->pwrdm_clkdms[i]; i++)
-		omap2_clkdm_deny_idle(pwrdm->pwrdm_clkdms[i]);
+	pwrdm_for_each_clkdm(pwrdm, _clkdm_deny_idle);
 
 	ret = pwrdm_set_next_pwrst(pwrdm, state);
 	if (ret) {
@@ -206,8 +220,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 		goto err;
 	}
 
-	for (i = 0; pwrdm->pwrdm_clkdms[i]; i++)
-		omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[i]);
+	pwrdm_for_each_clkdm(pwrdm, _clkdm_allow_idle);
 
 err:
 	return ret;

[PATCH 2/2] OMAP3 clockdomains: include D2D clockdomain on 34xx ES2+

[Paul Walmsley]

The OMAP34xx ES2+ TRMs do not document the CLKTRCTRL_D2D bit, even
though the clockdomain logic remains on the chip, and must be
programmed appropriately for the CORE clockdomain to go inactive.

Thanks to Rajendra Najak <rnayak@ti.com> and Richard Woodruff
<r-woodruff2@ti.com> of TI for providing more detail on this issue;
and to Jouni Högander <jouni.hogander@nokia.com> for proposing this
fix.

This patch obsoletes the D2D clockdomain workaround in pm34xx.c in
Jouni's recent patch set.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clockdomains.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index adbc170..b5d3244 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -168,12 +168,19 @@ static struct clockdomain sgx_clkdm = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 };
 
+/*
+ * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
+ * then that information was removed from the 34xx ES2+ TRM.  It is
+ * unclear whether the core is still there, but the clockdomain logic
+ * is there, and must be programmed to an appropriate state if the
+ * CORE clockdomain is to become inactive.
+ */
 static struct clockdomain d2d_clkdm = {
 	.name		= "d2d_clkdm",
 	.pwrdm_name	= "core_pwrdm",
 	.flags		= CLKDM_CAN_HWSUP,
 	.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
-	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
 static struct clockdomain core_l3_34xx_clkdm = {


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Re: [PATCH 0/2] Add D2D clockdomain on OMAP3 ES2+

[Högander Jouni]

"ext Paul Walmsley" <paul@pwsan.com> writes:

> Hello,
>
> This patch series adds D2D (die-to-die) clockdomain handling into
> OMAP3 ES2+ builds.  It seems the D2D clockdomain logic is still
> present on the chip and must be manually programmed to allow the
> CORE_D2D clockdomain to go inactive.
>
> For this to work, the pm34xx.c code also had to be modified to use the
> pwrdm_for_each_clkdm() iterator, lest the existing for-loop fall off
> the end of pwrdm->pwrdm_clkdms[].  This also should fix an oops with
> CONFIG_PM on any 3430ES1 boards out there.

That loop was a good catch, thanks.

Both patches acked.

>
> Tested on 3430SDP ES2.0.
>
>
> - Paul
>
>
> diffstat:
>  arch/arm/mach-omap2/clockdomains.h |    9 ++++++++-
>  arch/arm/mach-omap2/pm34xx.c       |   23 ++++++++++++++++++-----
>  2 files changed, 26 insertions(+), 6 deletions(-)
>
> size:
>    text    data     bss     dec     hex filename
> 3280225  155416   98792 3534433  35ee61 vmlinux.3430sdp.orig
> 3280305  155416   98792 3534513  35eeb1 vmlinux.3430sdp.patched
>

-- 
Jouni Högander

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Re: [PATCH 0/2] Add D2D clockdomain on OMAP3 ES2+

[Tony Lindgren]

* Högander Jouni <jouni.hogander@nokia.com> [080522 23:27]:
> "ext Paul Walmsley" <paul@pwsan.com> writes:
> 
> > Hello,
> >
> > This patch series adds D2D (die-to-die) clockdomain handling into
> > OMAP3 ES2+ builds.  It seems the D2D clockdomain logic is still
> > present on the chip and must be manually programmed to allow the
> > CORE_D2D clockdomain to go inactive.
> >
> > For this to work, the pm34xx.c code also had to be modified to use the
> > pwrdm_for_each_clkdm() iterator, lest the existing for-loop fall off
> > the end of pwrdm->pwrdm_clkdms[].  This also should fix an oops with
> > CONFIG_PM on any 3430ES1 boards out there.
> 
> That loop was a good catch, thanks.
> 
> Both patches acked.

Pushing both today.

Tony

> 
> >
> > Tested on 3430SDP ES2.0.
> >
> >
> > - Paul
> >
> >
> > diffstat:
> >  arch/arm/mach-omap2/clockdomains.h |    9 ++++++++-
> >  arch/arm/mach-omap2/pm34xx.c       |   23 ++++++++++++++++++-----
> >  2 files changed, 26 insertions(+), 6 deletions(-)
> >
> > size:
> >    text    data     bss     dec     hex filename
> > 3280225  155416   98792 3534433  35ee61 vmlinux.3430sdp.orig
> > 3280305  155416   98792 3534513  35eeb1 vmlinux.3430sdp.patched
> >
> 
> -- 
> Jouni Högander
> 
> --
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