* [PATCH 0/14] Big clean-up for multi-omap @ 2008-05-28 4:20 Tony Lindgren 2008-05-28 4:20 ` [PATCH 1/14] ARM: OMAP: Fix debug-macro for multi_omap Tony Lindgren 2008-05-30 21:41 ` [PATCH 0/14] Big clean-up " Tony Lindgren 0 siblings, 2 replies; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Hi all, Following patches clean up blockers for getting multi-omap closer to working for omap2 like we have for omap1: - Remove __REG macros, use omap_read/write() instead - Split omap24xx sram code so no register rewriting is needed - Introduce struct omap_globals to allow early cpu detection to work - Make PRM and CM registers work for multi-omap The __REG patches were posted earlier, but had some issues. They should be fixed now. The first patch is to test primitive omap type detection with DEBUG_LL. Could somebody please try it out on 15xx and make sure you get output from DEBUG_LL? Once the DEBU_LL patch works on all omaps, we can use the similar detection for multi-omap non-optimized get_irq_nr_and_base too :) These patches are against current linux-omap tree, I pushed few fixes there so you pull before trying out these patches. Regards, Tony ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/14] ARM: OMAP: Fix debug-macro for multi_omap 2008-05-28 4:20 [PATCH 0/14] Big clean-up for multi-omap Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 2/14] CF: Change omap_cf.c to use omap_readw/writew instead of __REG for multi-omap Tony Lindgren 2008-05-30 21:41 ` [PATCH 0/14] Big clean-up " Tony Lindgren 1 sibling, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Use ARM revision register to set debug serial port base. Signed-off-by: Tony Lindgren <tony@atomide.com> --- include/asm-arm/arch-omap/debug-macro.S | 40 ++++++++++++++++++++++-------- 1 files changed, 29 insertions(+), 11 deletions(-) diff --git a/include/asm-arm/arch-omap/debug-macro.S b/include/asm-arm/arch-omap/debug-macro.S index 3866e04..a7ca8c8 100644 --- a/include/asm-arm/arch-omap/debug-macro.S +++ b/include/asm-arm/arch-omap/debug-macro.S @@ -12,34 +12,51 @@ */ .macro addruart,rx - mrc p15, 0, \rx, c1, c0 + + /* Detect omap */ + mrc p15, 0, \rx, c0, c0, 0 @ get processor revision + and \rx, \rx, #0x000f0000 @ only check architecture + cmp \rx, #0x00060000 @ is v6? + beq 1000f @ found 925 or 926 (omap1) + cmp \rx, #0x00070000 @ is v7? + beq 2000f @ found arm11 (omap2) + cmp \rx, #0x000f0000 @ is cortex? + beq 3000f @ found cortex (omap3) + +1000: /* Found omap1 */ + mrc p15, 0, \rx, c1, c0 @ get control register tst \rx, #1 @ MMU enabled? -#ifdef CONFIG_ARCH_OMAP1 moveq \rx, #0xff000000 @ physical base address movne \rx, #0xfe000000 @ virtual base - orr \rx, \rx, #0x00fb0000 -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - orr \rx, \rx, #0x00009000 @ UART 3 -#endif + orr \rx, \rx, #0x00fb0000 @ UART 1 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) orr \rx, \rx, #0x00000800 @ UART 2 & 3 #endif +#ifdef CONFIG_OMAP_LL_DEBUG_UART3 + orr \rx, \rx, #0x00009000 @ UART 3 +#endif + b 9999f @ goto out -#elif CONFIG_ARCH_OMAP2 +2000: /* Found omap2 */ + mrc p15, 0, \rx, c1, c0 @ get control register + tst \rx, #1 @ MMU enabled? moveq \rx, #0x48000000 @ physical base address movne \rx, #0xd8000000 @ virtual base - orr \rx, \rx, #0x0006a000 + orr \rx, \rx, #0x0006a000 @ UART 1 #ifdef CONFIG_OMAP_LL_DEBUG_UART2 add \rx, \rx, #0x00002000 @ UART 2 #endif #ifdef CONFIG_OMAP_LL_DEBUG_UART3 add \rx, \rx, #0x00004000 @ UART 3 #endif + b 9999f @ goto out -#elif CONFIG_ARCH_OMAP3 +3000: /* Found omap3 */ + mrc p15, 0, \rx, c1, c0 @ get control register + tst \rx, #1 @ MMU enabled? moveq \rx, #0x48000000 @ physical base address movne \rx, #0xd8000000 @ virtual base - orr \rx, \rx, #0x0006a000 + orr \rx, \rx, #0x0006a000 @ UART 1 #ifdef CONFIG_OMAP_LL_DEBUG_UART2 add \rx, \rx, #0x00002000 @ UART 2 #endif @@ -47,7 +64,8 @@ add \rx, \rx, #0x00fb0000 @ UART 3 add \rx, \rx, #0x00006000 #endif -#endif + +9999: .endm .macro senduart,rd,rx -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/14] CF: Change omap_cf.c to use omap_readw/writew instead of __REG for multi-omap 2008-05-28 4:20 ` [PATCH 1/14] ARM: OMAP: Fix debug-macro for multi_omap Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 3/14] USB: Change omap USB code to use omap_read/write " Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Change omap_cf.c to use omap_readw/writew instead of __REG for multi-omap Signed-off-by: Tony Lindren <tony@atomide.com> --- drivers/pcmcia/omap_cf.c | 19 ++++++++++--------- 1 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c index 46314b4..a7d9e4b 100644 --- a/drivers/pcmcia/omap_cf.c +++ b/drivers/pcmcia/omap_cf.c @@ -38,19 +38,19 @@ #define CF_BASE 0xfffe2800 /* status; read after IRQ */ -#define CF_STATUS_REG __REG16(CF_BASE + 0x00) +#define CF_STATUS (CF_BASE + 0x00) # define CF_STATUS_BAD_READ (1 << 2) # define CF_STATUS_BAD_WRITE (1 << 1) # define CF_STATUS_CARD_DETECT (1 << 0) /* which chipselect (CS0..CS3) is used for CF (active low) */ -#define CF_CFG_REG __REG16(CF_BASE + 0x02) +#define CF_CFG (CF_BASE + 0x02) /* card reset */ -#define CF_CONTROL_REG __REG16(CF_BASE + 0x04) +#define CF_CONTROL (CF_BASE + 0x04) # define CF_CONTROL_RESET (1 << 0) -#define omap_cf_present() (!(CF_STATUS_REG & CF_STATUS_CARD_DETECT)) +#define omap_cf_present() (!(omap_readw(CF_STATUS) & CF_STATUS_CARD_DETECT)) /*--------------------------------------------------------------------------*/ @@ -139,11 +139,11 @@ omap_cf_set_socket(struct pcmcia_socket *sock, struct socket_state_t *s) return -EINVAL; } - control = CF_CONTROL_REG; + control = omap_readw(CF_CONTROL); if (s->flags & SS_RESET) - CF_CONTROL_REG = CF_CONTROL_RESET; + omap_writew(CF_CONTROL_RESET, CF_CONTROL); else - CF_CONTROL_REG = 0; + omap_writew(0, CF_CONTROL); pr_debug("%s: Vcc %d, io_irq %d, flags %04x csc %04x\n", driver_name, s->Vcc, s->io_irq, s->flags, s->csc_mask); @@ -270,7 +270,7 @@ static int __init omap_cf_probe(struct platform_device *pdev) omap_cfg_reg(V10_1610_CF_IREQ); omap_cfg_reg(W10_1610_CF_RESET); - CF_CFG_REG = ~(1 << seg); + omap_writew(~(1 << seg), CF_CFG); pr_info("%s: cs%d on irq %d\n", driver_name, seg, irq); @@ -286,7 +286,8 @@ static int __init omap_cf_probe(struct platform_device *pdev) /* CF uses armxor_ck, which is "always" available */ pr_debug("%s: sts %04x cfg %04x control %04x %s\n", driver_name, - CF_STATUS_REG, CF_CFG_REG, CF_CONTROL_REG, + omap_readw(CF_STATUS), omap_readw(CF_CFG), + omap_readw(CF_CONTROL), omap_cf_present() ? "present" : "(not present)"); cf->socket.owner = THIS_MODULE; -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/14] USB: Change omap USB code to use omap_read/write instead of __REG for multi-omap 2008-05-28 4:20 ` [PATCH 2/14] CF: Change omap_cf.c to use omap_readw/writew instead of __REG for multi-omap Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 4/14] ARM: OMAP: Change __REG access to omap/read write for traffic controller Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Change omap USB code to use omap_read/write instead of __REG for multi-omap Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap1/board-osk.c | 7 +- arch/arm/plat-omap/usb.c | 132 ++++++++---- drivers/cbus/tahvo-usb.c | 91 +++++--- drivers/i2c/chips/isp1301_omap.c | 163 ++++++++----- drivers/i2c/chips/twl4030-usb.c | 39 ++-- drivers/usb/gadget/omap_udc.c | 472 +++++++++++++++++++++----------------- drivers/usb/gadget/omap_udc.h | 61 +++--- drivers/usb/host/ohci-omap.c | 5 +- include/asm-arm/arch-omap/usb.h | 23 +- 9 files changed, 586 insertions(+), 407 deletions(-) diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index a66505f..f2c47b9 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -526,6 +526,8 @@ static void __init osk_mistral_init(void) { } static void __init osk_init(void) { + u32 l; + /* Workaround for wrong CS3 (NOR flash) timing * There are some U-Boot versions out there which configure * wrong CS3 memory timings. This mainly leads to CRC @@ -539,7 +541,10 @@ static void __init osk_init(void) platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices)); omap_board_config = osk_config; omap_board_config_size = ARRAY_SIZE(osk_config); - USB_TRANSCEIVER_CTRL_REG |= (3 << 1); + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l |= (3 << 1); + omap_writel(l, USB_TRANSCEIVER_CTRL); /* irq for tps65010 chip */ /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index a619475..0c4d860 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -156,8 +156,12 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) if (nwires == 0) { if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { + u32 l; + /* pulldown D+/D- */ - USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1); + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~(3 << 1); + omap_writel(l, USB_TRANSCEIVER_CTRL); } return 0; } @@ -171,6 +175,8 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) /* internal transceiver (unavailable on 17xx, 24xx) */ if (!cpu_class_is_omap2() && nwires == 2) { + u32 l; + // omap_cfg_reg(P9_USB_DP); // omap_cfg_reg(R8_USB_DM); @@ -185,9 +191,12 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) * - OTG support on this port not yet written */ - USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4); - if (!is_device) - USB_TRANSCEIVER_CTRL_REG |= (3 << 1); + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~(7 << 4); + if (!is_device) { + l |= (3 << 1); + } + omap_writel(l, USB_TRANSCEIVER_CTRL); return 3 << 16; } @@ -217,8 +226,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) * with VBUS switching and overcurrent detection. */ - if (cpu_class_is_omap1() && nwires != 6) - USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R; + if (cpu_class_is_omap1() && nwires != 6) { + u32 l; + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~CONF_USB2_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } switch (nwires) { case 3: @@ -238,9 +252,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) omap_cfg_reg(K20_24XX_USB0_VM); omap2_usb_devconf_set(0, USB_UNIDIR); } else { + u32 l; + omap_cfg_reg(AA9_USB0_VP); omap_cfg_reg(R9_USB0_VM); - USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R; + l = omap_readl(USB_TRANSCEIVER_CTRL); + l |= CONF_USB2_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); } break; default: @@ -254,8 +272,13 @@ static u32 __init omap_usb1_init(unsigned nwires) { u32 syscon1 = 0; - if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) - USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R; + if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) { + u32 l; + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~CONF_USB1_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } if (cpu_is_omap24xx()) omap2_usb_devconf_clear(1, USB_BIDIR_TLL); @@ -316,8 +339,13 @@ static u32 __init omap_usb1_init(unsigned nwires) syscon1 = 3; omap_cfg_reg(USB1_VP); omap_cfg_reg(USB1_VM); - if (!cpu_is_omap15xx()) - USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R; + if (!cpu_is_omap15xx()) { + u32 l; + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l |= CONF_USB1_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } break; default: bad: @@ -340,8 +368,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) if (alt_pingroup || nwires == 0) return 0; - if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) - USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R; + if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) { + u32 l; + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~CONF_USB2_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } /* external transceiver */ if (cpu_is_omap15xx()) { @@ -410,9 +443,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) omap_cfg_reg(USB2_VP); omap_cfg_reg(USB2_VM); } else { + u32 l; + omap_cfg_reg(AA9_USB2_VP); omap_cfg_reg(R9_USB2_VM); - USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R; + l = omap_readl(USB_TRANSCEIVER_CTRL); + l |= CONF_USB2_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); } break; default: @@ -531,10 +568,6 @@ static struct platform_device otg_device = { /*-------------------------------------------------------------------------*/ -#define ULPD_CLOCK_CTRL_REG __REG16(ULPD_CLOCK_CTRL) -#define ULPD_SOFT_REQ_REG __REG16(ULPD_SOFT_REQ) - - // FIXME correct answer depends on hmc_mode, // as does (on omap1) any nonzero value for config->otg port number #ifdef CONFIG_USB_GADGET_OMAP @@ -550,17 +583,17 @@ static struct platform_device otg_device = { void __init omap_otg_init(struct omap_usb_config *config) { - u32 syscon = OTG_SYSCON_1_REG & 0xffff; + u32 syscon; int status; int alt_pingroup = 0; /* NOTE: no bus or clock setup (yet?) */ - syscon = OTG_SYSCON_1_REG & 0xffff; + syscon = omap_readl(OTG_SYSCON_1) & 0xffff; if (!(syscon & OTG_RESET_DONE)) pr_debug("USB resets not complete?\n"); - // OTG_IRQ_EN_REG = 0; + //omap_writew(0, OTG_IRQ_EN); /* pin muxing and transceiver pinouts */ if (config->pins[0] > 2) /* alt pingroup 2 */ @@ -568,8 +601,8 @@ omap_otg_init(struct omap_usb_config *config) syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); syscon |= omap_usb1_init(config->pins[1]); syscon |= omap_usb2_init(config->pins[2], alt_pingroup); - pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon); - OTG_SYSCON_1_REG = syscon; + pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); + omap_writel(syscon, OTG_SYSCON_1); syscon = config->hmc_mode; syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; @@ -578,9 +611,10 @@ omap_otg_init(struct omap_usb_config *config) syscon |= OTG_EN; #endif if (cpu_class_is_omap1()) - pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG); - pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon); - OTG_SYSCON_2_REG = syscon; + pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", + omap_readl(USB_TRANSCEIVER_CTRL)); + pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); + omap_writel(syscon, OTG_SYSCON_2); printk("USB: hmc %d", config->hmc_mode); if (!alt_pingroup) @@ -597,12 +631,19 @@ omap_otg_init(struct omap_usb_config *config) printk("\n"); if (cpu_class_is_omap1()) { + u16 w; + /* leave USB clocks/controllers off until needed */ - ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ; - ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN; - ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK; + w = omap_readw(ULPD_SOFT_REQ); + w &= ~SOFT_USB_CLK_REQ; + omap_writew(w, ULPD_SOFT_REQ); + + w = omap_readw(ULPD_CLOCK_CTRL); + w &= ~USB_MCLK_EN; + w |= DIS_USB_PVCI_CLK; + omap_writew(w, ULPD_CLOCK_CTRL); } - syscon = OTG_SYSCON_1_REG; + syscon = omap_readl(OTG_SYSCON_1); syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; #ifdef CONFIG_USB_GADGET_OMAP @@ -639,8 +680,8 @@ omap_otg_init(struct omap_usb_config *config) pr_debug("can't register OTG device, %d\n", status); } #endif - pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon); - OTG_SYSCON_1_REG = syscon; + pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); + omap_writel(syscon, OTG_SYSCON_1); status = 0; } @@ -653,18 +694,19 @@ static inline void omap_otg_init(struct omap_usb_config *config) {} #ifdef CONFIG_ARCH_OMAP15XX -#define ULPD_DPLL_CTRL_REG __REG16(ULPD_DPLL_CTRL) +/* ULPD_DPLL_CTRL */ #define DPLL_IOB (1 << 13) #define DPLL_PLL_ENABLE (1 << 4) #define DPLL_LOCK (1 << 0) -#define ULPD_APLL_CTRL_REG __REG16(ULPD_APLL_CTRL) +/* ULPD_APLL_CTRL */ #define APLL_NDPLL_SWITCH (1 << 0) static void __init omap_1510_usb_init(struct omap_usb_config *config) { unsigned int val; + u16 w; omap_usb0_init(config->pins[0], is_usb0_device(config)); omap_usb1_init(config->pins[1]); @@ -685,12 +727,22 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config) printk("\n"); /* use DPLL for 48 MHz function clock */ - pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG, - ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG); - ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH; - ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE; - ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ; - while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK)) + pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL), + omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ)); + + w = omap_readw(ULPD_APLL_CTRL); + w &= ~APLL_NDPLL_SWITCH; + omap_writew(w, ULPD_APLL_CTRL); + + w = omap_readw(ULPD_DPLL_CTRL); + w |= DPLL_IOB | DPLL_PLL_ENABLE; + omap_writew(w, ULPD_DPLL_CTRL); + + w = omap_readw(ULPD_SOFT_REQ); + w |= SOFT_UDC_REQ | SOFT_DPLL_REQ; + omap_writew(w, ULPD_SOFT_REQ); + + while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) cpu_relax(); #ifdef CONFIG_USB_GADGET_OMAP diff --git a/drivers/cbus/tahvo-usb.c b/drivers/cbus/tahvo-usb.c index 230cf8e..65ea14f 100644 --- a/drivers/cbus/tahvo-usb.c +++ b/drivers/cbus/tahvo-usb.c @@ -62,7 +62,7 @@ #define USBR_NSUSPEND (1 << 1) #define USBR_SEMODE (1 << 0) -/* bits in OTG_CTRL_REG */ +/* bits in OTG_CTRL */ /* Bits that are controlled by OMAP OTG and are read-only */ #define OTG_CTRL_OMAP_MASK (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|\ @@ -118,27 +118,27 @@ static irqreturn_t omap_otg_irq(int irq, void *arg) struct tahvo_usb *tu = (struct tahvo_usb *) otg_dev->dev.driver_data; u16 otg_irq; - otg_irq = OTG_IRQ_SRC_REG; + otg_irq = omap_readw(OTG_IRQ_SRC); if (otg_irq & OPRT_CHG) { - OTG_IRQ_SRC_REG = OPRT_CHG; + omap_writew(OPRT_CHG, OTG_IRQ_SRC); } else if (otg_irq & B_SRP_TMROUT) { - OTG_IRQ_SRC_REG = B_SRP_TMROUT; + omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC); } else if (otg_irq & B_HNP_FAIL) { - OTG_IRQ_SRC_REG = B_HNP_FAIL; + omap_writew(B_HNP_FAIL, OTG_IRQ_SRC); } else if (otg_irq & A_SRP_DETECT) { - OTG_IRQ_SRC_REG = A_SRP_DETECT; + omap_writew(A_SRP_DETECT, OTG_IRQ_SRC); } else if (otg_irq & A_REQ_TMROUT) { - OTG_IRQ_SRC_REG = A_REQ_TMROUT; + omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC); } else if (otg_irq & A_VBUS_ERR) { - OTG_IRQ_SRC_REG = A_VBUS_ERR; + omap_writew(A_VBUS_ERR, OTG_IRQ_SRC); } else if (otg_irq & DRIVER_SWITCH) { - if ((!(OTG_CTRL_REG & OTG_DRIVER_SEL)) && + if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) && tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) { /* role is host */ usb_bus_start_enum(tu->otg.host, tu->otg.host->otg_port); } - OTG_IRQ_SRC_REG = DRIVER_SWITCH; + omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC); } else return IRQ_NONE; @@ -148,6 +148,7 @@ static irqreturn_t omap_otg_irq(int irq, void *arg) static int omap_otg_init(void) { + u32 l; #ifdef CONFIG_USB_OTG if (!tahvo_otg_dev) { @@ -155,11 +156,15 @@ static int omap_otg_init(void) return -ENODEV; } #endif - OTG_SYSCON_1_REG &= ~OTG_IDLE_EN; + + l = omap_readl(OTG_SYSCON_1); + l &= ~OTG_IDLE_EN; + omap_writel(l, OTG_SYSCON_1); udelay(100); /* some of these values are board-specific... */ - OTG_SYSCON_2_REG |= OTG_EN + l = omap_readl(OTG_SYSCON_2); + l |= OTG_EN /* for B-device: */ | SRP_GPDATA /* 9msec Bdev D+ pulse */ | SRP_GPDVBUS /* discharge after VBUS pulse */ @@ -168,11 +173,15 @@ static int omap_otg_init(void) | (0 << 20) /* 200ms nominal A_WAIT_VRISE timer */ | SRP_DPW /* detect 167+ns SRP pulses */ | SRP_DATA | SRP_VBUS; /* accept both kinds of SRP pulse */ + omap_writel(l, OTG_SYSCON_2); - OTG_IRQ_EN_REG = DRIVER_SWITCH | OPRT_CHG + omap_writew(DRIVER_SWITCH | OPRT_CHG | B_SRP_TMROUT | B_HNP_FAIL - | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT; - OTG_SYSCON_2_REG |= OTG_EN; + | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT, + OTG_IRQ_EN); + l = omap_readl(OTG_SYSCON_2); + l |= OTG_EN; + omap_writel(l, OTG_SYSCON_2); return 0; } @@ -272,6 +281,8 @@ static void check_vbus_state(struct tahvo_usb *tu) reg = tahvo_read_reg(TAHVO_REG_IDSR); if (reg & 0x01) { + u32 l; + vbus_active = 1; switch (tu->otg.state) { case OTG_STATE_B_IDLE: @@ -280,7 +291,10 @@ static void check_vbus_state(struct tahvo_usb *tu) usb_gadget_vbus_connect(tu->otg.gadget); /* Set B-session valid and not B-sessio ended to indicate * Vbus to be ok. */ - OTG_CTRL_REG = (OTG_CTRL_REG & ~OTG_BSESSEND) | OTG_BSESSVLD; + l = omap_readl(OTG_CTRL); + l &= ~OTG_BSESSEND; + l |= OTG_BSESSVLD; + omap_writel(l, OTG_CTRL); tu->otg.state = OTG_STATE_B_PERIPHERAL; break; @@ -324,10 +338,10 @@ static void tahvo_usb_become_host(struct tahvo_usb *tu) * also mark the A-session is always valid */ omap_otg_init(); - l = OTG_CTRL_REG; - l &= ~(OTG_CTRL_XCVR_MASK|OTG_CTRL_SYS_MASK); + l = omap_readl(OTG_CTRL); + l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK); l |= OTG_ASESSVLD; - OTG_CTRL_REG = l; + omap_writel(l, OTG_CTRL); /* Power up the transceiver in USB host mode */ tahvo_write_reg(TAHVO_REG_USBR, USBR_REGOUT | USBR_NSUSPEND | @@ -345,12 +359,16 @@ static void tahvo_usb_stop_host(struct tahvo_usb *tu) static void tahvo_usb_become_peripheral(struct tahvo_usb *tu) { + u32 l; + /* Clear system and transceiver controlled bits * and enable ID to mark peripheral mode and * BSESSEND to mark no Vbus */ omap_otg_init(); - OTG_CTRL_REG = (OTG_CTRL_REG & ~(OTG_CTRL_XCVR_MASK|OTG_CTRL_SYS_MASK|OTG_BSESSVLD)) - | OTG_ID | OTG_BSESSEND; + l = omap_readl(OTG_CTRL); + l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD); + l |= OTG_ID | OTG_BSESSEND; + omap_writel(l, OTG_CTRL); /* Power up transceiver and set it in USB perhiperal mode */ tahvo_write_reg(TAHVO_REG_USBR, USBR_SLAVE_CONTROL | USBR_REGOUT | USBR_NSUSPEND | USBR_SLAVE_SW); @@ -361,7 +379,13 @@ static void tahvo_usb_become_peripheral(struct tahvo_usb *tu) static void tahvo_usb_stop_peripheral(struct tahvo_usb *tu) { - OTG_CTRL_REG = (OTG_CTRL_REG & ~OTG_BSESSVLD) | OTG_BSESSEND; + u32 l; + + l = omap_readl(OTG_CTRL); + l &= ~OTG_BSESSVLD; + l |= OTG_BSESSEND; + omap_writel(l, OTG_CTRL); + if (tu->otg.gadget) usb_gadget_vbus_disconnect(tu->otg.gadget); tu->otg.state = OTG_STATE_B_IDLE; @@ -384,15 +408,19 @@ static void tahvo_usb_power_off(struct tahvo_usb *tu) id = OTG_ID; else id = 0; - l = OTG_CTRL_REG; + l = omap_readl(OTG_CTRL); l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD); l |= id | OTG_BSESSEND; - OTG_CTRL_REG = l; - OTG_IRQ_EN_REG = 0; + omap_writel(l, OTG_CTRL); + omap_writew(0, OTG_IRQ_EN); - OTG_SYSCON_2_REG &= ~OTG_EN; + l = omap_readl(OTG_SYSCON_2); + l &= ~OTG_EN; + omap_writel(l, OTG_SYSCON_2); - OTG_SYSCON_1_REG |= OTG_IDLE_EN; + l = omap_readl(OTG_SYSCON_1); + l |= OTG_IDLE_EN; + omap_writel(l, OTG_SYSCON_1); /* Power off transceiver */ tahvo_write_reg(TAHVO_REG_USBR, 0); @@ -439,13 +467,13 @@ static int tahvo_usb_start_srp(struct otg_transceiver *dev) if (!dev || tu->otg.state != OTG_STATE_B_IDLE) return -ENODEV; - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); if (!(otg_ctrl & OTG_BSESSEND)) return -EINVAL; otg_ctrl |= OTG_B_BUSREQ; otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_SYS_MASK; - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); tu->otg.state = OTG_STATE_B_SRP_INIT; return 0; @@ -465,6 +493,7 @@ static int tahvo_usb_start_hnp(struct otg_transceiver *otg) static int tahvo_usb_set_host(struct otg_transceiver *otg, struct usb_bus *host) { struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg); + u32 l; dev_dbg(&tu->pt_dev->dev, "set_host %p\n", host); @@ -483,7 +512,9 @@ static int tahvo_usb_set_host(struct otg_transceiver *otg, struct usb_bus *host) return 0; } - OTG_SYSCON_1_REG &= ~(OTG_IDLE_EN | HST_IDLE_EN | DEV_IDLE_EN); + l = omap_readl(OTG_SYSCON_1); + l &= ~(OTG_IDLE_EN | HST_IDLE_EN | DEV_IDLE_EN); + omap_writel(l, OTG_SYSCON_1); if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) { tu->otg.host = NULL; diff --git a/drivers/i2c/chips/isp1301_omap.c b/drivers/i2c/chips/isp1301_omap.c index 135ffb8..7a5dcfb 100644 --- a/drivers/i2c/chips/isp1301_omap.c +++ b/drivers/i2c/chips/isp1301_omap.c @@ -70,7 +70,7 @@ struct isp1301 { }; -/* bits in OTG_CTRL_REG */ +/* bits in OTG_CTRL */ #define OTG_XCEIV_OUTPUTS \ (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID) @@ -187,8 +187,8 @@ isp1301_clear_bits(struct isp1301 *isp, u8 reg, u8 bits) /* operational registers */ #define ISP1301_MODE_CONTROL_1 0x04 /* u8 read, set, +1 clear */ -# define MC1_SPEED_REG (1 << 0) -# define MC1_SUSPEND_REG (1 << 1) +# define MC1_SPEED (1 << 0) +# define MC1_SUSPEND (1 << 1) # define MC1_DAT_SE0 (1 << 2) # define MC1_TRANSPARENT (1 << 3) # define MC1_BDIS_ACON_EN (1 << 4) @@ -275,7 +275,7 @@ static void power_down(struct isp1301 *isp) isp->otg.state = OTG_STATE_UNDEFINED; // isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); - isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG); + isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND); isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_ID_PULLDOWN); isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0); @@ -284,7 +284,7 @@ static void power_down(struct isp1301 *isp) static void power_up(struct isp1301 *isp) { // isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); - isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG); + isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND); /* do this only when cpu is driving transceiver, * so host won't see a low speed device... @@ -361,6 +361,8 @@ isp1301_defer_work(struct isp1301 *isp, int work) /* called from irq handlers */ static void a_idle(struct isp1301 *isp, const char *tag) { + u32 l; + if (isp->otg.state == OTG_STATE_A_IDLE) return; @@ -374,13 +376,17 @@ static void a_idle(struct isp1301 *isp, const char *tag) gadget_suspend(isp); } isp->otg.state = OTG_STATE_A_IDLE; - isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS; + l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; + omap_writel(l, OTG_CTRL); + isp->last_otg_ctrl = l; pr_debug(" --> %s/%s\n", state_name(isp), tag); } /* called from irq handlers */ static void b_idle(struct isp1301 *isp, const char *tag) { + u32 l; + if (isp->otg.state == OTG_STATE_B_IDLE) return; @@ -394,7 +400,9 @@ static void b_idle(struct isp1301 *isp, const char *tag) gadget_suspend(isp); } isp->otg.state = OTG_STATE_B_IDLE; - isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS; + l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; + omap_writel(l, OTG_CTRL); + isp->last_otg_ctrl = l; pr_debug(" --> %s/%s\n", state_name(isp), tag); } @@ -407,7 +415,7 @@ dump_regs(struct isp1301 *isp, const char *label) u8 src = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE); pr_debug("otg: %06x, %s %s, otg/%02x stat/%02x.%02x\n", - OTG_CTRL_REG, label, state_name(isp), + omap_readl(OTG_CTRL), label, state_name(isp), ctrl, status, src); /* mode control and irq enables don't change much */ #endif @@ -430,7 +438,7 @@ dump_regs(struct isp1301 *isp, const char *label) static void check_state(struct isp1301 *isp, const char *tag) { enum usb_otg_state state = OTG_STATE_UNDEFINED; - u8 fsm = OTG_TEST_REG & 0x0ff; + u8 fsm = omap_readw(OTG_TEST) & 0x0ff; unsigned extra = 0; switch (fsm) { @@ -495,7 +503,8 @@ static void check_state(struct isp1301 *isp, const char *tag) if (isp->otg.state == state && !extra) return; pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag, - state_string(state), fsm, state_name(isp), OTG_CTRL_REG); + state_string(state), fsm, state_name(isp), + omap_readl(OTG_CTRL)); } #else @@ -510,10 +519,11 @@ static void update_otg1(struct isp1301 *isp, u8 int_src) u32 otg_ctrl; u8 int_id; - otg_ctrl = OTG_CTRL_REG - & OTG_CTRL_MASK - & ~OTG_XCEIV_INPUTS - & ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD); + otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; + otg_ctrl &= ~OTG_XCEIV_INPUTS; + otg_ctrl &= ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD); + + if (int_src & INTR_SESS_VLD) otg_ctrl |= OTG_ASESSVLD; else if (isp->otg.state == OTG_STATE_A_WAIT_VFALL) { @@ -539,7 +549,7 @@ static void update_otg1(struct isp1301 *isp, u8 int_src) return; } } - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); } /* outputs from ISP1301_OTG_STATUS */ @@ -547,15 +557,14 @@ static void update_otg2(struct isp1301 *isp, u8 otg_status) { u32 otg_ctrl; - otg_ctrl = OTG_CTRL_REG - & OTG_CTRL_MASK - & ~OTG_XCEIV_INPUTS - & ~(OTG_BSESSVLD|OTG_BSESSEND); + otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; + otg_ctrl &= ~OTG_XCEIV_INPUTS; + otg_ctrl &= ~(OTG_BSESSVLD | OTG_BSESSEND); if (otg_status & OTG_B_SESS_VLD) otg_ctrl |= OTG_BSESSVLD; else if (otg_status & OTG_B_SESS_END) otg_ctrl |= OTG_BSESSEND; - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); } /* inputs going to ISP1301 */ @@ -564,7 +573,7 @@ static void otg_update_isp(struct isp1301 *isp) u32 otg_ctrl, otg_change; u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP; - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); otg_change = otg_ctrl ^ isp->last_otg_ctrl; isp->last_otg_ctrl = otg_ctrl; otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS; @@ -644,6 +653,8 @@ pulldown: /* HNP switch to host or peripheral; and SRP */ if (otg_change & OTG_PULLUP) { + u32 l; + switch (isp->otg.state) { case OTG_STATE_B_IDLE: if (clr & OTG1_DP_PULLUP) @@ -660,7 +671,9 @@ pulldown: default: break; } - OTG_CTRL_REG |= OTG_PULLUP; + l = omap_readl(OTG_CTRL); + l |= OTG_PULLUP; + omap_writel(l, OTG_CTRL); } check_state(isp, __func__); @@ -669,20 +682,20 @@ pulldown: static irqreturn_t omap_otg_irq(int irq, void *_isp) { - u16 otg_irq = OTG_IRQ_SRC_REG; + u16 otg_irq = omap_readw(OTG_IRQ_SRC); u32 otg_ctrl; int ret = IRQ_NONE; struct isp1301 *isp = _isp; /* update ISP1301 transciever from OTG controller */ if (otg_irq & OPRT_CHG) { - OTG_IRQ_SRC_REG = OPRT_CHG; + omap_writew(OPRT_CHG, OTG_IRQ_SRC); isp1301_defer_work(isp, WORK_UPDATE_ISP); ret = IRQ_HANDLED; /* SRP to become b_peripheral failed */ } else if (otg_irq & B_SRP_TMROUT) { - pr_debug("otg: B_SRP_TIMEOUT, %06x\n", OTG_CTRL_REG); + pr_debug("otg: B_SRP_TIMEOUT, %06x\n", omap_readl(OTG_CTRL)); notresponding(isp); /* gadget drivers that care should monitor all kinds of @@ -692,31 +705,31 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) if (isp->otg.state == OTG_STATE_B_SRP_INIT) b_idle(isp, "srp_timeout"); - OTG_IRQ_SRC_REG = B_SRP_TMROUT; + omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC); ret = IRQ_HANDLED; /* HNP to become b_host failed */ } else if (otg_irq & B_HNP_FAIL) { pr_debug("otg: %s B_HNP_FAIL, %06x\n", - state_name(isp), OTG_CTRL_REG); + state_name(isp), omap_readl(OTG_CTRL)); notresponding(isp); - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); otg_ctrl |= OTG_BUSDROP; otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); /* subset of b_peripheral()... */ isp->otg.state = OTG_STATE_B_PERIPHERAL; pr_debug(" --> b_peripheral\n"); - OTG_IRQ_SRC_REG = B_HNP_FAIL; + omap_writew(B_HNP_FAIL, OTG_IRQ_SRC); ret = IRQ_HANDLED; /* detect SRP from B-device ... */ } else if (otg_irq & A_SRP_DETECT) { pr_debug("otg: %s SRP_DETECT, %06x\n", - state_name(isp), OTG_CTRL_REG); + state_name(isp), omap_readl(OTG_CTRL)); isp1301_defer_work(isp, WORK_UPDATE_OTG); switch (isp->otg.state) { @@ -724,49 +737,49 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) if (!isp->otg.host) break; isp1301_defer_work(isp, WORK_HOST_RESUME); - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); otg_ctrl |= OTG_A_BUSREQ; otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ) & ~OTG_XCEIV_INPUTS & OTG_CTRL_MASK; - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); break; default: break; } - OTG_IRQ_SRC_REG = A_SRP_DETECT; + omap_writew(A_SRP_DETECT, OTG_IRQ_SRC); ret = IRQ_HANDLED; /* timer expired: T(a_wait_bcon) and maybe T(a_wait_vrise) * we don't track them separately */ } else if (otg_irq & A_REQ_TMROUT) { - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); pr_info("otg: BCON_TMOUT from %s, %06x\n", state_name(isp), otg_ctrl); notresponding(isp); otg_ctrl |= OTG_BUSDROP; otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); isp->otg.state = OTG_STATE_A_WAIT_VFALL; - OTG_IRQ_SRC_REG = A_REQ_TMROUT; + omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC); ret = IRQ_HANDLED; /* A-supplied voltage fell too low; overcurrent */ } else if (otg_irq & A_VBUS_ERR) { - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); printk(KERN_ERR "otg: %s, VBUS_ERR %04x ctrl %06x\n", state_name(isp), otg_irq, otg_ctrl); otg_ctrl |= OTG_BUSDROP; otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); isp->otg.state = OTG_STATE_A_VBUS_ERR; - OTG_IRQ_SRC_REG = A_VBUS_ERR; + omap_writew(A_VBUS_ERR, OTG_IRQ_SRC); ret = IRQ_HANDLED; /* switch driver; the transciever code activates it, @@ -775,7 +788,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) } else if (otg_irq & DRIVER_SWITCH) { int kick = 0; - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); printk(KERN_NOTICE "otg: %s, SWITCH to %s, ctrl %06x\n", state_name(isp), (otg_ctrl & OTG_DRIVER_SEL) @@ -798,7 +811,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) } else { if (!(otg_ctrl & OTG_ID)) { otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; - OTG_CTRL_REG = otg_ctrl | OTG_A_BUSREQ; + omap_writel(otg_ctrl | OTG_A_BUSREQ, OTG_CTRL); } if (isp->otg.host) { @@ -823,7 +836,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) } } - OTG_IRQ_SRC_REG = DRIVER_SWITCH; + omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC); ret = IRQ_HANDLED; if (kick) @@ -839,12 +852,15 @@ static struct platform_device *otg_dev; static int otg_init(struct isp1301 *isp) { + u32 l; + if (!otg_dev) return -ENODEV; dump_regs(isp, __func__); /* some of these values are board-specific... */ - OTG_SYSCON_2_REG |= OTG_EN + l = omap_readl(OTG_SYSCON_2); + l |= OTG_EN /* for B-device: */ | SRP_GPDATA /* 9msec Bdev D+ pulse */ | SRP_GPDVBUS /* discharge after VBUS pulse */ @@ -854,18 +870,22 @@ static int otg_init(struct isp1301 *isp) | SRP_DPW /* detect 167+ns SRP pulses */ | SRP_DATA | SRP_VBUS /* accept both kinds of SRP pulse */ ; + omap_writel(l, OTG_SYSCON_2); update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE)); update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS)); check_state(isp, __func__); pr_debug("otg: %s, %s %06x\n", - state_name(isp), __func__, OTG_CTRL_REG); + state_name(isp), __func__, omap_readl(OTG_CTRL)); - OTG_IRQ_EN_REG = DRIVER_SWITCH | OPRT_CHG + omap_writew(DRIVER_SWITCH | OPRT_CHG | B_SRP_TMROUT | B_HNP_FAIL - | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT; - OTG_SYSCON_2_REG |= OTG_EN; + | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT, OTG_IRQ_EN); + + l = omap_readl(OTG_SYSCON_2); + l |= OTG_EN; + omap_writel(l, OTG_SYSCON_2); return 0; } @@ -932,7 +952,11 @@ static void otg_unbind(struct isp1301 *isp) static void b_peripheral(struct isp1301 *isp) { - OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS; + u32 l; + + l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; + omap_writel(l, OTG_CTRL); + usb_gadget_vbus_connect(isp->otg.gadget); #ifdef CONFIG_USB_OTG @@ -1004,6 +1028,8 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat) isp_bstat = 0; } } else { + u32 l; + /* if user unplugged mini-A end of cable, * don't bypass A_WAIT_VFALL. */ @@ -1024,8 +1050,9 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat) isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_BDIS_ACON_EN); isp->otg.state = OTG_STATE_B_IDLE; - OTG_CTRL_REG &= OTG_CTRL_REG & OTG_CTRL_MASK - & ~OTG_CTRL_BITS; + l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; + l &= ~OTG_CTRL_BITS; + omap_writel(l, OTG_CTRL); break; case OTG_STATE_B_IDLE: break; @@ -1051,7 +1078,8 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat) /* FALLTHROUGH */ case OTG_STATE_B_SRP_INIT: b_idle(isp, __func__); - OTG_CTRL_REG &= OTG_CTRL_REG & OTG_XCEIV_OUTPUTS; + l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; + omap_writel(l, OTG_CTRL); /* FALLTHROUGH */ case OTG_STATE_B_IDLE: if (isp->otg.gadget && (isp_bstat & OTG_B_SESS_VLD)) { @@ -1135,11 +1163,11 @@ isp1301_work(struct work_struct *work) case OTG_STATE_A_WAIT_VRISE: isp->otg.state = OTG_STATE_A_HOST; pr_debug(" --> a_host\n"); - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); otg_ctrl |= OTG_A_BUSREQ; otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ) & OTG_CTRL_MASK; - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); break; case OTG_STATE_B_WAIT_ACON: isp->otg.state = OTG_STATE_B_HOST; @@ -1278,7 +1306,7 @@ isp1301_set_host(struct otg_transceiver *otg, struct usb_bus *host) return -ENODEV; if (!host) { - OTG_IRQ_EN_REG = 0; + omap_writew(0, OTG_IRQ_EN); power_down(isp); isp->otg.host = 0; return 0; @@ -1326,12 +1354,13 @@ static int isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) { struct isp1301 *isp = container_of(otg, struct isp1301, otg); + u32 l; if (!otg || isp != the_transceiver) return -ENODEV; if (!gadget) { - OTG_IRQ_EN_REG = 0; + omap_writew(0, OTG_IRQ_EN); if (!isp->otg.default_a) enable_vbus_draw(isp, 0); usb_gadget_vbus_disconnect(isp->otg.gadget); @@ -1352,9 +1381,11 @@ isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) isp->otg.gadget = gadget; // FIXME update its refcount - OTG_CTRL_REG = (OTG_CTRL_REG & OTG_CTRL_MASK - & ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS)) - | OTG_ID; + l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; + l &= ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS); + l |= OTG_ID; + omap_writel(l, OTG_CTRL); + power_up(isp); isp->otg.state = OTG_STATE_B_IDLE; @@ -1407,16 +1438,17 @@ isp1301_start_srp(struct otg_transceiver *dev) || isp->otg.state != OTG_STATE_B_IDLE) return -ENODEV; - otg_ctrl = OTG_CTRL_REG; + otg_ctrl = omap_readl(OTG_CTRL); if (!(otg_ctrl & OTG_BSESSEND)) return -EINVAL; otg_ctrl |= OTG_B_BUSREQ; otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK; - OTG_CTRL_REG = otg_ctrl; + omap_writel(otg_ctrl, OTG_CTRL); isp->otg.state = OTG_STATE_B_SRP_INIT; - pr_debug("otg: SRP, %s ... %06x\n", state_name(isp), OTG_CTRL_REG); + pr_debug("otg: SRP, %s ... %06x\n", state_name(isp), + omap_readl(OTG_CTRL)); #ifdef CONFIG_USB_OTG check_state(isp, __func__); #endif @@ -1428,6 +1460,7 @@ isp1301_start_hnp(struct otg_transceiver *dev) { #ifdef CONFIG_USB_OTG struct isp1301 *isp = container_of(dev, struct isp1301, otg); + u32 l; if (!dev || isp != the_transceiver) return -ENODEV; @@ -1458,7 +1491,9 @@ isp1301_start_hnp(struct otg_transceiver *dev) #endif /* caller must suspend then clear A_BUSREQ */ usb_gadget_vbus_connect(isp->otg.gadget); - OTG_CTRL_REG |= OTG_A_SETB_HNPEN; + l = omap_readl(OTG_CTRL); + l |= OTG_A_SETB_HNPEN; + omap_writel(l, OTG_CTRL); break; case OTG_STATE_A_PERIPHERAL: @@ -1468,7 +1503,7 @@ isp1301_start_hnp(struct otg_transceiver *dev) return -EILSEQ; } pr_debug("otg: HNP %s, %06x ...\n", - state_name(isp), OTG_CTRL_REG); + state_name(isp), omap_readl(OTG_CTRL)); check_state(isp, __func__); return 0; #else diff --git a/drivers/i2c/chips/twl4030-usb.c b/drivers/i2c/chips/twl4030-usb.c index 041ae60..7f93b4f 100644 --- a/drivers/i2c/chips/twl4030-usb.c +++ b/drivers/i2c/chips/twl4030-usb.c @@ -67,15 +67,15 @@ #define IFC_CTRL_CARKITMODE (1 << 2) #define IFC_CTRL_FSLSSERIALMODE_3PIN (1 << 1) -#define OTG_CTRL 0x0A -#define OTG_CTRL_SET 0x0B -#define OTG_CTRL_CLR 0x0C -#define OTG_CTRL_DRVVBUS (1 << 5) -#define OTG_CTRL_CHRGVBUS (1 << 4) -#define OTG_CTRL_DISCHRGVBUS (1 << 3) -#define OTG_CTRL_DMPULLDOWN (1 << 2) -#define OTG_CTRL_DPPULLDOWN (1 << 1) -#define OTG_CTRL_IDPULLUP (1 << 0) +#define TWL4030_OTG_CTRL 0x0A +#define TWL4030_OTG_CTRL_SET 0x0B +#define TWL4030_OTG_CTRL_CLR 0x0C +#define TWL4030_OTG_CTRL_DRVVBUS (1 << 5) +#define TWL4030_OTG_CTRL_CHRGVBUS (1 << 4) +#define TWL4030_OTG_CTRL_DISCHRGVBUS (1 << 3) +#define TWL4030_OTG_CTRL_DMPULLDOWN (1 << 2) +#define TWL4030_OTG_CTRL_DPPULLDOWN (1 << 1) +#define TWL4030_OTG_CTRL_IDPULLUP (1 << 0) #define USB_INT_EN_RISE 0x0D #define USB_INT_EN_RISE_SET 0x0E @@ -253,7 +253,7 @@ /* internal define on top of container_of */ #define xceiv_to_twl(x) container_of((x), struct twl4030_usb, otg); -/* bits in OTG_CTRL_REG */ +/* bits in OTG_CTRL */ #define OTG_XCEIV_OUTPUTS \ (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID) @@ -626,12 +626,13 @@ static int twl4030_set_peripheral(struct otg_transceiver *xceiv, struct usb_gadget *gadget) { struct twl4030_usb *twl = xceiv_to_twl(xceiv); + u32 l; if (!xceiv) return -ENODEV; if (!gadget) { - OTG_IRQ_EN_REG = 0; + omap_writew(0, OTG_IRQ_EN); twl4030_phy_suspend(1); twl->otg.gadget = NULL; @@ -641,9 +642,10 @@ static int twl4030_set_peripheral(struct otg_transceiver *xceiv, twl->otg.gadget = gadget; twl4030_phy_resume(); - OTG_CTRL_REG = (OTG_CTRL_REG & OTG_CTRL_MASK - & ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS)) - | OTG_ID; + l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; + l &= ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS); + l |= OTG_ID; + omap_writel(l, OTG_CTRL); twl->otg.state = OTG_STATE_B_IDLE; @@ -663,7 +665,7 @@ static int twl4030_set_host(struct otg_transceiver *xceiv, struct usb_bus *host) return -ENODEV; if (!host) { - OTG_IRQ_EN_REG = 0; + omap_writew(0, OTG_IRQ_EN); twl4030_phy_suspend(1); twl->otg.host = NULL; @@ -673,12 +675,13 @@ static int twl4030_set_host(struct otg_transceiver *xceiv, struct usb_bus *host) twl->otg.host = host; twl4030_phy_resume(); - twl4030_usb_set_bits(twl, OTG_CTRL, - OTG_CTRL_DMPULLDOWN | OTG_CTRL_DPPULLDOWN); + twl4030_usb_set_bits(twl, TWL4030_OTG_CTRL, + TWL4030_OTG_CTRL_DMPULLDOWN + | TWL4030_OTG_CTRL_DPPULLDOWN); twl4030_usb_set_bits(twl, USB_INT_EN_RISE, USB_INT_IDGND); twl4030_usb_set_bits(twl, USB_INT_EN_FALL, USB_INT_IDGND); twl4030_usb_set_bits(twl, FUNC_CTRL, FUNC_CTRL_SUSPENDM); - twl4030_usb_set_bits(twl, OTG_CTRL, OTG_CTRL_DRVVBUS); + twl4030_usb_set_bits(twl, TWL4030_OTG_CTRL, TWL4030_OTG_CTRL_DRVVBUS); return 0; } diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c index 22aabd4..3528f49 100644 --- a/drivers/usb/gadget/omap_udc.c +++ b/drivers/usb/gadget/omap_udc.c @@ -136,13 +136,17 @@ static void use_ep(struct omap_ep *ep, u16 select) if (ep->bEndpointAddress & USB_DIR_IN) num |= UDC_EP_DIR; - UDC_EP_NUM_REG = num | select; + omap_writew(num | select, UDC_EP_NUM); /* when select, MUST deselect later !! */ } static inline void deselect_ep(void) { - UDC_EP_NUM_REG &= ~UDC_EP_SEL; + u16 w; + + w = omap_readw(UDC_EP_NUM); + w &= ~UDC_EP_SEL; + omap_writew(w, UDC_EP_NUM); /* 6 wait states before TX will happen */ } @@ -217,7 +221,7 @@ static int omap_ep_enable(struct usb_ep *_ep, ep->has_dma = 0; ep->lch = -1; use_ep(ep, UDC_EP_SEL); - UDC_CTRL_REG = udc->clr_halt; + omap_writew(udc->clr_halt, UDC_CTRL); ep->ackwait = 0; deselect_ep(); @@ -233,7 +237,7 @@ static int omap_ep_enable(struct usb_ep *_ep, if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC && !ep->has_dma && !(ep->bEndpointAddress & USB_DIR_IN)) { - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); ep->ackwait = 1 + ep->double_buf; } @@ -260,7 +264,7 @@ static int omap_ep_disable(struct usb_ep *_ep) nuke (ep, -ESHUTDOWN); ep->ep.maxpacket = ep->maxpacket; ep->has_dma = 0; - UDC_CTRL_REG = UDC_SET_HALT; + omap_writew(UDC_SET_HALT, UDC_CTRL); list_del_init(&ep->iso); del_timer(&ep->timer); @@ -361,13 +365,13 @@ write_packet(u8 *buf, struct omap_req *req, unsigned max) if (likely((((int)buf) & 1) == 0)) { wp = (u16 *)buf; while (max >= 2) { - UDC_DATA_REG = *wp++; + omap_writew(*wp++, UDC_DATA); max -= 2; } buf = (u8 *)wp; } while (max--) - *(volatile u8 *)&UDC_DATA_REG = *buf++; + omap_writeb(*buf++, UDC_DATA); return len; } @@ -386,13 +390,13 @@ static int write_fifo(struct omap_ep *ep, struct omap_req *req) prefetch(buf); /* PIO-IN isn't double buffered except for iso */ - ep_stat = UDC_STAT_FLG_REG; + ep_stat = omap_readw(UDC_STAT_FLG); if (ep_stat & UDC_FIFO_UNWRITABLE) return 0; count = ep->ep.maxpacket; count = write_packet(buf, req, count); - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); ep->ackwait = 1; /* last packet is often short (sometimes a zlp) */ @@ -426,13 +430,13 @@ read_packet(u8 *buf, struct omap_req *req, unsigned avail) if (likely((((int)buf) & 1) == 0)) { wp = (u16 *)buf; while (avail >= 2) { - *wp++ = UDC_DATA_REG; + *wp++ = omap_readw(UDC_DATA); avail -= 2; } buf = (u8 *)wp; } while (avail--) - *buf++ = *(volatile u8 *)&UDC_DATA_REG; + *buf++ = omap_readb(UDC_DATA); return len; } @@ -447,7 +451,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) prefetchw(buf); for (;;) { - u16 ep_stat = UDC_STAT_FLG_REG; + u16 ep_stat = omap_readw(UDC_STAT_FLG); is_last = 0; if (ep_stat & FIFO_EMPTY) { @@ -461,7 +465,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) if (ep_stat & UDC_FIFO_FULL) avail = ep->ep.maxpacket; else { - avail = UDC_RXFSTAT_REG; + avail = omap_readw(UDC_RXFSTAT); ep->fnf = ep->double_buf; } count = read_packet(buf, req, avail); @@ -474,7 +478,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) req->req.status = -EOVERFLOW; avail -= count; while (avail--) - (void) *(volatile u8 *)&UDC_DATA_REG; + omap_readw(UDC_DATA); } } else if (req->req.length == req->req.actual) is_last = 1; @@ -536,7 +540,7 @@ static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) static void next_in_dma(struct omap_ep *ep, struct omap_req *req) { - u16 txdma_ctrl; + u16 txdma_ctrl, w; unsigned length = req->req.length - req->req.actual; const int sync_mode = cpu_is_omap15xx() ? OMAP_DMA_SYNC_FRAME @@ -568,13 +572,17 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req) omap_start_dma(ep->lch); ep->dma_counter = omap_get_dma_src_pos(ep->lch); - UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel); - UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl; + w = omap_readw(UDC_DMA_IRQ_EN); + w |= UDC_TX_DONE_IE(ep->dma_channel); + omap_writew(w, UDC_DMA_IRQ_EN); + omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel)); req->dma_bytes = length; } static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) { + u16 w; + if (status == 0) { req->req.actual += req->dma_bytes; @@ -591,7 +599,9 @@ static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) /* tx completion */ omap_stop_dma(ep->lch); - UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel); + w = omap_readw(UDC_DMA_IRQ_EN); + w &= ~UDC_TX_DONE_IE(ep->dma_channel); + omap_writew(w, UDC_DMA_IRQ_EN); done(ep, req, status); } @@ -599,6 +609,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) { unsigned packets = req->req.length - req->req.actual; int dma_trigger = 0; + u16 w; if (cpu_is_omap24xx()) dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel); @@ -627,10 +638,12 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) 0, 0); ep->dma_counter = omap_get_dma_dst_pos(ep->lch); - UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1); - UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel); - UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf); - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel)); + w = omap_readw(UDC_DMA_IRQ_EN); + w |= UDC_RX_EOT_IE(ep->dma_channel); + omap_writew(w, UDC_DMA_IRQ_EN); + omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM); + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); omap_start_dma(ep->lch); } @@ -638,7 +651,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) static void finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) { - u16 count; + u16 count, w; if (status == 0) ep->dma_counter = (u16) (req->req.dma + req->req.actual); @@ -657,13 +670,15 @@ finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) return; /* rx completion */ - UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel); + w = omap_readw(UDC_DMA_IRQ_EN); + w &= ~UDC_RX_EOT_IE(ep->dma_channel); + omap_writew(w, UDC_DMA_IRQ_EN); done(ep, req, status); } static void dma_irq(struct omap_udc *udc, u16 irq_src) { - u16 dman_stat = UDC_DMAN_STAT_REG; + u16 dman_stat = omap_readw(UDC_DMAN_STAT); struct omap_ep *ep; struct omap_req *req; @@ -677,7 +692,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) struct omap_req, queue); finish_in_dma(ep, req, 0); } - UDC_IRQ_SRC_REG = UDC_TXN_DONE; + omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC); if (!list_empty (&ep->queue)) { req = container_of(ep->queue.next, @@ -696,7 +711,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) struct omap_req, queue); finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); } - UDC_IRQ_SRC_REG = UDC_RXN_EOT; + omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC); if (!list_empty (&ep->queue)) { req = container_of(ep->queue.next, @@ -710,7 +725,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) ep->irqs++; /* omap15xx does this unasked... */ VDBG("%s, RX_CNT irq?\n", ep->ep.name); - UDC_IRQ_SRC_REG = UDC_RXN_CNT; + omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC); } } @@ -733,9 +748,9 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) is_in = ep->bEndpointAddress & USB_DIR_IN; if (is_in) - reg = UDC_TXDMA_CFG_REG; + reg = omap_readw(UDC_TXDMA_CFG); else - reg = UDC_RXDMA_CFG_REG; + reg = omap_readw(UDC_RXDMA_CFG); reg |= UDC_DMA_REQ; /* "pulse" activated */ ep->dma_channel = 0; @@ -763,7 +778,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) status = omap_request_dma(dma_channel, ep->ep.name, dma_error, ep, &ep->lch); if (status == 0) { - UDC_TXDMA_CFG_REG = reg; + omap_writew(reg, UDC_TXDMA_CFG); /* EMIFF or SDRC */ omap_set_dma_src_burst_mode(ep->lch, OMAP_DMA_DATA_BURST_4); @@ -772,7 +787,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_TIPB, OMAP_DMA_AMODE_CONSTANT, - (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), + (unsigned long) io_v2p(UDC_DATA_DMA), 0, 0); } } else { @@ -784,12 +799,12 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) status = omap_request_dma(dma_channel, ep->ep.name, dma_error, ep, &ep->lch); if (status == 0) { - UDC_RXDMA_CFG_REG = reg; + omap_writew(reg, UDC_RXDMA_CFG); /* TIPB */ omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_TIPB, OMAP_DMA_AMODE_CONSTANT, - (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), + (unsigned long) io_v2p(UDC_DATA_DMA), 0, 0); /* EMIFF or SDRC */ omap_set_dma_dest_burst_mode(ep->lch, @@ -831,7 +846,7 @@ just_restart: (is_in ? write_fifo : read_fifo)(ep, req); deselect_ep(); if (!is_in) { - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); ep->ackwait = 1 + ep->double_buf; } /* IN: 6 wait states before it'll tx */ @@ -865,23 +880,25 @@ static void dma_channel_release(struct omap_ep *ep) /* wait till current packet DMA finishes, and fifo empties */ if (ep->bEndpointAddress & USB_DIR_IN) { - UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; + omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ, + UDC_TXDMA_CFG); if (req) { finish_in_dma(ep, req, -ECONNRESET); /* clear FIFO; hosts probably won't empty it */ use_ep(ep, UDC_EP_SEL); - UDC_CTRL_REG = UDC_CLR_EP; + omap_writew(UDC_CLR_EP, UDC_CTRL); deselect_ep(); } - while (UDC_TXDMA_CFG_REG & mask) + while (omap_readw(UDC_TXDMA_CFG) & mask) udelay(10); } else { - UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; + omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ, + UDC_RXDMA_CFG); /* dma empties the fifo */ - while (UDC_RXDMA_CFG_REG & mask) + while (omap_readw(UDC_RXDMA_CFG) & mask) udelay(10); if (req) finish_out_dma(ep, req, -ECONNRESET, 0); @@ -968,9 +985,13 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) req->req.actual = 0; /* maybe kickstart non-iso i/o queues */ - if (is_iso) - UDC_IRQ_EN_REG |= UDC_SOF_IE; - else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { + if (is_iso) { + u16 w; + + w = omap_readw(UDC_IRQ_EN); + w |= UDC_SOF_IE; + omap_writew(w, UDC_IRQ_EN); + } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { int is_in; if (ep->bEndpointAddress == 0) { @@ -988,23 +1009,23 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) * requests to non-control endpoints */ if (udc->ep0_set_config) { - u16 irq_en = UDC_IRQ_EN_REG; + u16 irq_en = omap_readw(UDC_IRQ_EN); irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; if (!udc->ep0_reset_config) irq_en |= UDC_EPN_RX_IE | UDC_EPN_TX_IE; - UDC_IRQ_EN_REG = irq_en; + omap_writew(irq_en, UDC_IRQ_EN); } /* STATUS for zero length DATA stages is * always an IN ... even for IN transfers, * a weird case which seem to stall OMAP. */ - UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR); - UDC_CTRL_REG = UDC_CLR_EP; - UDC_CTRL_REG = UDC_SET_FIFO_EN; - UDC_EP_NUM_REG = UDC_EP_DIR; + omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM); + omap_writew(UDC_CLR_EP, UDC_CTRL); + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); + omap_writew(UDC_EP_DIR, UDC_EP_NUM); /* cleanup */ udc->ep0_pending = 0; @@ -1013,11 +1034,11 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) /* non-empty DATA stage */ } else if (is_in) { - UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; + omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM); } else { if (udc->ep0_setup) goto irq_wait; - UDC_EP_NUM_REG = UDC_EP_SEL; + omap_writew(UDC_EP_SEL, UDC_EP_NUM); } } else { is_in = ep->bEndpointAddress & USB_DIR_IN; @@ -1033,7 +1054,7 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) req = NULL; deselect_ep(); if (!is_in) { - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); ep->ackwait = 1 + ep->double_buf; } /* IN: 6 wait states before it'll tx */ @@ -1101,9 +1122,9 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) else if (value) { if (ep->udc->ep0_set_config) { WARN("error changing config?\n"); - UDC_SYSCON2_REG = UDC_CLR_CFG; + omap_writew(UDC_CLR_CFG, UDC_SYSCON2); } - UDC_SYSCON2_REG = UDC_STALL_CMD; + omap_writew(UDC_STALL_CMD, UDC_SYSCON2); ep->udc->ep0_pending = 0; status = 0; } else /* NOP */ @@ -1130,8 +1151,8 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) channel = 0; use_ep(ep, UDC_EP_SEL); - if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) { - UDC_CTRL_REG = UDC_SET_HALT; + if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) { + omap_writew(UDC_SET_HALT, UDC_CTRL); status = 0; } else status = -EAGAIN; @@ -1141,10 +1162,10 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) dma_channel_claim(ep, channel); } else { use_ep(ep, 0); - UDC_CTRL_REG = ep->udc->clr_halt; + omap_writew(ep->udc->clr_halt, UDC_CTRL); ep->ackwait = 0; if (!(ep->bEndpointAddress & USB_DIR_IN)) { - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); ep->ackwait = 1 + ep->double_buf; } } @@ -1176,7 +1197,7 @@ static struct usb_ep_ops omap_ep_ops = { static int omap_get_frame(struct usb_gadget *gadget) { - u16 sof = UDC_SOF_REG; + u16 sof = omap_readw(UDC_SOF); return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; } @@ -1195,7 +1216,7 @@ static int omap_wakeup(struct usb_gadget *gadget) */ if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { DBG("remote wakeup...\n"); - UDC_SYSCON2_REG = UDC_RMT_WKP; + omap_writew(UDC_RMT_WKP, UDC_SYSCON2); retval = 0; } @@ -1218,12 +1239,12 @@ omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) udc = container_of(gadget, struct omap_udc, gadget); spin_lock_irqsave(&udc->lock, flags); - syscon1 = UDC_SYSCON1_REG; + syscon1 = omap_readw(UDC_SYSCON1); if (is_selfpowered) syscon1 |= UDC_SELF_PWR; else syscon1 &= ~UDC_SELF_PWR; - UDC_SYSCON1_REG = syscon1; + omap_writew(syscon1, UDC_SYSCON1); spin_unlock_irqrestore(&udc->lock, flags); return 0; @@ -1236,18 +1257,36 @@ static int can_pullup(struct omap_udc *udc) static void pullup_enable(struct omap_udc *udc) { - UDC_SYSCON1_REG |= UDC_PULLUP_EN; - if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) - OTG_CTRL_REG |= OTG_BSESSVLD; - UDC_IRQ_EN_REG = UDC_DS_CHG_IE; + u16 w; + + w = omap_readw(UDC_SYSCON1); + w |= UDC_PULLUP_EN; + omap_writew(w, UDC_SYSCON1); + if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { + u32 l; + + l = omap_readl(OTG_CTRL); + l |= OTG_BSESSVLD; + omap_writel(l, OTG_CTRL); + } + omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); } static void pullup_disable(struct omap_udc *udc) { - if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) - OTG_CTRL_REG &= ~OTG_BSESSVLD; - UDC_IRQ_EN_REG = UDC_DS_CHG_IE; - UDC_SYSCON1_REG &= ~UDC_PULLUP_EN; + u16 w; + + if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { + u32 l; + + l = omap_readl(OTG_CTRL); + l &= ~OTG_BSESSVLD; + omap_writel(l, OTG_CTRL); + } + omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); + w = omap_readw(UDC_SYSCON1); + w &= ~UDC_PULLUP_EN; + omap_writew(w, UDC_SYSCON1); } static struct omap_udc *udc; @@ -1275,6 +1314,7 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active) { struct omap_udc *udc; unsigned long flags; + u32 l; udc = container_of(gadget, struct omap_udc, gadget); spin_lock_irqsave(&udc->lock, flags); @@ -1282,10 +1322,12 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active) udc->vbus_active = (is_active != 0); if (cpu_is_omap15xx()) { /* "software" detect, ignored if !VBUS_MODE_1510 */ + l = omap_readl(FUNC_MUX_CTRL_0); if (is_active) - FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510; + l |= VBUS_CTRL_1510; else - FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; + l &= ~VBUS_CTRL_1510; + omap_writel(l, FUNC_MUX_CTRL_0); } if (udc->dc_clk != NULL && is_active) { if (!udc->clk_requested) { @@ -1355,9 +1397,9 @@ static void nuke(struct omap_ep *ep, int status) dma_channel_release(ep); use_ep(ep, 0); - UDC_CTRL_REG = UDC_CLR_EP; + omap_writew(UDC_CLR_EP, UDC_CTRL); if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) - UDC_CTRL_REG = UDC_SET_HALT; + omap_writew(UDC_SET_HALT, UDC_CTRL); while (!list_empty(&ep->queue)) { req = list_entry(ep->queue.next, struct omap_req, queue); @@ -1385,8 +1427,8 @@ static void update_otg(struct omap_udc *udc) if (!gadget_is_otg(&udc->gadget)) return; - if (OTG_CTRL_REG & OTG_ID) - devstat = UDC_DEVSTAT_REG; + if (omap_readl(OTG_CTRL) & OTG_ID) + devstat = omap_readw(UDC_DEVSTAT); else devstat = 0; @@ -1397,9 +1439,14 @@ static void update_otg(struct omap_udc *udc) /* Enable HNP early, avoiding races on suspend irq path. * ASSUMES OTG state machine B_BUS_REQ input is true. */ - if (udc->gadget.b_hnp_enable) - OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ) - & ~OTG_PULLUP; + if (udc->gadget.b_hnp_enable) { + u32 l; + + l = omap_readl(OTG_CTRL); + l |= OTG_B_HNPEN | OTG_B_BUSREQ; + l &= ~OTG_PULLUP; + omap_writel(l, OTG_CTRL); + } } static void ep0_irq(struct omap_udc *udc, u16 irq_src) @@ -1417,7 +1464,7 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) nuke(ep0, 0); if (ack) { - UDC_IRQ_SRC_REG = ack; + omap_writew(ack, UDC_IRQ_SRC); irq_src = UDC_SETUP; } } @@ -1437,9 +1484,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) if (irq_src & UDC_EP0_TX) { int stat; - UDC_IRQ_SRC_REG = UDC_EP0_TX; - UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; - stat = UDC_STAT_FLG_REG; + omap_writew(UDC_EP0_TX, UDC_IRQ_SRC); + omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); + stat = omap_readw(UDC_STAT_FLG); if (stat & UDC_ACK) { if (udc->ep0_in) { /* write next IN packet from response, @@ -1447,26 +1494,26 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) */ if (req) stat = write_fifo(ep0, req); - UDC_EP_NUM_REG = UDC_EP_DIR; + omap_writew(UDC_EP_DIR, UDC_EP_NUM); if (!req && udc->ep0_pending) { - UDC_EP_NUM_REG = UDC_EP_SEL; - UDC_CTRL_REG = UDC_CLR_EP; - UDC_CTRL_REG = UDC_SET_FIFO_EN; - UDC_EP_NUM_REG = 0; + omap_writew(UDC_EP_SEL, UDC_EP_NUM); + omap_writew(UDC_CLR_EP, UDC_CTRL); + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); + omap_writew(0, UDC_EP_NUM); udc->ep0_pending = 0; } /* else: 6 wait states before it'll tx */ } else { /* ack status stage of OUT transfer */ - UDC_EP_NUM_REG = UDC_EP_DIR; + omap_writew(UDC_EP_DIR, UDC_EP_NUM); if (req) done(ep0, req, 0); } req = NULL; } else if (stat & UDC_STALL) { - UDC_CTRL_REG = UDC_CLR_HALT; - UDC_EP_NUM_REG = UDC_EP_DIR; + omap_writew(UDC_CLR_HALT, UDC_CTRL); + omap_writew(UDC_EP_DIR, UDC_EP_NUM); } else { - UDC_EP_NUM_REG = UDC_EP_DIR; + omap_writew(UDC_EP_DIR, UDC_EP_NUM); } } @@ -1474,9 +1521,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) if (irq_src & UDC_EP0_RX) { int stat; - UDC_IRQ_SRC_REG = UDC_EP0_RX; - UDC_EP_NUM_REG = UDC_EP_SEL; - stat = UDC_STAT_FLG_REG; + omap_writew(UDC_EP0_RX, UDC_IRQ_SRC); + omap_writew(UDC_EP_SEL, UDC_EP_NUM); + stat = omap_readw(UDC_STAT_FLG); if (stat & UDC_ACK) { if (!udc->ep0_in) { stat = 0; @@ -1484,34 +1531,35 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) * reactiviting the fifo; stall on errors. */ if (!req || (stat = read_fifo(ep0, req)) < 0) { - UDC_SYSCON2_REG = UDC_STALL_CMD; + omap_writew(UDC_STALL_CMD, UDC_SYSCON2); udc->ep0_pending = 0; stat = 0; } else if (stat == 0) - UDC_CTRL_REG = UDC_SET_FIFO_EN; - UDC_EP_NUM_REG = 0; + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); + omap_writew(0, UDC_EP_NUM); /* activate status stage */ if (stat == 1) { done(ep0, req, 0); /* that may have STALLed ep0... */ - UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; - UDC_CTRL_REG = UDC_CLR_EP; - UDC_CTRL_REG = UDC_SET_FIFO_EN; - UDC_EP_NUM_REG = UDC_EP_DIR; + omap_writew(UDC_EP_SEL | UDC_EP_DIR, + UDC_EP_NUM); + omap_writew(UDC_CLR_EP, UDC_CTRL); + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); + omap_writew(UDC_EP_DIR, UDC_EP_NUM); udc->ep0_pending = 0; } } else { /* ack status stage of IN transfer */ - UDC_EP_NUM_REG = 0; + omap_writew(0, UDC_EP_NUM); if (req) done(ep0, req, 0); } } else if (stat & UDC_STALL) { - UDC_CTRL_REG = UDC_CLR_HALT; - UDC_EP_NUM_REG = 0; + omap_writew(UDC_CLR_HALT, UDC_CTRL); + omap_writew(0, UDC_EP_NUM); } else { - UDC_EP_NUM_REG = 0; + omap_writew(0, UDC_EP_NUM); } } @@ -1526,14 +1574,14 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) /* read the (latest) SETUP message */ do { - UDC_EP_NUM_REG = UDC_SETUP_SEL; + omap_writew(UDC_SETUP_SEL, UDC_EP_NUM); /* two bytes at a time */ - u.word[0] = UDC_DATA_REG; - u.word[1] = UDC_DATA_REG; - u.word[2] = UDC_DATA_REG; - u.word[3] = UDC_DATA_REG; - UDC_EP_NUM_REG = 0; - } while (UDC_IRQ_SRC_REG & UDC_SETUP); + u.word[0] = omap_readw(UDC_DATA); + u.word[1] = omap_readw(UDC_DATA); + u.word[2] = omap_readw(UDC_DATA); + u.word[3] = omap_readw(UDC_DATA); + omap_writew(0, UDC_EP_NUM); + } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP); #define w_value le16_to_cpu(u.r.wValue) #define w_index le16_to_cpu(u.r.wIndex) @@ -1564,9 +1612,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) * later if it fails the request. */ if (udc->ep0_reset_config) - UDC_SYSCON2_REG = UDC_CLR_CFG; + omap_writew(UDC_CLR_CFG, UDC_SYSCON2); else - UDC_SYSCON2_REG = UDC_DEV_CFG; + omap_writew(UDC_DEV_CFG, UDC_SYSCON2); update_otg(udc); goto delegate; case USB_REQ_CLEAR_FEATURE: @@ -1584,10 +1632,10 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) || !ep->desc) goto do_stall; use_ep(ep, 0); - UDC_CTRL_REG = udc->clr_halt; + omap_writew(udc->clr_halt, UDC_CTRL); ep->ackwait = 0; if (!(ep->bEndpointAddress & USB_DIR_IN)) { - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); ep->ackwait = 1 + ep->double_buf; } /* NOTE: assumes the host behaves sanely, @@ -1620,15 +1668,15 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) } use_ep(ep, 0); /* can't halt if fifo isn't empty... */ - UDC_CTRL_REG = UDC_CLR_EP; - UDC_CTRL_REG = UDC_SET_HALT; + omap_writew(UDC_CLR_EP, UDC_CTRL); + omap_writew(UDC_SET_HALT, UDC_CTRL); VDBG("%s halted by host\n", ep->name); ep0out_status_stage: status = 0; - UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; - UDC_CTRL_REG = UDC_CLR_EP; - UDC_CTRL_REG = UDC_SET_FIFO_EN; - UDC_EP_NUM_REG = UDC_EP_DIR; + omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); + omap_writew(UDC_CLR_EP, UDC_CTRL); + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); + omap_writew(UDC_EP_DIR, UDC_EP_NUM); udc->ep0_pending = 0; break; case USB_REQ_GET_STATUS: @@ -1665,10 +1713,10 @@ intf_status: zero_status: /* return two zero bytes */ - UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; - UDC_DATA_REG = 0; - UDC_CTRL_REG = UDC_SET_FIFO_EN; - UDC_EP_NUM_REG = UDC_EP_DIR; + omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); + omap_writew(0, UDC_DATA); + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); + omap_writew(UDC_EP_DIR, UDC_EP_NUM); status = 0; VDBG("GET_STATUS, interface %d\n", w_index); /* next, status stage */ @@ -1677,8 +1725,8 @@ zero_status: delegate: /* activate the ep0out fifo right away */ if (!udc->ep0_in && w_length) { - UDC_EP_NUM_REG = 0; - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(0, UDC_EP_NUM); + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); } /* gadget drivers see class/vendor specific requests, @@ -1719,9 +1767,9 @@ do_stall: if (udc->ep0_reset_config) WARN("error resetting config?\n"); else - UDC_SYSCON2_REG = UDC_CLR_CFG; + omap_writew(UDC_CLR_CFG, UDC_SYSCON2); } - UDC_SYSCON2_REG = UDC_STALL_CMD; + omap_writew(UDC_STALL_CMD, UDC_SYSCON2); udc->ep0_pending = 0; } } @@ -1735,7 +1783,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) { u16 devstat, change; - devstat = UDC_DEVSTAT_REG; + devstat = omap_readw(UDC_DEVSTAT); change = devstat ^ udc->devstat; udc->devstat = devstat; @@ -1775,7 +1823,8 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) INFO("USB reset done, gadget %s\n", udc->driver->driver.name); /* ep0 traffic is legal from now on */ - UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE; + omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE, + UDC_IRQ_EN); } change &= ~UDC_USB_RESET; } @@ -1819,7 +1868,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) VDBG("devstat %03x, ignore change %03x\n", devstat, change); - UDC_IRQ_SRC_REG = UDC_DS_CHG; + omap_writew(UDC_DS_CHG, UDC_IRQ_SRC); } static irqreturn_t omap_udc_irq(int irq, void *_udc) @@ -1830,7 +1879,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc) unsigned long flags; spin_lock_irqsave(&udc->lock, flags); - irq_src = UDC_IRQ_SRC_REG; + irq_src = omap_readw(UDC_IRQ_SRC); /* Device state change (usb ch9 stuff) */ if (irq_src & UDC_DS_CHG) { @@ -1853,7 +1902,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc) irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); } - irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX); + irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX); if (irq_src) DBG("udc_irq, unhandled %03x\n", irq_src); spin_unlock_irqrestore(&udc->lock, flags); @@ -1874,7 +1923,7 @@ static void pio_out_timer(unsigned long _ep) spin_lock_irqsave(&ep->udc->lock, flags); if (!list_empty(&ep->queue) && ep->ackwait) { use_ep(ep, UDC_EP_SEL); - stat_flg = UDC_STAT_FLG_REG; + stat_flg = omap_readw(UDC_STAT_FLG); if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) || (ep->double_buf && HALF_FULL(stat_flg)))) { @@ -1884,8 +1933,8 @@ static void pio_out_timer(unsigned long _ep) req = container_of(ep->queue.next, struct omap_req, queue); (void) read_fifo(ep, req); - UDC_EP_NUM_REG = ep->bEndpointAddress; - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(ep->bEndpointAddress, UDC_EP_NUM); + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); ep->ackwait = 1 + ep->double_buf; } else deselect_ep(); @@ -1905,20 +1954,20 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) unsigned long flags; spin_lock_irqsave(&udc->lock, flags); - epn_stat = UDC_EPN_STAT_REG; - irq_src = UDC_IRQ_SRC_REG; + epn_stat = omap_readw(UDC_EPN_STAT); + irq_src = omap_readw(UDC_IRQ_SRC); /* handle OUT first, to avoid some wasteful NAKs */ if (irq_src & UDC_EPN_RX) { epnum = (epn_stat >> 8) & 0x0f; - UDC_IRQ_SRC_REG = UDC_EPN_RX; + omap_writew(UDC_EPN_RX, UDC_IRQ_SRC); status = IRQ_HANDLED; ep = &udc->ep[epnum]; ep->irqs++; - UDC_EP_NUM_REG = epnum | UDC_EP_SEL; + omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM); ep->fnf = 0; - if ((UDC_STAT_FLG_REG & UDC_ACK)) { + if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { ep->ackwait--; if (!list_empty(&ep->queue)) { int stat; @@ -1930,15 +1979,15 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) } } /* min 6 clock delay before clearing EP_SEL ... */ - epn_stat = UDC_EPN_STAT_REG; - epn_stat = UDC_EPN_STAT_REG; - UDC_EP_NUM_REG = epnum; + epn_stat = omap_readw(UDC_EPN_STAT); + epn_stat = omap_readw(UDC_EPN_STAT); + omap_writew(epnum, UDC_EP_NUM); /* enabling fifo _after_ clearing ACK, contrary to docs, * reduces lossage; timer still needed though (sigh). */ if (ep->fnf) { - UDC_CTRL_REG = UDC_SET_FIFO_EN; + omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); ep->ackwait = 1 + ep->double_buf; } mod_timer(&ep->timer, PIO_OUT_TIMEOUT); @@ -1947,13 +1996,13 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) /* then IN transfers */ else if (irq_src & UDC_EPN_TX) { epnum = epn_stat & 0x0f; - UDC_IRQ_SRC_REG = UDC_EPN_TX; + omap_writew(UDC_EPN_TX, UDC_IRQ_SRC); status = IRQ_HANDLED; ep = &udc->ep[16 + epnum]; ep->irqs++; - UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL; - if ((UDC_STAT_FLG_REG & UDC_ACK)) { + omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM); + if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { ep->ackwait = 0; if (!list_empty(&ep->queue)) { req = container_of(ep->queue.next, @@ -1962,9 +2011,9 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) } } /* min 6 clock delay before clearing EP_SEL ... */ - epn_stat = UDC_EPN_STAT_REG; - epn_stat = UDC_EPN_STAT_REG; - UDC_EP_NUM_REG = epnum | UDC_EP_DIR; + epn_stat = omap_readw(UDC_EPN_STAT); + epn_stat = omap_readw(UDC_EPN_STAT); + omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM); /* then 6 clocks before it'd tx */ } @@ -1992,7 +2041,7 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) req = list_entry(ep->queue.next, struct omap_req, queue); use_ep(ep, UDC_EP_SEL); - stat = UDC_STAT_FLG_REG; + stat = omap_readw(UDC_STAT_FLG); /* NOTE: like the other controller drivers, this isn't * currently reporting lost or damaged frames. @@ -2024,9 +2073,14 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) if (!list_empty(&ep->queue)) pending = 1; } - if (!pending) - UDC_IRQ_EN_REG &= ~UDC_SOF_IE; - UDC_IRQ_SRC_REG = UDC_SOF; + if (!pending) { + u16 w; + + w = omap_readw(UDC_IRQ_EN); + w &= ~UDC_SOF_IE; + omap_writew(w, UDC_IRQ_EN); + } + omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC); spin_unlock_irqrestore(&udc->lock, flags); return IRQ_HANDLED; @@ -2075,7 +2129,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver) if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) continue; use_ep(ep, 0); - UDC_CTRL_REG = UDC_SET_HALT; + omap_writew(UDC_SET_HALT, UDC_CTRL); } udc->ep0_pending = 0; udc->ep[0].irqs = 0; @@ -2099,7 +2153,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver) } DBG("bound to driver %s\n", driver->driver.name); - UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; + omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); /* connect to bus through transceiver */ if (udc->transceiver) { @@ -2196,7 +2250,7 @@ static void proc_ep_show(struct seq_file *s, struct omap_ep *ep) else buf[0] = 0; - stat_flg = UDC_STAT_FLG_REG; + stat_flg = omap_readw(UDC_STAT_FLG); seq_printf(s, "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", ep->name, buf, @@ -2257,12 +2311,12 @@ static int proc_otg_show(struct seq_file *s) u32 trans; char *ctrl_name; - tmp = OTG_REV_REG; + tmp = omap_readw(OTG_REV); if (cpu_is_omap24xx()) { /* * REVISIT: Not clear how this works on OMAP2. trans * is ANDed to produce bits 7 and 8, which might make - * sense for USB_TRANSCEIVER_CTRL_REG on OMAP1, + * sense for USB_TRANSCEIVER_CTRL on OMAP1, * but with CONTROL_DEVCONF, these bits have something to * do with the frame adjustment counter and McBSP2. */ @@ -2270,11 +2324,11 @@ static int proc_otg_show(struct seq_file *s) trans = omap_ctrl_readb(OMAP2_CONTROL_DEVCONF0); } else { ctrl_name = "tranceiver_ctrl"; - trans = USB_TRANSCEIVER_CTRL_REG; + trans = omap_readw(USB_TRANSCEIVER_CTRL); } seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", tmp >> 4, tmp & 0xf, ctrl_name, trans); - tmp = OTG_SYSCON_1_REG; + tmp = omap_readw(OTG_SYSCON_1); seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," FOURBITS "\n", tmp, trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), @@ -2286,7 +2340,7 @@ static int proc_otg_show(struct seq_file *s) (tmp & HST_IDLE_EN) ? " !host" : "", (tmp & DEV_IDLE_EN) ? " !dev" : "", (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); - tmp = OTG_SYSCON_2_REG; + tmp = omap_readl(OTG_SYSCON_2); seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS " b_ase_brst=%d hmc=%d\n", tmp, (tmp & OTG_EN) ? " otg_en" : "", @@ -2301,7 +2355,7 @@ static int proc_otg_show(struct seq_file *s) (tmp & HMC_TLLATTACH) ? " tllattach" : "", B_ASE_BRST(tmp), OTG_HMC(tmp)); - tmp = OTG_CTRL_REG; + tmp = omap_readl(OTG_CTRL); seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, (tmp & OTG_ASESSVLD) ? " asess" : "", (tmp & OTG_BSESSEND) ? " bsess_end" : "", @@ -2321,13 +2375,13 @@ static int proc_otg_show(struct seq_file *s) (tmp & OTG_PU_VBUS) ? " pu_vb" : "", (tmp & OTG_PU_ID) ? " pu_id" : "" ); - tmp = OTG_IRQ_EN_REG; + tmp = omap_readw(OTG_IRQ_EN); seq_printf(s, "otg_irq_en %04x" "\n", tmp); - tmp = OTG_IRQ_SRC_REG; + tmp = omap_readw(OTG_IRQ_SRC); seq_printf(s, "otg_irq_src %04x" "\n", tmp); - tmp = OTG_OUTCTRL_REG; + tmp = omap_readw(OTG_OUTCTRL); seq_printf(s, "otg_outctrl %04x" "\n", tmp); - tmp = OTG_TEST_REG; + tmp = omap_readw(OTG_TEST); seq_printf(s, "otg_test %04x" "\n", tmp); return 0; } @@ -2348,7 +2402,7 @@ static int proc_udc_show(struct seq_file *s, void *_) driver_desc, use_dma ? " (dma)" : ""); - tmp = UDC_REV_REG & 0xff; + tmp = omap_readw(UDC_REV) & 0xff; seq_printf(s, "UDC rev %d.%d, fifo mode %d, gadget %s\n" "hmc %d, transceiver %s\n", @@ -2362,16 +2416,16 @@ static int proc_udc_show(struct seq_file *s, void *_) ? "external" : "(none)")); if (cpu_class_is_omap1()) { seq_printf(s, "ULPD control %04x req %04x status %04x\n", - __REG16(ULPD_CLOCK_CTRL), - __REG16(ULPD_SOFT_REQ), - __REG16(ULPD_STATUS_REQ)); + omap_readw(ULPD_CLOCK_CTRL), + omap_readw(ULPD_SOFT_REQ), + omap_readw(ULPD_STATUS_REQ)); } /* OTG controller registers */ if (!cpu_is_omap15xx()) proc_otg_show(s); - tmp = UDC_SYSCON1_REG; + tmp = omap_readw(UDC_SYSCON1); seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", @@ -2390,7 +2444,7 @@ static int proc_udc_show(struct seq_file *s, void *_) return 0; } - tmp = UDC_DEVSTAT_REG; + tmp = omap_readw(UDC_DEVSTAT); seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", @@ -2402,20 +2456,20 @@ static int proc_udc_show(struct seq_file *s, void *_) (tmp & UDC_ADD) ? " ADD" : "", (tmp & UDC_DEF) ? " DEF" : "", (tmp & UDC_ATT) ? " ATT" : ""); - seq_printf(s, "sof %04x\n", UDC_SOF_REG); - tmp = UDC_IRQ_EN_REG; + seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF)); + tmp = omap_readw(UDC_IRQ_EN); seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, (tmp & UDC_SOF_IE) ? " sof" : "", (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", (tmp & UDC_EP0_IE) ? " ep0" : ""); - tmp = UDC_IRQ_SRC_REG; + tmp = omap_readw(UDC_IRQ_SRC); seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, (tmp & UDC_TXN_DONE) ? " txn_done" : "", (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", - (tmp & UDC_SOF) ? " sof" : "", + (tmp & UDC_IRQ_SOF) ? " sof" : "", (tmp & UDC_EPN_RX) ? " epn_rx" : "", (tmp & UDC_EPN_TX) ? " epn_tx" : "", (tmp & UDC_DS_CHG) ? " ds_chg" : "", @@ -2425,7 +2479,7 @@ static int proc_udc_show(struct seq_file *s, void *_) if (use_dma) { unsigned i; - tmp = UDC_DMA_IRQ_EN_REG; + tmp = omap_readw(UDC_DMA_IRQ_EN); seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", @@ -2439,29 +2493,29 @@ static int proc_udc_show(struct seq_file *s, void *_) (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); - tmp = UDC_RXDMA_CFG_REG; + tmp = omap_readw(UDC_RXDMA_CFG); seq_printf(s, "rxdma_cfg %04x\n", tmp); if (tmp) { for (i = 0; i < 3; i++) { if ((tmp & (0x0f << (i * 4))) == 0) continue; seq_printf(s, "rxdma[%d] %04x\n", i, - UDC_RXDMA_REG(i + 1)); + omap_readw(UDC_RXDMA(i + 1))); } } - tmp = UDC_TXDMA_CFG_REG; + tmp = omap_readw(UDC_TXDMA_CFG); seq_printf(s, "txdma_cfg %04x\n", tmp); if (tmp) { for (i = 0; i < 3; i++) { if (!(tmp & (0x0f << (i * 4)))) continue; seq_printf(s, "txdma[%d] %04x\n", i, - UDC_TXDMA_REG(i + 1)); + omap_readw(UDC_TXDMA(i + 1))); } } } - tmp = UDC_DEVSTAT_REG; + tmp = omap_readw(UDC_DEVSTAT); if (tmp & UDC_ATT) { proc_ep_show(s, &udc->ep[0]); if (tmp & UDC_ADD) { @@ -2513,7 +2567,7 @@ static inline void remove_proc_file(void) {} * buffer space among the endpoints we'll be operating. * * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when - * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that + * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that * capability yet though. */ static unsigned __init @@ -2577,9 +2631,9 @@ omap_ep_setup(char *name, u8 addr, u8 type, name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); if (addr & USB_DIR_IN) - UDC_EP_TX_REG(addr & 0xf) = epn_rxtx; + omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf)); else - UDC_EP_RX_REG(addr) = epn_rxtx; + omap_writew(epn_rxtx, UDC_EP_RX(addr)); /* next endpoint's buffer starts after this one's */ buf += maxp; @@ -2618,15 +2672,15 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) unsigned tmp, buf; /* abolish any previous hardware state */ - UDC_SYSCON1_REG = 0; - UDC_IRQ_EN_REG = 0; - UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; - UDC_DMA_IRQ_EN_REG = 0; - UDC_RXDMA_CFG_REG = 0; - UDC_TXDMA_CFG_REG = 0; + omap_writew(0, UDC_SYSCON1); + omap_writew(0, UDC_IRQ_EN); + omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); + omap_writew(0, UDC_DMA_IRQ_EN); + omap_writew(0, UDC_RXDMA_CFG); + omap_writew(0, UDC_TXDMA_CFG); /* UDC_PULLUP_EN gates the chip clock */ - // OTG_SYSCON_1_REG |= DEV_IDLE_EN; + // OTG_SYSCON_1 |= DEV_IDLE_EN; udc = kzalloc(sizeof(*udc), GFP_KERNEL); if (!udc) @@ -2657,8 +2711,8 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) /* initially disable all non-ep0 endpoints */ for (tmp = 1; tmp < 15; tmp++) { - UDC_EP_RX_REG(tmp) = 0; - UDC_EP_TX_REG(tmp) = 0; + omap_writew(0, UDC_EP_RX(tmp)); + omap_writew(0, UDC_EP_TX(tmp)); } #define OMAP_BULK_EP(name,addr) \ @@ -2743,7 +2797,7 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) ERR("unsupported fifo_mode #%d\n", fifo_mode); return -ENODEV; } - UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR; + omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1); INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); return 0; } @@ -2787,7 +2841,7 @@ static int __init omap_udc_probe(struct platform_device *pdev) } INFO("OMAP UDC rev %d.%d%s\n", - UDC_REV_REG >> 4, UDC_REV_REG & 0xf, + omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf, config->otg ? ", Mini-AB" : ""); /* use the mode given to us by board init code */ @@ -2802,12 +2856,12 @@ static int __init omap_udc_probe(struct platform_device *pdev) * know when to turn PULLUP_EN on/off; and that * means we always "need" the 48MHz clock. */ - u32 tmp = FUNC_MUX_CTRL_0_REG; - - FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; + u32 tmp = omap_readl(FUNC_MUX_CTRL_0); + tmp &= ~VBUS_CTRL_1510; + omap_writel(tmp, FUNC_MUX_CTRL_0); tmp |= VBUS_MODE_1510; tmp &= ~VBUS_CTRL_1510; - FUNC_MUX_CTRL_0_REG = tmp; + omap_writel(tmp, FUNC_MUX_CTRL_0); } } else { /* The transceiver may package some GPIO logic or handle @@ -2887,7 +2941,7 @@ known: #endif /* starting with omap1710 es2.0, clear toggle is a separate bit */ - if (UDC_REV_REG >= 0x61) + if (omap_readw(UDC_REV) >= 0x61) udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; else udc->clr_halt = UDC_RESET_EP; @@ -2985,7 +3039,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev) put_device(udc->transceiver->dev); udc->transceiver = NULL; } - UDC_SYSCON1_REG = 0; + omap_writew(0, UDC_SYSCON1); remove_proc_file(); @@ -3016,7 +3070,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev) * * REVISIT we should probably reject suspend requests when there's a host * session active, rather than disconnecting, at least on boards that can - * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to + * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to * make host resumes and VBUS detection trigger OMAP wakeup events; that * may involve talking to an external transceiver (e.g. isp1301). */ @@ -3025,7 +3079,7 @@ static int omap_udc_suspend(struct platform_device *dev, pm_message_t message) { u32 devstat; - devstat = UDC_DEVSTAT_REG; + devstat = omap_readw(UDC_DEVSTAT); /* we're requesting 48 MHz clock if the pullup is enabled * (== we're attached to the host) and we're not suspended, diff --git a/drivers/usb/gadget/omap_udc.h b/drivers/usb/gadget/omap_udc.h index c6b9cbc..8522bbb 100644 --- a/drivers/usb/gadget/omap_udc.h +++ b/drivers/usb/gadget/omap_udc.h @@ -8,23 +8,22 @@ /* * USB device/endpoint management registers */ -#define UDC_REG(offset) __REG16(UDC_BASE + (offset)) -#define UDC_REV_REG UDC_REG(0x0) /* Revision */ -#define UDC_EP_NUM_REG UDC_REG(0x4) /* Which endpoint */ +#define UDC_REV (UDC_BASE + 0x0) /* Revision */ +#define UDC_EP_NUM (UDC_BASE + 0x4) /* Which endpoint */ # define UDC_SETUP_SEL (1 << 6) # define UDC_EP_SEL (1 << 5) # define UDC_EP_DIR (1 << 4) /* low 4 bits for endpoint number */ -#define UDC_DATA_REG UDC_REG(0x08) /* Endpoint FIFO */ -#define UDC_CTRL_REG UDC_REG(0x0C) /* Endpoint control */ +#define UDC_DATA (UDC_BASE + 0x08) /* Endpoint FIFO */ +#define UDC_CTRL (UDC_BASE + 0x0C) /* Endpoint control */ # define UDC_CLR_HALT (1 << 7) # define UDC_SET_HALT (1 << 6) # define UDC_CLRDATA_TOGGLE (1 << 3) # define UDC_SET_FIFO_EN (1 << 2) # define UDC_CLR_EP (1 << 1) # define UDC_RESET_EP (1 << 0) -#define UDC_STAT_FLG_REG UDC_REG(0x10) /* Endpoint status */ +#define UDC_STAT_FLG (UDC_BASE + 0x10) /* Endpoint status */ # define UDC_NO_RXPACKET (1 << 15) # define UDC_MISS_IN (1 << 14) # define UDC_DATA_FLUSH (1 << 13) @@ -38,8 +37,8 @@ # define UDC_FIFO_EN (1 << 2) # define UDC_NON_ISO_FIFO_EMPTY (1 << 1) # define UDC_NON_ISO_FIFO_FULL (1 << 0) -#define UDC_RXFSTAT_REG UDC_REG(0x14) /* OUT bytecount */ -#define UDC_SYSCON1_REG UDC_REG(0x18) /* System config 1 */ +#define UDC_RXFSTAT (UDC_BASE + 0x14) /* OUT bytecount */ +#define UDC_SYSCON1 (UDC_BASE + 0x18) /* System config 1 */ # define UDC_CFG_LOCK (1 << 8) # define UDC_DATA_ENDIAN (1 << 7) # define UDC_DMA_ENDIAN (1 << 6) @@ -48,12 +47,12 @@ # define UDC_SELF_PWR (1 << 2) # define UDC_SOFF_DIS (1 << 1) # define UDC_PULLUP_EN (1 << 0) -#define UDC_SYSCON2_REG UDC_REG(0x1C) /* System config 2 */ +#define UDC_SYSCON2 (UDC_BASE + 0x1C) /* System config 2 */ # define UDC_RMT_WKP (1 << 6) # define UDC_STALL_CMD (1 << 5) # define UDC_DEV_CFG (1 << 3) # define UDC_CLR_CFG (1 << 2) -#define UDC_DEVSTAT_REG UDC_REG(0x20) /* Device status */ +#define UDC_DEVSTAT (UDC_BASE + 0x20) /* Device status */ # define UDC_B_HNP_ENABLE (1 << 9) # define UDC_A_HNP_SUPPORT (1 << 8) # define UDC_A_ALT_HNP_SUPPORT (1 << 7) @@ -64,26 +63,26 @@ # define UDC_ADD (1 << 2) # define UDC_DEF (1 << 1) # define UDC_ATT (1 << 0) -#define UDC_SOF_REG UDC_REG(0x24) /* Start of frame */ +#define UDC_SOF (UDC_BASE + 0x24) /* Start of frame */ # define UDC_FT_LOCK (1 << 12) # define UDC_TS_OK (1 << 11) # define UDC_TS 0x03ff -#define UDC_IRQ_EN_REG UDC_REG(0x28) /* Interrupt enable */ +#define UDC_IRQ_EN (UDC_BASE + 0x28) /* Interrupt enable */ # define UDC_SOF_IE (1 << 7) # define UDC_EPN_RX_IE (1 << 5) # define UDC_EPN_TX_IE (1 << 4) # define UDC_DS_CHG_IE (1 << 3) # define UDC_EP0_IE (1 << 0) -#define UDC_DMA_IRQ_EN_REG UDC_REG(0x2C) /* DMA irq enable */ +#define UDC_DMA_IRQ_EN (UDC_BASE + 0x2C) /* DMA irq enable */ /* rx/tx dma channels numbered 1-3 not 0-2 */ # define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2)) # define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3)) # define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4)) -#define UDC_IRQ_SRC_REG UDC_REG(0x30) /* Interrupt source */ +#define UDC_IRQ_SRC (UDC_BASE + 0x30) /* Interrupt source */ # define UDC_TXN_DONE (1 << 10) # define UDC_RXN_CNT (1 << 9) # define UDC_RXN_EOT (1 << 8) -# define UDC_SOF (1 << 7) +# define UDC_IRQ_SOF (1 << 7) # define UDC_EPN_RX (1 << 5) # define UDC_EPN_TX (1 << 4) # define UDC_DS_CHG (1 << 3) @@ -91,41 +90,41 @@ # define UDC_EP0_RX (1 << 1) # define UDC_EP0_TX (1 << 0) # define UDC_IRQ_SRC_MASK 0x7bf -#define UDC_EPN_STAT_REG UDC_REG(0x34) /* EP irq status */ -#define UDC_DMAN_STAT_REG UDC_REG(0x38) /* DMA irq status */ +#define UDC_EPN_STAT (UDC_BASE + 0x34) /* EP irq status */ +#define UDC_DMAN_STAT (UDC_BASE + 0x38) /* DMA irq status */ # define UDC_DMA_RX_SB (1 << 12) # define UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf) # define UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf) /* DMA configuration registers: up to three channels in each direction. */ -#define UDC_RXDMA_CFG_REG UDC_REG(0x40) /* 3 eps for RX DMA */ +#define UDC_RXDMA_CFG (UDC_BASE + 0x40) /* 3 eps for RX DMA */ # define UDC_DMA_REQ (1 << 12) -#define UDC_TXDMA_CFG_REG UDC_REG(0x44) /* 3 eps for TX DMA */ -#define UDC_DATA_DMA_REG UDC_REG(0x48) /* rx/tx fifo addr */ +#define UDC_TXDMA_CFG (UDC_BASE + 0x44) /* 3 eps for TX DMA */ +#define UDC_DATA_DMA (UDC_BASE + 0x48) /* rx/tx fifo addr */ /* rx/tx dma control, numbering channels 1-3 not 0-2 */ -#define UDC_TXDMA_REG(chan) UDC_REG(0x50 - 4 + 4 * (chan)) +#define UDC_TXDMA(chan) (UDC_BASE + 0x50 - 4 + 4 * (chan)) # define UDC_TXN_EOT (1 << 15) /* bytes vs packets */ # define UDC_TXN_START (1 << 14) /* start transfer */ # define UDC_TXN_TSC 0x03ff /* units in xfer */ -#define UDC_RXDMA_REG(chan) UDC_REG(0x60 - 4 + 4 * (chan)) +#define UDC_RXDMA(chan) (UDC_BASE + 0x60 - 4 + 4 * (chan)) # define UDC_RXN_STOP (1 << 15) /* enable EOT irq */ # define UDC_RXN_TC 0x00ff /* packets in xfer */ /* * Endpoint configuration registers (used before CFG_LOCK is set) - * UDC_EP_TX_REG(0) is unused + * UDC_EP_TX(0) is unused */ -#define UDC_EP_RX_REG(endpoint) UDC_REG(0x80 + (endpoint)*4) +#define UDC_EP_RX(endpoint) (UDC_BASE + 0x80 + (endpoint)*4) # define UDC_EPN_RX_VALID (1 << 15) # define UDC_EPN_RX_DB (1 << 14) /* buffer size in bits 13, 12 */ # define UDC_EPN_RX_ISO (1 << 11) /* buffer pointer in low 11 bits */ -#define UDC_EP_TX_REG(endpoint) UDC_REG(0xc0 + (endpoint)*4) - /* same bitfields as in RX_REG */ +#define UDC_EP_TX(endpoint) (UDC_BASE + 0xc0 + (endpoint)*4) + /* same bitfields as in RX */ /*-------------------------------------------------------------------------*/ @@ -195,14 +194,14 @@ struct omap_udc { /*-------------------------------------------------------------------------*/ -#define MOD_CONF_CTRL_0_REG __REG32(MOD_CONF_CTRL_0) -#define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */ +/* MOD_CONF_CTRL_0 */ +#define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */ -#define FUNC_MUX_CTRL_0_REG __REG32(FUNC_MUX_CTRL_0) +/* FUNC_MUX_CTRL_0 */ #define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */ #define VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */ -#define HMC_1510 ((MOD_CONF_CTRL_0_REG >> 1) & 0x3f) -#define HMC_1610 (OTG_SYSCON_2_REG & 0x3f) +#define HMC_1510 ((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f) +#define HMC_1610 (omap_readl(OTG_SYSCON_2) & 0x3f) #define HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610) diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index f14be49..c23caf6 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -169,13 +169,16 @@ static void start_hnp(struct ohci_hcd *ohci) { const unsigned port = ohci_to_hcd(ohci)->self.otg_port - 1; unsigned long flags; + u32 l; otg_start_hnp(ohci->transceiver); local_irq_save(flags); ohci->transceiver->state = OTG_STATE_A_SUSPEND; writel (RH_PS_PSS, &ohci->regs->roothub.portstatus [port]); - OTG_CTRL_REG &= ~OTG_A_BUSREQ; + l = omap_readl(OTG_CTRL); + l &= ~OTG_A_BUSREQ; + omap_writel(l, OTG_CTRL); local_irq_restore(flags); } diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h index 580a718..7a0967b 100644 --- a/include/asm-arm/arch-omap/usb.h +++ b/include/asm-arm/arch-omap/usb.h @@ -37,11 +37,8 @@ void __init usb_ehci_init(void); /* * OTG and transceiver registers, for OMAPs starting with ARM926 */ -#define OTG_REG32(offset) __REG32(OTG_BASE + (offset)) -#define OTG_REG16(offset) __REG16(OTG_BASE + (offset)) - -#define OTG_REV_REG OTG_REG32(0x00) -#define OTG_SYSCON_1_REG OTG_REG32(0x04) +#define OTG_REV (OTG_BASE + 0x00) +#define OTG_SYSCON_1 (OTG_BASE + 0x04) # define USB2_TRX_MODE(w) (((w)>>24)&0x07) # define USB1_TRX_MODE(w) (((w)>>20)&0x07) # define USB0_TRX_MODE(w) (((w)>>16)&0x07) @@ -50,7 +47,7 @@ void __init usb_ehci_init(void); # define DEV_IDLE_EN (1 << 13) # define OTG_RESET_DONE (1 << 2) # define OTG_SOFT_RESET (1 << 1) -#define OTG_SYSCON_2_REG OTG_REG32(0x08) +#define OTG_SYSCON_2 (OTG_BASE + 0x08) # define OTG_EN (1 << 31) # define USBX_SYNCHRO (1 << 30) # define OTG_MST16 (1 << 29) @@ -68,7 +65,7 @@ void __init usb_ehci_init(void); # define HMC_TLLSPEED (1 << 7) # define HMC_TLLATTACH (1 << 6) # define OTG_HMC(w) (((w)>>0)&0x3f) -#define OTG_CTRL_REG OTG_REG32(0x0c) +#define OTG_CTRL (OTG_BASE + 0x0c) # define OTG_USB2_EN (1 << 29) # define OTG_USB2_DP (1 << 28) # define OTG_USB2_DM (1 << 27) @@ -95,7 +92,7 @@ void __init usb_ehci_init(void); # define OTG_PD_VBUS (1 << 2) # define OTG_PU_VBUS (1 << 1) # define OTG_PU_ID (1 << 0) -#define OTG_IRQ_EN_REG OTG_REG16(0x10) +#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ # define DRIVER_SWITCH (1 << 15) # define A_VBUS_ERR (1 << 13) # define A_REQ_TMROUT (1 << 12) @@ -105,9 +102,9 @@ void __init usb_ehci_init(void); # define B_SRP_DONE (1 << 8) # define B_SRP_STARTED (1 << 7) # define OPRT_CHG (1 << 0) -#define OTG_IRQ_SRC_REG OTG_REG16(0x14) +#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ // same bits as in IRQ_EN -#define OTG_OUTCTRL_REG OTG_REG16(0x18) +#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ # define OTGVPD (1 << 14) # define OTGVPU (1 << 13) # define OTGPUID (1 << 12) @@ -120,13 +117,13 @@ void __init usb_ehci_init(void); # define USB0VDR (1 << 2) # define USB0PDEN (1 << 1) # define USB0PUEN (1 << 0) -#define OTG_TEST_REG OTG_REG16(0x20) -#define OTG_VENDOR_CODE_REG OTG_REG32(0xfc) +#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ +#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ /*-------------------------------------------------------------------------*/ /* OMAP1 */ -#define USB_TRANSCEIVER_CTRL_REG __REG32(0xfffe1000 + 0x0064) +#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) # define CONF_USB2_UNI_R (1 << 8) # define CONF_USB1_UNI_R (1 << 7) # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/14] ARM: OMAP: Change __REG access to omap/read write for traffic controller 2008-05-28 4:20 ` [PATCH 3/14] USB: Change omap USB code to use omap_read/write " Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 5/14] musb_hdrc: Change __REG access to omap_read/write for multi-boot Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Change __REG access to omap/read write for traffic controller Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap1/board-osk.c | 11 ++++++++--- drivers/mtd/maps/omap_nor.c | 15 +++++++++++---- drivers/pcmcia/omap_cf.c | 6 +++--- include/asm-arm/arch-omap/tc.h | 10 ++++------ 4 files changed, 26 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index f2c47b9..845c663 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -267,13 +267,17 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = { static void __init osk_init_smc91x(void) { + u32 l; + if ((gpio_request(0, "smc_irq")) < 0) { printk("Error requesting gpio 0 for smc91x irq\n"); return; } /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */ - EMIFS_CCS(1) |= 0x3; + l = omap_readl(EMIFS_CCS(1)); + l |= 0x3; + omap_writel(l, EMIFS_CCS(1)); } static void __init osk_init_cf(void) @@ -533,8 +537,9 @@ static void __init osk_init(void) * wrong CS3 memory timings. This mainly leads to CRC * or similar errors if you use NOR flash (e.g. with JFFS2) */ - if (EMIFS_CCS(3) != EMIFS_CS3_VAL) - EMIFS_CCS(3) = EMIFS_CS3_VAL; + l = omap_readl(EMIFS_CCS(3)); + if (l != EMIFS_CS3_VAL) + omap_writel(EMIFS_CS3_VAL, EMIFS_CCS(3)); osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys(); osk_flash_resource.end += SZ_32M - 1; diff --git a/drivers/mtd/maps/omap_nor.c b/drivers/mtd/maps/omap_nor.c index dca13a7..2e0a277 100644 --- a/drivers/mtd/maps/omap_nor.c +++ b/drivers/mtd/maps/omap_nor.c @@ -60,14 +60,21 @@ struct omapflash_info { static void omap_set_vpp(struct map_info *map, int enable) { static int count; + u32 l; if (cpu_class_is_omap1()) { if (enable) { - if (count++ == 0) - OMAP_EMIFS_CONFIG_REG |= OMAP_EMIFS_CONFIG_WP; + if (count++ == 0) { + l = omap_readl(EMIFS_CONFIG); + l |= OMAP_EMIFS_CONFIG_WP; + omap_writel(l, EMIFS_CONFIG); + } } else { - if (count && (--count == 0)) - OMAP_EMIFS_CONFIG_REG &= ~OMAP_EMIFS_CONFIG_WP; + if (count && (--count == 0)) { + l = omap_readl(EMIFS_CONFIG); + l &= ~OMAP_EMIFS_CONFIG_WP; + omap_writel(l, EMIFS_CONFIG); + } } } } diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c index a7d9e4b..569b746 100644 --- a/drivers/pcmcia/omap_cf.c +++ b/drivers/pcmcia/omap_cf.c @@ -279,9 +279,9 @@ static int __init omap_cf_probe(struct platform_device *pdev) * CF/PCMCIA variants... */ pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", driver_name, - seg, EMIFS_CCS(seg), EMIFS_ACS(seg)); - EMIFS_CCS(seg) = 0x0004a1b3; /* synch mode 4 etc */ - EMIFS_ACS(seg) = 0x00000000; /* OE hold/setup */ + seg, omap_readl(EMIFS_CCS(seg)), omap_readl(EMIFS_ACS(seg))); + omap_writel(0x0004a1b3, EMIFS_CCS(seg)); /* synch mode 4 etc */ + omap_writel(0x00000000, EMIFS_ACS(seg)); /* OE hold/setup */ /* CF uses armxor_ck, which is "always" available */ diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h index 8ded218..65a9c82 100644 --- a/include/asm-arm/arch-omap/tc.h +++ b/include/asm-arm/arch-omap/tc.h @@ -75,16 +75,14 @@ #ifndef __ASSEMBLER__ /* EMIF Slow Interface Configuration Register */ -#define OMAP_EMIFS_CONFIG_REG __REG32(EMIFS_CONFIG) - #define OMAP_EMIFS_CONFIG_FR (1 << 4) #define OMAP_EMIFS_CONFIG_PDE (1 << 3) #define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) #define OMAP_EMIFS_CONFIG_BM (1 << 1) #define OMAP_EMIFS_CONFIG_WP (1 << 0) -#define EMIFS_CCS(n) __REG32(EMIFS_CS0_CONFIG + (4 * (n))) -#define EMIFS_ACS(n) __REG32(EMIFS_ACS0 + (4 * (n))) +#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) +#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) /* Almost all documentation for chip and board memory maps assumes * BM is clear. Most devel boards have a switch to control booting @@ -93,13 +91,13 @@ */ static inline u32 omap_cs0_phys(void) { - return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) ? OMAP_CS3_PHYS : 0; } static inline u32 omap_cs3_phys(void) { - return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) ? 0 : OMAP_CS3_PHYS; } -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/14] musb_hdrc: Change __REG access to omap_read/write for multi-boot 2008-05-28 4:20 ` [PATCH 4/14] ARM: OMAP: Change __REG access to omap/read write for traffic controller Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 6/14] ARM: OMAP: Remove __REG access for multi-omap Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Change __REG access to omap_read/write for multi-boot Signed-off-by: Tony Lindgren <tony@atomide.com> --- drivers/usb/musb/omap2430.c | 48 ++++++++++++++++++++++++++++++------------ drivers/usb/musb/omap2430.h | 14 ++++++------ 2 files changed, 41 insertions(+), 21 deletions(-) diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index 36f1739..472c304 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -216,6 +216,7 @@ void musb_platform_set_mode(struct musb *musb, u8 musb_mode) int __init musb_platform_init(struct musb *musb) { struct otg_transceiver *xceiv = otg_get_transceiver(); + u32 l; #if defined(CONFIG_ARCH_OMAP2430) omap_cfg_reg(AE5_2430_USB0HS_STP); @@ -224,20 +225,25 @@ int __init musb_platform_init(struct musb *musb) musb->xceiv = *xceiv; musb_platform_resume(musb); - OTG_SYSCONFIG_REG &= ~ENABLEWAKEUP; /* disable wakeup */ - OTG_SYSCONFIG_REG &= ~NOSTDBY; /* remove possible nostdby */ - OTG_SYSCONFIG_REG |= SMARTSTDBY; /* enable smart standby */ - OTG_SYSCONFIG_REG &= ~AUTOIDLE; /* disable auto idle */ - OTG_SYSCONFIG_REG &= ~NOIDLE; /* remove possible noidle */ - OTG_SYSCONFIG_REG |= SMARTIDLE; /* enable smart idle */ - OTG_SYSCONFIG_REG |= AUTOIDLE; /* enable auto idle */ + l = omap_readl(OTG_SYSCONFIG); + l &= ~ENABLEWAKEUP; /* disable wakeup */ + l &= ~NOSTDBY; /* remove possible nostdby */ + l |= SMARTSTDBY; /* enable smart standby */ + l &= ~AUTOIDLE; /* disable auto idle */ + l &= ~NOIDLE; /* remove possible noidle */ + l |= SMARTIDLE; /* enable smart idle */ + l |= AUTOIDLE; /* enable auto idle */ + omap_writel(l, OTG_SYSCONFIG); - OTG_INTERFSEL_REG |= ULPI_12PIN; + l = omap_readl(OTG_INTERFSEL); + l |= ULPI_12PIN; + omap_writel(l, OTG_INTERFSEL); pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, " "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", - OTG_REVISION_REG, OTG_SYSCONFIG_REG, OTG_SYSSTATUS_REG, - OTG_INTERFSEL_REG, OTG_SIMENABLE_REG); + omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG), + omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL), + omap_readl(OTG_SIMENABLE)); omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1); @@ -254,12 +260,19 @@ int __init musb_platform_init(struct musb *musb) int musb_platform_suspend(struct musb *musb) { + u32 l; + if (!musb->clock) return 0; /* in any role */ - OTG_FORCESTDBY_REG |= ENABLEFORCE; /* enable MSTANDBY */ - OTG_SYSCONFIG_REG |= ENABLEWAKEUP; /* enable wakeup */ + l = omap_readl(OTG_FORCESTDBY); + l |= ENABLEFORCE; /* enable MSTANDBY */ + omap_writel(l, OTG_FORCESTDBY); + + l = omap_readl(OTG_SYSCONFIG); + l |= ENABLEWAKEUP; /* enable wakeup */ + omap_writel(l, OTG_SYSCONFIG); if (musb->xceiv.set_suspend) musb->xceiv.set_suspend(&musb->xceiv, 1); @@ -274,6 +287,8 @@ int musb_platform_suspend(struct musb *musb) int musb_platform_resume(struct musb *musb) { + u32 l; + if (!musb->clock) return 0; @@ -285,8 +300,13 @@ int musb_platform_resume(struct musb *musb) else clk_enable(musb->clock); - OTG_SYSCONFIG_REG &= ~ENABLEWAKEUP; /* disable wakeup */ - OTG_FORCESTDBY_REG &= ~ENABLEFORCE; /* disable MSTANDBY */ + l = omap_readl(OTG_SYSCONFIG); + l &= ~ENABLEWAKEUP; /* disable wakeup */ + omap_writel(l, OTG_SYSCONFIG); + + l = omap_readl(OTG_FORCESTDBY); + l &= ~ENABLEFORCE; /* disable MSTANDBY */ + omap_writel(l, OTG_FORCESTDBY); return 0; } diff --git a/drivers/usb/musb/omap2430.h b/drivers/usb/musb/omap2430.h index d036382..786a620 100644 --- a/drivers/usb/musb/omap2430.h +++ b/drivers/usb/musb/omap2430.h @@ -24,9 +24,9 @@ #elif defined(CONFIG_ARCH_OMAP3430) #define OMAP_HSOTG_BASE (OMAP34XX_HSUSB_OTG_BASE) #endif -#define OMAP_HSOTG(offset) __REG32(OMAP_HSOTG_BASE + 0x400 + (offset)) -#define OTG_REVISION_REG OMAP_HSOTG(0x0) -#define OTG_SYSCONFIG_REG OMAP_HSOTG(0x4) +#define OMAP_HSOTG(offset) (OMAP_HSOTG_BASE + 0x400 + (offset)) +#define OTG_REVISION OMAP_HSOTG(0x0) +#define OTG_SYSCONFIG OMAP_HSOTG(0x4) # define MIDLEMODE 12 /* bit position */ # define FORCESTDBY (0 << MIDLEMODE) # define NOSTDBY (1 << MIDLEMODE) @@ -38,17 +38,17 @@ # define ENABLEWAKEUP (1 << 2) # define SOFTRST (1 << 1) # define AUTOIDLE (1 << 0) -#define OTG_SYSSTATUS_REG OMAP_HSOTG(0x8) +#define OTG_SYSSTATUS OMAP_HSOTG(0x8) # define RESETDONE (1 << 0) -#define OTG_INTERFSEL_REG OMAP_HSOTG(0xc) +#define OTG_INTERFSEL OMAP_HSOTG(0xc) # define EXTCP (1 << 2) # define PHYSEL 0 /* bit position */ # define UTMI_8BIT (0 << PHYSEL) # define ULPI_12PIN (1 << PHYSEL) # define ULPI_8PIN (2 << PHYSEL) -#define OTG_SIMENABLE_REG OMAP_HSOTG(0x10) +#define OTG_SIMENABLE OMAP_HSOTG(0x10) # define TM1 (1 << 0) -#define OTG_FORCESTDBY_REG OMAP_HSOTG(0x14) +#define OTG_FORCESTDBY OMAP_HSOTG(0x14) # define ENABLEFORCE (1 << 0) #endif /* CONFIG_ARCH_OMAP2430 */ -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 6/14] ARM: OMAP: Remove __REG access for multi-omap 2008-05-28 4:20 ` [PATCH 5/14] musb_hdrc: Change __REG access to omap_read/write for multi-boot Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 7/14] ARM: OMAP: Split sleep24xx.S into sleep242x.S and sleep243x.S Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren This does not play nicely with multi-omap as it cannot be replaced by a function in io.c for omaps with different IO bases. Signed-off-by: Tony Lindgren <tony@atomide.com> --- include/asm-arm/arch-omap/io.h | 23 ----------------------- 1 files changed, 0 insertions(+), 23 deletions(-) diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index 160578e..e1fb7ec 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -183,35 +183,12 @@ #define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) #define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) -/* 16 bit uses LDRH/STRH, base +/- offset_8 */ -typedef struct { volatile u16 offset[256]; } __regbase16; -#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ - ->offset[((vaddr)&0xff)>>1] -#define __REG16(paddr) __REGV16(io_p2v(paddr)) - -/* 8/32 bit uses LDR/STR, base +/- offset_12 */ -typedef struct { volatile u8 offset[4096]; } __regbase8; -#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ - ->offset[((vaddr)&4095)>>0] -#define __REG8(paddr) __REGV8(io_p2v(paddr)) - -typedef struct { volatile u32 offset[4096]; } __regbase32; -#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ - ->offset[((vaddr)&4095)>>2] -#define __REG32(paddr) __REGV32(io_p2v(paddr)) - extern void omap1_map_common_io(void); extern void omap1_init_common_hw(void); extern void omap2_map_common_io(void); extern void omap2_init_common_hw(void); -#else - -#define __REG8(paddr) io_p2v(paddr) -#define __REG16(paddr) io_p2v(paddr) -#define __REG32(paddr) io_p2v(paddr) - #endif #endif -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 7/14] ARM: OMAP: Split sleep24xx.S into sleep242x.S and sleep243x.S 2008-05-28 4:20 ` [PATCH 6/14] ARM: OMAP: Remove __REG access for multi-omap Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 8/14] ARM: OMAP: Split sram24xx.S into sram242x.S and sram243x.S Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Split sleep24xx.S into sleep242x.S and sleep243x.S. This is easier to follow than rewriting the registers. Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/Makefile | 13 ++-- arch/arm/mach-omap2/pm24xx.c | 30 ++++----- arch/arm/mach-omap2/sleep242x.S | 131 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/sleep243x.S | 131 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/sleep24xx.S | 133 --------------------------------------- include/asm-arm/arch-omap/pm.h | 12 +++- 6 files changed, 289 insertions(+), 161 deletions(-) create mode 100644 arch/arm/mach-omap2/sleep242x.S create mode 100644 arch/arm/mach-omap2/sleep243x.S delete mode 100644 arch/arm/mach-omap2/sleep24xx.S diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b617b66..db82eb1 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -14,15 +14,14 @@ obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o # Power Management obj-$(CONFIG_PM) += pm.o -ifeq ($(CONFIG_ARCH_OMAP2),y) -obj-$(CONFIG_PM) += pm24xx.o sleep24xx.o +ifeq ($(CONFIG_PM),y) +obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o +obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o +obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o +obj-$(CONFIG_PM_DEBUG) += pm-debug.o endif -ifeq ($(CONFIG_ARCH_OMAP3),y) -obj-$(CONFIG_PM) += pm34xx.o sleep34xx.o -endif -obj-$(CONFIG_PM_DEBUG) += pm-debug.o - # Clock framework obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 787a95e..aab079e 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -52,10 +52,6 @@ #include "sdrc.h" #include "pm.h" -/* These addrs are in assembly language code to be patched at runtime */ -extern void *omap2_ocs_sdrc_power; -extern void *omap2_ocs_sdrc_dlla_ctrl; - static void (*omap2_sram_idle)(void); static void (*omap2_sram_suspend)(void __iomem *dllctrl); static void (*saved_idle)(void); @@ -495,19 +491,19 @@ int __init omap2_pm_init(void) * These routines need to be in SRAM as that's the only * memory the MPU can see when it wakes up. */ - omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend, - omap24xx_idle_loop_suspend_sz); - - omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, - omap24xx_cpu_suspend_sz); - - /* Patch in the correct register addresses for multiboot */ - omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power, - omap2_sram_suspend, - OMAP_SDRC_REGADDR(SDRC_POWER)); - omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl, - omap2_sram_suspend, - OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL)); + if (cpu_is_omap242x()) { + omap2_sram_idle = omap_sram_push(omap242x_idle_loop_suspend, + omap242x_idle_loop_suspend_sz); + + omap2_sram_suspend = omap_sram_push(omap242x_cpu_suspend, + omap242x_cpu_suspend_sz); + } else { + omap2_sram_idle = omap_sram_push(omap243x_idle_loop_suspend, + omap243x_idle_loop_suspend_sz); + + omap2_sram_suspend = omap_sram_push(omap243x_cpu_suspend, + omap243x_cpu_suspend_sz); + } suspend_set_ops(&omap_pm_ops); pm_idle = omap2_pm_idle; diff --git a/arch/arm/mach-omap2/sleep242x.S b/arch/arm/mach-omap2/sleep242x.S new file mode 100644 index 0000000..33bdd01 --- /dev/null +++ b/arch/arm/mach-omap2/sleep242x.S @@ -0,0 +1,131 @@ +/* + * linux/arch/arm/mach-omap2/sleep.S + * + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * (C) Copyright 2006 Nokia Corporation + * Fixed idle loop sleep + * Igor Stoppa <igor.stoppa@nokia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/arch/io.h> +#include <asm/arch/pm.h> + +#include <asm/arch/omap24xx.h> + +#include "sdrc.h" + +/* First address of reserved address space? apparently valid for OMAP2 & 3 */ +#define A_SDRC0_V (0xC0000000) + + .text + +/* + * Forces OMAP into idle state + * + * omap242x_idle_loop_suspend() - This bit of code just executes the WFI + * for normal idles. + * + * Note: This code get's copied to internal SRAM at boot. When the OMAP + * wakes up it continues execution at the point it went to sleep. + */ +ENTRY(omap242x_idle_loop_suspend) + stmfd sp!, {r0, lr} @ save registers on stack + mov r0, #0x0 @ clear for mrc call + mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt + ldmfd sp!, {r0, pc} @ restore regs and return + +ENTRY(omap242x_idle_loop_suspend_sz) + .word . - omap242x_idle_loop_suspend + +/* + * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing + * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore + * SDRC. + * + * Input: + * R0 : DLL ctrl value pre-Sleep + * + * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on + * when we get called, but the DLL probably isn't. We will wait a bit more in + * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even + * if in unlocked mode. + * + * For less than 242x-ES2.2 upon wake from a sleep mode where the external + * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz + * clock can pass into the PRCM can cause problems at DSP and IVA. + * To work around this the code will switch to the 32kHz source prior to sleep. + * Post sleep we will shift back to using the DPLL. Apparently, + * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait + * 3x12MHz + 3x32kHz clocks for a full switch. + * + * The DLL load value is not kept in RETENTION or OFF. It needs to be restored + * at wake + */ +ENTRY(omap242x_cpu_suspend) + stmfd sp!, {r0 - r12, lr} @ save registers on stack + mov r3, #0x0 @ clear for mrc call + mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished + nop + nop + ldr r3, omap2_ocs_sdrc_power @ addr of sdrc power + ldr r4, [r3] @ value of sdrc power + orr r4, r4, #0x40 @ enable self refresh on idle req + mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) + str r4, [r3] @ make it so + mov r2, #0 + nop + mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt + nop +loop: + subs r5, r5, #0x1 @ awake, wait just a bit + bne loop + + /* The DPLL has on before we take the DDR out of self refresh */ + bic r4, r4, #0x40 @ now clear self refresh bit. + str r4, [r3] @ put vlaue back. + ldr r4, A_SDRC0 @ make a clock happen + ldr r4, [r4] + nop @ start auto refresh only after clk ok + movs r0, r0 @ see if DDR or SDR + ldrne r1, omap2_ocs_sdrc_dlla_ctrl @ get addr of DLL ctrl + strne r0, [r1] @ rewrite DLLA to force DLL reload + addne r1, r1, #0x8 @ move to DLLB + strne r0, [r1] @ rewrite DLLB to force DLL reload + + mov r5, #0x1000 +loop2: + subs r5, r5, #0x1 + bne loop2 + /* resume*/ + ldmfd sp!, {r0 - r12, pc} @ restore regs and return + +omap2_ocs_sdrc_power: + .word OMAP242X_SDRC_REGADDR(SDRC_POWER) +A_SDRC0: + .word A_SDRC0_V +omap2_ocs_sdrc_dlla_ctrl: + .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) + +ENTRY(omap242x_cpu_suspend_sz) + .word . - omap242x_cpu_suspend + diff --git a/arch/arm/mach-omap2/sleep243x.S b/arch/arm/mach-omap2/sleep243x.S new file mode 100644 index 0000000..9a2b4b7 --- /dev/null +++ b/arch/arm/mach-omap2/sleep243x.S @@ -0,0 +1,131 @@ +/* + * linux/arch/arm/mach-omap2/sleep.S + * + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * (C) Copyright 2006 Nokia Corporation + * Fixed idle loop sleep + * Igor Stoppa <igor.stoppa@nokia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/arch/io.h> +#include <asm/arch/pm.h> + +#include <asm/arch/omap24xx.h> + +#include "sdrc.h" + +/* First address of reserved address space? apparently valid for OMAP2 & 3 */ +#define A_SDRC0_V (0xC0000000) + + .text + +/* + * Forces OMAP into idle state + * + * omap243x_idle_loop_suspend() - This bit of code just executes the WFI + * for normal idles. + * + * Note: This code get's copied to internal SRAM at boot. When the OMAP + * wakes up it continues execution at the point it went to sleep. + */ +ENTRY(omap243x_idle_loop_suspend) + stmfd sp!, {r0, lr} @ save registers on stack + mov r0, #0x0 @ clear for mrc call + mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt + ldmfd sp!, {r0, pc} @ restore regs and return + +ENTRY(omap243x_idle_loop_suspend_sz) + .word . - omap243x_idle_loop_suspend + +/* + * omap243x_cpu_suspend() - Forces OMAP into deep sleep state by completing + * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore + * SDRC. + * + * Input: + * R0 : DLL ctrl value pre-Sleep + * + * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on + * when we get called, but the DLL probably isn't. We will wait a bit more in + * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even + * if in unlocked mode. + * + * For less than 242x-ES2.2 upon wake from a sleep mode where the external + * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz + * clock can pass into the PRCM can cause problems at DSP and IVA. + * To work around this the code will switch to the 32kHz source prior to sleep. + * Post sleep we will shift back to using the DPLL. Apparently, + * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait + * 3x12MHz + 3x32kHz clocks for a full switch. + * + * The DLL load value is not kept in RETENTION or OFF. It needs to be restored + * at wake + */ +ENTRY(omap243x_cpu_suspend) + stmfd sp!, {r0 - r12, lr} @ save registers on stack + mov r3, #0x0 @ clear for mrc call + mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished + nop + nop + ldr r3, omap2_ocs_sdrc_power @ addr of sdrc power + ldr r4, [r3] @ value of sdrc power + orr r4, r4, #0x40 @ enable self refresh on idle req + mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) + str r4, [r3] @ make it so + mov r2, #0 + nop + mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt + nop +loop: + subs r5, r5, #0x1 @ awake, wait just a bit + bne loop + + /* The DPLL has on before we take the DDR out of self refresh */ + bic r4, r4, #0x40 @ now clear self refresh bit. + str r4, [r3] @ put vlaue back. + ldr r4, A_SDRC0 @ make a clock happen + ldr r4, [r4] + nop @ start auto refresh only after clk ok + movs r0, r0 @ see if DDR or SDR + ldrne r1, omap2_ocs_sdrc_dlla_ctrl @ get addr of DLL ctrl + strne r0, [r1] @ rewrite DLLA to force DLL reload + addne r1, r1, #0x8 @ move to DLLB + strne r0, [r1] @ rewrite DLLB to force DLL reload + + mov r5, #0x1000 +loop2: + subs r5, r5, #0x1 + bne loop2 + /* resume*/ + ldmfd sp!, {r0 - r12, pc} @ restore regs and return + +omap2_ocs_sdrc_power: + .word OMAP243X_SDRC_REGADDR(SDRC_POWER) +A_SDRC0: + .word A_SDRC0_V +omap2_ocs_sdrc_dlla_ctrl: + .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL) + +ENTRY(omap243x_cpu_suspend_sz) + .word . - omap243x_cpu_suspend + diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S deleted file mode 100644 index 3e0a7dc..0000000 --- a/arch/arm/mach-omap2/sleep24xx.S +++ /dev/null @@ -1,133 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/sleep.S - * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * (C) Copyright 2006 Nokia Corporation - * Fixed idle loop sleep - * Igor Stoppa <igor.stoppa@nokia.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <linux/linkage.h> -#include <linux/poison.h> /* for SRAM_VA_MAGIC */ -#include <asm/assembler.h> -#include <asm/arch/io.h> -#include <asm/arch/pm.h> - -#include <asm/arch/omap24xx.h> - -/* First address of reserved address space? apparently valid for OMAP2 & 3 */ -#define A_SDRC0_V (0xC0000000) - - .text - -/* - * Forces OMAP into idle state - * - * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI - * for normal idles. - * - * Note: This code get's copied to internal SRAM at boot. When the OMAP - * wakes up it continues execution at the point it went to sleep. - */ -ENTRY(omap24xx_idle_loop_suspend) - stmfd sp!, {r0, lr} @ save registers on stack - mov r0, #0x0 @ clear for mrc call - mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt - ldmfd sp!, {r0, pc} @ restore regs and return - -ENTRY(omap24xx_idle_loop_suspend_sz) - .word . - omap24xx_idle_loop_suspend - -/* - * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing - * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore - * SDRC. - * - * Input: - * R0 : DLL ctrl value pre-Sleep - * - * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on - * when we get called, but the DLL probably isn't. We will wait a bit more in - * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even - * if in unlocked mode. - * - * For less than 242x-ES2.2 upon wake from a sleep mode where the external - * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz - * clock can pass into the PRCM can cause problems at DSP and IVA. - * To work around this the code will switch to the 32kHz source prior to sleep. - * Post sleep we will shift back to using the DPLL. Apparently, - * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait - * 3x12MHz + 3x32kHz clocks for a full switch. - * - * The DLL load value is not kept in RETENTION or OFF. It needs to be restored - * at wake - */ -ENTRY(omap24xx_cpu_suspend) - stmfd sp!, {r0 - r12, lr} @ save registers on stack - mov r3, #0x0 @ clear for mrc call - mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished - nop - nop - ldr r3, omap2_ocs_sdrc_power @ addr of sdrc power - ldr r4, [r3] @ value of sdrc power - orr r4, r4, #0x40 @ enable self refresh on idle req - mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) - str r4, [r3] @ make it so - mov r2, #0 - nop - mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt - nop -loop: - subs r5, r5, #0x1 @ awake, wait just a bit - bne loop - - /* The DPLL has on before we take the DDR out of self refresh */ - bic r4, r4, #0x40 @ now clear self refresh bit. - str r4, [r3] @ put vlaue back. - ldr r4, A_SDRC0 @ make a clock happen - ldr r4, [r4] - nop @ start auto refresh only after clk ok - movs r0, r0 @ see if DDR or SDR - ldrne r1, omap2_ocs_sdrc_dlla_ctrl @ get addr of DLL ctrl - strne r0, [r1] @ rewrite DLLA to force DLL reload - addne r1, r1, #0x8 @ move to DLLB - strne r0, [r1] @ rewrite DLLB to force DLL reload - - mov r5, #0x1000 -loop2: - subs r5, r5, #0x1 - bne loop2 - /* resume*/ - ldmfd sp!, {r0 - r12, pc} @ restore regs and return - - .globl omap2_ocs_sdrc_power - .globl omap2_ocs_sdrc_dlla_ctrl - -omap2_ocs_sdrc_power: - .word SRAM_VA_MAGIC -A_SDRC0: - .word A_SDRC0_V -omap2_ocs_sdrc_dlla_ctrl: - .word SRAM_VA_MAGIC - -ENTRY(omap24xx_cpu_suspend_sz) - .word . - omap24xx_cpu_suspend - diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h index d0c7d4d..bafe109 100644 --- a/include/asm-arm/arch-omap/pm.h +++ b/include/asm-arm/arch-omap/pm.h @@ -145,22 +145,26 @@ static inline void omap2_allow_sleep(void) { } extern void omap730_cpu_suspend(unsigned short, unsigned short); extern void omap1510_cpu_suspend(unsigned short, unsigned short); extern void omap1610_cpu_suspend(unsigned short, unsigned short); -extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); +extern void omap242x_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); +extern void omap243x_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); extern void omap34xx_cpu_suspend(u32 *addr, int save_state); extern void omap730_idle_loop_suspend(void); extern void omap1510_idle_loop_suspend(void); extern void omap1610_idle_loop_suspend(void); -extern void omap24xx_idle_loop_suspend(void); +extern void omap242x_idle_loop_suspend(void); +extern void omap243x_idle_loop_suspend(void); extern unsigned int omap730_cpu_suspend_sz; extern unsigned int omap1510_cpu_suspend_sz; extern unsigned int omap1610_cpu_suspend_sz; -extern unsigned int omap24xx_cpu_suspend_sz; +extern unsigned int omap242x_cpu_suspend_sz; +extern unsigned int omap243x_cpu_suspend_sz; extern unsigned int omap34xx_cpu_suspend_sz; extern unsigned int omap730_idle_loop_suspend_sz; extern unsigned int omap1510_idle_loop_suspend_sz; extern unsigned int omap1610_idle_loop_suspend_sz; -extern unsigned int omap24xx_idle_loop_suspend_sz; +extern unsigned int omap242x_idle_loop_suspend_sz; +extern unsigned int omap243x_idle_loop_suspend_sz; extern unsigned int omap34xx_suspend_sz; #ifdef CONFIG_OMAP_SERIAL_WAKE -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 8/14] ARM: OMAP: Split sram24xx.S into sram242x.S and sram243x.S 2008-05-28 4:20 ` [PATCH 7/14] ARM: OMAP: Split sleep24xx.S into sleep242x.S and sleep243x.S Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 9/14] ARM: OMAP: Remove omap_sram_patch_va Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Split sram24xx.S into sram242x.S and sram243x.S Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/clock.c | 7 +- arch/arm/mach-omap2/pm24xx.c | 4 +- arch/arm/mach-omap2/prcm-common.h | 1 + arch/arm/mach-omap2/prm.h | 19 ++- arch/arm/mach-omap2/sram242x.S | 321 +++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/sram243x.S | 321 +++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/sram24xx.S | 337 ------------------------------------- arch/arm/plat-omap/sram.c | 121 ++++---------- include/asm-arm/arch-omap/sram.h | 25 ++- 10 files changed, 723 insertions(+), 436 deletions(-) create mode 100644 arch/arm/mach-omap2/sram242x.S create mode 100644 arch/arm/mach-omap2/sram243x.S delete mode 100644 arch/arm/mach-omap2/sram24xx.S diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index db82eb1..ad99039 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -8,7 +8,8 @@ obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ clockdomain.o # Functions loaded to SRAM -obj-$(CONFIG_ARCH_OMAP2) += sram24xx.o +obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o +obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o # Power Management diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 0742359..d53d81f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -652,7 +652,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) clk->rate = clk->parent->rate / new_div; if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { - __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); + prm_write_mod_reg(OMAP24XX_VALID_CONFIG, + OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); wmb(); } @@ -748,8 +749,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) wmb(); if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { - __raw_writel(OMAP24XX_VALID_CONFIG, - OMAP24XX_PRCM_CLKCFG_CTRL); + prm_write_mod_reg(OMAP24XX_VALID_CONFIG, + OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); wmb(); } diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index aab079e..10088e0 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -437,12 +437,12 @@ static void __init prcm_setup_regs(void) /* Configure automatic voltage transition */ __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP); - __raw_writel(OMAP24XX_AUTO_EXTVOLT | + prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | OMAP24XX_MEMRETCTRL | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), - OMAP24XX_PRCM_VOLTCTRL); + OMAP24XX_GR_MOD, OMAP24XX_PRCM_VOLTCTRL_OFFSET); /* Enable wake-up events */ prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1, diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 99a582d..4a32822 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -32,6 +32,7 @@ /* Chip-specific module offsets */ +#define OMAP24XX_GR_MOD OCP_MOD #define OMAP24XX_DSP_MOD 0x800 #define OMAP2430_MDM_MOD 0xc00 diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 27d44e2..478a8d2 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -38,18 +38,33 @@ * */ +/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */ +#define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050 +#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080 + +/* 242x GR_MOD registers, use these only for assembly code */ +#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_VOLTCTRL_OFFSET) +#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) + +/* 243x GR_MOD registers, use these only for assembly code */ +#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_VOLTCTRL_OFFSET) +#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) + +/* These will disappear */ #define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) #define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) #define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) #define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) -#define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050) #define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) #define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080) #define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) #define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) #define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S new file mode 100644 index 0000000..4c27451 --- /dev/null +++ b/arch/arm/mach-omap2/sram242x.S @@ -0,0 +1,321 @@ +/* + * linux/arch/arm/mach-omap2/sram242x.S + * + * Omap2 specific functions that need to be run in internal SRAM + * + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/arch/io.h> +#include <asm/hardware.h> + +#include "prm.h" +#include "cm.h" +#include "sdrc.h" + + .text + +ENTRY(omap242x_sram_ddr_init) + stmfd sp!, {r0 - r12, lr} @ save registers on stack + + mov r12, r2 @ capture CS1 vs CS0 + mov r8, r3 @ capture force parameter + + /* frequency shift down */ + ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg + mov r3, #0x1 @ value for 1x operation + str r3, [r2] @ go to L1-freq operation + + /* voltage shift down */ + mov r9, #0x1 @ set up for L1 voltage call + bl voltage_shift @ go drop voltage + + /* dll lock mode */ + ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl + ldr r10, [r11] @ get current val + cmp r12, #0x1 @ cs1 base (2422 es2.05/1) + addeq r11, r11, #0x8 @ if cs1 base, move to DLLB + mvn r9, #0x4 @ mask to get clear bit2 + and r10, r10, r9 @ clear bit2 for lock mode. + orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) + orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz + str r10, [r11] @ commit to DLLA_CTRL + bl i_dll_wait @ wait for dll to lock + + /* get dll value */ + add r11, r11, #0x4 @ get addr of status reg + ldr r10, [r11] @ get locked value + + /* voltage shift up */ + mov r9, #0x0 @ shift back to L0-voltage + bl voltage_shift @ go raise voltage + + /* frequency shift up */ + mov r3, #0x2 @ value for 2x operation + str r3, [r2] @ go to L0-freq operation + + /* reset entry mode for dllctrl */ + sub r11, r11, #0x4 @ move from status to ctrl + cmp r12, #0x1 @ normalize if cs1 based + subeq r11, r11, #0x8 @ possibly back to DLLA + cmp r8, #0x1 @ if forced unlock exit + orreq r1, r1, #0x4 @ make sure exit with unlocked value + str r1, [r11] @ restore DLLA_CTRL high value + add r11, r11, #0x8 @ move to DLLB_CTRL addr + str r1, [r11] @ set value DLLB_CTRL + bl i_dll_wait @ wait for possible lock + + /* set up for return, DDR should be good */ + str r10, [r0] @ write dll_status and return counter + ldmfd sp!, {r0 - r12, pc} @ restore regs and return + + /* ensure the DLL has relocked */ +i_dll_wait: + mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks +i_dll_delay: + subs r4, r4, #0x1 + bne i_dll_delay + mov pc, lr + + /* + * shift up or down voltage, use R9 as input to tell level. + * wait for it to finish, use 32k sync counter, 1tick=31uS. + */ +voltage_shift: + ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl. + ldr r5, [r4] @ get value. + ldr r6, prcm_mask_val @ get value of mask + and r5, r5, r6 @ apply mask to clear bits + orr r5, r5, r9 @ bulld value for L0/L1-volt operation. + str r5, [r4] @ set up for change. + mov r3, #0x4000 @ get val for force + orr r5, r5, r3 @ build value for force + str r5, [r4] @ Force transition to L1 + + ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter + ldr r5, [r3] @ get value + add r5, r5, #0x3 @ give it at most 93uS +volt_delay: + ldr r7, [r3] @ get timer value + cmp r5, r7 @ time up? + bhi volt_delay @ not yet->branch + mov pc, lr @ back to caller. + +omap242x_sdi_cm_clksel2_pll: + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) +omap242x_sdi_sdrc_dlla_ctrl: + .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) +omap242x_sdi_prcm_voltctrl: + .word OMAP242X_PRCM_VOLTCTRL +prcm_mask_val: + .word 0xFFFF3FFC +omap242x_sdi_timer_32ksynct_cr: + .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) +ENTRY(omap242x_sram_ddr_init_sz) + .word . - omap242x_sram_ddr_init + +/* + * Reprograms memory timings. + * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] + * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 + */ +ENTRY(omap242x_sram_reprogram_sdrc) + stmfd sp!, {r0 - r10, lr} @ save registers on stack + mov r3, #0x0 @ clear for mrc call + mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR + nop + nop + ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg + ldr r5, [r6] @ get value + mov r5, r5, lsr #8 @ isolate rfr field and drop burst + + cmp r0, #0x1 @ going to half speed? + movne r9, #0x0 @ if up set flag up for pre up, hi volt + + blne voltage_shift_c @ adjust voltage + + cmp r0, #0x1 @ going to half speed (post branch link) + moveq r5, r5, lsr #1 @ divide by 2 if to half + movne r5, r5, lsl #1 @ mult by 2 if to full + mov r5, r5, lsl #8 @ put rfr field back into place + add r5, r5, #0x1 @ turn on burst of 1 + ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg + ldr r3, [r4] @ get curr value + orr r3, r3, #0x3 + bic r3, r3, #0x3 @ clear lower bits + orr r3, r3, r0 @ new state value + str r3, [r4] @ set new state (pll/x, x=1 or 2) + nop + nop + + moveq r9, #0x1 @ if speed down, post down, drop volt + bleq voltage_shift_c + + mcr p15, 0, r3, c7, c10, 4 @ memory barrier + str r5, [r6] @ set new RFR_1 value + add r6, r6, #0x30 @ get RFR_2 addr + str r5, [r6] @ set RFR_2 + nop + cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL + bne freq_out @ leave if SDR, no DLL function + + /* With DDR, we need to take care of the DLL for the frequency change */ + ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl + str r1, [r2] @ write out new SDRC_DLLA_CTRL + add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL + str r1, [r2] @ commit to SDRC_DLLB_CTRL + mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks +dll_wait: + subs r1, r1, #0x1 + bne dll_wait +freq_out: + ldmfd sp!, {r0 - r10, pc} @ restore regs and return + + /* + * shift up or down voltage, use R9 as input to tell level. + * wait for it to finish, use 32k sync counter, 1tick=31uS. + */ +voltage_shift_c: + ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl + ldr r8, [r10] @ get value + ldr r7, ddr_prcm_mask_val @ get value of mask + and r8, r8, r7 @ apply mask to clear bits + orr r8, r8, r9 @ bulld value for L0/L1-volt operation. + str r8, [r10] @ set up for change. + mov r7, #0x4000 @ get val for force + orr r8, r8, r7 @ build value for force + str r8, [r10] @ Force transition to L1 + + ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter + ldr r8, [r10] @ get value + add r8, r8, #0x2 @ give it at most 62uS (min 31+) +volt_delay_c: + ldr r7, [r10] @ get timer value + cmp r8, r7 @ time up? + bhi volt_delay_c @ not yet->branch + mov pc, lr @ back to caller + +omap242x_srs_cm_clksel2_pll: + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) +omap242x_srs_sdrc_dlla_ctrl: + .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) +omap242x_srs_sdrc_rfr_ctrl: + .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) +omap242x_srs_prcm_voltctrl: + .word OMAP242X_PRCM_VOLTCTRL +ddr_prcm_mask_val: + .word 0xFFFF3FFC +omap242x_srs_timer_32ksynct: + .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) + +ENTRY(omap242x_sram_reprogram_sdrc_sz) + .word . - omap242x_sram_reprogram_sdrc + +/* + * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. + */ +ENTRY(omap242x_sram_set_prcm) + stmfd sp!, {r0-r12, lr} @ regs to stack + adr r4, pbegin @ addr of preload start + adr r8, pend @ addr of preload end + mcrr p15, 1, r8, r4, c12 @ preload into icache +pbegin: + /* move into fast relock bypass */ + ldr r8, omap242x_ssp_pll_ctl @ get addr + ldr r5, [r8] @ get val + mvn r6, #0x3 @ clear mask + and r5, r5, r6 @ clear field + orr r7, r5, #0x2 @ fast relock val + str r7, [r8] @ go to fast relock + ldr r4, omap242x_ssp_pll_stat @ addr of stat +block: + /* wait for bypass */ + ldr r8, [r4] @ stat value + and r8, r8, #0x3 @ mask for stat + cmp r8, #0x1 @ there yet + bne block @ loop if not + + /* set new dpll dividers _after_ in bypass */ + ldr r4, omap242x_ssp_pll_div @ get addr + str r0, [r4] @ set dpll ctrl val + + ldr r4, omap242x_ssp_set_config @ get addr + mov r8, #1 @ valid cfg msk + str r8, [r4] @ make dividers take + + mov r4, #100 @ dead spin a bit +wait_a_bit: + subs r4, r4, #1 @ dec loop + bne wait_a_bit @ delay done? + + /* check if staying in bypass */ + cmp r2, #0x1 @ stay in bypass? + beq pend @ jump over dpll relock + + /* relock DPLL with new vals */ + ldr r5, omap242x_ssp_pll_stat @ get addr + ldr r4, omap242x_ssp_pll_ctl @ get addr + orr r8, r7, #0x3 @ val for lock dpll + str r8, [r4] @ set val + mov r0, #1000 @ dead spin a bit +wait_more: + subs r0, r0, #1 @ dec loop + bne wait_more @ delay done? +wait_lock: + ldr r8, [r5] @ get lock val + and r8, r8, #3 @ isolate field + cmp r8, #2 @ locked? + bne wait_lock @ wait if not +pend: + /* update memory timings & briefly lock dll */ + ldr r4, omap242x_ssp_sdrc_rfr @ get addr + str r1, [r4] @ update refresh timing + ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl + ldr r10, [r11] @ get current val + mvn r9, #0x4 @ mask to get clear bit2 + and r10, r10, r9 @ clear bit2 for lock mode + orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) + str r10, [r11] @ commit to DLLA_CTRL + add r11, r11, #0x8 @ move to dllb + str r10, [r11] @ hit DLLB also + + mov r4, #0x800 @ relock time (min 0x400 L3 clocks) +wait_dll_lock: + subs r4, r4, #0x1 + bne wait_dll_lock + nop + ldmfd sp!, {r0-r12, pc} @ restore regs and return + +omap242x_ssp_set_config: + .word OMAP242X_PRCM_CLKCFG_CTRL +omap242x_ssp_pll_ctl: + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN) +omap242x_ssp_pll_stat: + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST) +omap242x_ssp_pll_div: + .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1) +omap242x_ssp_sdrc_rfr: + .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) +omap242x_ssp_dlla_ctrl: + .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) + +ENTRY(omap242x_sram_set_prcm_sz) + .word . - omap242x_sram_set_prcm diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S new file mode 100644 index 0000000..a3fa48d --- /dev/null +++ b/arch/arm/mach-omap2/sram243x.S @@ -0,0 +1,321 @@ +/* + * linux/arch/arm/mach-omap2/sram243x.S + * + * Omap2 specific functions that need to be run in internal SRAM + * + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/arch/io.h> +#include <asm/hardware.h> + +#include "prm.h" +#include "cm.h" +#include "sdrc.h" + + .text + +ENTRY(omap243x_sram_ddr_init) + stmfd sp!, {r0 - r12, lr} @ save registers on stack + + mov r12, r2 @ capture CS1 vs CS0 + mov r8, r3 @ capture force parameter + + /* frequency shift down */ + ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg + mov r3, #0x1 @ value for 1x operation + str r3, [r2] @ go to L1-freq operation + + /* voltage shift down */ + mov r9, #0x1 @ set up for L1 voltage call + bl voltage_shift @ go drop voltage + + /* dll lock mode */ + ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl + ldr r10, [r11] @ get current val + cmp r12, #0x1 @ cs1 base (2422 es2.05/1) + addeq r11, r11, #0x8 @ if cs1 base, move to DLLB + mvn r9, #0x4 @ mask to get clear bit2 + and r10, r10, r9 @ clear bit2 for lock mode. + orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) + orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz + str r10, [r11] @ commit to DLLA_CTRL + bl i_dll_wait @ wait for dll to lock + + /* get dll value */ + add r11, r11, #0x4 @ get addr of status reg + ldr r10, [r11] @ get locked value + + /* voltage shift up */ + mov r9, #0x0 @ shift back to L0-voltage + bl voltage_shift @ go raise voltage + + /* frequency shift up */ + mov r3, #0x2 @ value for 2x operation + str r3, [r2] @ go to L0-freq operation + + /* reset entry mode for dllctrl */ + sub r11, r11, #0x4 @ move from status to ctrl + cmp r12, #0x1 @ normalize if cs1 based + subeq r11, r11, #0x8 @ possibly back to DLLA + cmp r8, #0x1 @ if forced unlock exit + orreq r1, r1, #0x4 @ make sure exit with unlocked value + str r1, [r11] @ restore DLLA_CTRL high value + add r11, r11, #0x8 @ move to DLLB_CTRL addr + str r1, [r11] @ set value DLLB_CTRL + bl i_dll_wait @ wait for possible lock + + /* set up for return, DDR should be good */ + str r10, [r0] @ write dll_status and return counter + ldmfd sp!, {r0 - r12, pc} @ restore regs and return + + /* ensure the DLL has relocked */ +i_dll_wait: + mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks +i_dll_delay: + subs r4, r4, #0x1 + bne i_dll_delay + mov pc, lr + + /* + * shift up or down voltage, use R9 as input to tell level. + * wait for it to finish, use 32k sync counter, 1tick=31uS. + */ +voltage_shift: + ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl. + ldr r5, [r4] @ get value. + ldr r6, prcm_mask_val @ get value of mask + and r5, r5, r6 @ apply mask to clear bits + orr r5, r5, r9 @ bulld value for L0/L1-volt operation. + str r5, [r4] @ set up for change. + mov r3, #0x4000 @ get val for force + orr r5, r5, r3 @ build value for force + str r5, [r4] @ Force transition to L1 + + ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter + ldr r5, [r3] @ get value + add r5, r5, #0x3 @ give it at most 93uS +volt_delay: + ldr r7, [r3] @ get timer value + cmp r5, r7 @ time up? + bhi volt_delay @ not yet->branch + mov pc, lr @ back to caller. + +omap243x_sdi_cm_clksel2_pll: + .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2) +omap243x_sdi_sdrc_dlla_ctrl: + .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL) +omap243x_sdi_prcm_voltctrl: + .word OMAP243X_PRCM_VOLTCTRL +prcm_mask_val: + .word 0xFFFF3FFC +omap243x_sdi_timer_32ksynct_cr: + .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) +ENTRY(omap243x_sram_ddr_init_sz) + .word . - omap243x_sram_ddr_init + +/* + * Reprograms memory timings. + * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] + * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 + */ +ENTRY(omap243x_sram_reprogram_sdrc) + stmfd sp!, {r0 - r10, lr} @ save registers on stack + mov r3, #0x0 @ clear for mrc call + mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR + nop + nop + ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg + ldr r5, [r6] @ get value + mov r5, r5, lsr #8 @ isolate rfr field and drop burst + + cmp r0, #0x1 @ going to half speed? + movne r9, #0x0 @ if up set flag up for pre up, hi volt + + blne voltage_shift_c @ adjust voltage + + cmp r0, #0x1 @ going to half speed (post branch link) + moveq r5, r5, lsr #1 @ divide by 2 if to half + movne r5, r5, lsl #1 @ mult by 2 if to full + mov r5, r5, lsl #8 @ put rfr field back into place + add r5, r5, #0x1 @ turn on burst of 1 + ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg + ldr r3, [r4] @ get curr value + orr r3, r3, #0x3 + bic r3, r3, #0x3 @ clear lower bits + orr r3, r3, r0 @ new state value + str r3, [r4] @ set new state (pll/x, x=1 or 2) + nop + nop + + moveq r9, #0x1 @ if speed down, post down, drop volt + bleq voltage_shift_c + + mcr p15, 0, r3, c7, c10, 4 @ memory barrier + str r5, [r6] @ set new RFR_1 value + add r6, r6, #0x30 @ get RFR_2 addr + str r5, [r6] @ set RFR_2 + nop + cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL + bne freq_out @ leave if SDR, no DLL function + + /* With DDR, we need to take care of the DLL for the frequency change */ + ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl + str r1, [r2] @ write out new SDRC_DLLA_CTRL + add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL + str r1, [r2] @ commit to SDRC_DLLB_CTRL + mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks +dll_wait: + subs r1, r1, #0x1 + bne dll_wait +freq_out: + ldmfd sp!, {r0 - r10, pc} @ restore regs and return + + /* + * shift up or down voltage, use R9 as input to tell level. + * wait for it to finish, use 32k sync counter, 1tick=31uS. + */ +voltage_shift_c: + ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl + ldr r8, [r10] @ get value + ldr r7, ddr_prcm_mask_val @ get value of mask + and r8, r8, r7 @ apply mask to clear bits + orr r8, r8, r9 @ bulld value for L0/L1-volt operation. + str r8, [r10] @ set up for change. + mov r7, #0x4000 @ get val for force + orr r8, r8, r7 @ build value for force + str r8, [r10] @ Force transition to L1 + + ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter + ldr r8, [r10] @ get value + add r8, r8, #0x2 @ give it at most 62uS (min 31+) +volt_delay_c: + ldr r7, [r10] @ get timer value + cmp r8, r7 @ time up? + bhi volt_delay_c @ not yet->branch + mov pc, lr @ back to caller + +omap243x_srs_cm_clksel2_pll: + .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2) +omap243x_srs_sdrc_dlla_ctrl: + .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL) +omap243x_srs_sdrc_rfr_ctrl: + .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0) +omap243x_srs_prcm_voltctrl: + .word OMAP243X_PRCM_VOLTCTRL +ddr_prcm_mask_val: + .word 0xFFFF3FFC +omap243x_srs_timer_32ksynct: + .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) + +ENTRY(omap243x_sram_reprogram_sdrc_sz) + .word . - omap243x_sram_reprogram_sdrc + +/* + * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. + */ +ENTRY(omap243x_sram_set_prcm) + stmfd sp!, {r0-r12, lr} @ regs to stack + adr r4, pbegin @ addr of preload start + adr r8, pend @ addr of preload end + mcrr p15, 1, r8, r4, c12 @ preload into icache +pbegin: + /* move into fast relock bypass */ + ldr r8, omap243x_ssp_pll_ctl @ get addr + ldr r5, [r8] @ get val + mvn r6, #0x3 @ clear mask + and r5, r5, r6 @ clear field + orr r7, r5, #0x2 @ fast relock val + str r7, [r8] @ go to fast relock + ldr r4, omap243x_ssp_pll_stat @ addr of stat +block: + /* wait for bypass */ + ldr r8, [r4] @ stat value + and r8, r8, #0x3 @ mask for stat + cmp r8, #0x1 @ there yet + bne block @ loop if not + + /* set new dpll dividers _after_ in bypass */ + ldr r4, omap243x_ssp_pll_div @ get addr + str r0, [r4] @ set dpll ctrl val + + ldr r4, omap243x_ssp_set_config @ get addr + mov r8, #1 @ valid cfg msk + str r8, [r4] @ make dividers take + + mov r4, #100 @ dead spin a bit +wait_a_bit: + subs r4, r4, #1 @ dec loop + bne wait_a_bit @ delay done? + + /* check if staying in bypass */ + cmp r2, #0x1 @ stay in bypass? + beq pend @ jump over dpll relock + + /* relock DPLL with new vals */ + ldr r5, omap243x_ssp_pll_stat @ get addr + ldr r4, omap243x_ssp_pll_ctl @ get addr + orr r8, r7, #0x3 @ val for lock dpll + str r8, [r4] @ set val + mov r0, #1000 @ dead spin a bit +wait_more: + subs r0, r0, #1 @ dec loop + bne wait_more @ delay done? +wait_lock: + ldr r8, [r5] @ get lock val + and r8, r8, #3 @ isolate field + cmp r8, #2 @ locked? + bne wait_lock @ wait if not +pend: + /* update memory timings & briefly lock dll */ + ldr r4, omap243x_ssp_sdrc_rfr @ get addr + str r1, [r4] @ update refresh timing + ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl + ldr r10, [r11] @ get current val + mvn r9, #0x4 @ mask to get clear bit2 + and r10, r10, r9 @ clear bit2 for lock mode + orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) + str r10, [r11] @ commit to DLLA_CTRL + add r11, r11, #0x8 @ move to dllb + str r10, [r11] @ hit DLLB also + + mov r4, #0x800 @ relock time (min 0x400 L3 clocks) +wait_dll_lock: + subs r4, r4, #0x1 + bne wait_dll_lock + nop + ldmfd sp!, {r0-r12, pc} @ restore regs and return + +omap243x_ssp_set_config: + .word OMAP243X_PRCM_CLKCFG_CTRL +omap243x_ssp_pll_ctl: + .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN) +omap243x_ssp_pll_stat: + .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST) +omap243x_ssp_pll_div: + .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1) +omap243x_ssp_sdrc_rfr: + .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0) +omap243x_ssp_dlla_ctrl: + .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL) + +ENTRY(omap243x_sram_set_prcm_sz) + .word . - omap243x_sram_set_prcm diff --git a/arch/arm/mach-omap2/sram24xx.S b/arch/arm/mach-omap2/sram24xx.S deleted file mode 100644 index 5f1a305..0000000 --- a/arch/arm/mach-omap2/sram24xx.S +++ /dev/null @@ -1,337 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/sram-fn.S - * - * Omap2 specific functions that need to be run in internal SRAM - * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <asm/arch/io.h> -#include <asm/hardware.h> -#include <linux/poison.h> - - .text - -ENTRY(omap24xx_sram_ddr_init) - stmfd sp!, {r0 - r12, lr} @ save registers on stack - - mov r12, r2 @ capture CS1 vs CS0 - mov r8, r3 @ capture force parameter - - /* frequency shift down */ - ldr r2, omap24xx_sdi_cm_clksel2_pll @ get address of dpllout reg - mov r3, #0x1 @ value for 1x operation - str r3, [r2] @ go to L1-freq operation - - /* voltage shift down */ - mov r9, #0x1 @ set up for L1 voltage call - bl voltage_shift @ go drop voltage - - /* dll lock mode */ - ldr r11, omap24xx_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl - ldr r10, [r11] @ get current val - cmp r12, #0x1 @ cs1 base (2422 es2.05/1) - addeq r11, r11, #0x8 @ if cs1 base, move to DLLB - mvn r9, #0x4 @ mask to get clear bit2 - and r10, r10, r9 @ clear bit2 for lock mode. - orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) - orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz - str r10, [r11] @ commit to DLLA_CTRL - bl i_dll_wait @ wait for dll to lock - - /* get dll value */ - add r11, r11, #0x4 @ get addr of status reg - ldr r10, [r11] @ get locked value - - /* voltage shift up */ - mov r9, #0x0 @ shift back to L0-voltage - bl voltage_shift @ go raise voltage - - /* frequency shift up */ - mov r3, #0x2 @ value for 2x operation - str r3, [r2] @ go to L0-freq operation - - /* reset entry mode for dllctrl */ - sub r11, r11, #0x4 @ move from status to ctrl - cmp r12, #0x1 @ normalize if cs1 based - subeq r11, r11, #0x8 @ possibly back to DLLA - cmp r8, #0x1 @ if forced unlock exit - orreq r1, r1, #0x4 @ make sure exit with unlocked value - str r1, [r11] @ restore DLLA_CTRL high value - add r11, r11, #0x8 @ move to DLLB_CTRL addr - str r1, [r11] @ set value DLLB_CTRL - bl i_dll_wait @ wait for possible lock - - /* set up for return, DDR should be good */ - str r10, [r0] @ write dll_status and return counter - ldmfd sp!, {r0 - r12, pc} @ restore regs and return - - /* ensure the DLL has relocked */ -i_dll_wait: - mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks -i_dll_delay: - subs r4, r4, #0x1 - bne i_dll_delay - mov pc, lr - - /* - * shift up or down voltage, use R9 as input to tell level. - * wait for it to finish, use 32k sync counter, 1tick=31uS. - */ -voltage_shift: - ldr r4, omap24xx_sdi_prcm_voltctrl @ get addr of volt ctrl. - ldr r5, [r4] @ get value. - ldr r6, prcm_mask_val @ get value of mask - and r5, r5, r6 @ apply mask to clear bits - orr r5, r5, r9 @ bulld value for L0/L1-volt operation. - str r5, [r4] @ set up for change. - mov r3, #0x4000 @ get val for force - orr r5, r5, r3 @ build value for force - str r5, [r4] @ Force transition to L1 - - ldr r3, omap24xx_sdi_timer_32ksynct_cr @ get addr of counter - ldr r5, [r3] @ get value - add r5, r5, #0x3 @ give it at most 93uS -volt_delay: - ldr r7, [r3] @ get timer value - cmp r5, r7 @ time up? - bhi volt_delay @ not yet->branch - mov pc, lr @ back to caller. - -/* relative load constants */ - .globl omap24xx_sdi_cm_clksel2_pll - .globl omap24xx_sdi_sdrc_dlla_ctrl - .globl omap24xx_sdi_prcm_voltctrl - .globl omap24xx_sdi_timer_32ksynct_cr - -omap24xx_sdi_cm_clksel2_pll: - .word SRAM_VA_MAGIC -omap24xx_sdi_sdrc_dlla_ctrl: - .word SRAM_VA_MAGIC -omap24xx_sdi_prcm_voltctrl: - .word SRAM_VA_MAGIC -prcm_mask_val: - .word 0xFFFF3FFC -omap24xx_sdi_timer_32ksynct_cr: - .word SRAM_VA_MAGIC -ENTRY(omap24xx_sram_ddr_init_sz) - .word . - omap24xx_sram_ddr_init - -/* - * Reprograms memory timings. - * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] - * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 - */ -ENTRY(omap24xx_sram_reprogram_sdrc) - stmfd sp!, {r0 - r10, lr} @ save registers on stack - mov r3, #0x0 @ clear for mrc call - mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR - nop - nop - ldr r6, omap24xx_srs_sdrc_rfr_ctrl @ get addr of refresh reg - ldr r5, [r6] @ get value - mov r5, r5, lsr #8 @ isolate rfr field and drop burst - - cmp r0, #0x1 @ going to half speed? - movne r9, #0x0 @ if up set flag up for pre up, hi volt - - blne voltage_shift_c @ adjust voltage - - cmp r0, #0x1 @ going to half speed (post branch link) - moveq r5, r5, lsr #1 @ divide by 2 if to half - movne r5, r5, lsl #1 @ mult by 2 if to full - mov r5, r5, lsl #8 @ put rfr field back into place - add r5, r5, #0x1 @ turn on burst of 1 - ldr r4, omap24xx_srs_cm_clksel2_pll @ get address of out reg - ldr r3, [r4] @ get curr value - orr r3, r3, #0x3 - bic r3, r3, #0x3 @ clear lower bits - orr r3, r3, r0 @ new state value - str r3, [r4] @ set new state (pll/x, x=1 or 2) - nop - nop - - moveq r9, #0x1 @ if speed down, post down, drop volt - bleq voltage_shift_c - - mcr p15, 0, r3, c7, c10, 4 @ memory barrier - str r5, [r6] @ set new RFR_1 value - add r6, r6, #0x30 @ get RFR_2 addr - str r5, [r6] @ set RFR_2 - nop - cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL - bne freq_out @ leave if SDR, no DLL function - - /* With DDR, we need to take care of the DLL for the frequency change */ - ldr r2, omap24xx_srs_sdrc_dlla_ctrl @ addr of dlla ctrl - str r1, [r2] @ write out new SDRC_DLLA_CTRL - add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL - str r1, [r2] @ commit to SDRC_DLLB_CTRL - mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks -dll_wait: - subs r1, r1, #0x1 - bne dll_wait -freq_out: - ldmfd sp!, {r0 - r10, pc} @ restore regs and return - - /* - * shift up or down voltage, use R9 as input to tell level. - * wait for it to finish, use 32k sync counter, 1tick=31uS. - */ -voltage_shift_c: - ldr r10, omap24xx_srs_prcm_voltctrl @ get addr of volt ctrl - ldr r8, [r10] @ get value - ldr r7, ddr_prcm_mask_val @ get value of mask - and r8, r8, r7 @ apply mask to clear bits - orr r8, r8, r9 @ bulld value for L0/L1-volt operation. - str r8, [r10] @ set up for change. - mov r7, #0x4000 @ get val for force - orr r8, r8, r7 @ build value for force - str r8, [r10] @ Force transition to L1 - - ldr r10, omap24xx_srs_timer_32ksynct @ get addr of counter - ldr r8, [r10] @ get value - add r8, r8, #0x2 @ give it at most 62uS (min 31+) -volt_delay_c: - ldr r7, [r10] @ get timer value - cmp r8, r7 @ time up? - bhi volt_delay_c @ not yet->branch - mov pc, lr @ back to caller - - .globl omap24xx_srs_cm_clksel2_pll - .globl omap24xx_srs_sdrc_dlla_ctrl - .globl omap24xx_srs_sdrc_rfr_ctrl - .globl omap24xx_srs_prcm_voltctrl - .globl omap24xx_srs_timer_32ksynct - -omap24xx_srs_cm_clksel2_pll: - .word SRAM_VA_MAGIC -omap24xx_srs_sdrc_dlla_ctrl: - .word SRAM_VA_MAGIC -omap24xx_srs_sdrc_rfr_ctrl: - .word SRAM_VA_MAGIC -omap24xx_srs_prcm_voltctrl: - .word SRAM_VA_MAGIC -ddr_prcm_mask_val: - .word 0xFFFF3FFC -omap24xx_srs_timer_32ksynct: - .word SRAM_VA_MAGIC - -ENTRY(omap24xx_sram_reprogram_sdrc_sz) - .word . - omap24xx_sram_reprogram_sdrc - -/* - * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. - */ -ENTRY(omap24xx_sram_set_prcm) - stmfd sp!, {r0-r12, lr} @ regs to stack - adr r4, pbegin @ addr of preload start - adr r8, pend @ addr of preload end - mcrr p15, 1, r8, r4, c12 @ preload into icache -pbegin: - /* move into fast relock bypass */ - ldr r8, omap24xx_ssp_pll_ctl @ get addr - ldr r5, [r8] @ get val - mvn r6, #0x3 @ clear mask - and r5, r5, r6 @ clear field - orr r7, r5, #0x2 @ fast relock val - str r7, [r8] @ go to fast relock - ldr r4, omap24xx_ssp_pll_stat @ addr of stat -block: - /* wait for bypass */ - ldr r8, [r4] @ stat value - and r8, r8, #0x3 @ mask for stat - cmp r8, #0x1 @ there yet - bne block @ loop if not - - /* set new dpll dividers _after_ in bypass */ - ldr r4, omap24xx_ssp_pll_div @ get addr - str r0, [r4] @ set dpll ctrl val - - ldr r4, omap24xx_ssp_set_config @ get addr - mov r8, #1 @ valid cfg msk - str r8, [r4] @ make dividers take - - mov r4, #100 @ dead spin a bit -wait_a_bit: - subs r4, r4, #1 @ dec loop - bne wait_a_bit @ delay done? - - /* check if staying in bypass */ - cmp r2, #0x1 @ stay in bypass? - beq pend @ jump over dpll relock - - /* relock DPLL with new vals */ - ldr r5, omap24xx_ssp_pll_stat @ get addr - ldr r4, omap24xx_ssp_pll_ctl @ get addr - orr r8, r7, #0x3 @ val for lock dpll - str r8, [r4] @ set val - mov r0, #1000 @ dead spin a bit -wait_more: - subs r0, r0, #1 @ dec loop - bne wait_more @ delay done? -wait_lock: - ldr r8, [r5] @ get lock val - and r8, r8, #3 @ isolate field - cmp r8, #2 @ locked? - bne wait_lock @ wait if not -pend: - /* update memory timings & briefly lock dll */ - ldr r4, omap24xx_ssp_sdrc_rfr @ get addr - str r1, [r4] @ update refresh timing - ldr r11, omap24xx_ssp_dlla_ctrl @ get addr of DLLA ctrl - ldr r10, [r11] @ get current val - mvn r9, #0x4 @ mask to get clear bit2 - and r10, r10, r9 @ clear bit2 for lock mode - orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) - str r10, [r11] @ commit to DLLA_CTRL - add r11, r11, #0x8 @ move to dllb - str r10, [r11] @ hit DLLB also - - mov r4, #0x800 @ relock time (min 0x400 L3 clocks) -wait_dll_lock: - subs r4, r4, #0x1 - bne wait_dll_lock - nop - ldmfd sp!, {r0-r12, pc} @ restore regs and return - - .globl omap24xx_ssp_set_config - .globl omap24xx_ssp_pll_ctl - .globl omap24xx_ssp_pll_stat - .globl omap24xx_ssp_pll_div - .globl omap24xx_ssp_sdrc_rfr - .globl omap24xx_ssp_dlla_ctrl - -omap24xx_ssp_set_config: - .word SRAM_VA_MAGIC -omap24xx_ssp_pll_ctl: - .word SRAM_VA_MAGIC -omap24xx_ssp_pll_stat: - .word SRAM_VA_MAGIC -omap24xx_ssp_pll_div: - .word SRAM_VA_MAGIC -omap24xx_ssp_sdrc_rfr: - .word SRAM_VA_MAGIC -omap24xx_ssp_dlla_ctrl: - .word SRAM_VA_MAGIC - -ENTRY(omap24xx_sram_set_prcm_sz) - .word . - omap24xx_sram_set_prcm diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index fb3f0d1..388ecfc 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -76,24 +76,6 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, unsigned long pstart_avail, unsigned long size_avail); -/* Global symbols in sram-fn.S to be patched with omap_sram_patch_va() */ -extern void *omap24xx_sdi_cm_clksel2_pll; -extern void *omap24xx_sdi_sdrc_dlla_ctrl; -extern void *omap24xx_sdi_prcm_voltctrl; -extern void *omap24xx_sdi_timer_32ksynct_cr; -extern void *omap24xx_srs_cm_clksel2_pll; -extern void *omap24xx_srs_sdrc_dlla_ctrl; -extern void *omap24xx_srs_sdrc_rfr_ctrl; -extern void *omap24xx_srs_prcm_voltctrl; -extern void *omap24xx_srs_timer_32ksynct; -extern void *omap24xx_ssp_set_config; -extern void *omap24xx_ssp_pll_ctl; -extern void *omap24xx_ssp_pll_stat; -extern void *omap24xx_ssp_pll_div; -extern void *omap24xx_ssp_sdrc_rfr; -extern void *omap24xx_ssp_dlla_ctrl; - - /* * Depending on the target RAMFS firewall setup, the public usable amount of * SRAM varies. The default accessible size for all device types is 2k. A GP @@ -386,76 +368,43 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) } #endif -#ifdef CONFIG_ARCH_OMAP2 -int __init omap24xx_sram_init(void) +#ifdef CONFIG_ARCH_OMAP2420 +int __init omap242x_sram_init(void) +{ + _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, + omap242x_sram_ddr_init_sz); + + _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc, + omap242x_sram_reprogram_sdrc_sz); + + _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm, + omap242x_sram_set_prcm_sz); + + return 0; +} +#else +static inline int omap242x_sram_init(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +int __init omap243x_sram_init(void) { - _omap2_sram_ddr_init = omap_sram_push(omap24xx_sram_ddr_init, - omap24xx_sram_ddr_init_sz); - - /* Patch in the correct register addresses for multiboot */ - omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_cm_clksel2_pll, - _omap2_sram_ddr_init, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2)); - omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_sdrc_dlla_ctrl, - _omap2_sram_ddr_init, - OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL)); - omap_sram_patch_va(omap24xx_sram_ddr_init, &omap24xx_sdi_prcm_voltctrl, - _omap2_sram_ddr_init, OMAP24XX_PRCM_VOLTCTRL); - omap_sram_patch_va(omap24xx_sram_ddr_init, - &omap24xx_sdi_timer_32ksynct_cr, - _omap2_sram_ddr_init, - (void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)); - - _omap2_sram_reprogram_sdrc = omap_sram_push(omap24xx_sram_reprogram_sdrc, - omap24xx_sram_reprogram_sdrc_sz); - - omap_sram_patch_va(omap24xx_sram_reprogram_sdrc, - &omap24xx_srs_cm_clksel2_pll, - _omap2_sram_reprogram_sdrc, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2)); - omap_sram_patch_va(omap24xx_sram_reprogram_sdrc, - &omap24xx_srs_sdrc_dlla_ctrl, - _omap2_sram_reprogram_sdrc, - OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL)); - omap_sram_patch_va(omap24xx_sram_reprogram_sdrc, - &omap24xx_srs_sdrc_rfr_ctrl, - _omap2_sram_reprogram_sdrc, - OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0)); - omap_sram_patch_va(omap24xx_sram_reprogram_sdrc, - &omap24xx_srs_prcm_voltctrl, - _omap2_sram_reprogram_sdrc, - OMAP24XX_PRCM_VOLTCTRL); - omap_sram_patch_va(omap24xx_sram_reprogram_sdrc, - &omap24xx_srs_timer_32ksynct, - _omap2_sram_reprogram_sdrc, - (void __iomem *)IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)); - - _omap2_set_prcm = omap_sram_push(omap24xx_sram_set_prcm, - omap24xx_sram_set_prcm_sz); - - omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_set_config, - _omap2_set_prcm, - OMAP24XX_PRCM_CLKCFG_CTRL); - omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_ctl, - _omap2_set_prcm, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)); - omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_stat, - _omap2_set_prcm, - OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST)); - omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_pll_div, - _omap2_set_prcm, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1)); - omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_sdrc_rfr, - _omap2_set_prcm, - OMAP_SDRC_REGADDR(SDRC_RFR_CTRL_0)); - omap_sram_patch_va(omap24xx_sram_set_prcm, &omap24xx_ssp_dlla_ctrl, - _omap2_set_prcm, - OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL)); + _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, + omap243x_sram_ddr_init_sz); + + _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc, + omap243x_sram_reprogram_sdrc_sz); + + _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm, + omap243x_sram_set_prcm_sz); return 0; } #else -static inline int omap24xx_sram_init(void) +static inline int omap243x_sram_init(void) { return 0; } @@ -529,8 +478,10 @@ int __init omap_sram_init(void) if (!(cpu_class_is_omap2())) omap1_sram_init(); - else if (cpu_is_omap24xx()) - omap24xx_sram_init(); + else if (cpu_is_omap242x()) + omap242x_sram_init(); + else if (cpu_is_omap2430()) + omap243x_sram_init(); else if (cpu_is_omap34xx()) omap34xx_sram_init(); diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h index 830e0fa..866b864 100644 --- a/include/asm-arm/arch-omap/sram.h +++ b/include/asm-arm/arch-omap/sram.h @@ -31,17 +31,30 @@ extern unsigned long omap1_sram_reprogram_clock_sz; extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl); extern unsigned long omap24xx_sram_reprogram_clock_sz; -extern void omap24xx_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, +extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, u32 base_cs, u32 force_unlock); -extern unsigned long omap24xx_sram_ddr_init_sz; +extern unsigned long omap242x_sram_ddr_init_sz; -extern u32 omap24xx_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, +extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); -extern unsigned long omap24xx_sram_set_prcm_sz; +extern unsigned long omap242x_sram_set_prcm_sz; -extern void omap24xx_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, +extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type); -extern unsigned long omap24xx_sram_reprogram_sdrc_sz; +extern unsigned long omap242x_sram_reprogram_sdrc_sz; + + +extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, + u32 base_cs, u32 force_unlock); +extern unsigned long omap243x_sram_ddr_init_sz; + +extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, + int bypass); +extern unsigned long omap243x_sram_set_prcm_sz; + +extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, + u32 mem_type); +extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern void omap34xx_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 9/14] ARM: OMAP: Remove omap_sram_patch_va 2008-05-28 4:20 ` [PATCH 8/14] ARM: OMAP: Split sram24xx.S into sram242x.S and sram243x.S Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 10/14] ARM: OMAP: Introduce omap_globals and prcm access functions for multi-omap Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren This is no longer needed as the 24xx *.S files have been split into 242x and 243x specific files. Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/plat-omap/Kconfig | 10 ------ arch/arm/plat-omap/sram.c | 60 -------------------------------------- include/asm-arm/arch-omap/sram.h | 3 -- include/linux/poison.h | 6 ---- 4 files changed, 0 insertions(+), 79 deletions(-) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index ba858a8..b085b07 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -32,16 +32,6 @@ config OMAP_DEBUG_LEDS depends on OMAP_DEBUG_DEVICES default y if LEDS || LEDS_OMAP_DEBUG -config OMAP_DEBUG_SRAM_PATCH - bool "Extra sanity checking for SRAM patch code" - depends on ARCH_OMAP - default y - help - Say Y here if you want the kernel to use extra caution - in patching SRAM virtual addresses. If you are - confident in your SRAM code, disabling this will save - about 600 bytes. - config OMAP_DEBUG_POWERDOMAIN bool "Emit debug messages from powerdomain layer" depends on ARCH_OMAP2 || ARCH_OMAP3 diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 388ecfc..554ee58 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -241,66 +241,6 @@ void * omap_sram_push(void * start, unsigned long size) return (void *)omap_sram_ceil; } -/** - * omap_sram_patch_va - patch a virtual address into SRAM code - * @srcfn: original start address (in DRAM) of function to patch - * @srcd: original address (in DRAM) of location to patch - * @sramfn: start address (in SRAM) of function to patch - * @d: virtual address to insert - * - * Replace a location in SRAM containing a magic number - * (SRAM_VA_MAGIC) with a caller-specified virtual address. Used to - * dynamically patch SRAM code at runtime for multiboot, since some - * register addresses change depending on the OMAP chip in use. - * Returns 1 upon success, 0 upon failure. - */ -int omap_sram_patch_va(void *srcfn, void *srcd, void *sramfn, void __iomem *d) -{ - unsigned long sram_addr; - long offs; - - offs = (unsigned long)srcd - (unsigned long)srcfn; - sram_addr = (unsigned long)sramfn + offs; - -#ifdef CONFIG_OMAP_DEBUG_SRAM_PATCH - if (offs < 0) { - printk(KERN_ERR "sram: patch address 0x%0lx < function start " - "address 0x%0lx\n", (unsigned long)srcd, - (unsigned long)srcfn); - WARN_ON(1); - return 0; - } - - /* - * REVISIT: We should probably pass in the function's size also, - * so we can verify that the address to patch exists within - * the function - */ - if (sram_addr > omap_sram_base + omap_sram_size || - sram_addr < omap_sram_base + SRAM_BOOTLOADER_SZ) { - printk(KERN_ERR "sram: invalid patch address 0x%0lx\n", - sram_addr); - WARN_ON(1); - return 0; - } - - if (*(typeof(SRAM_VA_MAGIC) *)sram_addr != SRAM_VA_MAGIC) { - printk(KERN_ERR "sram: will not patch address 0x%0lx: " - "no magic\n", sram_addr); - WARN_ON(1); - return 0; - } -#endif /* CONFIG_OMAP_DEBUG_SRAM_PATCH */ - - pr_debug("sram: patching 0x%0lx with 0x%0lx\n", sram_addr, - (unsigned long)d); - - *(unsigned long *)sram_addr = (unsigned long)d; - - return 1; -} - - static void omap_sram_error(void) { panic("Uninitialized SRAM function\n"); diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h index 866b864..6c577f7 100644 --- a/include/asm-arm/arch-omap/sram.h +++ b/include/asm-arm/arch-omap/sram.h @@ -11,11 +11,8 @@ #ifndef __ARCH_ARM_OMAP_SRAM_H #define __ARCH_ARM_OMAP_SRAM_H -#include <linux/poison.h> /* for SRAM_VA_MAGIC */ - extern int __init omap_sram_init(void); extern void * omap_sram_push(void * start, unsigned long size); -extern int omap_sram_patch_va(void *srcfn, void *srcd, void *sramfn, void __iomem *d); extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, diff --git a/include/linux/poison.h b/include/linux/poison.h index 03620da..9f31683 100644 --- a/include/linux/poison.h +++ b/include/linux/poison.h @@ -68,10 +68,4 @@ /********** sound/oss/ **********/ #define OSS_POISON_FREE 0xAB -/* - * Used in arch/arm/plat-omap/sram.h to mark SRAM addresses that - * will be patched at runtime - */ -#define SRAM_VA_MAGIC 0xbadfeed1 - #endif -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 10/14] ARM: OMAP: Introduce omap_globals and prcm access functions for multi-omap 2008-05-28 4:20 ` [PATCH 9/14] ARM: OMAP: Remove omap_sram_patch_va Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 11/14] ARM: OMAP: Remove OMAP_PRM_REGADDR Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren New struct omap_globals contains the omap processor specific module bases. Use omap_globals to set the various base addresses before to make detecting omap chip type simpler. Also introduce OMAP2_IO_ADDRESS for future multi-omap patches. Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/cm.h | 12 +------ arch/arm/mach-omap2/control.c | 12 +++--- arch/arm/mach-omap2/memory.c | 11 +++++- arch/arm/mach-omap2/mux.c | 2 +- arch/arm/mach-omap2/prcm.c | 51 ++++++++++++++++++++++++++++++ arch/arm/mach-omap2/prm.h | 14 +------- arch/arm/mach-omap2/sdrc.h | 10 ++--- arch/arm/plat-omap/common.c | 59 +++++++++++++++++++++++++++++----- include/asm-arm/arch-omap/common.h | 15 +++++++++ include/asm-arm/arch-omap/control.h | 4 +-- include/asm-arm/arch-omap/io.h | 3 ++ 11 files changed, 144 insertions(+), 49 deletions(-) diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index c8e3692..1d5afee 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -114,17 +114,9 @@ static __inline__ u32 __attribute__((unused)) cm_rmw_reg_bits(u32 mask, /* Clock management domain register get/set */ #ifndef __ASSEMBLER__ -static __inline__ void __attribute__((unused)) cm_write_mod_reg(u32 val, - s16 module, s16 idx) -{ - __raw_writel(val, OMAP_CM_REGADDR(module, idx)); -} -static __inline__ u32 __attribute__((unused)) cm_read_mod_reg(s16 module, - s16 idx) -{ - return __raw_readl(OMAP_CM_REGADDR(module, idx)); -} +extern u32 cm_read_mod_reg(s16 module, u16 idx); +extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); /* Read-modify-write bits in a CM register (by domain) */ static __inline__ u32 __attribute__((unused)) cm_rmw_mod_reg_bits(u32 mask, diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 400114b..19a5f30 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -15,19 +15,19 @@ #include <linux/kernel.h> #include <linux/io.h> +#include <asm/arch/common.h> #include <asm/arch/control.h> -static u32 omap2_ctrl_base; +static void __iomem *omap2_ctrl_base; -#define OMAP_CTRL_REGADDR(reg) \ - (__force void __iomem *)IO_ADDRESS(omap2_ctrl_base + (reg)) +#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) -void omap_ctrl_base_set(u32 base) +void __init omap2_set_globals_control(struct omap_globals *omap2_globals) { - omap2_ctrl_base = base; + omap2_ctrl_base = omap2_globals->ctrl; } -u32 omap_ctrl_base_get(void) +void __iomem *omap_ctrl_base_get(void) { return omap2_ctrl_base; } diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 1247908..73cadb2 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -24,6 +24,7 @@ #include <asm/io.h> +#include <asm/arch/common.h> #include <asm/arch/clock.h> #include <asm/arch/sram.h> @@ -32,8 +33,8 @@ #include "memory.h" #include "sdrc.h" -unsigned long omap2_sdrc_base; -unsigned long omap2_sms_base; +void __iomem *omap2_sdrc_base; +void __iomem *omap2_sms_base; static struct memory_timings mem_timings; static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; @@ -154,6 +155,12 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); } +void __init omap2_set_globals_memory(struct omap_globals *omap2_globals) +{ + omap2_sdrc_base = omap2_globals->sdrc; + omap2_sms_base = omap2_globals->sms; +} + /* turn on smart idle modes for SDRAM scheduler and controller */ void __init omap2_init_memory(void) { diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 7d56516..6919d52 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -381,7 +381,7 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r warn = (orig != reg); if (debug || warn) printk(KERN_WARNING - "MUX: setup %s (0x%08x): 0x%04x -> 0x%04x\n", + "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n", cfg->name, omap_ctrl_base_get() + cfg->mux_reg, orig, reg); } diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 0d2a99a..6d88f1c 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -18,12 +18,16 @@ #include <linux/clk.h> #include <linux/io.h> +#include <asm/arch/common.h> #include <asm/arch/prcm.h> #include "clock.h" #include "prm.h" #include "prm-regbits-24xx.h" +static void __iomem *prm_base; +static void __iomem *cm_base; + u32 omap_prcm_get_reset_sources(void) { /* XXX This presumably needs modification for 34XX */ @@ -46,3 +50,50 @@ void omap_prcm_arch_reset(char mode) prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); } + +static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) +{ + BUG_ON(!base); + return __raw_readl(base + module + reg); +} + +static inline void __omap_prcm_write(u32 value, void __iomem *base, + s16 module, u16 reg) +{ + BUG_ON(!base); + __raw_writel(value, base + module + reg); +} + +/* Read a register in a PRM module */ +u32 prm_read_mod_reg(s16 module, u16 idx) +{ + return __omap_prcm_read(prm_base, module, idx); +} +EXPORT_SYMBOL(prm_read_mod_reg); + +/* Write into a register in a PRM module */ +void prm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + __omap_prcm_write(val, prm_base, module, idx); +} +EXPORT_SYMBOL(prm_write_mod_reg); + +/* Read a register in a CM module */ +u32 cm_read_mod_reg(s16 module, u16 idx) +{ + return __omap_prcm_read(cm_base, module, idx); +} +EXPORT_SYMBOL(cm_read_mod_reg); + +/* Write into a register in a CM module */ +void cm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + __omap_prcm_write(val, cm_base, module, idx); +} +EXPORT_SYMBOL(cm_write_mod_reg); + +void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) +{ + prm_base = omap2_globals->prm; + cm_base = omap2_globals->cm; +} diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 478a8d2..5eed16d 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -201,18 +201,8 @@ static u32 __attribute__((unused)) prm_clear_mod_reg_bits(u32 bits, s16 module, } /* Power/reset management domain register get/set */ - -static __inline__ void __attribute__((unused)) prm_write_mod_reg(u32 val, - s16 module, s16 idx) -{ - __raw_writel(val, OMAP_PRM_REGADDR(module, idx)); -} - -static __inline__ u32 __attribute__((unused)) prm_read_mod_reg(s16 module, - s16 idx) -{ - return __raw_readl(OMAP_PRM_REGADDR(module, idx)); -} +extern u32 prm_read_mod_reg(s16 module, u16 idx); +extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); #endif diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index ce3be73..eff3bd9 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h @@ -18,13 +18,11 @@ #include <asm/arch/sdrc.h> #ifndef __ASSEMBLER__ -extern unsigned long omap2_sdrc_base; -extern unsigned long omap2_sms_base; +extern void __iomem *omap2_sdrc_base; +extern void __iomem *omap2_sms_base; -#define OMAP_SDRC_REGADDR(reg) \ - (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg)) -#define OMAP_SMS_REGADDR(reg) \ - (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg)) +#define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg)) +#define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg)) /* SDRC global register get/set */ diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index fd6f329..dfe9c46 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -26,6 +26,7 @@ #include <asm/io.h> #include <asm/setup.h> +#include <asm/arch/common.h> #include <asm/arch/board.h> #include <asm/arch/control.h> #include <asm/arch/mux.h> @@ -261,30 +262,70 @@ arch_initcall(omap_init_clocksource_32k); /* Global address base setup code */ +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + +static struct omap_globals *omap2_globals; + +static void __init __omap2_set_globals(void) +{ + omap2_set_globals_memory(omap2_globals); + omap2_set_globals_control(omap2_globals); + omap2_set_globals_prcm(omap2_globals); +} + +#endif + #if defined(CONFIG_ARCH_OMAP2420) + +static struct omap_globals omap242x_globals = { + .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000), + .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE), + .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE), + .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE), + .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE), + .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE), +}; + void __init omap2_set_globals_242x(void) { - omap2_sdrc_base = OMAP2420_SDRC_BASE; - omap2_sms_base = OMAP2420_SMS_BASE; - omap_ctrl_base_set(OMAP2420_CTRL_BASE); + omap2_globals = &omap242x_globals; + __omap2_set_globals(); } #endif #if defined(CONFIG_ARCH_OMAP2430) + +static struct omap_globals omap243x_globals = { + .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000), + .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE), + .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE), + .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE), + .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE), + .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE), +}; + void __init omap2_set_globals_243x(void) { - omap2_sdrc_base = OMAP243X_SDRC_BASE; - omap2_sms_base = OMAP243X_SMS_BASE; - omap_ctrl_base_set(OMAP243X_CTRL_BASE); + omap2_globals = &omap243x_globals; + __omap2_set_globals(); } #endif #if defined(CONFIG_ARCH_OMAP3430) + +static struct omap_globals omap343x_globals = { + .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000), + .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE), + .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE), + .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE), + .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE), + .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE), +}; + void __init omap2_set_globals_343x(void) { - omap2_sdrc_base = OMAP343X_SDRC_BASE; - omap2_sms_base = OMAP343X_SMS_BASE; - omap_ctrl_base_set(OMAP343X_CTRL_BASE); + omap2_globals = &omap343x_globals; + __omap2_set_globals(); } #endif diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h index 6c072de..e015e94 100644 --- a/include/asm-arm/arch-omap/common.h +++ b/include/asm-arm/arch-omap/common.h @@ -48,8 +48,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, } #endif +/* IO bases for various OMAP processors */ +struct omap_globals { + void __iomem *tap; /* Control module ID code */ + void __iomem *sdrc; /* SDRAM Controller */ + void __iomem *sms; /* SDRAM Memory Scheduler */ + void __iomem *ctrl; /* System Control Module */ + void __iomem *prm; /* Power and Reset Management */ + void __iomem *cm; /* Clock Management */ +}; + void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_343x(void); +/* These get called from omap2_set_globals_xxxx(), do not call these */ +void omap2_set_globals_memory(struct omap_globals *); +void omap2_set_globals_control(struct omap_globals *); +void omap2_set_globals_prcm(struct omap_globals *); + #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h index 1d95cc2..0fc0b60 100644 --- a/include/asm-arm/arch-omap/control.h +++ b/include/asm-arm/arch-omap/control.h @@ -173,8 +173,7 @@ #ifndef __ASSEMBLY__ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -extern void omap_ctrl_base_set(u32 base); -extern u32 omap_ctrl_base_get(void); +extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); @@ -182,7 +181,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); #else -#define omap_ctrl_base_set(x) WARN_ON(1) #define omap_ctrl_base_get() 0 #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index e1fb7ec..0b13557 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -60,6 +60,7 @@ #define IO_SIZE 0x40000 #define IO_VIRT (IO_PHYS - IO_OFFSET) #define IO_ADDRESS(pa) ((pa) - IO_OFFSET) +#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET) #define io_p2v(pa) ((pa) - IO_OFFSET) #define io_v2p(va) ((va) + IO_OFFSET) @@ -91,6 +92,7 @@ #define IO_OFFSET 0x90000000 #define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ +#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ #define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ #define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ @@ -148,6 +150,7 @@ #define IO_OFFSET 0x90000000 #define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ +#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ #define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ #define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 11/14] ARM: OMAP: Remove OMAP_PRM_REGADDR 2008-05-28 4:20 ` [PATCH 10/14] ARM: OMAP: Introduce omap_globals and prcm access functions for multi-omap Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 12/14] ARM: OMAP: Remove OMAP_CM_REGADDR for multi-boot Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Remove OMAP_PRM_REGADDR. Use prm_read/write_mod_reg() instead. For assembly, use OMAPXXXX_PRM_REGADDR macros. Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/clock24xx.c | 55 +++++++++- arch/arm/mach-omap2/clock24xx.h | 27 +++--- arch/arm/mach-omap2/clock34xx.h | 2 +- arch/arm/mach-omap2/memory.c | 3 +- arch/arm/mach-omap2/pm24xx.c | 21 +++-- arch/arm/mach-omap2/prcm.c | 14 +++ arch/arm/mach-omap2/prm.h | 192 +++++++++++++++++++----------------- arch/arm/plat-omap/common.c | 1 + include/asm-arm/arch-omap/clock.h | 3 +- include/asm-arm/arch-omap/common.h | 5 + 10 files changed, 206 insertions(+), 117 deletions(-) diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index efe4436..84a0d10 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -28,6 +28,7 @@ #include <linux/io.h> #include <linux/cpufreq.h> +#include <asm/arch/common.h> #include <asm/arch/clock.h> #include <asm/arch/sram.h> #include <asm/div64.h> @@ -77,16 +78,16 @@ static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) static int omap2_enable_osc_ck(struct clk *clk) { - prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0, - OMAP24XX_PRCM_CLKSRC_CTRL); + prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0, + OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET); return 0; } static void omap2_disable_osc_ck(struct clk *clk) { - prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK, - OMAP24XX_PRCM_CLKSRC_CTRL); + prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK, + OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET); } /* Enable an APLL if off */ @@ -443,7 +444,8 @@ static u32 omap2_get_sysclkdiv(void) { u32 div; - div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); + div = prm_read_mod_reg(OMAP24XX_GR_MOD, + OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET); div &= OMAP_SYSCLKDIV_MASK; div >>= OMAP_SYSCLKDIV_SHIFT; @@ -499,6 +501,37 @@ static int __init omap2_clk_arch_init(void) } arch_initcall(omap2_clk_arch_init); +static u32 prm_base; +static u32 cm_base; + +/* + * Since we share clock data for 242x and 243x, we need to rewrite some + * some register base offsets. Assume offset is at prm_base if flagged, + * else assume it's cm_base. + */ +static inline void omap2_clk_check_reg(u32 flags, void __iomem **reg) +{ + u32 tmp = (__force u32)*reg; + + if ((tmp >> 24) != 0) + return; + + if (flags & OFFSET_GR_MOD) + tmp += prm_base; + else + tmp += cm_base; + + *reg = (__force void __iomem *)tmp; +} + +void __init omap2_clk_rewrite_base(struct clk *clk) +{ + omap2_clk_check_reg(clk->flags, &clk->clksel_reg); + omap2_clk_check_reg(clk->flags, &clk->enable_reg); + if (clk->dpll_data) + omap2_clk_check_reg(0, &clk->dpll_data->mult_div1_reg); +} + int __init omap2_clk_init(void) { struct prcm_config *prcm; @@ -510,6 +543,12 @@ int __init omap2_clk_init(void) else if (cpu_is_omap2430()) cpu_mask = RATE_IN_243X; + for (clkp = onchip_24xx_clks; + clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); + clkp++) { + omap2_clk_rewrite_base(*clkp); + } + clk_init(&omap2_clk_functions); omap2_osc_clk_recalc(&osc_ck); @@ -561,3 +600,9 @@ int __init omap2_clk_init(void) return 0; } + +void __init omap2_set_globals_clock24xx(struct omap_globals *omap2_globals) +{ + prm_base = (__force u32)omap2_globals->prm; + cm_base = (__force u32)omap2_globals->cm; +} diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index c439be8..c9f3fcf 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -600,6 +600,8 @@ static struct prcm_config rate_table[] = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, }; +#define _GR_MOD_OFFSET(reg) ((void __iomem*)(OMAP24XX_GR_MOD + (reg))) + /*------------------------------------------------------------------------- * 24xx clock tree. * @@ -877,11 +879,11 @@ static struct clk sys_clkout_src = { .name = "sys_clkout_src", .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES, - .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, + RATE_PROPAGATES | OFFSET_GR_MOD, + .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, + .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, .clksel = common_clkout_src_clksel, .recalc = &omap2_clksel_recalc, @@ -907,8 +909,8 @@ static struct clk sys_clkout = { .name = "sys_clkout", .parent = &sys_clkout_src, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - PARENT_CONTROLS_CLOCK, - .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, + PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD, + .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, .clksel = sys_clkout_clksel, .recalc = &omap2_clksel_recalc, @@ -920,11 +922,11 @@ static struct clk sys_clkout = { static struct clk sys_clkout2_src = { .name = "sys_clkout2_src", .parent = &func_54m_ck, - .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, - .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, + .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD, + .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, + .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, .clksel = common_clkout_src_clksel, .recalc = &omap2_clksel_recalc, @@ -941,8 +943,9 @@ static const struct clksel sys_clkout2_clksel[] = { static struct clk sys_clkout2 = { .name = "sys_clkout2", .parent = &sys_clkout2_src, - .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, - .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, + .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK | + OFFSET_GR_MOD, + .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, .recalc = &omap2_clksel_recalc, @@ -953,8 +956,8 @@ static struct clk sys_clkout2 = { static struct clk emul_ck = { .name = "emul_ck", .parent = &func_54m_ck, - .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, + .flags = CLOCK_IN_OMAP242X | OFFSET_GR_MOD, + .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET), .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, .recalc = &followparent_recalc, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 284c796..4cc9142 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -2219,7 +2219,7 @@ static struct clk usbhost_sar_fck = { .name = "usbhost_sar_fck", .parent = &osc_sys_ck, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), + .enable_reg = OMAP34XX_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "usbhost_clkdm", diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 73cadb2..2ad29fd 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -94,7 +94,8 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force) m_type = omap2_memory_get_type(); local_irq_save(flags); - __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); + prm_write_mod_reg(0xffff, OMAP24XX_GR_MOD, + OMAP24XX_PRCM_VOLTSETUP_OFFSET); omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); curr_perf_level = level; local_irq_restore(flags); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 10088e0..3e34f13 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -134,14 +134,16 @@ no_sleep: prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); /* MPU domain wake events */ - l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU); + l = prm_read_mod_reg(OCP_MOD, OMAP24XX_PRCM_IRQSTATUS_MPU_OFFSET); if (l & 0x01) - __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU); + prm_write_mod_reg(0x01, OCP_MOD, + OMAP24XX_PRCM_IRQSTATUS_MPU_OFFSET); if (l & 0x20) - __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU); + prm_write_mod_reg(0x20, OCP_MOD, + OMAP24XX_PRCM_IRQSTATUS_MPU_OFFSET); /* Mask future PRCM-to-MPU interrupts */ - __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU); + prm_write_mod_reg(0x0, OCP_MOD, OMAP24XX_PRCM_IRQSTATUS_MPU_OFFSET); } static int omap2_i2c_active(void) @@ -327,7 +329,8 @@ static void __init prcm_setup_regs(void) u32 l; /* Enable autoidle */ - __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG); + prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, + OMAP24XX_PRCM_SYSCONFIG_OFFSET); /* Set all domain wakeup dependencies */ prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP); @@ -433,10 +436,12 @@ static void __init prcm_setup_regs(void) /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk * stabilisation */ - __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP); + prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, + OMAP24XX_PRCM_CLKSSETUP_OFFSET); /* Configure automatic voltage transition */ - __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP); + prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, + OMAP24XX_PRCM_VOLTSETUP_OFFSET); prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | OMAP24XX_MEMRETCTRL | @@ -454,7 +459,7 @@ int __init omap2_pm_init(void) u32 l; printk(KERN_INFO "Power Management for OMAP2 initializing\n"); - l = __raw_readl(OMAP24XX_PRCM_REVISION); + l = prm_read_mod_reg(OCP_MOD, OMAP24XX_PRCM_REVISION_OFFSET); printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); osc_ck = clk_get(NULL, "osc_ck"); diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 6d88f1c..ad17933 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -78,6 +78,20 @@ void prm_write_mod_reg(u32 val, s16 module, u16 idx) } EXPORT_SYMBOL(prm_write_mod_reg); +/* Read-modify-write a register in a PRM module. Caller must lock */ +u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +{ + u32 v; + + v = prm_read_mod_reg(module, idx); + v &= ~mask; + v |= bits; + prm_write_mod_reg(v, module, idx); + + return v; +} +EXPORT_SYMBOL(prm_rmw_mod_reg_bits); + /* Read a register in a CM module */ u32 cm_read_mod_reg(s16 module, u16 idx) { diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 5eed16d..f255579 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -16,21 +16,16 @@ #include "prcm-common.h" -#ifndef __ASSEMBLER__ -#define OMAP_PRM_REGADDR(module, reg) \ - (__force void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) -#else #define OMAP2420_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) #define OMAP2430_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) #define OMAP34XX_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) -#endif /* * Architecture-specific global PRM registers - * Use __raw_{read,write}l() with these registers. + * Use prm_{read,write}_mod_reg() with these registers. * * With a few exceptions, these are the register names beginning with * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the @@ -38,9 +33,67 @@ * */ -/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */ +/* 24xx register offsets in OCP_MOD */ +#define OMAP24XX_PRCM_REVISION_OFFSET 0x0000 +#define OMAP24XX_PRCM_SYSCONFIG_OFFSET 0x0010 +#define OMAP24XX_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 +#define OMAP24XX_PRCM_IRQENABLE_MPU_OFFSET 0x001c + +/* 24xx register offsets in OMAP24XX_GR_MOD (Same as OCP_MOD for 24xx) */ #define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050 +#define OMAP24XX_PRCM_VOLTST_OFFSET 0x0054 +#define OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET 0x0060 +#define OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 #define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080 +#define OMAP24XX_PRCM_CLKCFG_STATUS_OFFSET 0x0084 +#define OMAP24XX_PRCM_VOLTSETUP_OFFSET 0x0090 +#define OMAP24XX_PRCM_CLKSSETUP_OFFSET 0x0094 +#define OMAP24XX_PRCM_POLCTRL_OFFSET 0x0098 + +/* 34xx register offsets in OCP_MOD */ +#define OMAP3430_PRM_REVISION_OFFSET 0x0004 +#define OMAP3430_PRM_SYSCONFIG_OFFSET 0x0014 +#define OMAP3430_PRM_IRQSTATUS_MPU_OFFSET 0x0018 +#define OMAP3430_PRM_IRQENABLE_MPU_OFFSET 0x001c + +/* 34xx register offsets in GR_MOD */ +#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 +#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 +#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 +#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c +#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 +#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 +#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 +#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c +#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 +#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 +#define OMAP3_PRM_RSTST_OFFSET 0x0058 +#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 +#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 +#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 +#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 +#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 +#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 +#define OMAP3_PRM_POLCTRL_OFFSET 0x009c +#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 +#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 +#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 +#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 +#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc +#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 +#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 +#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 +#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 +#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 +#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc +#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 +#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 + +/* 34xx register offsets in CCR_MOD */ +#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 +#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 + /* 242x GR_MOD registers, use these only for assembly code */ #define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ @@ -55,79 +108,45 @@ OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) /* These will disappear */ -#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098) - -#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004) -#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014) - -#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) -#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) -#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) -#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) -#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) -#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) -#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) -#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) -#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) -#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) -#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) -#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) -#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) -#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) -#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) -#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) -#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) -#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) -#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) -#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) -#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) -#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) -#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) -#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) -#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) -#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) -#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) -#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) -#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) -#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) -#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) - -#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) -#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) - -#ifndef __ASSEMBLER__ - -/* Read-modify-write bits in a PRM register */ -static __inline__ u32 __attribute__((unused)) prm_rmw_reg_bits(u32 mask, - u32 bits, void __iomem *va) -{ - u32 v; - - v = __raw_readl(va); - v &= ~mask; - v |= bits; - __raw_writel(v, va); - - return v; -} -#endif +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) + +/* 34xx GR_MOD registers, use these only for assembly code */ +#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) +#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) +#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) +#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) +#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) +#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) +#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) +#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) +#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) +#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) +#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) +#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) +#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) +#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) +#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) +#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) +#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) +#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) +#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) +#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) +#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) +#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) + +#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) +#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) /* * Module specific PRM registers from PRM_BASE + domain offset @@ -183,13 +202,12 @@ static __inline__ u32 __attribute__((unused)) prm_rmw_reg_bits(u32 mask, #ifndef __ASSEMBLER__ -/* Read-modify-write bits in a PRM register (by domain) */ -static u32 __attribute__((unused)) prm_rmw_mod_reg_bits(u32 mask, u32 bits, - s16 module, s16 idx) -{ - return prm_rmw_reg_bits(mask, bits, OMAP_PRM_REGADDR(module, idx)); -} +/* Power/reset management domain register get/set */ +extern u32 prm_read_mod_reg(s16 module, u16 idx); +extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +/* Read-modify-write bits in a PRM register (by domain) */ static u32 __attribute__((unused)) prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) { return prm_rmw_mod_reg_bits(bits, bits, module, idx); @@ -200,10 +218,6 @@ static u32 __attribute__((unused)) prm_clear_mod_reg_bits(u32 bits, s16 module, return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } -/* Power/reset management domain register get/set */ -extern u32 prm_read_mod_reg(s16 module, u16 idx); -extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); - #endif /* diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index dfe9c46..8a718ff 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -271,6 +271,7 @@ static void __init __omap2_set_globals(void) omap2_set_globals_memory(omap2_globals); omap2_set_globals_control(omap2_globals); omap2_set_globals_prcm(omap2_globals); + omap2_set_globals_clock24xx(omap2_globals); } #endif diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 0e28247..bfaf7b6 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -139,7 +139,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ -/* bits 13-20 are currently free */ +#define OFFSET_GR_MOD (1 << 13) /* 24xx GR_MOD reg as offset */ +/* bits 14-20 are currently free */ #define CLOCK_IN_OMAP310 (1 << 21) #define CLOCK_IN_OMAP730 (1 << 22) #define CLOCK_IN_OMAP1510 (1 << 23) diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h index e015e94..e4cce2e 100644 --- a/include/asm-arm/arch-omap/common.h +++ b/include/asm-arm/arch-omap/common.h @@ -66,5 +66,10 @@ void omap2_set_globals_343x(void); void omap2_set_globals_memory(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); +#ifdef CONFIG_ARCH_OMAP24XX +void omap2_set_globals_clock24xx(struct omap_globals *); +#else +#define omap2_set_globals_clock24xx(x) do { } while (0) +#endif #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 12/14] ARM: OMAP: Remove OMAP_CM_REGADDR for multi-boot 2008-05-28 4:20 ` [PATCH 11/14] ARM: OMAP: Remove OMAP_PRM_REGADDR Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 13/14] ARM: OMAP: Change to use CM offsets for clocks for multi-omap Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Please use OMAP2420_CM_REGADDR, OMAP2430_CM_REGADDR or OMAP34XX_CM_REGADDR instead. Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/clock.c | 5 +- arch/arm/mach-omap2/clock34xx.h | 409 ++++++++++++++++++++------------------- arch/arm/mach-omap2/cm.h | 15 +- 3 files changed, 217 insertions(+), 212 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index d53d81f..963c259 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -28,6 +28,7 @@ #include <asm/arch/clockdomain.h> #include <asm/arch/sram.h> #include <asm/arch/cpu.h> +#include <asm/arch/prcm.h> #include <asm/div64.h> #include "memory.h" @@ -245,8 +246,8 @@ static void omap2_clk_wait_ready(struct clk *clk) /* REVISIT: What are the appropriate exclusions for 34XX? */ /* OMAP3: ignore DSS-mod clocks */ if (cpu_is_omap34xx() && - ((reg & ~0xff) == (__force u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) || - (((reg & ~0xff) == (__force u32)OMAP_CM_REGADDR(CORE_MOD, 0)) && + ((reg & ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) || + (((reg & ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) && clk->enable_bit == OMAP3430_EN_SSI_SHIFT))) return; diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 4cc9142..ebd664e 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -257,23 +257,26 @@ static const struct clksel_rate div16_dpll_rates[] = { { .div = 0 } }; +#define _OMAP34XX_CM_REGADDR(module, reg) \ + ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg)))) + /* DPLL1 */ /* MPU clock source */ /* Type: DPLL */ static struct dpll_data dpll1_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .mult_div1_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), + .control_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), + .autoidle_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + .idlest_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, .max_multiplier = OMAP3_MAX_DPLL_MULT, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -316,7 +319,7 @@ static struct clk dpll1_x2m2_ck = { .name = "dpll1_x2m2_ck", .parent = &dpll1_x2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), + .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll1_x2m2_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -329,20 +332,20 @@ static struct clk dpll1_x2m2_ck = { /* Type: DPLL */ static struct dpll_data dpll2_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .mult_div1_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), + .control_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | (1 << DPLL_LOW_POWER_BYPASS), .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), + .autoidle_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), + .idlest_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, .max_multiplier = OMAP3_MAX_DPLL_MULT, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -374,7 +377,7 @@ static struct clk dpll2_m2_ck = { .name = "dpll2_m2_ck", .parent = &dpll2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll2_m2x2_clksel, @@ -389,16 +392,16 @@ static struct clk dpll2_m2_ck = { * REVISIT: Also supports fast relock bypass - not included below */ static struct dpll_data dpll3_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_div1_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .control_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), + .autoidle_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -475,7 +478,7 @@ static struct clk dpll3_m2_ck = { .name = "dpll3_m2_ck", .parent = &dpll3_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, .clksel = div31_dpll3m2_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -492,7 +495,7 @@ static const struct clksel core_ck_clksel[] = { static struct clk core_ck = { .name = "core_ck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = core_ck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -509,7 +512,7 @@ static const struct clksel dpll3_m2x2_ck_clksel[] = { static struct clk dpll3_m2x2_ck = { .name = "dpll3_m2x2_ck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = dpll3_m2x2_ck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -528,7 +531,7 @@ static struct clk dpll3_m3_ck = { .name = "dpll3_m3_ck", .parent = &dpll3_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, .clksel = div16_dpll3_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -540,7 +543,7 @@ static struct clk dpll3_m3_ck = { static struct clk dpll3_m3x2_ck = { .name = "dpll3_m3x2_ck", .parent = &dpll3_m3_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, .recalc = &omap3_clkoutx2_recalc, @@ -556,7 +559,7 @@ static struct clk emu_core_alwon_ck = { .name = "emu_core_alwon_ck", .parent = &dpll3_m3x2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = emu_core_alwon_ck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -568,19 +571,19 @@ static struct clk emu_core_alwon_ck = { /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ /* Type: DPLL */ static struct dpll_data dpll4_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), + .mult_div1_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2), .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .control_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), + .autoidle_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .idlest_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, .max_multiplier = OMAP3_MAX_DPLL_MULT, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -622,7 +625,7 @@ static struct clk dpll4_m2_ck = { .name = "dpll4_m2_ck", .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3430_DIV_96M_MASK, .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -634,7 +637,7 @@ static struct clk dpll4_m2_ck = { static struct clk dpll4_m2x2_ck = { .name = "dpll4_m2x2_ck", .parent = &dpll4_m2_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_96M_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, .recalc = &omap3_clkoutx2_recalc, @@ -650,7 +653,7 @@ static struct clk omap_96m_alwon_fck = { .name = "omap_96m_alwon_fck", .parent = &dpll4_m2x2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = omap_96m_alwon_fck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -676,7 +679,7 @@ static struct clk cm_96m_fck = { .name = "cm_96m_fck", .parent = &dpll4_m2x2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = cm_96m_fck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -689,7 +692,7 @@ static struct clk dpll4_m3_ck = { .name = "dpll4_m3_ck", .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_TV_MASK, .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -702,7 +705,7 @@ static struct clk dpll4_m3x2_ck = { .name = "dpll4_m3x2_ck", .parent = &dpll4_m3_ck, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_TV_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, .recalc = &omap3_clkoutx2_recalc, @@ -718,7 +721,7 @@ static struct clk virt_omap_54m_fck = { .name = "virt_omap_54m_fck", .parent = &dpll4_m3x2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = virt_omap_54m_fck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -745,7 +748,7 @@ static const struct clksel omap_54m_clksel[] = { static struct clk omap_54m_fck = { .name = "omap_54m_fck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_54M, .clksel = omap_54m_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -772,7 +775,7 @@ static const struct clksel omap_48m_clksel[] = { static struct clk omap_48m_fck = { .name = "omap_48m_fck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_48M, .clksel = omap_48m_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -794,7 +797,7 @@ static struct clk dpll4_m4_ck = { .name = "dpll4_m4_ck", .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -806,7 +809,7 @@ static struct clk dpll4_m4_ck = { static struct clk dpll4_m4x2_ck = { .name = "dpll4_m4x2_ck", .parent = &dpll4_m4_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, .recalc = &omap3_clkoutx2_recalc, @@ -817,7 +820,7 @@ static struct clk dpll4_m5_ck = { .name = "dpll4_m5_ck", .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -829,7 +832,7 @@ static struct clk dpll4_m5_ck = { static struct clk dpll4_m5x2_ck = { .name = "dpll4_m5x2_ck", .parent = &dpll4_m5_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, .recalc = &omap3_clkoutx2_recalc, @@ -840,7 +843,7 @@ static struct clk dpll4_m6_ck = { .name = "dpll4_m6_ck", .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL4_MASK, .clksel = div16_dpll4_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -853,7 +856,7 @@ static struct clk dpll4_m6x2_ck = { .name = "dpll4_m6x2_ck", .parent = &dpll4_m6_ck, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, .recalc = &omap3_clkoutx2_recalc, @@ -872,19 +875,19 @@ static struct clk emu_per_alwon_ck = { /* Type: DPLL */ /* 3430ES2 only */ static struct dpll_data dpll5_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), + .mult_div1_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), + .control_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), + .autoidle_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), + .idlest_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2), .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, .max_multiplier = OMAP3_MAX_DPLL_MULT, .max_divider = OMAP3_MAX_DPLL_DIV, @@ -912,7 +915,7 @@ static struct clk dpll5_m2_ck = { .name = "dpll5_m2_ck", .parent = &dpll5_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), .clksel_mask = OMAP3430ES2_DIV_120M_MASK, .clksel = div16_dpll5_clksel, .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | @@ -930,7 +933,7 @@ static struct clk omap_120m_fck = { .name = "omap_120m_fck", .parent = &dpll5_m2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2), .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, .clksel = omap_120m_fck_clksel, .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | @@ -971,9 +974,9 @@ static const struct clksel clkout2_src_clksel[] = { static struct clk clkout2_src_ck = { .name = "clkout2_src_ck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP3430_CM_CLKOUT_CTRL, + .enable_reg = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, - .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, + .clksel_reg = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, .clksel = clkout2_src_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, @@ -998,7 +1001,7 @@ static const struct clksel sys_clkout2_clksel[] = { static struct clk sys_clkout2 = { .name = "sys_clkout2", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, + .clksel_reg = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, @@ -1030,7 +1033,7 @@ static struct clk dpll1_fck = { .name = "dpll1_fck", .parent = &core_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, .clksel = div2_core_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -1054,7 +1057,7 @@ static struct clk mpu_ck = { .name = "mpu_ck", .parent = &dpll1_x2m2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = mpu_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -1079,7 +1082,7 @@ static struct clk arm_fck = { .name = "arm_fck", .parent = &mpu_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = arm_fck_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -1105,7 +1108,7 @@ static struct clk dpll2_fck = { .name = "dpll2_fck", .parent = &core_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, .clksel = div2_core_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -1130,9 +1133,9 @@ static struct clk iva2_ck = { .name = "iva2_ck", .parent = &dpll2_m2_ck, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, .clksel = iva2_clksel, @@ -1147,7 +1150,7 @@ static struct clk l3_ick = { .name = "l3_ick", .parent = &core_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L3_MASK, .clksel = div2_core_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -1165,7 +1168,7 @@ static struct clk l4_ick = { .name = "l4_ick", .parent = &l3_ick, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L4_MASK, .clksel = div2_l3_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | @@ -1184,7 +1187,7 @@ static struct clk rm_ick = { .name = "rm_ick", .parent = &l4_ick, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_RM_MASK, .clksel = div2_l4_clksel, .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, @@ -1205,7 +1208,7 @@ static struct clk gfx_l3_ck = { .name = "gfx_l3_ck", .parent = &l3_ick, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, .recalc = &followparent_recalc, @@ -1215,7 +1218,7 @@ static struct clk gfx_l3_fck = { .name = "gfx_l3_fck", .parent = &gfx_l3_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_l3_clksel, .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES | @@ -1236,7 +1239,7 @@ static struct clk gfx_cg1_ck = { .name = "gfx_cg1_ck", .parent = &gfx_l3_fck, /* REVISIT: correct? */ .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_2D_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "gfx_3430es1_clkdm", @@ -1247,7 +1250,7 @@ static struct clk gfx_cg2_ck = { .name = "gfx_cg2_ck", .parent = &gfx_l3_fck, /* REVISIT: correct? */ .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_3D_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "gfx_3430es1_clkdm", @@ -1277,9 +1280,9 @@ static const struct clksel sgx_clksel[] = { static struct clk sgx_fck = { .name = "sgx_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, .clksel = sgx_clksel, .flags = CLOCK_IN_OMAP3430ES2, @@ -1291,7 +1294,7 @@ static struct clk sgx_ick = { .name = "sgx_ick", .parent = &l3_ick, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "sgx_clkdm", @@ -1304,7 +1307,7 @@ static struct clk d2d_26m_fck = { .name = "d2d_26m_fck", .parent = &sys_ck, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "d2d_clkdm", @@ -1321,9 +1324,9 @@ static struct clk gpt10_fck = { .name = "gpt10_fck", .parent = &sys_ck, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -1335,9 +1338,9 @@ static struct clk gpt11_fck = { .name = "gpt11_fck", .parent = &sys_ck, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -1348,7 +1351,7 @@ static struct clk gpt11_fck = { static struct clk cpefuse_fck = { .name = "cpefuse_fck", .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .recalc = &followparent_recalc, @@ -1357,7 +1360,7 @@ static struct clk cpefuse_fck = { static struct clk ts_fck = { .name = "ts_fck", .parent = &omap_32k_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_TS_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .recalc = &followparent_recalc, @@ -1366,7 +1369,7 @@ static struct clk ts_fck = { static struct clk usbtll_fck = { .name = "usbtll_fck", .parent = &omap_120m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .recalc = &followparent_recalc, @@ -1387,7 +1390,7 @@ static struct clk mmchs3_fck = { .name = "mmchs_fck", .id = 3, .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "core_l4_clkdm", @@ -1398,7 +1401,7 @@ static struct clk mmchs2_fck = { .name = "mmchs_fck", .id = 2, .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1408,7 +1411,7 @@ static struct clk mmchs2_fck = { static struct clk mspro_fck = { .name = "mspro_fck", .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1419,7 +1422,7 @@ static struct clk mmchs1_fck = { .name = "mmchs_fck", .id = 1, .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1430,7 +1433,7 @@ static struct clk i2c3_fck = { .name = "i2c_fck", .id = 3, .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1441,7 +1444,7 @@ static struct clk i2c2_fck = { .name = "i2c_fck", .id = 2, .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1452,7 +1455,7 @@ static struct clk i2c1_fck = { .name = "i2c_fck", .id = 1, .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1482,7 +1485,7 @@ static const struct clksel mcbsp_15_clksel[] = { static struct clk mcbsp5_fck = { .name = "mcbsp5_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, @@ -1495,7 +1498,7 @@ static struct clk mcbsp5_fck = { static struct clk mcbsp1_fck = { .name = "mcbsp1_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, @@ -1520,7 +1523,7 @@ static struct clk mcspi4_fck = { .name = "mcspi_fck", .id = 4, .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -1530,7 +1533,7 @@ static struct clk mcspi3_fck = { .name = "mcspi_fck", .id = 3, .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -1540,7 +1543,7 @@ static struct clk mcspi2_fck = { .name = "mcspi_fck", .id = 2, .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -1550,7 +1553,7 @@ static struct clk mcspi1_fck = { .name = "mcspi_fck", .id = 1, .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -1559,7 +1562,7 @@ static struct clk mcspi1_fck = { static struct clk uart2_fck = { .name = "uart2_fck", .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -1568,7 +1571,7 @@ static struct clk uart2_fck = { static struct clk uart1_fck = { .name = "uart1_fck", .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -1577,7 +1580,7 @@ static struct clk uart1_fck = { static struct clk fshostusb_fck = { .name = "fshostusb_fck", .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, .recalc = &followparent_recalc, @@ -1597,7 +1600,7 @@ static struct clk core_12m_fck = { static struct clk hdq_fck = { .name = "hdq_fck", .parent = &core_12m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -1623,9 +1626,9 @@ static const struct clksel ssi_ssr_clksel[] = { static struct clk ssi_ssr_fck = { .name = "ssi_ssr_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, .clksel = ssi_ssr_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, @@ -1662,7 +1665,7 @@ static struct clk core_l3_ick = { static struct clk hsotgusb_ick = { .name = "hsotgusb_ick", .parent = &core_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l3_clkdm", @@ -1672,7 +1675,7 @@ static struct clk hsotgusb_ick = { static struct clk sdrc_ick = { .name = "sdrc_ick", .parent = &core_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SDRC_SHIFT, .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, .clkdm_name = "core_l3_clkdm", @@ -1701,7 +1704,7 @@ static struct clk security_l3_ick = { static struct clk pka_ick = { .name = "pka_ick", .parent = &security_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_PKA_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -1722,7 +1725,7 @@ static struct clk core_l4_ick = { static struct clk usbtll_ick = { .name = "usbtll_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "core_l4_clkdm", @@ -1733,7 +1736,7 @@ static struct clk mmchs3_ick = { .name = "mmchs_ick", .id = 3, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "core_l4_clkdm", @@ -1744,7 +1747,7 @@ static struct clk mmchs3_ick = { static struct clk icr_ick = { .name = "icr_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_ICR_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1754,7 +1757,7 @@ static struct clk icr_ick = { static struct clk aes2_ick = { .name = "aes2_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_AES2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1764,7 +1767,7 @@ static struct clk aes2_ick = { static struct clk sha12_ick = { .name = "sha12_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SHA12_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1774,7 +1777,7 @@ static struct clk sha12_ick = { static struct clk des2_ick = { .name = "des2_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_DES2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1785,7 +1788,7 @@ static struct clk mmchs2_ick = { .name = "mmchs_ick", .id = 2, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1796,7 +1799,7 @@ static struct clk mmchs1_ick = { .name = "mmchs_ick", .id = 1, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1806,7 +1809,7 @@ static struct clk mmchs1_ick = { static struct clk mspro_ick = { .name = "mspro_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1816,7 +1819,7 @@ static struct clk mspro_ick = { static struct clk hdq_ick = { .name = "hdq_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1827,7 +1830,7 @@ static struct clk mcspi4_ick = { .name = "mcspi_ick", .id = 4, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1838,7 +1841,7 @@ static struct clk mcspi3_ick = { .name = "mcspi_ick", .id = 3, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1849,7 +1852,7 @@ static struct clk mcspi2_ick = { .name = "mcspi_ick", .id = 2, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1860,7 +1863,7 @@ static struct clk mcspi1_ick = { .name = "mcspi_ick", .id = 1, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1871,7 +1874,7 @@ static struct clk i2c3_ick = { .name = "i2c_ick", .id = 3, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1882,7 +1885,7 @@ static struct clk i2c2_ick = { .name = "i2c_ick", .id = 2, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1893,7 +1896,7 @@ static struct clk i2c1_ick = { .name = "i2c_ick", .id = 1, .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1903,7 +1906,7 @@ static struct clk i2c1_ick = { static struct clk uart2_ick = { .name = "uart2_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1913,7 +1916,7 @@ static struct clk uart2_ick = { static struct clk uart1_ick = { .name = "uart1_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1923,7 +1926,7 @@ static struct clk uart1_ick = { static struct clk gpt11_ick = { .name = "gpt11_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1933,7 +1936,7 @@ static struct clk gpt11_ick = { static struct clk gpt10_ick = { .name = "gpt10_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1943,7 +1946,7 @@ static struct clk gpt10_ick = { static struct clk mcbsp5_ick = { .name = "mcbsp5_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1953,7 +1956,7 @@ static struct clk mcbsp5_ick = { static struct clk mcbsp1_ick = { .name = "mcbsp1_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1963,7 +1966,7 @@ static struct clk mcbsp1_ick = { static struct clk fac_ick = { .name = "fac_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "core_l4_clkdm", @@ -1973,7 +1976,7 @@ static struct clk fac_ick = { static struct clk mailboxes_ick = { .name = "mailboxes_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -1983,7 +1986,7 @@ static struct clk mailboxes_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, .recalc = &followparent_recalc, @@ -2003,7 +2006,7 @@ static struct clk ssi_l4_ick = { static struct clk ssi_ick = { .name = "ssi_ick", .parent = &ssi_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -2022,9 +2025,9 @@ static struct clk usb_l4_ick = { .name = "usb_l4_ick", .parent = &l4_ick, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, .clksel = usb_l4_clksel, .flags = CLOCK_IN_OMAP3430ES1, @@ -2046,7 +2049,7 @@ static struct clk security_l4_ick2 = { static struct clk aes1_ick = { .name = "aes1_ick", .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_AES1_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -2055,7 +2058,7 @@ static struct clk aes1_ick = { static struct clk rng_ick = { .name = "rng_ick", .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_RNG_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -2064,7 +2067,7 @@ static struct clk rng_ick = { static struct clk sha11_ick = { .name = "sha11_ick", .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_SHA11_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -2073,7 +2076,7 @@ static struct clk sha11_ick = { static struct clk des1_ick = { .name = "des1_ick", .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_DES1_SHIFT, .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, @@ -2090,9 +2093,9 @@ static struct clk dss1_alwon_fck = { .name = "dss1_alwon_fck", .parent = &dpll4_m4x2_ck, .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = dss1_alwon_fck_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2104,7 +2107,7 @@ static struct clk dss_tv_fck = { .name = "dss_tv_fck", .parent = &omap_54m_fck, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", @@ -2115,7 +2118,7 @@ static struct clk dss_96m_fck = { .name = "dss_96m_fck", .parent = &omap_96m_fck, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", @@ -2126,7 +2129,7 @@ static struct clk dss2_alwon_fck = { .name = "dss2_alwon_fck", .parent = &sys_ck, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", @@ -2138,7 +2141,7 @@ static struct clk dss_ick = { .name = "dss_ick", .parent = &l4_ick, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", @@ -2157,10 +2160,10 @@ static struct clk cam_mclk = { .name = "cam_mclk", .parent = &dpll4_m5x2_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .clksel_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = cam_mclk_clksel, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "cam_clkdm", @@ -2172,7 +2175,7 @@ static struct clk cam_ick = { .name = "cam_ick", .parent = &l4_ick, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "cam_clkdm", @@ -2185,7 +2188,7 @@ static struct clk usbhost_120m_fck = { .name = "usbhost_120m_fck", .parent = &omap_120m_fck, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "usbhost_clkdm", @@ -2196,7 +2199,7 @@ static struct clk usbhost_48m_fck = { .name = "usbhost_48m_fck", .parent = &omap_48m_fck, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "usbhost_clkdm", @@ -2208,7 +2211,7 @@ static struct clk usbhost_ick = { .name = "usbhost_ick", .parent = &l4_ick, .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "usbhost_clkdm", @@ -2255,9 +2258,9 @@ static const struct clksel usim_clksel[] = { static struct clk usim_fck = { .name = "usim_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, .clksel = usim_clksel, .flags = CLOCK_IN_OMAP3430ES2, @@ -2268,9 +2271,9 @@ static struct clk usim_fck = { static struct clk gpt1_fck = { .name = "gpt1_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2290,7 +2293,7 @@ static struct clk wkup_32k_fck = { static struct clk gpio1_fck = { .name = "gpio1_fck", .parent = &wkup_32k_fck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", @@ -2300,7 +2303,7 @@ static struct clk gpio1_fck = { static struct clk wdt2_fck = { .name = "wdt2_fck", .parent = &wkup_32k_fck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", @@ -2320,7 +2323,7 @@ static struct clk wkup_l4_ick = { static struct clk usim_ick = { .name = "usim_ick", .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "wkup_clkdm", @@ -2330,7 +2333,7 @@ static struct clk usim_ick = { static struct clk wdt2_ick = { .name = "wdt2_ick", .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", @@ -2340,7 +2343,7 @@ static struct clk wdt2_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", @@ -2350,7 +2353,7 @@ static struct clk wdt1_ick = { static struct clk gpio1_ick = { .name = "gpio1_ick", .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", @@ -2360,7 +2363,7 @@ static struct clk gpio1_ick = { static struct clk omap_32ksync_ick = { .name = "omap_32ksync_ick", .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", @@ -2371,7 +2374,7 @@ static struct clk omap_32ksync_ick = { static struct clk gpt12_ick = { .name = "gpt12_ick", .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT12_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", @@ -2381,7 +2384,7 @@ static struct clk gpt12_ick = { static struct clk gpt1_ick = { .name = "gpt1_ick", .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", @@ -2415,7 +2418,7 @@ static struct clk per_48m_fck = { static struct clk uart3_fck = { .name = "uart3_fck", .parent = &per_48m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2425,9 +2428,9 @@ static struct clk uart3_fck = { static struct clk gpt2_fck = { .name = "gpt2_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2438,9 +2441,9 @@ static struct clk gpt2_fck = { static struct clk gpt3_fck = { .name = "gpt3_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2451,9 +2454,9 @@ static struct clk gpt3_fck = { static struct clk gpt4_fck = { .name = "gpt4_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2464,9 +2467,9 @@ static struct clk gpt4_fck = { static struct clk gpt5_fck = { .name = "gpt5_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2477,9 +2480,9 @@ static struct clk gpt5_fck = { static struct clk gpt6_fck = { .name = "gpt6_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2490,9 +2493,9 @@ static struct clk gpt6_fck = { static struct clk gpt7_fck = { .name = "gpt7_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2503,9 +2506,9 @@ static struct clk gpt7_fck = { static struct clk gpt8_fck = { .name = "gpt8_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2516,9 +2519,9 @@ static struct clk gpt8_fck = { static struct clk gpt9_fck = { .name = "gpt9_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, @@ -2537,7 +2540,7 @@ static struct clk per_32k_alwon_fck = { static struct clk gpio6_fck = { .name = "gpio6_fck", .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2547,7 +2550,7 @@ static struct clk gpio6_fck = { static struct clk gpio5_fck = { .name = "gpio5_fck", .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2557,7 +2560,7 @@ static struct clk gpio5_fck = { static struct clk gpio4_fck = { .name = "gpio4_fck", .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2567,7 +2570,7 @@ static struct clk gpio4_fck = { static struct clk gpio3_fck = { .name = "gpio3_fck", .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2577,7 +2580,7 @@ static struct clk gpio3_fck = { static struct clk gpio2_fck = { .name = "gpio2_fck", .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2587,7 +2590,7 @@ static struct clk gpio2_fck = { static struct clk wdt3_fck = { .name = "wdt3_fck", .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2606,7 +2609,7 @@ static struct clk per_l4_ick = { static struct clk gpio6_ick = { .name = "gpio6_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2616,7 +2619,7 @@ static struct clk gpio6_ick = { static struct clk gpio5_ick = { .name = "gpio5_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2626,7 +2629,7 @@ static struct clk gpio5_ick = { static struct clk gpio4_ick = { .name = "gpio4_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2636,7 +2639,7 @@ static struct clk gpio4_ick = { static struct clk gpio3_ick = { .name = "gpio3_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2646,7 +2649,7 @@ static struct clk gpio3_ick = { static struct clk gpio2_ick = { .name = "gpio2_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2656,7 +2659,7 @@ static struct clk gpio2_ick = { static struct clk wdt3_ick = { .name = "wdt3_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2666,7 +2669,7 @@ static struct clk wdt3_ick = { static struct clk uart3_ick = { .name = "uart3_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2676,7 +2679,7 @@ static struct clk uart3_ick = { static struct clk gpt9_ick = { .name = "gpt9_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2686,7 +2689,7 @@ static struct clk gpt9_ick = { static struct clk gpt8_ick = { .name = "gpt8_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2696,7 +2699,7 @@ static struct clk gpt8_ick = { static struct clk gpt7_ick = { .name = "gpt7_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2706,7 +2709,7 @@ static struct clk gpt7_ick = { static struct clk gpt6_ick = { .name = "gpt6_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2716,7 +2719,7 @@ static struct clk gpt6_ick = { static struct clk gpt5_ick = { .name = "gpt5_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2726,7 +2729,7 @@ static struct clk gpt5_ick = { static struct clk gpt4_ick = { .name = "gpt4_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2736,7 +2739,7 @@ static struct clk gpt4_ick = { static struct clk gpt3_ick = { .name = "gpt3_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2746,7 +2749,7 @@ static struct clk gpt3_ick = { static struct clk gpt2_ick = { .name = "gpt2_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2756,7 +2759,7 @@ static struct clk gpt2_ick = { static struct clk mcbsp2_ick = { .name = "mcbsp2_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2766,7 +2769,7 @@ static struct clk mcbsp2_ick = { static struct clk mcbsp3_ick = { .name = "mcbsp3_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2776,7 +2779,7 @@ static struct clk mcbsp3_ick = { static struct clk mcbsp4_ick = { .name = "mcbsp4_ick", .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", @@ -2792,7 +2795,7 @@ static const struct clksel mcbsp_234_clksel[] = { static struct clk mcbsp2_fck = { .name = "mcbsp2_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, @@ -2805,7 +2808,7 @@ static struct clk mcbsp2_fck = { static struct clk mcbsp3_fck = { .name = "mcbsp3_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, @@ -2818,7 +2821,7 @@ static struct clk mcbsp3_fck = { static struct clk mcbsp4_fck = { .name = "mcbsp4_fck", .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, @@ -2868,7 +2871,7 @@ static const struct clksel emu_src_clksel[] = { static struct clk emu_src_ck = { .name = "emu_src_ck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_MUX_CTRL_MASK, .clksel = emu_src_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, @@ -2892,7 +2895,7 @@ static const struct clksel pclk_emu_clksel[] = { static struct clk pclk_fck = { .name = "pclk_fck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel = pclk_emu_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, @@ -2915,7 +2918,7 @@ static const struct clksel pclkx2_emu_clksel[] = { static struct clk pclkx2_fck = { .name = "pclkx2_fck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel = pclkx2_emu_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, @@ -2931,7 +2934,7 @@ static const struct clksel atclk_emu_clksel[] = { static struct clk atclk_fck = { .name = "atclk_fck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel = atclk_emu_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, @@ -2942,7 +2945,7 @@ static struct clk atclk_fck = { static struct clk traceclk_src_fck = { .name = "traceclk_src_fck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel = emu_src_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, @@ -2965,7 +2968,7 @@ static const struct clksel traceclk_clksel[] = { static struct clk traceclk_fck = { .name = "traceclk_fck", .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, .clksel = traceclk_clksel, .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, @@ -2979,7 +2982,7 @@ static struct clk traceclk_fck = { static struct clk sr1_fck = { .name = "sr1_fck", .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR1_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, @@ -2989,7 +2992,7 @@ static struct clk sr1_fck = { static struct clk sr2_fck = { .name = "sr2_fck", .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR2_SHIFT, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 1d5afee..68e4971 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -19,26 +19,27 @@ #ifndef __ASSEMBLER__ #define OMAP_CM_REGADDR(module, reg) \ (__force void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) -#else +#endif + #define OMAP2420_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) #define OMAP2430_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) #define OMAP34XX_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) -#endif /* * Architecture-specific global CM registers - * Use cm_{read,write}_reg() with these registers. + * Use __raw_{read,write}l() with these registers. * These registers appear once per CM module. */ -#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) -#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) -#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) +#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) +#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) +#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) -#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) +#define OMAP3430_CM_CLKOUT_CTRL \ + OMAP34XX_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) #ifndef __ASSEMBLER__ -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 13/14] ARM: OMAP: Change to use CM offsets for clocks for multi-omap 2008-05-28 4:20 ` [PATCH 12/14] ARM: OMAP: Remove OMAP_CM_REGADDR for multi-boot Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 2008-05-28 4:20 ` [PATCH 14/14] ARM: OMAP: Use omap_globals for CPU detection " Tony Lindgren 0 siblings, 1 reply; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren Change to use CM offsets for clocks for multi-omap Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/clock24xx.c | 9 +- arch/arm/mach-omap2/clock24xx.h | 295 ++++++++++++++++++++------------------- arch/arm/mach-omap2/cm.h | 13 +-- arch/arm/mach-omap2/prcm.c | 14 ++ 4 files changed, 172 insertions(+), 159 deletions(-) diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 84a0d10..9acc580 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -94,6 +94,7 @@ static void omap2_disable_osc_ck(struct clk *clk) static int omap2_clk_fixed_enable(struct clk *clk) { u32 cval, apll_mask; + void __iomem *idlest; apll_mask = EN_APLL_LOCKED << clk->enable_bit; @@ -111,8 +112,12 @@ static int omap2_clk_fixed_enable(struct clk *clk) else if (clk == &apll54_ck) cval = OMAP24XX_ST_54M_APLL; - omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, - clk->name); + if (cpu_is_omap242x()) + idlest = OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST); + else + idlest = OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST); + + omap2_wait_clock_ready(idlest, cval, clk->name); /* * REVISIT: Should we return an error code if omap2_wait_clock_ready() diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index c9f3fcf..1327fed 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -600,6 +600,11 @@ static struct prcm_config rate_table[] = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, }; +/* + * Since 2420 and 2430 have different cm_base, we use offsets only here. + * Clock code will rewrite the register address as needed. + */ +#define _CM_REG_OFFSET(module, reg) ((void __iomem *)(module) + (reg)) #define _GR_MOD_OFFSET(reg) ((void __iomem*)(OMAP24XX_GR_MOD + (reg))) /*------------------------------------------------------------------------- @@ -668,7 +673,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ */ static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_div1_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP24XX_DPLL_MULT_MASK, .div1_mask = OMAP24XX_DPLL_DIV_MASK, .max_multiplier = 1024, @@ -696,7 +701,7 @@ static struct clk apll96_ck = { .rate = 96000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, .enable = &omap2_clk_fixed_enable, .disable = &omap2_clk_fixed_disable, @@ -709,7 +714,7 @@ static struct clk apll54_ck = { .rate = 54000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, .enable = &omap2_clk_fixed_enable, .disable = &omap2_clk_fixed_disable, @@ -744,7 +749,7 @@ static struct clk func_54m_ck = { .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_54M_SOURCE, .clksel = func_54m_clksel, .recalc = &omap2_clksel_recalc, @@ -782,7 +787,7 @@ static struct clk func_96m_ck = { .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP2430_96M_SOURCE, .clksel = func_96m_clksel, .recalc = &omap2_clksel_recalc, @@ -814,7 +819,7 @@ static struct clk func_48m_ck = { .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_48M_SOURCE, .clksel = func_48m_clksel, .recalc = &omap2_clksel_recalc, @@ -994,7 +999,7 @@ static struct clk mpu_ck = { /* Control cpu */ ALWAYS_ENABLED | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), + .clksel_reg = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, .clksel = mpu_clksel, .recalc = &omap2_clksel_recalc, @@ -1034,9 +1039,9 @@ static struct clk dsp_fck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + .clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, .clksel = dsp_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1066,7 +1071,7 @@ static struct clk dsp_irate_ick = { .parent = &dsp_fck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + .clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, .clksel = dsp_irate_ick_clksel, .recalc = &omap2_clksel_recalc, @@ -1079,7 +1084,7 @@ static struct clk dsp_ick = { .name = "dsp_ick", /* apparently ipi and isp */ .parent = &dsp_irate_ick, .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN), .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ }; @@ -1088,7 +1093,7 @@ static struct clk iva2_1_ick = { .name = "iva2_1_ick", .parent = &dsp_irate_ick, .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, }; @@ -1097,9 +1102,9 @@ static struct clk iva1_ifck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + .clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, .clksel = dsp_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1112,7 +1117,7 @@ static struct clk iva1_mpu_int_ifck = { .name = "iva1_mpu_int_ifck", .parent = &iva1_ifck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .fixed_div = 2, .recalc = &omap2_fixed_divisor_recalc, @@ -1159,7 +1164,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, .clksel = core_l3_clksel, .recalc = &omap2_clksel_recalc, @@ -1185,9 +1190,9 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, .clksel = usb_l4_ick_clksel, .recalc = &omap2_clksel_recalc, @@ -1224,9 +1229,9 @@ static struct clk ssi_ssr_sst_fck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, .clksel = ssi_ssr_sst_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1257,9 +1262,9 @@ static struct clk gfx_3d_fck = { .name = "gfx_3d_fck", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_3D_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + .clksel_reg = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1271,9 +1276,9 @@ static struct clk gfx_2d_fck = { .name = "gfx_2d_fck", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_2D_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + .clksel_reg = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1285,7 +1290,7 @@ static struct clk gfx_ick = { .name = "gfx_ick", /* From l3 */ .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, .recalc = &followparent_recalc, }; @@ -1314,9 +1319,9 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ .name = "mdm_ick", .parent = &core_ck, .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, - .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN), .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), + .clksel_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL), .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, .clksel = mdm_ick_clksel, .recalc = &omap2_clksel_recalc, @@ -1328,7 +1333,7 @@ static struct clk mdm_osc_ck = { .name = "mdm_osc_ck", .parent = &osc_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN), .enable_bit = OMAP2430_EN_OSC_SHIFT, .recalc = &followparent_recalc, }; @@ -1356,7 +1361,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */ .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, .clksel = l4_clksel, .recalc = &omap2_clksel_recalc, @@ -1368,7 +1373,7 @@ static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_SSI_SHIFT, .recalc = &followparent_recalc, }; @@ -1412,7 +1417,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ .name = "dss_ick", .parent = &l4_ck, /* really both l3 and l4 */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_DSS1_SHIFT, .recalc = &followparent_recalc, }; @@ -1422,10 +1427,10 @@ static struct clk dss1_fck = { .parent = &core_ck, /* Core or sys */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_DSS1_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, .clksel = dss1_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -1454,10 +1459,10 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_DSS2_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, .clksel = dss2_fck_clksel, .recalc = &followparent_recalc, @@ -1467,7 +1472,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ .name = "dss_54m_fck", /* 54m tv clk */ .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_TV_SHIFT, .recalc = &followparent_recalc, }; @@ -1494,7 +1499,7 @@ static struct clk gpt1_ick = { .name = "gpt1_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, .recalc = &followparent_recalc, }; @@ -1503,10 +1508,10 @@ static struct clk gpt1_fck = { .name = "gpt1_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(WKUP_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1518,7 +1523,7 @@ static struct clk gpt2_ick = { .name = "gpt2_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT2_SHIFT, .recalc = &followparent_recalc, }; @@ -1527,10 +1532,10 @@ static struct clk gpt2_fck = { .name = "gpt2_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT2_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1540,7 +1545,7 @@ static struct clk gpt3_ick = { .name = "gpt3_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT3_SHIFT, .recalc = &followparent_recalc, }; @@ -1549,10 +1554,10 @@ static struct clk gpt3_fck = { .name = "gpt3_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT3_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1562,7 +1567,7 @@ static struct clk gpt4_ick = { .name = "gpt4_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT4_SHIFT, .recalc = &followparent_recalc, }; @@ -1571,10 +1576,10 @@ static struct clk gpt4_fck = { .name = "gpt4_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT4_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1584,7 +1589,7 @@ static struct clk gpt5_ick = { .name = "gpt5_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT5_SHIFT, .recalc = &followparent_recalc, }; @@ -1593,10 +1598,10 @@ static struct clk gpt5_fck = { .name = "gpt5_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT5_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1606,7 +1611,7 @@ static struct clk gpt6_ick = { .name = "gpt6_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT6_SHIFT, .recalc = &followparent_recalc, }; @@ -1615,10 +1620,10 @@ static struct clk gpt6_fck = { .name = "gpt6_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT6_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1628,7 +1633,7 @@ static struct clk gpt7_ick = { .name = "gpt7_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, .recalc = &followparent_recalc, }; @@ -1637,10 +1642,10 @@ static struct clk gpt7_fck = { .name = "gpt7_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1650,7 +1655,7 @@ static struct clk gpt8_ick = { .name = "gpt8_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT8_SHIFT, .recalc = &followparent_recalc, }; @@ -1659,10 +1664,10 @@ static struct clk gpt8_fck = { .name = "gpt8_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT8_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1672,7 +1677,7 @@ static struct clk gpt9_ick = { .name = "gpt9_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT9_SHIFT, .recalc = &followparent_recalc, }; @@ -1681,10 +1686,10 @@ static struct clk gpt9_fck = { .name = "gpt9_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT9_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1694,7 +1699,7 @@ static struct clk gpt10_ick = { .name = "gpt10_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT10_SHIFT, .recalc = &followparent_recalc, }; @@ -1703,10 +1708,10 @@ static struct clk gpt10_fck = { .name = "gpt10_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT10_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1716,7 +1721,7 @@ static struct clk gpt11_ick = { .name = "gpt11_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT11_SHIFT, .recalc = &followparent_recalc, }; @@ -1725,10 +1730,10 @@ static struct clk gpt11_fck = { .name = "gpt11_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT11_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1738,7 +1743,7 @@ static struct clk gpt12_ick = { .name = "gpt12_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, .recalc = &followparent_recalc, }; @@ -1747,10 +1752,10 @@ static struct clk gpt12_fck = { .name = "gpt12_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL2), .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, .clksel = omap24xx_gpt_clksel, .recalc = &omap2_clksel_recalc, @@ -1760,7 +1765,7 @@ static struct clk mcbsp1_ick = { .name = "mcbsp1_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, .recalc = &followparent_recalc, }; @@ -1769,7 +1774,7 @@ static struct clk mcbsp1_fck = { .name = "mcbsp1_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, .recalc = &followparent_recalc, }; @@ -1778,7 +1783,7 @@ static struct clk mcbsp2_ick = { .name = "mcbsp2_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, .recalc = &followparent_recalc, }; @@ -1787,7 +1792,7 @@ static struct clk mcbsp2_fck = { .name = "mcbsp2_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, .recalc = &followparent_recalc, }; @@ -1796,7 +1801,7 @@ static struct clk mcbsp3_ick = { .name = "mcbsp3_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, .recalc = &followparent_recalc, }; @@ -1805,7 +1810,7 @@ static struct clk mcbsp3_fck = { .name = "mcbsp3_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, .recalc = &followparent_recalc, }; @@ -1814,7 +1819,7 @@ static struct clk mcbsp4_ick = { .name = "mcbsp4_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, .recalc = &followparent_recalc, }; @@ -1823,7 +1828,7 @@ static struct clk mcbsp4_fck = { .name = "mcbsp4_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, .recalc = &followparent_recalc, }; @@ -1832,7 +1837,7 @@ static struct clk mcbsp5_ick = { .name = "mcbsp5_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, .recalc = &followparent_recalc, }; @@ -1841,7 +1846,7 @@ static struct clk mcbsp5_fck = { .name = "mcbsp5_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, .recalc = &followparent_recalc, }; @@ -1851,7 +1856,7 @@ static struct clk mcspi1_ick = { .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, .recalc = &followparent_recalc, }; @@ -1861,7 +1866,7 @@ static struct clk mcspi1_fck = { .id = 1, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, .recalc = &followparent_recalc, }; @@ -1871,7 +1876,7 @@ static struct clk mcspi2_ick = { .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, .recalc = &followparent_recalc, }; @@ -1881,7 +1886,7 @@ static struct clk mcspi2_fck = { .id = 2, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, .recalc = &followparent_recalc, }; @@ -1891,7 +1896,7 @@ static struct clk mcspi3_ick = { .id = 3, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, .recalc = &followparent_recalc, }; @@ -1901,7 +1906,7 @@ static struct clk mcspi3_fck = { .id = 3, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, .recalc = &followparent_recalc, }; @@ -1910,7 +1915,7 @@ static struct clk uart1_ick = { .name = "uart1_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_UART1_SHIFT, .recalc = &followparent_recalc, }; @@ -1919,7 +1924,7 @@ static struct clk uart1_fck = { .name = "uart1_fck", .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_UART1_SHIFT, .recalc = &followparent_recalc, }; @@ -1928,7 +1933,7 @@ static struct clk uart2_ick = { .name = "uart2_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_UART2_SHIFT, .recalc = &followparent_recalc, }; @@ -1937,7 +1942,7 @@ static struct clk uart2_fck = { .name = "uart2_fck", .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_UART2_SHIFT, .recalc = &followparent_recalc, }; @@ -1946,7 +1951,7 @@ static struct clk uart3_ick = { .name = "uart3_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_UART3_SHIFT, .recalc = &followparent_recalc, }; @@ -1955,7 +1960,7 @@ static struct clk uart3_fck = { .name = "uart3_fck", .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_UART3_SHIFT, .recalc = &followparent_recalc, }; @@ -1964,7 +1969,7 @@ static struct clk gpios_ick = { .name = "gpios_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .recalc = &followparent_recalc, }; @@ -1973,7 +1978,7 @@ static struct clk gpios_fck = { .name = "gpios_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .recalc = &followparent_recalc, }; @@ -1982,7 +1987,7 @@ static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .recalc = &followparent_recalc, }; @@ -1991,7 +1996,7 @@ static struct clk mpu_wdt_fck = { .name = "mpu_wdt_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .recalc = &followparent_recalc, }; @@ -2000,7 +2005,7 @@ static struct clk sync_32k_ick = { .name = "sync_32k_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, .recalc = &followparent_recalc, }; @@ -2008,7 +2013,7 @@ static struct clk wdt1_ick = { .name = "wdt1_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_WDT1_SHIFT, .recalc = &followparent_recalc, }; @@ -2016,7 +2021,7 @@ static struct clk omapctrl_ick = { .name = "omapctrl_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, .recalc = &followparent_recalc, }; @@ -2024,7 +2029,7 @@ static struct clk icr_ick = { .name = "icr_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP2430_EN_ICR_SHIFT, .recalc = &followparent_recalc, }; @@ -2033,7 +2038,7 @@ static struct clk cam_ick = { .name = "cam_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_CAM_SHIFT, .recalc = &followparent_recalc, }; @@ -2042,7 +2047,7 @@ static struct clk cam_fck = { .name = "cam_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_CAM_SHIFT, .recalc = &followparent_recalc, }; @@ -2051,7 +2056,7 @@ static struct clk mailboxes_ick = { .name = "mailboxes_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, .recalc = &followparent_recalc, }; @@ -2060,7 +2065,7 @@ static struct clk wdt4_ick = { .name = "wdt4_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_WDT4_SHIFT, .recalc = &followparent_recalc, }; @@ -2069,7 +2074,7 @@ static struct clk wdt4_fck = { .name = "wdt4_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_WDT4_SHIFT, .recalc = &followparent_recalc, }; @@ -2078,7 +2083,7 @@ static struct clk wdt3_ick = { .name = "wdt3_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_WDT3_SHIFT, .recalc = &followparent_recalc, }; @@ -2087,7 +2092,7 @@ static struct clk wdt3_fck = { .name = "wdt3_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_WDT3_SHIFT, .recalc = &followparent_recalc, }; @@ -2096,7 +2101,7 @@ static struct clk mspro_ick = { .name = "mspro_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, .recalc = &followparent_recalc, }; @@ -2105,7 +2110,7 @@ static struct clk mspro_fck = { .name = "mspro_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, .recalc = &followparent_recalc, }; @@ -2114,7 +2119,7 @@ static struct clk mmc_ick = { .name = "mmc_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_MMC_SHIFT, .recalc = &followparent_recalc, }; @@ -2123,7 +2128,7 @@ static struct clk mmc_fck = { .name = "mmc_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_MMC_SHIFT, .recalc = &followparent_recalc, }; @@ -2132,7 +2137,7 @@ static struct clk fac_ick = { .name = "fac_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_FAC_SHIFT, .recalc = &followparent_recalc, }; @@ -2141,7 +2146,7 @@ static struct clk fac_fck = { .name = "fac_fck", .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_FAC_SHIFT, .recalc = &followparent_recalc, }; @@ -2150,7 +2155,7 @@ static struct clk eac_ick = { .name = "eac_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_EAC_SHIFT, .recalc = &followparent_recalc, }; @@ -2159,7 +2164,7 @@ static struct clk eac_fck = { .name = "eac_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_EAC_SHIFT, .recalc = &followparent_recalc, }; @@ -2168,7 +2173,7 @@ static struct clk hdq_ick = { .name = "hdq_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_HDQ_SHIFT, .recalc = &followparent_recalc, }; @@ -2177,7 +2182,7 @@ static struct clk hdq_fck = { .name = "hdq_fck", .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_HDQ_SHIFT, .recalc = &followparent_recalc, }; @@ -2187,7 +2192,7 @@ static struct clk i2c2_ick = { .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_I2C2_SHIFT, .recalc = &followparent_recalc, }; @@ -2197,7 +2202,7 @@ static struct clk i2c2_fck = { .id = 2, .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_I2C2_SHIFT, .recalc = &followparent_recalc, }; @@ -2207,7 +2212,7 @@ static struct clk i2chs2_fck = { .id = 2, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, .recalc = &followparent_recalc, }; @@ -2217,7 +2222,7 @@ static struct clk i2c1_ick = { .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_I2C1_SHIFT, .recalc = &followparent_recalc, }; @@ -2227,7 +2232,7 @@ static struct clk i2c1_fck = { .id = 1, .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_I2C1_SHIFT, .recalc = &followparent_recalc, }; @@ -2237,7 +2242,7 @@ static struct clk i2chs1_fck = { .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, .recalc = &followparent_recalc, }; @@ -2267,7 +2272,7 @@ static struct clk vlynq_ick = { .name = "vlynq_ick", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, .recalc = &followparent_recalc, }; @@ -2301,10 +2306,10 @@ static struct clk vlynq_fck = { .name = "vlynq_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | DELAYED_APP, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, .clksel = vlynq_fck_clksel, .recalc = &omap2_clksel_recalc, @@ -2316,7 +2321,7 @@ static struct clk sdrc_ick = { .name = "sdrc_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP2430_EN_SDRC_SHIFT, .recalc = &followparent_recalc, }; @@ -2325,7 +2330,7 @@ static struct clk des_ick = { .name = "des_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_DES_SHIFT, .recalc = &followparent_recalc, }; @@ -2334,7 +2339,7 @@ static struct clk sha_ick = { .name = "sha_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_SHA_SHIFT, .recalc = &followparent_recalc, }; @@ -2343,7 +2348,7 @@ static struct clk rng_ick = { .name = "rng_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_RNG_SHIFT, .recalc = &followparent_recalc, }; @@ -2352,7 +2357,7 @@ static struct clk aes_ick = { .name = "aes_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_AES_SHIFT, .recalc = &followparent_recalc, }; @@ -2361,7 +2366,7 @@ static struct clk pka_ick = { .name = "pka_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_PKA_SHIFT, .recalc = &followparent_recalc, }; @@ -2370,7 +2375,7 @@ static struct clk usb_fck = { .name = "usb_fck", .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_USB_SHIFT, .recalc = &followparent_recalc, }; @@ -2379,7 +2384,7 @@ static struct clk usbhs_ick = { .name = "usbhs_ick", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_USBHS_SHIFT, .recalc = &followparent_recalc, }; @@ -2389,7 +2394,7 @@ static struct clk mmchs1_ick = { .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, .recalc = &followparent_recalc, }; @@ -2399,7 +2404,7 @@ static struct clk mmchs1_fck = { .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, .recalc = &followparent_recalc, }; @@ -2409,7 +2414,7 @@ static struct clk mmchs2_ick = { .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, .recalc = &followparent_recalc, }; @@ -2419,7 +2424,7 @@ static struct clk mmchs2_fck = { .id = 2, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, .recalc = &followparent_recalc, }; @@ -2428,7 +2433,7 @@ static struct clk gpio5_ick = { .name = "gpio5_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_GPIO5_SHIFT, .recalc = &followparent_recalc, }; @@ -2437,7 +2442,7 @@ static struct clk gpio5_fck = { .name = "gpio5_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_GPIO5_SHIFT, .recalc = &followparent_recalc, }; @@ -2446,7 +2451,7 @@ static struct clk mdm_intc_ick = { .name = "mdm_intc_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, .recalc = &followparent_recalc, }; @@ -2456,7 +2461,7 @@ static struct clk mmchsdb1_fck = { .id = 1, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, .recalc = &followparent_recalc, }; @@ -2466,7 +2471,7 @@ static struct clk mmchsdb2_fck = { .id = 2, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, .recalc = &followparent_recalc, }; diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 68e4971..da5e83a 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -16,11 +16,6 @@ #include "prcm-common.h" -#ifndef __ASSEMBLER__ -#define OMAP_CM_REGADDR(module, reg) \ - (__force void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) -#endif - #define OMAP2420_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) #define OMAP2430_CM_REGADDR(module, reg) \ @@ -118,13 +113,7 @@ static __inline__ u32 __attribute__((unused)) cm_rmw_reg_bits(u32 mask, extern u32 cm_read_mod_reg(s16 module, u16 idx); extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); - -/* Read-modify-write bits in a CM register (by domain) */ -static __inline__ u32 __attribute__((unused)) cm_rmw_mod_reg_bits(u32 mask, - u32 bits, s16 module, s16 idx) -{ - return cm_rmw_reg_bits(mask, bits, OMAP_CM_REGADDR(module, idx)); -} +extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); static __inline__ u32 __attribute__((unused)) cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index ad17933..fd92a80 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -106,6 +106,20 @@ void cm_write_mod_reg(u32 val, s16 module, u16 idx) } EXPORT_SYMBOL(cm_write_mod_reg); +/* Read-modify-write a register in a CM module. Caller must lock */ +u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +{ + u32 v; + + v = cm_read_mod_reg(module, idx); + v &= ~mask; + v |= bits; + cm_write_mod_reg(v, module, idx); + + return v; +} +EXPORT_SYMBOL(cm_rmw_mod_reg_bits); + void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) { prm_base = omap2_globals->prm; -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 14/14] ARM: OMAP: Use omap_globals for CPU detection for multi-omap 2008-05-28 4:20 ` [PATCH 13/14] ARM: OMAP: Change to use CM offsets for clocks for multi-omap Tony Lindgren @ 2008-05-28 4:20 ` Tony Lindgren 0 siblings, 0 replies; 16+ messages in thread From: Tony Lindgren @ 2008-05-28 4:20 UTC (permalink / raw) To: linux-omap; +Cc: Tony Lindgren This allows to get rid of the ifdefs and will allow simpler CPU detection in the future. Signed-off-by: Tony Lindgren <tony@atomide.com> --- arch/arm/mach-omap2/id.c | 43 ++++++++++++++++++++++------------- arch/arm/plat-omap/common.c | 4 +++ include/asm-arm/arch-omap/common.h | 2 + include/asm-arm/arch-omap/cpu.h | 5 ++++ 4 files changed, 38 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 0db34ba..27dfdca 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -16,24 +16,15 @@ #include <linux/init.h> #include <linux/io.h> +#include <asm/arch/common.h> #include <asm/arch/control.h> #include <asm/arch/cpu.h> -#if defined(CONFIG_ARCH_OMAP2420) -#define TAP_BASE (__force void __iomem *)io_p2v(0x48014000) -#elif defined(CONFIG_ARCH_OMAP2430) -#define TAP_BASE (__force void __iomem *)io_p2v(0x4900A000) -#elif defined(CONFIG_ARCH_OMAP34XX) -#define TAP_BASE (__force void __iomem *)io_p2v(0x4830A000) -#endif +static u32 class; +static void __iomem *tap_base; +static u16 tap_prod_id; #define OMAP_TAP_IDCODE 0x0204 -#if defined(CONFIG_ARCH_OMAP34XX) -#define OMAP_TAP_PROD_ID 0x0210 -#else -#define OMAP_TAP_PROD_ID 0x0208 -#endif - #define OMAP_TAP_DIE_ID_0 0x0218 #define OMAP_TAP_DIE_ID_1 0x021C #define OMAP_TAP_DIE_ID_2 0x0220 @@ -92,18 +83,24 @@ static u32 __init read_tap_reg(int reg) * it means its Cortex r0p0 which is 3430 ES1 */ if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) { + + if (reg == tap_prod_id) { + regval = 0x000F00F0; + goto out; + } + switch (reg) { case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break; /* Making DevType as 0xF in ES1 to differ from ES2 */ - case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break; case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break; case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break; case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break; case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break; } } else - regval = __raw_readl(TAP_BASE + reg); + regval = __raw_readl(tap_base + reg); +out: return regval; } @@ -202,7 +199,7 @@ void __init omap2_check_revision(void) u8 rev; idcode = read_tap_reg(OMAP_TAP_IDCODE); - prod_id = read_tap_reg(OMAP_TAP_PROD_ID); + prod_id = read_tap_reg(tap_prod_id); hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0x0f; dev_type = (prod_id >> 16) & 0x0f; @@ -275,6 +272,9 @@ static int __init omap3_check_l2cache(void) { u32 val; + if (class < OMAP3430_REV_ES1_0) + return -ENODEV; + /* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */ asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val)); @@ -289,3 +289,14 @@ static int __init omap3_check_l2cache(void) arch_initcall(omap3_check_l2cache); #endif /* CONFIG_ARCH_OMAP3 */ + +void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) +{ + class = omap2_globals->class; + tap_base = omap2_globals->tap; + + if (class == 0x3430) + tap_prod_id = 0x0210; + else + tap_prod_id = 0x0208; +} diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 8a718ff..132a758 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -268,6 +268,7 @@ static struct omap_globals *omap2_globals; static void __init __omap2_set_globals(void) { + omap2_set_globals_tap(omap2_globals); omap2_set_globals_memory(omap2_globals); omap2_set_globals_control(omap2_globals); omap2_set_globals_prcm(omap2_globals); @@ -279,6 +280,7 @@ static void __init __omap2_set_globals(void) #if defined(CONFIG_ARCH_OMAP2420) static struct omap_globals omap242x_globals = { + .class = OMAP242X_CLASS, .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000), .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE), .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE), @@ -297,6 +299,7 @@ void __init omap2_set_globals_242x(void) #if defined(CONFIG_ARCH_OMAP2430) static struct omap_globals omap243x_globals = { + .class = OMAP243X_CLASS, .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000), .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE), .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE), @@ -315,6 +318,7 @@ void __init omap2_set_globals_243x(void) #if defined(CONFIG_ARCH_OMAP3430) static struct omap_globals omap343x_globals = { + .class = OMAP343X_CLASS, .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000), .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE), .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE), diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h index e4cce2e..7a48fc9 100644 --- a/include/asm-arm/arch-omap/common.h +++ b/include/asm-arm/arch-omap/common.h @@ -50,6 +50,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, /* IO bases for various OMAP processors */ struct omap_globals { + u32 class; /* OMAP class to detect */ void __iomem *tap; /* Control module ID code */ void __iomem *sdrc; /* SDRAM Controller */ void __iomem *sms; /* SDRAM Memory Scheduler */ @@ -63,6 +64,7 @@ void omap2_set_globals_243x(void); void omap2_set_globals_343x(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ +void omap2_set_globals_tap(struct omap_globals *); void omap2_set_globals_memory(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h index 0f1cf78..fd1155e 100644 --- a/include/asm-arm/arch-omap/cpu.h +++ b/include/asm-arm/arch-omap/cpu.h @@ -348,9 +348,14 @@ IS_OMAP_TYPE(3430, 0x3430) get_sil_revision(system_rev) /* Various silicon macros defined here */ +#define OMAP242X_CLASS 0x24200000 #define OMAP2420_REV_ES1_0 0x24200000 #define OMAP2420_REV_ES2_0 0x24201000 + +#define OMAP243X_CLASS 0x24300000 #define OMAP2430_REV_ES1_0 0x24300000 + +#define OMAP343X_CLASS 0x34300000 #define OMAP3430_REV_ES1_0 0x34300000 #define OMAP3430_REV_ES2_0 0x34301000 #define OMAP3430_REV_ES2_1 0x34302000 -- 1.5.3.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 0/14] Big clean-up for multi-omap 2008-05-28 4:20 [PATCH 0/14] Big clean-up for multi-omap Tony Lindgren 2008-05-28 4:20 ` [PATCH 1/14] ARM: OMAP: Fix debug-macro for multi_omap Tony Lindgren @ 2008-05-30 21:41 ` Tony Lindgren 1 sibling, 0 replies; 16+ messages in thread From: Tony Lindgren @ 2008-05-30 21:41 UTC (permalink / raw) To: linux-omap * Tony Lindgren <tony@atomide.com> [080527 21:20]: > Hi all, > > Following patches clean up blockers for getting multi-omap closer > to working for omap2 like we have for omap1: > > - Remove __REG macros, use omap_read/write() instead > > - Split omap24xx sram code so no register rewriting is needed > > - Introduce struct omap_globals to allow early cpu detection to > work > > - Make PRM and CM registers work for multi-omap > > The __REG patches were posted earlier, but had some issues. They > should be fixed now. > > The first patch is to test primitive omap type detection with > DEBUG_LL. Could somebody please try it out on 15xx and make sure > you get output from DEBUG_LL? > > Once the DEBU_LL patch works on all omaps, we can use the similar > detection for multi-omap non-optimized get_irq_nr_and_base too :) > > These patches are against current linux-omap tree, I pushed few > fixes there so you pull before trying out these patches. I've pushed this series refreshed and in slightly different order. I also left out the DEBUG_LL patch for now. Regards, Tony ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2008-05-30 21:41 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2008-05-28 4:20 [PATCH 0/14] Big clean-up for multi-omap Tony Lindgren 2008-05-28 4:20 ` [PATCH 1/14] ARM: OMAP: Fix debug-macro for multi_omap Tony Lindgren 2008-05-28 4:20 ` [PATCH 2/14] CF: Change omap_cf.c to use omap_readw/writew instead of __REG for multi-omap Tony Lindgren 2008-05-28 4:20 ` [PATCH 3/14] USB: Change omap USB code to use omap_read/write " Tony Lindgren 2008-05-28 4:20 ` [PATCH 4/14] ARM: OMAP: Change __REG access to omap/read write for traffic controller Tony Lindgren 2008-05-28 4:20 ` [PATCH 5/14] musb_hdrc: Change __REG access to omap_read/write for multi-boot Tony Lindgren 2008-05-28 4:20 ` [PATCH 6/14] ARM: OMAP: Remove __REG access for multi-omap Tony Lindgren 2008-05-28 4:20 ` [PATCH 7/14] ARM: OMAP: Split sleep24xx.S into sleep242x.S and sleep243x.S Tony Lindgren 2008-05-28 4:20 ` [PATCH 8/14] ARM: OMAP: Split sram24xx.S into sram242x.S and sram243x.S Tony Lindgren 2008-05-28 4:20 ` [PATCH 9/14] ARM: OMAP: Remove omap_sram_patch_va Tony Lindgren 2008-05-28 4:20 ` [PATCH 10/14] ARM: OMAP: Introduce omap_globals and prcm access functions for multi-omap Tony Lindgren 2008-05-28 4:20 ` [PATCH 11/14] ARM: OMAP: Remove OMAP_PRM_REGADDR Tony Lindgren 2008-05-28 4:20 ` [PATCH 12/14] ARM: OMAP: Remove OMAP_CM_REGADDR for multi-boot Tony Lindgren 2008-05-28 4:20 ` [PATCH 13/14] ARM: OMAP: Change to use CM offsets for clocks for multi-omap Tony Lindgren 2008-05-28 4:20 ` [PATCH 14/14] ARM: OMAP: Use omap_globals for CPU detection " Tony Lindgren 2008-05-30 21:41 ` [PATCH 0/14] Big clean-up " Tony Lindgren
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