[PATCH 0/4] OMAP3: fix powerdomain hardware save-and-restore support

[PATCH 0/4] OMAP3: fix powerdomain hardware save-and-restore support

[Paul Walmsley]

This series revises the support for automatic hardware-controlled
powerdomain context save-and-restore (SAR).  Previously, this was
partially handled through the clock framework; but handling it via the
powerdomain framework is a better solution.

The patches:

- add functions to the powerdomain code to enable and disable
  automatic SAR,

- move the USBHOST SAR support from the clock fw to the powerdomain
  layer,

- add support for USBTLL SAR,

- enable SAR for all powerdomains that support it upon powerdomain
  initialization.

Boot-tested on 3430SDP ES2.

Signed-off-by: Paul Walmsley <paul@pwsan.com> 

---

size:
   text    data     bss     dec     hex filename
3391246  156920  107144 3655310  37c68e vmlinux.3430sdp.orig
3391422  156872  107144 3655438  37c70e vmlinux.3430sdp.patched

 arch/arm/mach-omap2/clock34xx.h         |   12 -----
 arch/arm/mach-omap2/pm34xx.c            |    4 ++
 arch/arm/mach-omap2/powerdomain.c       |   68 +++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/powerdomains.h      |    3 +
 arch/arm/mach-omap2/powerdomains34xx.h  |   24 ++++++++++-
 include/asm-arm/arch-omap/powerdomain.h |   11 +++++
 6 files changed, 107 insertions(+), 15 deletions(-)

[PATCH 1/4] OMAP3 pwrdm: add hardware save-and-restore (SAR) support

[Paul Walmsley]

OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR).  Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1].  This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.

This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code.  Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar().  A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.

Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.


1.  For the USBHOST controller module, context loss occurs when the
    USBHOST powerdomain enters off-idle.  For USBTLL, context loss
    occurs either if CORE enters off-idle, or if the CORE logic is
    configured to turn off when CORE enters retention-idle (OSWR).
    34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/powerdomain.c       |   68 +++++++++++++++++++++++++++++++
 include/asm-arm/arch-omap/powerdomain.h |   11 +++++
 2 files changed, 79 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 3a8dae0..7615f9d 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1003,6 +1003,74 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm
+ * @pwrdm: struct powerdomain *
+ *
+ * Enable automatic context save-and-restore upon power state change
+ * for some devices in a powerdomain.  Warning: this only affects a
+ * subset of devices in a powerdomain; check the TRM closely.  Returns
+ * -EINVAL if the powerdomain pointer is null or if the powerdomain
+ * does not support automatic save-and-restore, or returns 0 upon
+ * success.
+ */
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
+{
+	if (!pwrdm)
+		return -EINVAL;
+
+	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
+		return -EINVAL;
+
+	pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
+		 pwrdm->name);
+
+	prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+			     pwrdm->prcm_offs, PM_PWSTCTRL);
+
+	return 0;
+}
+
+/**
+ * pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm
+ * @pwrdm: struct powerdomain *
+ *
+ * Disable automatic context save-and-restore upon power state change
+ * for some devices in a powerdomain.  Warning: this only affects a
+ * subset of devices in a powerdomain; check the TRM closely.  Returns
+ * -EINVAL if the powerdomain pointer is null or if the powerdomain
+ * does not support automatic save-and-restore, or returns 0 upon
+ * success.
+ */
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
+{
+	if (!pwrdm)
+		return -EINVAL;
+
+	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
+		return -EINVAL;
+
+	pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
+		 pwrdm->name);
+
+	prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
+			     pwrdm->prcm_offs, PM_PWSTCTRL);
+
+	return 0;
+}
+
+/**
+ * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
+ * @pwrdm: struct powerdomain *
+ *
+ * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore
+ * for some devices, or 0 if it does not.
+ */
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
+{
+	return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
+}
+
+/**
  * pwrdm_wait_transition - wait for powerdomain power transition to finish
  * @pwrdm: struct powerdomain * to wait for
  *
diff --git a/include/asm-arm/arch-omap/powerdomain.h b/include/asm-arm/arch-omap/powerdomain.h
index 39b7df6..0e79459 100644
--- a/include/asm-arm/arch-omap/powerdomain.h
+++ b/include/asm-arm/arch-omap/powerdomain.h
@@ -38,6 +38,10 @@
 #define PWRSTS_OFF_RET_ON	(PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
 
 
+/* Powerdomain flags */
+#define PWRDM_HAS_HDWR_SAR	(1 << 0) /* hardware save-and-restore support */
+
+
 /*
  * Number of memory banks that are power-controllable.	On OMAP3430, the
  * maximum is 4.
@@ -96,6 +100,9 @@ struct powerdomain {
 	/* Possible logic power states when pwrdm in RETENTION */
 	const u8 pwrsts_logic_ret;
 
+	/* Powerdomain flags */
+	const u8 flags;
+
 	/* Number of software-controllable memory banks in this powerdomain */
 	const u8 banks;
 
@@ -151,6 +158,10 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
+
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 
 #endif


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[PATCH 2/4] OMAP3: move USBHOST SAR handling from clock framework to powerdomain layer

[Paul Walmsley]

Remove usbhost_sar_fclk from the OMAP3 clock framework.  The bit that
the clock was tweaking doesn't actually enable or disable a clock; it
controls whether the hardware will save and restore USBHOST state
when the powerdomain changes state.  (That happens to coincidentally
enable a clock for the duration of the operation, hence the earlier
confusion.)

In place of the clock, mark the USBHOST powerdomain as supporting
hardware save-and-restore functionality.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clock34xx.h        |   12 ------------
 arch/arm/mach-omap2/powerdomains34xx.h |    1 +
 2 files changed, 1 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index b4dceea..2140463 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2231,17 +2231,6 @@ static struct clk usbhost_ick = {
 	.recalc		= &followparent_recalc,
 };
 
-static struct clk usbhost_sar_fck = {
-	.name		= "usbhost_sar_fck",
-	.parent		= &osc_sys_ck,
-	.init		= &omap2_init_clk_clkdm,
-	.enable_reg	= OMAP34XX_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
-	.enable_bit	= OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-	.flags		= CLOCK_IN_OMAP3430ES2,
-	.clkdm_name	= "usbhost_clkdm",
-	.recalc		= &followparent_recalc,
-};
-
 /* WKUP */
 
 static const struct clksel_rate usim_96m_rates[] = {
@@ -3189,7 +3178,6 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&usbhost_120m_fck,
 	&usbhost_48m_fck,
 	&usbhost_ick,
-	&usbhost_sar_fck,
 	&usim_fck,
 	&gpt1_fck,
 	&wkup_32k_fck,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 1e1146a..88f85ea 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -312,6 +312,7 @@ static struct powerdomain usbhost_pwrdm = {
 	.sleepdep_srcs	  = dss_per_usbhost_sleepdeps,
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRDM_POWER_RET,
+	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
 	.banks		  = 1,
 	.pwrsts_mem_ret	  = {
 		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */

[PATCH 3/4] OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)

[Paul Walmsley]

34xx TRM Delta G->H notes that the CORE powerdomain has a hardware
save-and-restore (SAR) control bit for the USBTLL module, similar to
the USBHOST powerdomain SAR bit.  Split the existing core_34xx struct
powerdomain into two structs, one for ES1 and one for ES2, and add the
PWRDM_HAS_HDWR_SAR flag to the ES2 powerdomain.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/powerdomains.h     |    3 ++-
 arch/arm/mach-omap2/powerdomains34xx.h |   23 +++++++++++++++++++++--
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 5ad9cb0..3152811 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -171,7 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
 	&iva2_pwrdm,
 	&mpu_34xx_pwrdm,
 	&neon_pwrdm,
-	&core_34xx_pwrdm,
+	&core_34xx_es1_pwrdm,
+	&core_34xx_es2_pwrdm,
 	&cam_pwrdm,
 	&dss_pwrdm,
 	&per_pwrdm,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 88f85ea..0c07bf7 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -200,12 +200,31 @@ static struct powerdomain mpu_34xx_pwrdm = {
 };
 
 /* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_pwrdm = {
+static struct powerdomain core_34xx_es1_pwrdm = {
 	.name		  = "core_pwrdm",
 	.prcm_offs	  = CORE_MOD,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
+	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.dep_bit	  = OMAP3430_EN_CORE_SHIFT,
+	.banks		  = 2,
+	.pwrsts_mem_ret	  = {
+		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
+		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
+	},
+	.pwrsts_mem_on	  = {
+		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+	},
+};
+
+/* No wkdeps or sleepdeps for 34xx core apparently */
+static struct powerdomain core_34xx_es2_pwrdm = {
+	.name		  = "core_pwrdm",
+	.prcm_offs	  = CORE_MOD,
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.dep_bit	  = OMAP3430_EN_CORE_SHIFT,
+	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
 	.banks		  = 2,
 	.pwrsts_mem_ret	  = {
 		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */

[PATCH 4/4] OMAP3 PM: enable hardware SAR for USBHOST, USBTLL modules

[Paul Walmsley]

Enable hardware save-and-restore for the CORE and USBHOST powerdomains
during PM layer initialization.  On OMAP3, this only affects the
USBTLL and USBHOST modules.

There is probably a sleep and wakeup latency penalty with these
enabled.  No one seems to have quantified it yet.  If the added
latency is measurable, an alternate approach would be to only enable
hardware save-and-restore if there are USB devices attached.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/pm34xx.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c7493f5..202c269 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -357,6 +357,10 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
 	pwrst->pwrdm = pwrdm;
 	pwrst->next_state = PWRDM_POWER_RET;
 	list_add(&pwrst->node, &pwrst_list);
+
+	if (pwrdm_has_hdwr_sar(pwrdm))
+		pwrdm_enable_hdwr_sar(pwrdm);
+
 	return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 }
 

Re: [PATCH 0/4] OMAP3: fix powerdomain hardware save-and-restore support

[Tony Lindgren]

* Paul Walmsley <paul@pwsan.com> [080626 03:17]:
> This series revises the support for automatic hardware-controlled
> powerdomain context save-and-restore (SAR).  Previously, this was
> partially handled through the clock framework; but handling it via the
> powerdomain framework is a better solution.
> 
> The patches:
> 
> - add functions to the powerdomain code to enable and disable
>   automatic SAR,
> 
> - move the USBHOST SAR support from the clock fw to the powerdomain
>   layer,
> 
> - add support for USBTLL SAR,
> 
> - enable SAR for all powerdomains that support it upon powerdomain
>   initialization.
> 
> Boot-tested on 3430SDP ES2.

Pushing these today.

Tony

> 
> Signed-off-by: Paul Walmsley <paul@pwsan.com> 
> 
> ---
> 
> size:
>    text    data     bss     dec     hex filename
> 3391246  156920  107144 3655310  37c68e vmlinux.3430sdp.orig
> 3391422  156872  107144 3655438  37c70e vmlinux.3430sdp.patched
> 
>  arch/arm/mach-omap2/clock34xx.h         |   12 -----
>  arch/arm/mach-omap2/pm34xx.c            |    4 ++
>  arch/arm/mach-omap2/powerdomain.c       |   68 +++++++++++++++++++++++++++++++
>  arch/arm/mach-omap2/powerdomains.h      |    3 +
>  arch/arm/mach-omap2/powerdomains34xx.h  |   24 ++++++++++-
>  include/asm-arm/arch-omap/powerdomain.h |   11 +++++
>  6 files changed, 107 insertions(+), 15 deletions(-)
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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