[PATCH 1/4] OMAP2/3 clock: clean up omap2_clk_wait_ready()

[PATCH 1/4] OMAP2/3 clock: clean up omap2_clk_wait_ready()

[Paul Walmsley]

Minor cleanup on omap2_clk_wait_ready() in preparation for DSS, SSI fix
patches.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clock.c |   26 ++++++++++++++------------
 1 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ed15868..57e3217 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -222,20 +222,22 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
  */
 static void omap2_clk_wait_ready(struct clk *clk)
 {
-	u32 bit, reg, other_reg, st_reg;
+	u32 bit;
+	unsigned long reg, other_reg, st_reg, prcm_mod, prcm_regid;
 
-	reg = (__force u32)clk->enable_reg;
-	if (((reg & 0xff) >= CM_FCLKEN1) &&
-	    ((reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
+	reg = (unsigned long)clk->enable_reg;
+	prcm_mod = reg & ~0xff;
+	prcm_regid = reg & 0xff;
+
+	if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
 		other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
-	else if (((reg & 0xff) >= CM_ICLKEN1) &&
-		 ((reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
+	else if (prcm_regid >= CM_ICLKEN1 && prcm_regid <= OMAP24XX_CM_ICLKEN4)
 		other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
 	else
 		return;
 
-	/* REVISIT: What are the appropriate exclusions for 34XX? */
-	/* No check for DSS or cam clocks */
+	/* No check for DSS or CAM clocks on 24xx */
+	/* REVISIT: This should check prcm_mod against CORE_MOD */
 	if (cpu_is_omap24xx() && (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
 		if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
 		    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
@@ -246,19 +248,19 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	/* REVISIT: What are the appropriate exclusions for 34XX? */
 	/* OMAP3: ignore DSS-mod clocks */
 	if (cpu_is_omap34xx() &&
-	    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
-	     (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
+	    (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
+	     (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
 	      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
 		return;
 
 	/* Check if both functional and interface clocks
 	 * are running. */
 	bit = 1 << clk->enable_bit;
-	if (!(__raw_readl((__force void __iomem *)other_reg) & bit))
+	if (!(__raw_readl((void __iomem *)other_reg) & bit))
 		return;
 	st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
 
-	omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);
+	omap2_wait_clock_ready((void __iomem *)st_reg, bit, clk->name);
 }
 
 /* Enables clock without considering parent dependencies or use count

[PATCH 2/4] OMAP3 clock: fix omap2_clk_wait_ready() for OMAP3430ES2+ DSS

[Paul Walmsley]

On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit.  This is a departure from previous silicon,
which only had an initiator standby bit.

This means we need to test the target idle bit after enabling
dss1_alwon_fclk.  Previous clock code has done the wrong thing since ES2
came out: it's either tested the wrong bit, causing

    Clock dss1_alwon_fck failed to enable in 100000 tries

messages, or not tested anything at all, causing crashes during DISPC
initialization with:

    Unhandled fault: external abort on non-linefetch (0x1028)

This patch modifies omap2_clk_wait_ready() to wait for the DSS to become
accessible after dss1_alwon_fclk, dss_l3_iclk, and dss_l4_iclk are enabled.

Thanks to Anand Gadiyar <gadiyar@ti.com> for identifying one of the
problem patches, Koen Kooi <k.kooi@student.utwente.nl> for testing a
previous version of this patch, and Dirk Behme
<dirk.behme@googlemail.com> for review of a previous version.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clock.c           |   34 +++++++++++++++++++++++++++++----
 arch/arm/mach-omap2/cm-regbits-34xx.h |    4 +++-
 2 files changed, 33 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 57e3217..343477b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -246,11 +246,27 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	}
 
 	/* REVISIT: What are the appropriate exclusions for 34XX? */
-	/* OMAP3: ignore DSS-mod clocks */
 	if (cpu_is_omap34xx() &&
-	    (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
-	     (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
-	      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
+	    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
+
+		/* 3430ES1 DSS has no target idlest bits */
+		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
+			return;
+
+		/*
+		 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
+		 * dss_l3_iclk, dss_l4_iclk) are enabled
+		 */
+		if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
+			return;
+
+	}
+
+	/* REVISIT: SSI has a target idlest bit on OMAP3 */
+	/* REVISIT: This could accidentally exclude other clocks also */
+	if (cpu_is_omap34xx() &&
+	    prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
+	    clk->enable_bit == OMAP3430_EN_SSI_SHIFT)
 		return;
 
 	/* Check if both functional and interface clocks
@@ -258,6 +274,16 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	bit = 1 << clk->enable_bit;
 	if (!(__raw_readl((void __iomem *)other_reg) & bit))
 		return;
+
+	/*
+	 * OMAP3430ES2 DSS target idlest bit is at a different shift than
+	 * the corresponding {I,F}CLKEN bits
+	 */
+	if (cpu_is_omap34xx() &&
+	    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
+	    clk->enable_bit == OMAP3430_EN_DSS1_SHIFT)
+		bit = OMAP3430ES2_ST_DSS_IDLE;
+
 	st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
 
 	omap2_wait_clock_ready((void __iomem *)st_reg, bit, clk->name);
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6ec66f4..946c552 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -500,7 +500,9 @@
 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
 
 /* CM_IDLEST_DSS */
-#define OMAP3430_ST_DSS					(1 << 0)
+#define OMAP3430ES2_ST_DSS_IDLE				(1 << 1)
+#define OMAP3430ES2_ST_DSS_STDBY			(1 << 0)
+#define OMAP3430ES1_ST_DSS				(1 << 0)
 
 /* CM_AUTOIDLE_DSS */
 #define OMAP3430_AUTO_DSS				(1 << 0)

[PATCH 3/4] OMAP3 clock: OMAP3430ES2+ has SSI target idlest bit

[Paul Walmsley]

On OMAP3430ES2+, SSI has both an initiator standby CM_IDLEST bit, and a
target idle CM_IDLEST bit.  This is a departure from previous silicon,
which only had an initiator standby bit.

This means that omap2_clk_wait_ready() needs to wait for the SSI
module to indicate readiness after both SSI interface and functional
clocks are enabled.

Thanks to Igor Stoppa <igor.stoppa@nokia.com>, Richard Woodruff
<r-woodruff2@ti.com>, and Jouni Högander <jouni.hogander@nokia.com> for
help with this portion of the patch.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clock.c           |   59 ++++++++++++++++++++-------------
 arch/arm/mach-omap2/cm-regbits-34xx.h |    3 +-
 2 files changed, 38 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 343477b..59b042f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -246,28 +246,31 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	}
 
 	/* REVISIT: What are the appropriate exclusions for 34XX? */
-	if (cpu_is_omap34xx() &&
-	    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
+	if (cpu_is_omap34xx()) {
 
-		/* 3430ES1 DSS has no target idlest bits */
-		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
+		/* SSI */
+		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
+		    prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
+		    (reg & 0x0f) == 0 &&
+		    clk->enable_bit == OMAP3430_EN_SSI_SHIFT)
 			return;
 
-		/*
-		 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
-		 * dss_l3_iclk, dss_l4_iclk) are enabled
-		 */
-		if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
-			return;
+		/* DSS */
+		if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
 
-	}
+			/* 3430ES1 DSS has no target idlest bits */
+			if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
+				return;
 
-	/* REVISIT: SSI has a target idlest bit on OMAP3 */
-	/* REVISIT: This could accidentally exclude other clocks also */
-	if (cpu_is_omap34xx() &&
-	    prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
-	    clk->enable_bit == OMAP3430_EN_SSI_SHIFT)
-		return;
+			/*
+			 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
+			 * dss_l3_iclk, dss_l4_iclk) are enabled
+			 */
+			if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
+				return;
+		}
+
+	}
 
 	/* Check if both functional and interface clocks
 	 * are running. */
@@ -276,13 +279,23 @@ static void omap2_clk_wait_ready(struct clk *clk)
 		return;
 
 	/*
-	 * OMAP3430ES2 DSS target idlest bit is at a different shift than
-	 * the corresponding {I,F}CLKEN bits
+	 * OMAP3430ES2+ has target idlest bits at unusual offsets for
+	 * modules with both initiator and target agents
 	 */
-	if (cpu_is_omap34xx() &&
-	    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
-	    clk->enable_bit == OMAP3430_EN_DSS1_SHIFT)
-		bit = OMAP3430ES2_ST_DSS_IDLE;
+	if (cpu_is_omap34xx()) {
+
+		/* SSI */
+		if (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
+		    (reg & 0x0f) == 0 &&
+		    clk->enable_bit == OMAP3430_EN_SSI_SHIFT)
+			bit = OMAP3430ES2_ST_SSI_IDLE;
+
+		/* DSS */
+		if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
+		    clk->enable_bit == OMAP3430_EN_DSS1_SHIFT)
+			bit = OMAP3430ES2_ST_DSS_IDLE;
+
+	}
 
 	st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
 
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 946c552..971b9ad 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -190,11 +190,12 @@
 #define OMAP3430_ST_MSPRO				(1 << 23)
 #define OMAP3430_ST_HDQ					(1 << 22)
 #define OMAP3430ES1_ST_FAC				(1 << 8)
+#define OMAP3430ES2_ST_SSI_IDLE				(1 << 8)
 #define OMAP3430ES1_ST_MAILBOXES			(1 << 7)
 #define OMAP3430_ST_OMAPCTRL				(1 << 6)
 #define OMAP3430_ST_SDMA				(1 << 2)
 #define OMAP3430_ST_SDRC				(1 << 1)
-#define OMAP3430_ST_SSI					(1 << 0)
+#define OMAP3430_ST_SSI_STDBY				(1 << 0)
 
 /* CM_IDLEST2_CORE */
 #define OMAP3430_ST_PKA					(1 << 4)


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[PATCH 4/4] OMAP2 clock: check register address in omap2_clk_wait_ready()

[Paul Walmsley]

The test in omap2_clk_wait_ready() for DSS or CAM clocks didn't
verify that the PRCM {F,I}CLKEN1 register was in the CORE powerdomain.
Add this check in.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clock.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 59b042f..577be44 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -236,13 +236,17 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	else
 		return;
 
-	/* No check for DSS or CAM clocks on 24xx */
-	/* REVISIT: This should check prcm_mod against CORE_MOD */
-	if (cpu_is_omap24xx() && (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+	/* 24xx: DSS and CAM have no idlest bits for their target agents */
+	if (cpu_is_omap24xx() &&
+	    (prcm_mod == OMAP2420_CM_REGADDR(CORE_MOD, 0) ||
+	     prcm_mod == OMAP2430_CM_REGADDR(CORE_MOD, 0)) &&
+	    (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+
 		if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
 		    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
 		    clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
 			return;
+
 	}
 
 	/* REVISIT: What are the appropriate exclusions for 34XX? */

[PATCH 0/4] OMAP2/3 clock: fix some bugs in omap2_clk_wait_ready()

[Paul Walmsley]

This patch series fixes some bugs in omap2_clk_wait_ready().  This function
waits for an OMAP module to become ready after both its functional and
interface clocks are enabled.  Not all OMAP modules support this process.

In particular, this series:

- does some minor code cleanup,

- waits for DSS to become available on OMAP3430ES2+,

- waits for SSI to become available on OMAP3430ES2+,

- and adds a test for the OMAP2 portion of the code to verify that the
  clocks it tests for are in the CORE powerdomain.

These patches are possible due to the efforts of several people; credits
are listed in the individual patch descriptions.

Boot-tested on 3430SDP ES2 and 2430SDP.  


- Paul


---

size:
   text    data     bss     dec     hex filename
3391246  156920  107144 3655310  37c68e vmlinux.3430sdp.orig
3391374  156920  107144 3655438  37c70e vmlinux.3430sdp.fixed

 arch/arm/mach-omap2/clock.c           |   79 ++++++++++++++++++++++++++-------
 arch/arm/mach-omap2/cm-regbits-34xx.h |    7 ++-
 2 files changed, 67 insertions(+), 19 deletions(-)

RE: [PATCH 0/4] OMAP2/3 clock: fix some bugs in omap2_clk_wait_ready()

[Pandita, Vikram]

Paul

> To: linux-omap@vger.kernel.org
> Cc: Gadiyar, Anand; k.kooi@student.utwente.nl; dirk.behme@googlemail.com;
> igor.stoppa@nokia.com; Woodruff, Richard; jouni.hogander@nokia.comD
> Subject: [PATCH 0/4] OMAP2/3 clock: fix some bugs in
> omap2_clk_wait_ready()
>
> This patch series fixes some bugs in omap2_clk_wait_ready().  This
> function

I hope this has fixed:
"Clock usbhost_48m_fck didn't enable in 100000 tries"


> waits for an OMAP module to become ready after both its functional and
> interface clocks are enabled.  Not all OMAP modules support this process.
>

Re: [PATCH 0/4] OMAP2/3 clock: fix some bugs in omap2_clk_wait_ready()

[Tony Lindgren]

* Paul Walmsley <paul@pwsan.com> [080626 10:12]:
> This patch series fixes some bugs in omap2_clk_wait_ready().  This function
> waits for an OMAP module to become ready after both its functional and
> interface clocks are enabled.  Not all OMAP modules support this process.
> 
> In particular, this series:
> 
> - does some minor code cleanup,
> 
> - waits for DSS to become available on OMAP3430ES2+,
> 
> - waits for SSI to become available on OMAP3430ES2+,
> 
> - and adds a test for the OMAP2 portion of the code to verify that the
>   clocks it tests for are in the CORE powerdomain.
> 
> These patches are possible due to the efforts of several people; credits
> are listed in the individual patch descriptions.
> 
> Boot-tested on 3430SDP ES2 and 2430SDP.  

Pushing this series today.

Tony

> 
> 
> - Paul
> 
> 
> ---
> 
> size:
>    text    data     bss     dec     hex filename
> 3391246  156920  107144 3655310  37c68e vmlinux.3430sdp.orig
> 3391374  156920  107144 3655438  37c70e vmlinux.3430sdp.fixed
> 
>  arch/arm/mach-omap2/clock.c           |   79 ++++++++++++++++++++++++++-------
>  arch/arm/mach-omap2/cm-regbits-34xx.h |    7 ++-
>  2 files changed, 67 insertions(+), 19 deletions(-)
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [PATCH 0/4] OMAP2/3 clock: fix some bugs in omap2_clk_wait_ready()

[Paul Walmsley]

On Thu, 26 Jun 2008, Pandita, Vikram wrote:

> > To: linux-omap@vger.kernel.org
> > Cc: Gadiyar, Anand; k.kooi@student.utwente.nl; dirk.behme@googlemail.com;
> > igor.stoppa@nokia.com; Woodruff, Richard; jouni.hogander@nokia.comD
> > Subject: [PATCH 0/4] OMAP2/3 clock: fix some bugs in
> > omap2_clk_wait_ready()
> >
> > This patch series fixes some bugs in omap2_clk_wait_ready().  This
> > function
> 
> I hope this has fixed:
> "Clock usbhost_48m_fck didn't enable in 100000 tries"

First I've heard of it, Vikram.  Tell me more.


- Paul

RE: [PATCH 0/4] OMAP2/3 clock: fix some bugs in omap2_clk_wait_ready()

[Felipe Balbi]

Hi,

On Thu, 26 Jun 2008 11:13:10 -0600 (MDT), Paul Walmsley <paul@pwsan.com>
wrote:
>> I hope this has fixed:
>> "Clock usbhost_48m_fck didn't enable in 100000 tries"
> 
> First I've heard of it, Vikram.  Tell me more.

afaict this was fixed by a patch from Jouni Högander,
the problem was basically a shift value when checking
if the clock was already enabled.

Not sure about it, but that's what came to my mind by
reading the mail.

-- 
Best Regards,

Felipe Balbi
http://blog.felipebalbi.com
me@felipebalbi.com

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RE: [PATCH 0/4] OMAP2/3 clock: fix some bugs in omap2_clk_wait_ready()

[Paul Walmsley]

On Thu, 26 Jun 2008, Pandita, Vikram wrote:

> I hope this has fixed:
> "Clock usbhost_48m_fck didn't enable in 100000 tries"

This patch has been in the works for several days.  Maybe it fixes the 
problem you reported?  Please let me know either way.


- Paul

Fix some bugs in the OMAP3 clock tree pertaining to the 96MHz clocks.

From: Paul Walmsley <paul@pwsan.com>

The 96MHz portion of the clock tree should now have reasonable
fidelity to the 34xx TRM Rev I.

One remaining question mark: it's not clear exactly which 96MHz source
clock the USIM uses.  This patch sticks with the previous setting, which
seems reasonable.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---

 arch/arm/mach-omap2/clock34xx.h       |   60 +++++++++++++++++++++------------
 arch/arm/mach-omap2/cm-regbits-34xx.h |    8 +++-
 2 files changed, 44 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 1d40053..f2ccd5e 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -658,6 +658,12 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = {
 	{ .parent = NULL }
 };
 
+/*
+ * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
+ * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
+ * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
+ * CM_96K_(F)CLK.
+ */
 static struct clk omap_96m_alwon_fck = {
 	.name		= "omap_96m_alwon_fck",
 	.parent		= &dpll4_m2x2_ck,
@@ -666,31 +672,41 @@ static struct clk omap_96m_alwon_fck = {
 	.clksel_mask	= OMAP3430_ST_PERIPH_CLK_MASK,
 	.clksel		= omap_96m_alwon_fck_clksel,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-				 PARENT_CONTROLS_CLOCK,
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 
-static struct clk omap_96m_fck = {
-	.name		= "omap_96m_fck",
+static struct clk cm_96m_fck = {
+	.name		= "cm_96m_fck",
 	.parent		= &omap_96m_alwon_fck,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 
-static const struct clksel cm_96m_fck_clksel[] = {
-	{ .parent = &sys_ck,	    .rates = dpll_bypass_rates },
-	{ .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+static const struct clksel_rate omap_96m_dpll_rates[] = {
+	{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 0 }
+};
+
+static const struct clksel_rate omap_96m_sys_rates[] = {
+	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+	{ .div = 0 }
+};
+
+static const struct clksel omap_96m_fck_clksel[] = {
+	{ .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
+	{ .parent = &sys_ck,	 .rates = omap_96m_sys_rates },
 	{ .parent = NULL }
 };
 
-static struct clk cm_96m_fck = {
-	.name		= "cm_96m_fck",
-	.parent		= &dpll4_m2x2_ck,
+static struct clk omap_96m_fck = {
+	.name		= "omap_96m_fck",
+	.parent		= &sys_ck,
 	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
-	.clksel_mask	= OMAP3430_ST_PERIPH_CLK_MASK,
-	.clksel		= cm_96m_fck_clksel,
+	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+	.clksel_mask	= OMAP3430_SOURCE_96M_MASK,
+	.clksel		= omap_96m_fck_clksel,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
@@ -758,14 +774,14 @@ static struct clk omap_54m_fck = {
 	.name		= "omap_54m_fck",
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-	.clksel_mask	= OMAP3430_SOURCE_54M,
+	.clksel_mask	= OMAP3430_SOURCE_54M_MASK,
 	.clksel		= omap_54m_clksel,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 
-static const struct clksel_rate omap_48m_96md2_rates[] = {
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
 	{ .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 	{ .div = 0 }
 };
@@ -776,7 +792,7 @@ static const struct clksel_rate omap_48m_alt_rates[] = {
 };
 
 static const struct clksel omap_48m_clksel[] = {
-	{ .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
+	{ .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 	{ .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 	{ .parent = NULL }
 };
@@ -785,7 +801,7 @@ static struct clk omap_48m_fck = {
 	.name		= "omap_48m_fck",
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-	.clksel_mask	= OMAP3430_SOURCE_48M,
+	.clksel_mask	= OMAP3430_SOURCE_48M_MASK,
 	.clksel		= omap_48m_clksel,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 				PARENT_CONTROLS_CLOCK,
@@ -973,10 +989,10 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
 };
 
 static const struct clksel clkout2_src_clksel[] = {
-	{ .parent = &core_ck,		  .rates = clkout2_src_core_rates },
-	{ .parent = &sys_ck,		  .rates = clkout2_src_sys_rates },
-	{ .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
-	{ .parent = &omap_54m_fck,	  .rates = clkout2_src_54m_rates },
+	{ .parent = &core_ck,		.rates = clkout2_src_core_rates },
+	{ .parent = &sys_ck,		.rates = clkout2_src_sys_rates },
+	{ .parent = &cm_96m_fck,	.rates = clkout2_src_96m_rates },
+	{ .parent = &omap_54m_fck,	.rates = clkout2_src_54m_rates },
 	{ .parent = NULL }
 };
 
@@ -2804,8 +2820,8 @@ static struct clk mcbsp4_ick = {
 };
 
 static const struct clksel mcbsp_234_clksel[] = {
-	{ .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
-	{ .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
+	{ .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+	{ .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
 	{ .parent = NULL }
 };
 
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 971b9ad..07ab180 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -457,8 +457,12 @@
 #define OMAP3430_CORE_DPLL_MULT_MASK			(0x7ff << 16)
 #define OMAP3430_CORE_DPLL_DIV_SHIFT			8
 #define OMAP3430_CORE_DPLL_DIV_MASK			(0x7f << 8)
-#define OMAP3430_SOURCE_54M				(1 << 5)
-#define OMAP3430_SOURCE_48M				(1 << 3)
+#define OMAP3430_SOURCE_96M_SHIFT			6
+#define OMAP3430_SOURCE_96M_MASK			(1 << 6)
+#define OMAP3430_SOURCE_54M_SHIFT			5
+#define OMAP3430_SOURCE_54M_MASK			(1 << 5)
+#define OMAP3430_SOURCE_48M_SHIFT			3
+#define OMAP3430_SOURCE_48M_MASK			(1 << 3)
 
 /* CM_CLKSEL2_PLL */
 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8

RE: [PATCH 0/4] OMAP2/3 clock: fix some bugs in omap2_clk_wait_ready()

[Paul Walmsley]

On Thu, 26 Jun 2008, Pandita, Vikram wrote:

> I hope this has fixed:
> "Clock usbhost_48m_fck didn't enable in 100000 tries"

Just to follow up on this.  I was able to reproduce this with a Beagle, 
and have a patch for it coming soon.  In the interim, the above message 
shouldn't cause any problems, except perhaps delaying boot slightly.


- Paul