* [PATCH 1/9] OMAP2 SDRC: move mach-omap2/memory.h into include/asm-arm/arch-omap/sdrc.h
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
@ 2008-07-08 2:54 ` Paul Walmsley
2008-07-08 2:54 ` [PATCH 2/9] OMAP2 SDRC: rename memory.c to sdrc2xxx.c Paul Walmsley
` (9 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:54 UTC (permalink / raw)
To: linux-omap
Move the contents of the arch/arm/mach-omap2/memory.h file to the
existing include/asm-arm/arch-omap/sdrc.h file, and remove memory.h.
Modify files which include memory.h to include asm/arch/sdrc.h instead.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock.c | 2 +-
arch/arm/mach-omap2/clock24xx.c | 2 +-
arch/arm/mach-omap2/clock34xx.c | 2 +-
arch/arm/mach-omap2/gpmc.c | 2 +-
arch/arm/mach-omap2/io.c | 4 ++--
arch/arm/mach-omap2/memory.c | 9 +++++++-
arch/arm/mach-omap2/memory.h | 43 --------------------------------------
include/asm-arm/arch-omap/gpmc.h | 1 +
include/asm-arm/arch-omap/sdrc.h | 39 ++++++++++++++++++++++++++++------
9 files changed, 47 insertions(+), 57 deletions(-)
delete mode 100644 arch/arm/mach-omap2/memory.h
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 577be44..794059f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -31,7 +31,7 @@
#include <asm/arch/prcm.h>
#include <asm/div64.h>
-#include "memory.h"
+#include <asm/arch/sdrc.h>
#include "sdrc.h"
#include "clock.h"
#include "prm.h"
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 54cc6e1..aa3027c 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -33,7 +33,7 @@
#include <asm/arch/sram.h>
#include <asm/div64.h>
-#include "memory.h"
+#include <asm/arch/sdrc.h>
#include "clock.h"
#include "clock24xx.h"
#include "prm.h"
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6831ae9..482f05c 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -32,7 +32,7 @@
#include <asm/div64.h>
#include <asm/bitops.h>
-#include "memory.h"
+#include <asm/arch/sdrc.h>
#include "clock.h"
#include "clock34xx.h"
#include "prm.h"
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 83984f7..7e9457d 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -23,7 +23,7 @@
#include <asm/mach-types.h>
#include <asm/arch/gpmc.h>
-#include "memory.h"
+#include <asm/arch/sdrc.h>
/* GPMC register offsets */
#define GPMC_REVISION 0x00
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 314994b..4aa1abf 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -26,8 +26,8 @@
#include <asm/arch/mux.h>
#include <asm/arch/omapfb.h>
#include <asm/arch/sram.h>
-
-#include "memory.h"
+#include <asm/arch/sdrc.h>
+#include <asm/arch/gpmc.h>
#include "clock.h"
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 2ad29fd..176658f 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -30,9 +30,16 @@
#include "prm.h"
-#include "memory.h"
+#include <asm/arch/sdrc.h>
#include "sdrc.h"
+/* Memory timing, DLL mode flags */
+#define M_DDR 1
+#define M_LOCK_CTRL (1 << 2)
+#define M_UNLOCK 0
+#define M_LOCK 1
+
+
void __iomem *omap2_sdrc_base;
void __iomem *omap2_sms_base;
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
deleted file mode 100644
index bb3db80..0000000
--- a/arch/arm/mach-omap2/memory.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/memory.h
- *
- * Interface for memory timing related functions for OMAP24XX
- *
- * Copyright (C) 2005 Texas Instruments Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Copyright (C) 2005 Nokia Corporation
- * Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
-#define ARCH_ARM_MACH_OMAP2_MEMORY_H
-
-/* Memory timings */
-#define M_DDR 1
-#define M_LOCK_CTRL (1 << 2)
-#define M_UNLOCK 0
-#define M_LOCK 1
-
-struct memory_timings {
- u32 m_type; /* ddr = 1, sdr = 0 */
- u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
- u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
- u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
- u32 base_cs; /* base chip select to use for calculations */
-};
-
-extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
-extern u32 omap2_memory_get_slow_dll_ctrl(void);
-extern u32 omap2_memory_get_fast_dll_ctrl(void);
-extern u32 omap2_memory_get_type(void);
-u32 omap2_dll_force_needed(void);
-u32 omap2_reprogram_sdrc(u32 level, u32 force);
-void __init omap2_init_memory(void);
-void __init gpmc_init(void);
-
-#endif
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
index 53dc246..a3df76a 100644
--- a/include/asm-arm/arch-omap/gpmc.h
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -99,5 +99,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
extern void gpmc_cs_free(int cs);
extern int gpmc_cs_set_reserved(int cs, int reserved);
extern int gpmc_cs_reserved(int cs);
+extern void __init gpmc_init(void);
#endif
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
index 660da4d..0edce1c 100644
--- a/include/asm-arm/arch-omap/sdrc.h
+++ b/include/asm-arm/arch-omap/sdrc.h
@@ -4,10 +4,12 @@
/*
* OMAP2/3 SDRC/SMS register definitions
*
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
*
- * Written by Paul Walmsley
+ * Tony Lindgren
+ * Paul Walmsley
+ * Richard Woodruff
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -64,14 +66,37 @@
* SMS register access
*/
-
-#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
-#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
-#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+#define OMAP242X_SMS_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
/* SMS register offsets - read/write with sms_{read,write}_reg() */
#define SMS_SYSCONFIG 0x010
/* REVISIT: fill in other SMS registers here */
+
+#ifndef __ASSEMBLER__
+
+struct memory_timings {
+ u32 m_type; /* ddr = 1, sdr = 0 */
+ u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
+ u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
+ u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
+ u32 base_cs; /* base chip select to use for calculations */
+};
+
+extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
+extern u32 omap2_memory_get_slow_dll_ctrl(void);
+extern u32 omap2_memory_get_fast_dll_ctrl(void);
+extern u32 omap2_memory_get_type(void);
+u32 omap2_dll_force_needed(void);
+u32 omap2_reprogram_sdrc(u32 level, u32 force);
+void __init omap2_init_memory(void);
+
+#endif
+
#endif
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 2/9] OMAP2 SDRC: rename memory.c to sdrc2xxx.c
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
2008-07-08 2:54 ` [PATCH 1/9] OMAP2 SDRC: move mach-omap2/memory.h into include/asm-arm/arch-omap/sdrc.h Paul Walmsley
@ 2008-07-08 2:54 ` Paul Walmsley
2008-07-08 2:54 ` [PATCH 3/9] OMAP2 SDRC: separate common OMAP2/3 code from OMAP2xxx code Paul Walmsley
` (8 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:54 UTC (permalink / raw)
To: linux-omap
Rename arch/arm/mach-omap2/memory.c to arch/arm/mach-omap2/sdrc2xxx.c, since
it contains exclusively SDRAM-related functions. Most of the functions
are also OMAP2xxx-specific - those which are common will be separated out
in a following patch.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/Makefile | 2
arch/arm/mach-omap2/memory.c | 186 ----------------------------------------
arch/arm/mach-omap2/sdrc2xxx.c | 185 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 186 insertions(+), 187 deletions(-)
delete mode 100644 arch/arm/mach-omap2/memory.c
create mode 100644 arch/arm/mach-omap2/sdrc2xxx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7c46cba..ad70a15 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
#
# Common support
-obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
+obj-y := irq.o id.o io.o sdrc2xxx.o control.o prcm.o clock.o mux.o \
devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
clockdomain.o
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
deleted file mode 100644
index 176658f..0000000
--- a/arch/arm/mach-omap2/memory.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/memory.c
- *
- * Memory timing related functions for OMAP24XX
- *
- * Copyright (C) 2005 Texas Instruments Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Copyright (C) 2005 Nokia Corporation
- * Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
-
-#include "prm.h"
-
-#include <asm/arch/sdrc.h>
-#include "sdrc.h"
-
-/* Memory timing, DLL mode flags */
-#define M_DDR 1
-#define M_LOCK_CTRL (1 << 2)
-#define M_UNLOCK 0
-#define M_LOCK 1
-
-
-void __iomem *omap2_sdrc_base;
-void __iomem *omap2_sms_base;
-
-static struct memory_timings mem_timings;
-static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
-
-u32 omap2_memory_get_slow_dll_ctrl(void)
-{
- return mem_timings.slow_dll_ctrl;
-}
-
-u32 omap2_memory_get_fast_dll_ctrl(void)
-{
- return mem_timings.fast_dll_ctrl;
-}
-
-u32 omap2_memory_get_type(void)
-{
- return mem_timings.m_type;
-}
-
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compensate for the shifted DLL value in unlock mode.
- */
-u32 omap2_dll_force_needed(void)
-{
- /* dlla and dllb are a set */
- u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
-
- if ((dll_state & (1 << 2)) == (1 << 2))
- return 1;
- else
- return 0;
-}
-
-/*
- * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
- * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
- * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
- */
-u32 omap2_reprogram_sdrc(u32 level, u32 force)
-{
- u32 dll_ctrl, m_type;
- u32 prev = curr_perf_level;
- unsigned long flags;
-
- if ((curr_perf_level == level) && !force)
- return prev;
-
- if (level == CORE_CLK_SRC_DPLL) {
- dll_ctrl = omap2_memory_get_slow_dll_ctrl();
- } else if (level == CORE_CLK_SRC_DPLL_X2) {
- dll_ctrl = omap2_memory_get_fast_dll_ctrl();
- } else {
- return prev;
- }
-
- m_type = omap2_memory_get_type();
-
- local_irq_save(flags);
- prm_write_mod_reg(0xffff, OMAP24XX_GR_MOD,
- OMAP24XX_PRCM_VOLTSETUP_OFFSET);
- omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
- curr_perf_level = level;
- local_irq_restore(flags);
-
- return prev;
-}
-
-void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
-{
- unsigned long dll_cnt;
- u32 fast_dll = 0;
-
- mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
-
- /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
- * In the case of 2422, its ok to use CS1 instead of CS0.
- */
- if (cpu_is_omap2422())
- mem_timings.base_cs = 1;
- else
- mem_timings.base_cs = 0;
-
- if (mem_timings.m_type != M_DDR)
- return;
-
- /* With DDR we need to determine the low frequency DLL value */
- if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
- mem_timings.dll_mode = M_UNLOCK;
- else
- mem_timings.dll_mode = M_LOCK;
-
- if (mem_timings.base_cs == 0) {
- fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
- dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
- } else {
- fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
- dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
- }
- if (force_lock_to_unlock_mode) {
- fast_dll &= ~0xff00;
- fast_dll |= dll_cnt; /* Current lock mode */
- }
- /* set fast timings with DLL filter disabled */
- mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
-
- /* No disruptions, DDR will be offline & C-ABI not followed */
- omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
- mem_timings.fast_dll_ctrl,
- mem_timings.base_cs,
- force_lock_to_unlock_mode);
- mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
-
- /* Turn status into unlock ctrl */
- mem_timings.slow_dll_ctrl |=
- ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
-
- /* 90 degree phase for anything below 133Mhz + disable DLL filter */
- mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
-}
-
-void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
-{
- omap2_sdrc_base = omap2_globals->sdrc;
- omap2_sms_base = omap2_globals->sms;
-}
-
-/* turn on smart idle modes for SDRAM scheduler and controller */
-void __init omap2_init_memory(void)
-{
- u32 l;
-
- l = sms_read_reg(SMS_SYSCONFIG);
- l &= ~(0x3 << 3);
- l |= (0x2 << 3);
- sms_write_reg(l, SMS_SYSCONFIG);
-
- l = sdrc_read_reg(SDRC_SYSCONFIG);
- l &= ~(0x3 << 3);
- l |= (0x2 << 3);
- sdrc_write_reg(l, SDRC_SYSCONFIG);
-}
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
new file mode 100644
index 0000000..1dc1425
--- /dev/null
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -0,0 +1,185 @@
+/*
+ * linux/arch/arm/mach-omap2/memory.c
+ *
+ * Memory timing related functions for OMAP24XX
+ *
+ * Copyright (C) 2005 Texas Instruments Inc.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+
+#include "prm.h"
+
+#include <asm/arch/sdrc.h>
+#include "sdrc.h"
+
+/* Memory timing, DLL mode flags */
+#define M_DDR 1
+#define M_LOCK_CTRL (1 << 2)
+#define M_UNLOCK 0
+#define M_LOCK 1
+
+
+void __iomem *omap2_sdrc_base;
+void __iomem *omap2_sms_base;
+
+static struct memory_timings mem_timings;
+static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
+
+u32 omap2_memory_get_slow_dll_ctrl(void)
+{
+ return mem_timings.slow_dll_ctrl;
+}
+
+u32 omap2_memory_get_fast_dll_ctrl(void)
+{
+ return mem_timings.fast_dll_ctrl;
+}
+
+u32 omap2_memory_get_type(void)
+{
+ return mem_timings.m_type;
+}
+
+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compensate for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+ /* dlla and dllb are a set */
+ u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+
+ if ((dll_state & (1 << 2)) == (1 << 2))
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
+ * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
+ * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ */
+u32 omap2_reprogram_sdrc(u32 level, u32 force)
+{
+ u32 dll_ctrl, m_type;
+ u32 prev = curr_perf_level;
+ unsigned long flags;
+
+ if ((curr_perf_level == level) && !force)
+ return prev;
+
+ if (level == CORE_CLK_SRC_DPLL)
+ dll_ctrl = omap2_memory_get_slow_dll_ctrl();
+ else if (level == CORE_CLK_SRC_DPLL_X2) {
+ dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+ else
+ return prev;
+
+ m_type = omap2_memory_get_type();
+
+ local_irq_save(flags);
+ prm_write_mod_reg(0xffff, OMAP24XX_GR_MOD,
+ OMAP24XX_PRCM_VOLTSETUP_OFFSET);
+ omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
+ curr_perf_level = level;
+ local_irq_restore(flags);
+
+ return prev;
+}
+
+void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
+{
+ unsigned long dll_cnt;
+ u32 fast_dll = 0;
+
+ /* DDR = 1, SDR = 0 */
+ mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
+
+ /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
+ * In the case of 2422, its ok to use CS1 instead of CS0.
+ */
+ if (cpu_is_omap2422())
+ mem_timings.base_cs = 1;
+ else
+ mem_timings.base_cs = 0;
+
+ if (mem_timings.m_type != M_DDR)
+ return;
+
+ /* With DDR we need to determine the low frequency DLL value */
+ if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
+ mem_timings.dll_mode = M_UNLOCK;
+ else
+ mem_timings.dll_mode = M_LOCK;
+
+ if (mem_timings.base_cs == 0) {
+ fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
+ dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
+ } else {
+ fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
+ dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
+ }
+ if (force_lock_to_unlock_mode) {
+ fast_dll &= ~0xff00;
+ fast_dll |= dll_cnt; /* Current lock mode */
+ }
+ /* set fast timings with DLL filter disabled */
+ mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
+
+ /* No disruptions, DDR will be offline & C-ABI not followed */
+ omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
+ mem_timings.fast_dll_ctrl,
+ mem_timings.base_cs,
+ force_lock_to_unlock_mode);
+ mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
+
+ /* Turn status into unlock ctrl */
+ mem_timings.slow_dll_ctrl |=
+ ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
+
+ /* 90 degree phase for anything below 133Mhz + disable DLL filter */
+ mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
+}
+
+void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
+{
+ omap2_sdrc_base = omap2_globals->sdrc;
+ omap2_sms_base = omap2_globals->sms;
+}
+
+/* turn on smart idle modes for SDRAM scheduler and controller */
+void __init omap2_init_memory(void)
+{
+ u32 l;
+
+ l = sms_read_reg(SMS_SYSCONFIG);
+ l &= ~(0x3 << 3);
+ l |= (0x2 << 3);
+ sms_write_reg(l, SMS_SYSCONFIG);
+
+ l = sdrc_read_reg(SDRC_SYSCONFIG);
+ l &= ~(0x3 << 3);
+ l |= (0x2 << 3);
+ sdrc_write_reg(l, SDRC_SYSCONFIG);
+}
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 3/9] OMAP2 SDRC: separate common OMAP2/3 code from OMAP2xxx code
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
2008-07-08 2:54 ` [PATCH 1/9] OMAP2 SDRC: move mach-omap2/memory.h into include/asm-arm/arch-omap/sdrc.h Paul Walmsley
2008-07-08 2:54 ` [PATCH 2/9] OMAP2 SDRC: rename memory.c to sdrc2xxx.c Paul Walmsley
@ 2008-07-08 2:54 ` Paul Walmsley
2008-07-08 2:54 ` [PATCH 4/9] OMAP2 SDRC: add SDRAM timing parameter infrastructure Paul Walmsley
` (7 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:54 UTC (permalink / raw)
To: linux-omap
Separate SDRC code common to OMAP2/3 from mach-omap2/sdrc2xxx.c to
mach-omap2/sdrc.c. Rename the OMAP2xxx-specific functions to use an
'omap2xxx' prefix rather than an 'omap2' prefix, and use "sdrc" in the
function names rather than "memory." Mark several functions
as static that should not be used outside the sdrc2xxx.c file.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/Makefile | 6 +++-
arch/arm/mach-omap2/clock24xx.c | 23 ++++++++-------
arch/arm/mach-omap2/io.c | 2 +
arch/arm/mach-omap2/sdrc.c | 57 ++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/sdrc2xxx.c | 57 +++++++++++-------------------------
arch/arm/plat-omap/common.c | 2 +
include/asm-arm/arch-omap/common.h | 2 +
include/asm-arm/arch-omap/sdrc.h | 19 +++++++-----
8 files changed, 106 insertions(+), 62 deletions(-)
create mode 100644 arch/arm/mach-omap2/sdrc.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ad70a15..3d1b05a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
#
# Common support
-obj-y := irq.o id.o io.o sdrc2xxx.o control.o prcm.o clock.o mux.o \
+obj-y := irq.o id.o io.o sdrc.o control.o prcm.o clock.o mux.o \
devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
clockdomain.o
@@ -14,6 +14,10 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
+# SMS/SDRC
+obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
+# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
+
# Power Management
ifeq ($(CONFIG_PM),y)
obj-y += pm.o
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index aa3027c..47782ba 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -192,9 +192,9 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
mult &= OMAP24XX_CORE_CLK_SRC_MASK;
if ((rate == (cur_rate / 2)) && (mult == 2)) {
- omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
- omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
} else if (rate != cur_rate) {
valid_rate = omap2_dpllcore_round_rate(rate);
if (valid_rate != rate)
@@ -233,15 +233,16 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
bypass = 1;
- omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
+ /* For omap2xxx_sdrc_init_params() */
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
/* Force dll lock mode */
omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
bypass);
/* Errata: ret dll entry state */
- omap2_init_memory_params(omap2_dll_force_needed());
- omap2_reprogram_sdrc(done_rate, 0);
+ omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+ omap2xxx_sdrc_reprogram(done_rate, 0);
}
omap2_dpllcore_recalc(&dpll_ck);
ret = 0;
@@ -328,9 +329,9 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
if (prcm->dpll_speed == cur_rate / 2) {
- omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
} else if (prcm->dpll_speed == cur_rate * 2) {
- omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
} else if (prcm->dpll_speed != cur_rate) {
local_irq_save(flags);
@@ -361,14 +362,14 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
cm_write_mod_reg(prcm->cm_clksel_mdm,
OMAP2430_MDM_MOD, CM_CLKSEL);
- /* x2 to enter init_mem */
- omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+ /* x2 to enter omap2xxx_sdrc_init_params() */
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
bypass);
- omap2_init_memory_params(omap2_dll_force_needed());
- omap2_reprogram_sdrc(done_rate, 0);
+ omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+ omap2xxx_sdrc_reprogram(done_rate, 0);
local_irq_restore(flags);
}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4aa1abf..e3dcff9 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -200,6 +200,6 @@ void __init omap2_init_common_hw(void)
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init();
- omap2_init_memory();
+ omap2_sdrc_init();
gpmc_init();
}
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
new file mode 100644
index 0000000..0f17716
--- /dev/null
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -0,0 +1,57 @@
+/*
+ * SMS/SDRC (SDRAM controller) common code for OMAP2/3
+ *
+ * Copyright (C) 2005, 2008 Texas Instruments Inc.
+ * Copyright (C) 2005, 2008 Nokia Corporation
+ *
+ * Tony Lindgren <tony@atomide.com>
+ * Paul Walmsley
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+
+#include "prm.h"
+
+#include <asm/arch/sdrc.h>
+#include "sdrc.h"
+
+void __iomem *omap2_sdrc_base;
+void __iomem *omap2_sms_base;
+
+void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
+{
+ omap2_sdrc_base = omap2_globals->sdrc;
+ omap2_sms_base = omap2_globals->sms;
+}
+
+/* turn on smart idle modes for SDRAM scheduler and controller */
+void __init omap2_sdrc_init(void)
+{
+ u32 l;
+
+ l = sms_read_reg(SMS_SYSCONFIG);
+ l &= ~(0x3 << 3);
+ l |= (0x2 << 3);
+ sms_write_reg(l, SMS_SYSCONFIG);
+
+ l = sdrc_read_reg(SDRC_SYSCONFIG);
+ l &= ~(0x3 << 3);
+ l |= (0x2 << 3);
+ sdrc_write_reg(l, SDRC_SYSCONFIG);
+}
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 1dc1425..e98da5c 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -1,13 +1,14 @@
/*
* linux/arch/arm/mach-omap2/memory.c
*
- * Memory timing related functions for OMAP24XX
+ * Memory timing related functions for OMAP2xxx
*
- * Copyright (C) 2005 Texas Instruments Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (C) 2005, 2008 Texas Instruments Inc.
+ * Copyright (C) 2005, 2008 Nokia Corporation
*
- * Copyright (C) 2005 Nokia Corporation
* Tony Lindgren <tony@atomide.com>
+ * Paul Walmsley
+ * Richard Woodruff <r-woodruff2@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -39,23 +40,20 @@
#define M_LOCK 1
-void __iomem *omap2_sdrc_base;
-void __iomem *omap2_sms_base;
-
static struct memory_timings mem_timings;
static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
-u32 omap2_memory_get_slow_dll_ctrl(void)
+static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
{
return mem_timings.slow_dll_ctrl;
}
-u32 omap2_memory_get_fast_dll_ctrl(void)
+static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
{
return mem_timings.fast_dll_ctrl;
}
-u32 omap2_memory_get_type(void)
+static u32 omap2xxx_sdrc_get_type(void)
{
return mem_timings.m_type;
}
@@ -64,7 +62,7 @@ u32 omap2_memory_get_type(void)
* Check the DLL lock state, and return tue if running in unlock mode.
* This is needed to compensate for the shifted DLL value in unlock mode.
*/
-u32 omap2_dll_force_needed(void)
+u32 omap2xxx_sdrc_dll_is_unlocked(void)
{
/* dlla and dllb are a set */
u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
@@ -79,8 +77,10 @@ u32 omap2_dll_force_needed(void)
* 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
* Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
* CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ *
+ * Used by the clock framework during CORE DPLL changes
*/
-u32 omap2_reprogram_sdrc(u32 level, u32 force)
+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
{
u32 dll_ctrl, m_type;
u32 prev = curr_perf_level;
@@ -90,13 +90,13 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
return prev;
if (level == CORE_CLK_SRC_DPLL)
- dll_ctrl = omap2_memory_get_slow_dll_ctrl();
- else if (level == CORE_CLK_SRC_DPLL_X2) {
- dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+ dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
+ else if (level == CORE_CLK_SRC_DPLL_X2)
+ dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
else
return prev;
- m_type = omap2_memory_get_type();
+ m_type = omap2xxx_sdrc_get_type();
local_irq_save(flags);
prm_write_mod_reg(0xffff, OMAP24XX_GR_MOD,
@@ -108,7 +108,8 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
return prev;
}
-void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
+/* Used by the clock framework during CORE DPLL changes */
+void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;
u32 fast_dll = 0;
@@ -161,25 +162,3 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
/* 90 degree phase for anything below 133Mhz + disable DLL filter */
mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}
-
-void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
-{
- omap2_sdrc_base = omap2_globals->sdrc;
- omap2_sms_base = omap2_globals->sms;
-}
-
-/* turn on smart idle modes for SDRAM scheduler and controller */
-void __init omap2_init_memory(void)
-{
- u32 l;
-
- l = sms_read_reg(SMS_SYSCONFIG);
- l &= ~(0x3 << 3);
- l |= (0x2 << 3);
- sms_write_reg(l, SMS_SYSCONFIG);
-
- l = sdrc_read_reg(SDRC_SYSCONFIG);
- l &= ~(0x3 << 3);
- l |= (0x2 << 3);
- sdrc_write_reg(l, SDRC_SYSCONFIG);
-}
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 132a758..3a5f05e 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -269,7 +269,7 @@ static struct omap_globals *omap2_globals;
static void __init __omap2_set_globals(void)
{
omap2_set_globals_tap(omap2_globals);
- omap2_set_globals_memory(omap2_globals);
+ omap2_set_globals_sdrc(omap2_globals);
omap2_set_globals_control(omap2_globals);
omap2_set_globals_prcm(omap2_globals);
omap2_set_globals_clock24xx(omap2_globals);
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 7a48fc9..8a525ed 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -65,7 +65,7 @@ void omap2_set_globals_343x(void);
/* These get called from omap2_set_globals_xxxx(), do not call these */
void omap2_set_globals_tap(struct omap_globals *);
-void omap2_set_globals_memory(struct omap_globals *);
+void omap2_set_globals_sdrc(struct omap_globals *);
void omap2_set_globals_control(struct omap_globals *);
void omap2_set_globals_prcm(struct omap_globals *);
#ifdef CONFIG_ARCH_OMAP24XX
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
index 0edce1c..c75caf5 100644
--- a/include/asm-arm/arch-omap/sdrc.h
+++ b/include/asm-arm/arch-omap/sdrc.h
@@ -81,6 +81,10 @@
#ifndef __ASSEMBLER__
+void __init omap2_sdrc_init(void);
+
+#ifdef CONFIG_ARCH_OMAP2
+
struct memory_timings {
u32 m_type; /* ddr = 1, sdr = 0 */
u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
@@ -89,14 +93,13 @@ struct memory_timings {
u32 base_cs; /* base chip select to use for calculations */
};
-extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
-extern u32 omap2_memory_get_slow_dll_ctrl(void);
-extern u32 omap2_memory_get_fast_dll_ctrl(void);
-extern u32 omap2_memory_get_type(void);
-u32 omap2_dll_force_needed(void);
-u32 omap2_reprogram_sdrc(u32 level, u32 force);
-void __init omap2_init_memory(void);
+extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
-#endif
+u32 omap2xxx_sdrc_dll_is_unlocked(void);
+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
+
+#endif /* CONFIG_ARCH_OMAP2 */
+
+#endif /* __ASSEMBLER__ */
#endif
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 4/9] OMAP2 SDRC: add SDRAM timing parameter infrastructure
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
` (2 preceding siblings ...)
2008-07-08 2:54 ` [PATCH 3/9] OMAP2 SDRC: separate common OMAP2/3 code from OMAP2xxx code Paul Walmsley
@ 2008-07-08 2:54 ` Paul Walmsley
2008-07-08 2:54 ` [PATCH 5/9] OMAP2 SDRC: add timing data for Micron MT46H32M32LF-6 Paul Walmsley
` (6 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:54 UTC (permalink / raw)
To: linux-omap
For a given SDRAM clock rate, SDRAM chips require memory controllers
to use a specific set of timing minimums and maximums to transfer data
reliably. These parameters can be different for different memory chips
and can also potentially vary by board.
This patch adds the infrastructure for board-*.c files to pass this
timing data to the SDRAM controller init function. The timing data is
specified in an 'omap_sdrc_params' structure, in terms of SDRC
controller register values. An array of these structs, one per SDRC
target clock rate, is passed by the board-*.c file to
omap2_init_common_hw().
This patch does not define the values for different memory chips, nor
does it use the values for anything; those will come in subsequent patches.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/board-2430sdp.c | 2 +-
arch/arm/mach-omap2/board-3430sdp.c | 2 +-
arch/arm/mach-omap2/board-apollon.c | 2 +-
arch/arm/mach-omap2/board-generic.c | 2 +-
arch/arm/mach-omap2/board-h4.c | 2 +-
arch/arm/mach-omap2/board-ldp.c | 2 +-
arch/arm/mach-omap2/board-n800.c | 2 +-
arch/arm/mach-omap2/board-omap2evm.c | 2 +-
arch/arm/mach-omap2/board-omap3beagle.c | 2 +-
arch/arm/mach-omap2/board-omap3evm.c | 2 +-
arch/arm/mach-omap2/io.c | 4 ++-
arch/arm/mach-omap2/sdrc.c | 38 ++++++++++++++++++++++++++++++-
include/asm-arm/arch-omap/io.h | 4 ++-
include/asm-arm/arch-omap/sdrc.h | 22 ++++++++++++++++++
14 files changed, 74 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 780913e..b2f8b9c 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -347,7 +347,7 @@ out:
static void __init omap_2430sdp_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
sdp2430_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 7a216cc..137486b 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -248,7 +248,7 @@ static inline void __init sdp3430_init_smc91x(void)
static void __init omap_3430sdp_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
sdp3430_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index a06654a..41542a0 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -323,7 +323,7 @@ out:
static void __init omap_apollon_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 6e7b132..4df4e7b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
static void __init omap_generic_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
}
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 101b455..c5a353a 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -376,7 +376,7 @@ static void __init h4_init_flash(void)
static void __init omap_h4_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 2ac4c9b..1998d62 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -191,7 +191,7 @@ static struct platform_device *ldp_devices[] __initdata = {
static void __init omap_ldp_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
}
diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
index ae85c2c..d4cc47a 100644
--- a/arch/arm/mach-omap2/board-n800.c
+++ b/arch/arm/mach-omap2/board-n800.c
@@ -122,7 +122,7 @@ static struct lm8323_platform_data lm8323_pdata = {
void __init nokia_n800_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
diff --git a/arch/arm/mach-omap2/board-omap2evm.c b/arch/arm/mach-omap2/board-omap2evm.c
index bcdf4a6..0baf704 100644
--- a/arch/arm/mach-omap2/board-omap2evm.c
+++ b/arch/arm/mach-omap2/board-omap2evm.c
@@ -64,7 +64,7 @@ static inline void __init omap2evm_init_smc911x(void)
static void __init omap2_evm_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
omap2evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index fdce787..3523611 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -47,7 +47,7 @@ static int __init omap3_beagle_i2c_init(void)
static void __init omap3_beagle_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
}
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 0061512..1ba8a45 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -188,7 +188,7 @@ static struct platform_device omap3evm_kp_device = {
static void __init omap3_evm_init_irq(void)
{
- omap2_init_common_hw();
+ omap2_init_common_hw(NULL);
omap_init_irq();
omap_gpio_init();
omap3evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e3dcff9..e0191aa 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -194,12 +194,12 @@ void __init omap2_map_common_io(void)
omapfb_reserve_sdram();
}
-void __init omap2_init_common_hw(void)
+void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
{
omap2_mux_init();
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init();
- omap2_sdrc_init();
+ omap2_sdrc_init(sp);
gpmc_init();
}
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 0f17716..7c2e36c 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -12,6 +12,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+#undef DEBUG
#include <linux/module.h>
#include <linux/kernel.h>
@@ -31,9 +32,42 @@
#include <asm/arch/sdrc.h>
#include "sdrc.h"
+static struct omap_sdrc_params *sdrc_init_params;
+
void __iomem *omap2_sdrc_base;
void __iomem *omap2_sms_base;
+
+/**
+ * omap2_sdrc_get_params - return SDRC register values for a given clock rate
+ * @r: SDRC clock rate (in Hz)
+ *
+ * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
+ * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
+ * SDRC clock rate 'r'. These parameters control various timing
+ * delays in the SDRAM controller that are expressed in terms of the
+ * number of SDRC clock cycles to wait; hence the clock rate
+ * dependency. Note that sdrc_init_params must be sorted rate
+ * descending. Also assumes that both chip-selects use the same
+ * timing parameters. Returns a struct omap_sdrc_params * upon
+ * success, or NULL upon failure.
+ */
+struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
+{
+ struct omap_sdrc_params *sp;
+
+ sp = sdrc_init_params;
+
+ while (sp->rate != r)
+ sp++;
+
+ if (!sp->rate)
+ return NULL;
+
+ return sp;
+}
+
+
void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
{
omap2_sdrc_base = omap2_globals->sdrc;
@@ -41,7 +75,7 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
}
/* turn on smart idle modes for SDRAM scheduler and controller */
-void __init omap2_sdrc_init(void)
+void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
{
u32 l;
@@ -54,4 +88,6 @@ void __init omap2_sdrc_init(void)
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sdrc_write_reg(l, SDRC_SYSCONFIG);
+
+ sdrc_init_params = sp;
}
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 0b13557..1a14b4c 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -186,11 +186,13 @@
#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
+struct omap_sdrc_params;
+
extern void omap1_map_common_io(void);
extern void omap1_init_common_hw(void);
extern void omap2_map_common_io(void);
-extern void omap2_init_common_hw(void);
+extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
#endif
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
index c75caf5..00ba539 100644
--- a/include/asm-arm/arch-omap/sdrc.h
+++ b/include/asm-arm/arch-omap/sdrc.h
@@ -81,7 +81,29 @@
#ifndef __ASSEMBLER__
+/**
+ * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
+ * @rate: SDRC clock rate (in Hz)
+ * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
+ * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
+ * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
+ * @mr: Value to program to SDRC_MR for this rate
+ *
+ * This structure holds a pre-computed set of register values for the
+ * SDRC for a given SDRC clock rate and SDRAM chip. These are
+ * intended to be pre-computed and specified in an array in the board-*.c
+ * files. The structure is keyed off the 'rate' field.
+ */
+struct omap_sdrc_params {
+ unsigned long rate;
+ u32 actim_ctrla;
+ u32 actim_ctrlb;
+ u32 rfr_ctrl;
+ u32 mr;
+};
+
void __init omap2_sdrc_init(void);
+struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
#ifdef CONFIG_ARCH_OMAP2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 5/9] OMAP2 SDRC: add timing data for Micron MT46H32M32LF-6
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
` (3 preceding siblings ...)
2008-07-08 2:54 ` [PATCH 4/9] OMAP2 SDRC: add SDRAM timing parameter infrastructure Paul Walmsley
@ 2008-07-08 2:54 ` Paul Walmsley
2008-08-12 17:07 ` Steve Sakoman
2008-07-08 2:55 ` [PATCH 6/9] OMAP2 SDRC: add timing data for Qimonda HYB18M512160AF-6 Paul Walmsley
` (5 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:54 UTC (permalink / raw)
To: linux-omap; +Cc: Rajendra Nayak
Add timing data for the Micron MT46H32M32LF-6 SDRAM chip, used on the
OMAP3 Beagle and EVM boards. Original timing data is from the Micron
datasheet PDF downloaded from:
http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdram_t48m.pdf
Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying
the chips used on Beagle & OMAP3EVM.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/board-omap3beagle.c | 4 +-
arch/arm/mach-omap2/board-omap3evm.c | 4 +-
arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 55 +++++++++++++++++++++
include/asm-arm/arch-omap/sdrc.h | 2 -
4 files changed, 62 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 3523611..bf4b430 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,6 +33,8 @@
#include <asm/arch/hsmmc.h>
#include <asm/arch/common.h>
+#include "sdram-micron-mt46h32m32lf-6.h"
+
static struct omap_uart_config omap3_beagle_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
@@ -47,7 +49,7 @@ static int __init omap3_beagle_i2c_init(void)
static void __init omap3_beagle_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
}
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 1ba8a45..df81706 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -37,6 +37,8 @@
#include <asm/arch/common.h>
#include <asm/arch/mcspi.h>
+#include "sdram-micron-mt46h32m32lf-6.h"
+
static struct resource omap3evm_smc911x_resources[] = {
[0] = {
.start = OMAP3EVM_ETHR_START,
@@ -188,7 +190,7 @@ static struct platform_device omap3evm_kp_device = {
static void __init omap3_evm_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
omap3evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
new file mode 100644
index 0000000..f0ec104
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -0,0 +1,55 @@
+/*
+ * SDRC register values for the Micron MT46H32M32LF-6
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
+#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
+
+#include <asm/arch/sdrc.h>
+
+/* Micron MT46H32M32LF-6 */
+/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
+static struct omap_sdrc_params mt46h32m32lf_sdrc_params[] = {
+ [0] = {
+ .rate = 165941176,
+ .actim_ctrla = 0x9a9db4c6,
+ .actim_ctrlb = 0x00011217,
+ .rfr_ctrl = 0x0004dc01,
+ .mr = 0x00000032,
+ },
+ [1] = {
+ .rate = 133333333,
+ .actim_ctrla = 0x7a19b485,
+ .actim_ctrlb = 0x00011213,
+ .rfr_ctrl = 0x0003de01,
+ .mr = 0x00000032,
+ },
+ [2] = {
+ .rate = 82970588,
+ .actim_ctrla = 0x51512283,
+ .actim_ctrlb = 0x0001120c,
+ .rfr_ctrl = 0x00025501,
+ .mr = 0x00000032,
+ },
+ [3] = {
+ .rate = 66666666,
+ .actim_ctrla = 0x410d2243,
+ .actim_ctrlb = 0x0001120a,
+ .rfr_ctrl = 0x0001d601,
+ .mr = 0x00000032,
+ },
+ [4] = {
+ .rate = 0
+ },
+};
+
+#endif
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
index 00ba539..1d974a0 100644
--- a/include/asm-arm/arch-omap/sdrc.h
+++ b/include/asm-arm/arch-omap/sdrc.h
@@ -102,7 +102,7 @@ struct omap_sdrc_params {
u32 mr;
};
-void __init omap2_sdrc_init(void);
+void __init omap2_sdrc_init(struct omap_sdrc_params *);
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
#ifdef CONFIG_ARCH_OMAP2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 5/9] OMAP2 SDRC: add timing data for Micron MT46H32M32LF-6
2008-07-08 2:54 ` [PATCH 5/9] OMAP2 SDRC: add timing data for Micron MT46H32M32LF-6 Paul Walmsley
@ 2008-08-12 17:07 ` Steve Sakoman
2008-08-12 21:42 ` Paul Walmsley
0 siblings, 1 reply; 22+ messages in thread
From: Steve Sakoman @ 2008-08-12 17:07 UTC (permalink / raw)
To: Paul Walmsley; +Cc: linux-omap, Rajendra Nayak
Many early EVMs used Samsung memory (mine for example). Are these
timings compatible or is a separate Samsung header required?
Steve
On Mon, Jul 7, 2008 at 7:54 PM, Paul Walmsley <paul@pwsan.com> wrote:
> Add timing data for the Micron MT46H32M32LF-6 SDRAM chip, used on the
> OMAP3 Beagle and EVM boards. Original timing data is from the Micron
> datasheet PDF downloaded from:
>
> http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdram_t48m.pdf
>
> Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying
> the chips used on Beagle & OMAP3EVM.
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>
> arch/arm/mach-omap2/board-omap3beagle.c | 4 +-
> arch/arm/mach-omap2/board-omap3evm.c | 4 +-
> arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 55 +++++++++++++++++++++
> include/asm-arm/arch-omap/sdrc.h | 2 -
> 4 files changed, 62 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
>
> diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
> index 3523611..bf4b430 100644
> --- a/arch/arm/mach-omap2/board-omap3beagle.c
> +++ b/arch/arm/mach-omap2/board-omap3beagle.c
> @@ -33,6 +33,8 @@
> #include <asm/arch/hsmmc.h>
> #include <asm/arch/common.h>
>
> +#include "sdram-micron-mt46h32m32lf-6.h"
> +
> static struct omap_uart_config omap3_beagle_uart_config __initdata = {
> .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
> };
> @@ -47,7 +49,7 @@ static int __init omap3_beagle_i2c_init(void)
>
> static void __init omap3_beagle_init_irq(void)
> {
> - omap2_init_common_hw(NULL);
> + omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
> omap_init_irq();
> omap_gpio_init();
> }
> diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
> index 1ba8a45..df81706 100644
> --- a/arch/arm/mach-omap2/board-omap3evm.c
> +++ b/arch/arm/mach-omap2/board-omap3evm.c
> @@ -37,6 +37,8 @@
> #include <asm/arch/common.h>
> #include <asm/arch/mcspi.h>
>
> +#include "sdram-micron-mt46h32m32lf-6.h"
> +
> static struct resource omap3evm_smc911x_resources[] = {
> [0] = {
> .start = OMAP3EVM_ETHR_START,
> @@ -188,7 +190,7 @@ static struct platform_device omap3evm_kp_device = {
>
> static void __init omap3_evm_init_irq(void)
> {
> - omap2_init_common_hw(NULL);
> + omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
> omap_init_irq();
> omap_gpio_init();
> omap3evm_init_smc911x();
> diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
> new file mode 100644
> index 0000000..f0ec104
> --- /dev/null
> +++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
> @@ -0,0 +1,55 @@
> +/*
> + * SDRC register values for the Micron MT46H32M32LF-6
> + *
> + * Copyright (C) 2008 Texas Instruments, Inc.
> + * Copyright (C) 2008 Nokia Corporation
> + *
> + * Paul Walmsley
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
> +#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
> +
> +#include <asm/arch/sdrc.h>
> +
> +/* Micron MT46H32M32LF-6 */
> +/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
> +static struct omap_sdrc_params mt46h32m32lf_sdrc_params[] = {
> + [0] = {
> + .rate = 165941176,
> + .actim_ctrla = 0x9a9db4c6,
> + .actim_ctrlb = 0x00011217,
> + .rfr_ctrl = 0x0004dc01,
> + .mr = 0x00000032,
> + },
> + [1] = {
> + .rate = 133333333,
> + .actim_ctrla = 0x7a19b485,
> + .actim_ctrlb = 0x00011213,
> + .rfr_ctrl = 0x0003de01,
> + .mr = 0x00000032,
> + },
> + [2] = {
> + .rate = 82970588,
> + .actim_ctrla = 0x51512283,
> + .actim_ctrlb = 0x0001120c,
> + .rfr_ctrl = 0x00025501,
> + .mr = 0x00000032,
> + },
> + [3] = {
> + .rate = 66666666,
> + .actim_ctrla = 0x410d2243,
> + .actim_ctrlb = 0x0001120a,
> + .rfr_ctrl = 0x0001d601,
> + .mr = 0x00000032,
> + },
> + [4] = {
> + .rate = 0
> + },
> +};
> +
> +#endif
> diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
> index 00ba539..1d974a0 100644
> --- a/include/asm-arm/arch-omap/sdrc.h
> +++ b/include/asm-arm/arch-omap/sdrc.h
> @@ -102,7 +102,7 @@ struct omap_sdrc_params {
> u32 mr;
> };
>
> -void __init omap2_sdrc_init(void);
> +void __init omap2_sdrc_init(struct omap_sdrc_params *);
> struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
>
> #ifdef CONFIG_ARCH_OMAP2
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 5/9] OMAP2 SDRC: add timing data for Micron MT46H32M32LF-6
2008-08-12 17:07 ` Steve Sakoman
@ 2008-08-12 21:42 ` Paul Walmsley
0 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-08-12 21:42 UTC (permalink / raw)
To: Steve Sakoman; +Cc: linux-omap, Rajendra Nayak
Hello Steve,
On Tue, 12 Aug 2008, Steve Sakoman wrote:
> Many early EVMs used Samsung memory (mine for example). Are these
> timings compatible or is a separate Samsung header required?
Probably they will need fixing. Presumably we'll have to use least common
denominator values between the two, unless there is some way to
discriminate in software between the chips.
BTW, if anyone would like to calculate their own timings/rates, I have a
small utility here for doing so. The plan is to clean it up and post it
for inclusion eventually, but I would be happy to send it to anyone who
would like a copy in the interim, in the event that they are using some
other type of RAM or different DPLL3 timings on their OMAP3 board.
- Paul
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 6/9] OMAP2 SDRC: add timing data for Qimonda HYB18M512160AF-6
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
` (4 preceding siblings ...)
2008-07-08 2:54 ` [PATCH 5/9] OMAP2 SDRC: add timing data for Micron MT46H32M32LF-6 Paul Walmsley
@ 2008-07-08 2:55 ` Paul Walmsley
2008-07-08 2:55 ` [PATCH 7/9] OMAP3 SRAM: remove unused functions; rename remainder Paul Walmsley
` (4 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:55 UTC (permalink / raw)
To: linux-omap; +Cc: Rajendra Nayak
Add timing data for the Qimonda HYB18M512160AF-6 SDRAM chip, used on
the OMAP3430SDP boards.
Thanks to Rajendra Nayak <rnayak@ti.com> for his help identifying
the chip used on 3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/board-3430sdp.c | 4 +
.../mach-omap2/sdram-qimonda-hyb18m512160af-6.h | 55 ++++++++++++++++++++
2 files changed, 58 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 137486b..2b30aff 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -44,6 +44,8 @@
#include <asm/io.h>
#include <asm/delay.h>
+#include "sdram-qimonda-hyb18m512160af-6.h"
+
#define SDP3430_SMC91X_CS 3
#define ENABLE_VAUX3_DEDICATED 0x03
@@ -248,7 +250,7 @@ static inline void __init sdp3430_init_smc91x(void)
static void __init omap_3430sdp_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(hyb18m512160af6_sdrc_params);
omap_init_irq();
omap_gpio_init();
sdp3430_init_smc91x();
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
new file mode 100644
index 0000000..c932a6d
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -0,0 +1,55 @@
+/*
+ * SDRC register values for the Qimonda HYB18M512160AF-6
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
+#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
+
+#include <asm/arch/sdrc.h>
+
+/* Qimonda HYB18M512160AF-6 */
+/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
+static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
+ [0] = {
+ .rate = 165941176,
+ .actim_ctrla = 0x629db4c6,
+ .actim_ctrlb = 0x00012214,
+ .rfr_ctrl = 0x0004dc01,
+ .mr = 0x00000032,
+ },
+ [1] = {
+ .rate = 133333333,
+ .actim_ctrla = 0x5219b485,
+ .actim_ctrlb = 0x00012210,
+ .rfr_ctrl = 0x0003de01,
+ .mr = 0x00000032,
+ },
+ [2] = {
+ .rate = 82970588,
+ .actim_ctrla = 0x31512283,
+ .actim_ctrlb = 0x0001220a,
+ .rfr_ctrl = 0x00025501,
+ .mr = 0x00000022,
+ },
+ [3] = {
+ .rate = 66666666,
+ .actim_ctrla = 0x290d2243,
+ .actim_ctrlb = 0x00012208,
+ .rfr_ctrl = 0x0001d601,
+ .mr = 0x00000022,
+ },
+ [4] = {
+ .rate = 0
+ },
+};
+
+#endif
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 7/9] OMAP3 SRAM: remove unused functions; rename remainder
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
` (5 preceding siblings ...)
2008-07-08 2:55 ` [PATCH 6/9] OMAP2 SDRC: add timing data for Qimonda HYB18M512160AF-6 Paul Walmsley
@ 2008-07-08 2:55 ` Paul Walmsley
2008-07-08 2:55 ` [PATCH 8/9] OMAP3 clock/SRAM: fix CORE DPLL M2 divider mask Paul Walmsley
` (3 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:55 UTC (permalink / raw)
To: linux-omap
The only SRAM function currently used on OMAP3 is the CORE DPLL M2 divider
reprogramming function; remove the rest of the stubs.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 2 -
arch/arm/mach-omap2/sram34xx.S | 82 +++++++--------------
arch/arm/plat-omap/sram.c | 63 ++++++----------
include/asm-arm/arch-omap/sram.h | 25 ++----
4 files changed, 57 insertions(+), 115 deletions(-)
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
index f0ec104..d7c4193 100644
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -18,7 +18,7 @@
/* Micron MT46H32M32LF-6 */
/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
-static struct omap_sdrc_params mt46h32m32lf_sdrc_params[] = {
+static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
[0] = {
.rate = 165941176,
.actim_ctrla = 0x9a9db4c6,
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 74873df..63db781 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -37,31 +37,11 @@
.text
-ENTRY(omap34xx_sram_ddr_init)
- stmfd sp!, {r0 - r12, lr} @ save registers on stack
- ldmfd sp!, {r0 - r12, pc} @ restore regs and return
-ENTRY(omap34xx_sram_ddr_init_sz)
- .word . - omap34xx_sram_ddr_init
-
-ENTRY(omap34xx_sram_reprogram_sdrc)
- stmfd sp!, {r0 - r10, lr} @ save registers on stack
- ldmfd sp!, {r0 - r10, pc} @ restore regs and return
-ENTRY(omap34xx_sram_reprogram_sdrc_sz)
- .word . - omap34xx_sram_reprogram_sdrc
-
-/*
- * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
- */
-ENTRY(omap34xx_sram_set_prcm)
- stmfd sp!, {r0-r12, lr} @ regs to stack
-ENTRY(omap34xx_sram_set_prcm_sz)
- .word . - omap34xx_sram_set_prcm
-
/*
* Change frequency of core dpll
* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
*/
-ENTRY(omap34xx_sram_configure_core_dpll)
+ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
cmp r3, #0x2
blne configure_sdrc
@@ -81,13 +61,13 @@ ENTRY(omap34xx_sram_configure_core_dpll)
mov r0, #0 @ return value
ldmfd sp!, {r1-r12, pc} @ restore regs and return
unlock_dll:
- ldr r4, omap34xx_sdrc_dlla_ctrl
+ ldr r4, omap3_sdrc_dlla_ctrl
ldr r5, [r4]
orr r5, r5, #0x4
str r5, [r4]
bx lr
lock_dll:
- ldr r4, omap34xx_sdrc_dlla_ctrl
+ ldr r4, omap3_sdrc_dlla_ctrl
ldr r5, [r4]
bic r5, r5, #0x4
str r5, [r4]
@@ -95,23 +75,23 @@ lock_dll:
sdram_in_selfrefresh:
mov r5, #0x0 @ Move 0 to R5
mcr p15, 0, r5, c7, c10, 5 @ memory barrier
- ldr r4, omap34xx_sdrc_power @ read the SDRC_POWER register
+ ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
ldr r5, [r4] @ read the contents of SDRC_POWER
orr r5, r5, #0x40 @ enable self refresh on idle req
str r5, [r4] @ write back to SDRC_POWER register
- ldr r4, omap34xx_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
+ ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
ldr r5, [r4]
bic r5, r5, #0x2 @ disable iclk bit for SRDC
str r5, [r4]
wait_sdrc_idle:
- ldr r4, omap34xx_cm_idlest1_core
+ ldr r4, omap3_cm_idlest1_core
ldr r5, [r4]
and r5, r5, #0x2 @ check for SDRC idle
cmp r5, #2
bne wait_sdrc_idle
bx lr
configure_core_dpll:
- ldr r4, omap34xx_cm_clksel1_pll
+ ldr r4, omap3_cm_clksel1_pll
ldr r5, [r4]
ldr r6, core_m2_mask_val @ modify m2 for core dpll
and r5, r5, r6
@@ -136,74 +116,64 @@ wait_clk_stable:
nop
bx lr
enable_sdrc:
- ldr r4, omap34xx_cm_iclken1_core
+ ldr r4, omap3_cm_iclken1_core
ldr r5, [r4]
orr r5, r5, #0x2 @ enable iclk bit for SDRC
str r5, [r4]
wait_sdrc_idle1:
- ldr r4, omap34xx_cm_idlest1_core
+ ldr r4, omap3_cm_idlest1_core
ldr r5, [r4]
and r5, r5, #0x2
cmp r5, #0
bne wait_sdrc_idle1
- ldr r4, omap34xx_sdrc_power
+ ldr r4, omap3_sdrc_power
ldr r5, [r4]
bic r5, r5, #0x40
str r5, [r4]
bx lr
wait_dll_lock:
- ldr r4, omap34xx_sdrc_dlla_status
+ ldr r4, omap3_sdrc_dlla_status
ldr r5, [r4]
and r5, r5, #0x4
cmp r5, #0x4
bne wait_dll_lock
bx lr
wait_dll_unlock:
- ldr r4, omap34xx_sdrc_dlla_status
+ ldr r4, omap3_sdrc_dlla_status
ldr r5, [r4]
and r5, r5, #0x4
cmp r5, #0x0
bne wait_dll_unlock
bx lr
configure_sdrc:
- ldr r4, omap34xx_sdrc_rfr_ctrl
+ ldr r4, omap3_sdrc_rfr_ctrl
str r0, [r4]
- ldr r4, omap34xx_sdrc_actim_ctrla
+ ldr r4, omap3_sdrc_actim_ctrla
str r1, [r4]
- ldr r4, omap34xx_sdrc_actim_ctrlb
+ ldr r4, omap3_sdrc_actim_ctrlb
str r2, [r4]
bx lr
-omap34xx_sdrc_power:
+omap3_sdrc_power:
.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
-omap34xx_cm_clksel1_pll:
+omap3_cm_clksel1_pll:
.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
-omap34xx_cm_idlest1_core:
+omap3_cm_idlest1_core:
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
-omap34xx_cm_iclken1_core:
+omap3_cm_iclken1_core:
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
-omap34xx_sdrc_rfr_ctrl:
+omap3_sdrc_rfr_ctrl:
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap34xx_sdrc_actim_ctrla:
+omap3_sdrc_actim_ctrla:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A)
-omap34xx_sdrc_actim_ctrlb:
+omap3_sdrc_actim_ctrlb:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B)
-omap34xx_sdrc_dlla_status:
+omap3_sdrc_dlla_status:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
-omap34xx_sdrc_dlla_ctrl:
+omap3_sdrc_dlla_ctrl:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
core_m2_mask_val:
.word 0xE7FFFFFF
-ENTRY(omap34xx_sram_configure_core_dpll_sz)
- .word . - omap34xx_sram_configure_core_dpll
-
-/*
- * Reprogram GPMC
- */
-ENTRY(omap34xx_sram_reprogram_gpmc)
- stmfd sp!, {r0-r12, lr} @ regs to stack
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
-
-ENTRY(omap34xx_sram_reprogram_gpmc_sz)
- .word . - omap34xx_sram_reprogram_gpmc
+ENTRY(omap3_sram_configure_core_dpll_sz)
+ .word . - omap3_sram_configure_core_dpll
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 554ee58..71472b2 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -271,7 +271,7 @@ int __init omap1_sram_init(void)
#define omap1_sram_init() do {} while (0)
#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2)
static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
@@ -352,60 +352,41 @@ static inline int omap243x_sram_init(void)
#ifdef CONFIG_ARCH_OMAP3
-static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
-u32 omap2_sram_reprogram_gpmc(u32 perf_level)
-{
- if (!_omap2_sram_reprogram_gpmc)
+static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
+ u32 sdrc_actim_ctrla,
+ u32 sdrc_actim_ctrlb,
+ u32 m2);
+u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
+ u32 sdrc_actim_ctrlb, u32 m2)
+ {
+ if (!_omap3_sram_configure_core_dpll)
omap_sram_error();
- return _omap2_sram_reprogram_gpmc(perf_level);
-}
-
-static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
- u32 freqsel, u32 m2);
-u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
-{
- if (!_omap2_sram_configure_core_dpll)
- omap_sram_error();
-
- return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
-}
+ return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
+ sdrc_actim_ctrla,
+ sdrc_actim_ctrlb, m2);
+ }
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
void restore_sram_functions(void)
{
omap_sram_ceil = omap_sram_base + omap_sram_size;
- _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
- omap34xx_sram_reprogram_gpmc_sz);
-
- _omap2_sram_configure_core_dpll =
- omap_sram_push(omap34xx_sram_configure_core_dpll,
- omap34xx_sram_configure_core_dpll_sz);
+ _omap3_sram_configure_core_dpll =
+ omap_sram_push(omap3_sram_configure_core_dpll,
+ omap3_sram_configure_core_dpll_sz);
}
-int __init omap34xx_sram_init(void)
+int __init omap3_sram_init(void)
{
- _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
- omap34xx_sram_ddr_init_sz);
-
- _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
- omap34xx_sram_reprogram_sdrc_sz);
-
- _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
- omap34xx_sram_set_prcm_sz);
-
- _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
- omap34xx_sram_reprogram_gpmc_sz);
-
- _omap2_sram_configure_core_dpll =
- omap_sram_push(omap34xx_sram_configure_core_dpll,
- omap34xx_sram_configure_core_dpll_sz);
+ _omap3_sram_configure_core_dpll =
+ omap_sram_push(omap3_sram_configure_core_dpll,
+ omap3_sram_configure_core_dpll_sz);
return 0;
}
#else
-static inline int omap34xx_sram_init(void)
+static inline int omap3_sram_init(void)
{
return 0;
}
@@ -423,7 +404,7 @@ int __init omap_sram_init(void)
else if (cpu_is_omap2430())
omap243x_sram_init();
else if (cpu_is_omap34xx())
- omap34xx_sram_init();
+ omap3_sram_init();
return 0;
}
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index 6c577f7..79c386a 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -21,6 +21,10 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
+ u32 sdrc_actim_ctrla,
+ u32 sdrc_actim_ctrlb, u32 m2);
+
/* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
extern unsigned long omap1_sram_reprogram_clock_sz;
@@ -54,22 +58,9 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
extern unsigned long omap243x_sram_reprogram_sdrc_sz;
-extern void omap34xx_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
- u32 base_cs, u32 force_unlock);
-extern unsigned long omap34xx_sram_ddr_init_sz;
-
-extern void omap34xx_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
- u32 mem_type);
-extern unsigned long omap34xx_sram_reprogram_sdrc_sz;
-
-extern u32 omap34xx_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
- int bypass);
-extern unsigned long omap34xx_sram_set_prcm_sz;
-
-extern u32 omap34xx_sram_reprogram_gpmc(u32 perf_level);
-extern unsigned long omap34xx_sram_reprogram_gpmc_sz;
-
-extern u32 omap34xx_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2);
-extern unsigned long omap34xx_sram_configure_core_dpll_sz;
+extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
+ u32 sdrc_actim_ctrla,
+ u32 sdrc_actim_ctrlb, u32 m2);
+extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 8/9] OMAP3 clock/SRAM: fix CORE DPLL M2 divider mask
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
` (6 preceding siblings ...)
2008-07-08 2:55 ` [PATCH 7/9] OMAP3 SRAM: remove unused functions; rename remainder Paul Walmsley
@ 2008-07-08 2:55 ` Paul Walmsley
2008-07-08 2:55 ` [PATCH 9/9] OMAP3 clock: add omap3_core_dpll_m2_set_rate() Paul Walmsley
` (2 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:55 UTC (permalink / raw)
To: linux-omap
3430ES2+ CORE DPLL M2 divider can divide by 1 to 31, unlike ES1, which
was more limited. The SRAM code currently only supports dividing by 1
or 2, but we should mask off the full range of bits to guard against
the event that the previous contents of CM_CLKSEL_PLL1 included an M2
divider > 2.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sram34xx.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 63db781..1acdbe8 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -173,7 +173,7 @@ omap3_sdrc_dlla_status:
omap3_sdrc_dlla_ctrl:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
core_m2_mask_val:
- .word 0xE7FFFFFF
+ .word 0x07FFFFFF
ENTRY(omap3_sram_configure_core_dpll_sz)
.word . - omap3_sram_configure_core_dpll
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 9/9] OMAP3 clock: add omap3_core_dpll_m2_set_rate()
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
` (7 preceding siblings ...)
2008-07-08 2:55 ` [PATCH 8/9] OMAP3 clock/SRAM: fix CORE DPLL M2 divider mask Paul Walmsley
@ 2008-07-08 2:55 ` Paul Walmsley
2008-07-08 4:20 ` Paul Walmsley
2008-07-08 4:37 ` [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Rajendra Nayak
2008-08-05 12:13 ` Tony Lindgren
10 siblings, 1 reply; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 2:55 UTC (permalink / raw)
To: linux-omap
Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code,
which calls into the SRAM function omap3_sram_configure_core_dpll() to
change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes
on clocks upstream from the SDRC can glitch SDRAM accesses.)
Use this function for the set_rate function pointer in the dpll3_m2_ck
struct clk. With this function in place, PM/OPP code should be able to
alter SDRAM speed via code similar to:
clk_set_rate(&dpll3_m2_ck, target_rate).
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.c | 66 ++++++++++++++++++++++++++++++++++++++-
arch/arm/mach-omap2/clock34xx.h | 9 ++---
2 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 482f05c..0caa4dd 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -15,7 +15,6 @@
* published by the Free Software Foundation.
*/
#undef DEBUG
-#define DEBUG
#include <linux/module.h>
#include <linux/kernel.h>
@@ -410,6 +409,71 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
+
+/*
+ * CORE DPLL (DPLL3) rate programming functions
+ *
+ * These call into SRAM code to do the actual CM writes, since the SDRAM
+ * is clocked from DPLL3.
+ */
+
+/**
+ * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
+ * @clk: struct clk * of DPLL to set
+ * @rate: rounded target rate
+ *
+ * Program the DPLL M2 divider with the rounded target rate. Returns
+ * -EINVAL upon error, or 0 upon success.
+ */
+static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 new_div = 0;
+ unsigned long validrate, sdrcrate;
+ struct omap_sdrc_params *sp;
+
+ if (!clk || !rate)
+ return -EINVAL;
+
+ if (clk != &dpll3_m2_ck)
+ return -EINVAL;
+
+ if (rate == clk->rate)
+ return 0;
+
+ validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+ if (validrate != rate)
+ return -EINVAL;
+
+ sdrcrate = sdrc_ick.rate;
+ if (rate > clk->rate)
+ sdrcrate <<= ((rate / clk->rate) - 1);
+ else
+ sdrcrate >>= ((clk->rate / rate) - 1);
+
+ sp = omap2_sdrc_get_params(sdrcrate);
+ if (!sp)
+ return -EINVAL;
+
+ pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+ validrate);
+ pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
+ sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
+
+ /* REVISIT: SRAM code doesn't support other M2 divisors yet */
+ WARN_ON(new_div != 1 && new_div != 2);
+
+ /* REVISIT: Add SDRC_MR changing to this code also */
+ local_irq_disable();
+ omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
+ sp->actim_ctrlb, new_div);
+ local_irq_enable();
+
+ omap2_clksel_recalc(clk);
+
+ return 0;
+}
+
+
/* DPLL autoidle read/set code */
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 161da12..74a7e98 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -35,6 +35,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk);
static int omap3_noncore_dpll_enable(struct clk *clk);
static void omap3_noncore_dpll_disable(struct clk *clk);
static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
/* Maximum DPLL multiplier, divider values for OMAP3 */
#define OMAP3_MAX_DPLL_MULT 2048
@@ -481,11 +482,7 @@ static const struct clksel div31_dpll3m2_clksel[] = {
{ .parent = NULL }
};
-/*
- * DPLL3 output M2
- * REVISIT: This DPLL output divider must be changed in SRAM, so until
- * that code is ready, this should remain a 'read-only' clksel clock.
- */
+/* DPLL3 output M2 - primary control point for CORE speed */
static struct clk dpll3_m2_ck = {
.name = "dpll3_m2_ck",
.parent = &dpll3_ck,
@@ -495,6 +492,8 @@ static struct clk dpll3_m2_ck = {
.clksel = div31_dpll3m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap3_core_dpll_m2_set_rate,
.recalc = &omap2_clksel_recalc,
};
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 9/9] OMAP3 clock: add omap3_core_dpll_m2_set_rate()
2008-07-08 2:55 ` [PATCH 9/9] OMAP3 clock: add omap3_core_dpll_m2_set_rate() Paul Walmsley
@ 2008-07-08 4:20 ` Paul Walmsley
0 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 4:20 UTC (permalink / raw)
To: linux-omap
By the way, this last patch will need to be hand-edited to
remove the following part to apply cleanly on mainline. I'll post a
refreshed series later for merging.
- Paul
On Mon, 7 Jul 2008, Paul Walmsley wrote:
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index 482f05c..0caa4dd 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -15,7 +15,6 @@
> * published by the Free Software Foundation.
> */
> #undef DEBUG
> -#define DEBUG
>
> #include <linux/module.h>
> #include <linux/kernel.h>
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
` (8 preceding siblings ...)
2008-07-08 2:55 ` [PATCH 9/9] OMAP3 clock: add omap3_core_dpll_m2_set_rate() Paul Walmsley
@ 2008-07-08 4:37 ` Rajendra Nayak
2008-07-08 22:12 ` Paul Walmsley
2008-08-05 12:13 ` Tony Lindgren
10 siblings, 1 reply; 22+ messages in thread
From: Rajendra Nayak @ 2008-07-08 4:37 UTC (permalink / raw)
To: 'Paul Walmsley', linux-omap; +Cc: 'Igor Stoppa'
> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Tuesday, July 08, 2008 8:25 AM
> To: linux-omap@vger.kernel.org
> Cc: Rajendra Nayak; Igor Stoppa
> Subject: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2
> divider, clean up SDRC
>
> This patch series has three main objectives:
>
> - connect Rajendra Nayak's existing OMAP3 SRAM code for CORE DPLL M2
> divider reprogramming to the OMAP3 clock tree;
>
> - create a sane method to pass SDRAM timing parameters from board-*.c
> files into the SDRC, to allow optimal timing parameters to be set
> for a given clock rate;
>
> - clean up the existing OMAP2/3 SDRC code.
>
>
> A few notes:
>
> - The M2 divider switch does not seem to work consistently on the
> 3430SDP I use to test. In particular, the switch back to
> M2=1 results
> in a hung console.
SRAM being mapped as cacheable could be a possible reason for this.
>
> - Four SDRC rates are currently defined for the two SDRAM chip
> registers included in this patch set. The 165MHz and 83MHz rates
> are unusual and are intended to match the TI OPP rates set by the
> u-boot installation on the local 3430SDP. 133MHz and 66MHz rates
> are also present; per CDP 12.17, apparently these are used on Beagle
> and OMAP3EVM - not sure if these rates should also be derated
> slightly?
>
>
> The SDRAM timing parameter infrastructure is currently only used for
> OMAP3, but can be also extended to OMAP2 devices once information on
> the SDRAM parts used on those boards is available.
>
> Thanks to Rajendra Nayak <rnayak@ti.com> and Igor
> Stoppa <igor.stoppa@nokia.com> for finding some of the SDRAM
> datasheets for this patch set.
>
> Compile-tested for N800, 2430SDP, OMAP3430SDP, OMAP3EVM, OMAP3 Beagle.
> Runtime-tested on OMAP3430SDP ES2.
>
> If you have the debugfs set_rate patch, you can test the M2 divider
> code on OMAP3430SDP via:
>
> cd /debug/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck
>
> # Switch to M2 = 2 (assuming DPLL3 at 331MHz)
> echo -n 165941176 > rate
>
> # Switch back to M2 = 1
> echo -n 331882352 > rate
>
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
>
> ---
>
> size:
> text data bss dec hex filename
> 3404220 159104 108240 3671564 38060c vmlinux.3430sdp
> 3403080 159200 108208 3670488 3801d8 vmlinux.3430sdp.patched
>
> diffstat:
> arch/arm/mach-omap2/Makefile | 6 +
> arch/arm/mach-omap2/board-2430sdp.c | 2
> arch/arm/mach-omap2/board-3430sdp.c | 4
> arch/arm/mach-omap2/board-apollon.c | 2
> arch/arm/mach-omap2/board-generic.c | 2
> arch/arm/mach-omap2/board-h4.c | 2
> arch/arm/mach-omap2/board-ldp.c | 2
> arch/arm/mach-omap2/board-n800.c | 2
> arch/arm/mach-omap2/board-omap2evm.c | 2
> arch/arm/mach-omap2/board-omap3beagle.c | 4
> arch/arm/mach-omap2/board-omap3evm.c | 4
> arch/arm/mach-omap2/clock.c | 2
> arch/arm/mach-omap2/clock24xx.c | 25 +--
> arch/arm/mach-omap2/clock34xx.c | 68 +++++++-
> arch/arm/mach-omap2/clock34xx.h | 9 -
> arch/arm/mach-omap2/gpmc.c | 2
> arch/arm/mach-omap2/io.c | 8 -
> arch/arm/mach-omap2/memory.c | 179
> --------------------
> arch/arm/mach-omap2/memory.h | 43 -----
> arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 55 ++++++
> .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h | 55 ++++++
> arch/arm/mach-omap2/sdrc.c | 93 ++++++++++
> arch/arm/mach-omap2/sdrc2xxx.c | 164
> ++++++++++++++++++
> arch/arm/mach-omap2/sram34xx.S | 84 +++------
> arch/arm/plat-omap/common.c | 2
> arch/arm/plat-omap/sram.c | 63 ++-----
> include/asm-arm/arch-omap/common.h | 2
> include/asm-arm/arch-omap/gpmc.h | 1
> include/asm-arm/arch-omap/io.h | 4
> include/asm-arm/arch-omap/sdrc.h | 64 ++++++-
> include/asm-arm/arch-omap/sram.h | 25 +--
> 31 files changed, 597 insertions(+), 383 deletions(-)
> delete mode 100644 arch/arm/mach-omap2/memory.c
> delete mode 100644 arch/arm/mach-omap2/memory.h
> create mode 100644 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
> create mode 100644
> arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
> create mode 100644 arch/arm/mach-omap2/sdrc.c
> create mode 100644 arch/arm/mach-omap2/sdrc2xxx.c
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread* RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-08 4:37 ` [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Rajendra Nayak
@ 2008-07-08 22:12 ` Paul Walmsley
2008-07-08 23:12 ` Woodruff, Richard
0 siblings, 1 reply; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 22:12 UTC (permalink / raw)
To: Rajendra Nayak; +Cc: linux-omap, 'Igor Stoppa'
On Tue, 8 Jul 2008, Rajendra Nayak wrote:
> > From: Paul Walmsley [mailto:paul@pwsan.com]
> >
> > A few notes:
> >
> > - The M2 divider switch does not seem to work consistently on the
> > 3430SDP I use to test. In particular, the switch back to
> > M2=1 results
> > in a hung console.
>
> SRAM being mapped as cacheable could be a possible reason for this.
Certainly possible, and that change needs to be included. But why would
it only happen on the M2 2 -> 1 transition?
- Paul
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-08 22:12 ` Paul Walmsley
@ 2008-07-08 23:12 ` Woodruff, Richard
2008-07-08 23:46 ` Paul Walmsley
0 siblings, 1 reply; 22+ messages in thread
From: Woodruff, Richard @ 2008-07-08 23:12 UTC (permalink / raw)
To: Paul Walmsley, Nayak, Rajendra
Cc: linux-omap@vger.kernel.org, 'Igor Stoppa'
Hi Paul,
> > SRAM being mapped as cacheable could be a possible reason for this.
Second this.
> Certainly possible, and that change needs to be included. But why
> would
> it only happen on the M2 2 -> 1 transition?
Can you ping the board by chance when you are locked? Is only user space locked out or is the board dead.
The SRAM thing resulted in a dead lock where MPU was done.
I've also hit other paths in development where the networking device fails and the system gets caught in kernel space in some kind of livelock trying to get nfs root information.
Regards,
Richard W.
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-08 23:12 ` Woodruff, Richard
@ 2008-07-08 23:46 ` Paul Walmsley
2008-07-08 23:55 ` Woodruff, Richard
2008-07-09 4:42 ` Rajendra Nayak
0 siblings, 2 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-08 23:46 UTC (permalink / raw)
To: Woodruff, Richard
Cc: Nayak, Rajendra, linux-omap@vger.kernel.org,
'Igor Stoppa'
On Tue, 8 Jul 2008, Woodruff, Richard wrote:
> > > SRAM being mapped as cacheable could be a possible reason for this.
>
> Second this.
Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still
marked cacheable too, right? Did CORE M2 divider changes work in CDP
12.17?
Also still curious why, if it's the cache line eviction issue, it only
locks up on the low- to high-speed transition.
> Can you ping the board by chance when you are locked? Is only user
> space locked out or is the board dead. The SRAM thing resulted in a dead
> lock where MPU was done.
The board doesn't respond to pings.
- Paul
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-08 23:46 ` Paul Walmsley
@ 2008-07-08 23:55 ` Woodruff, Richard
2008-07-09 1:06 ` Paul Walmsley
2008-07-09 4:42 ` Rajendra Nayak
1 sibling, 1 reply; 22+ messages in thread
From: Woodruff, Richard @ 2008-07-08 23:55 UTC (permalink / raw)
To: Paul Walmsley
Cc: Nayak, Rajendra, linux-omap@vger.kernel.org,
'Igor Stoppa'
> > > > SRAM being mapped as cacheable could be a possible reason for
> this.
> >
> > Second this.
>
> Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still
> marked cacheable too, right? Did CORE M2 divider changes work in CDP
> 12.17?
No CDP has it marked strongly order for a while now. Probably around 12.14 or 15.
Yes DVFS works without noticeable hitches on CDP SDP. There was a transition period at the kernel jump it may have stopped but its working now. 12.19 is in pre-test.
> Also still curious why, if it's the cache line eviction issue, it only
> locks up on the low- to high-speed transition.
No answer. It could be another issue. Timing dependent?
Generally a high to low failure is either DDR'ish or an issue with low voltage operation.
If say your I2C failed to raise the voltage or you didn't program in enough setup time into volt control you might try and go fast with out having proper voltage yet.
With the MPU cache deadlock you could still attach with JTAG and assess the state of the system.
You at least can measure voltage at time of lock up. Using observability you can even have a go at correlating it to the first accesses.
Regards,
Richard W.
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-08 23:55 ` Woodruff, Richard
@ 2008-07-09 1:06 ` Paul Walmsley
2008-07-15 7:58 ` Paul Walmsley
0 siblings, 1 reply; 22+ messages in thread
From: Paul Walmsley @ 2008-07-09 1:06 UTC (permalink / raw)
To: Woodruff, Richard
Cc: Nayak, Rajendra, linux-omap@vger.kernel.org,
'Igor Stoppa'
Hello Richard,
On Tue, 8 Jul 2008, Woodruff, Richard wrote:
> If say your I2C failed to raise the voltage or you didn't program in
> enough setup time into volt control you might try and go fast with out
> having proper voltage yet.
Thanks for the ideas. Unfortunately, no access to an SDP with JTAG, so
can't test via JTAG. It's unlikely to be a voltage issue, since those
patches don't touch VDD2.
Added the following patch to mark SRAM as strongly-ordered; no change in
behavior.
- Paul
---
arch/arm/mm/mmu.c | 5 +++++
arch/arm/plat-omap/sram.c | 2 +-
include/asm-arm/mach/map.h | 13 +++++++------
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2d6d682..5b56539 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -239,6 +239,11 @@ static struct mem_type mem_types[] = {
.prot_sect = PMD_TYPE_SECT,
.domain = DOMAIN_KERNEL,
},
+ [MT_MEMORY_STRONGLY_ORDERED] = {
+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE |
+ PMD_SECT_UNCACHED,
+ .domain = DOMAIN_KERNEL,
+ },
};
const struct mem_type *get_mem_type(unsigned int type)
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 71472b2..e0d1b7b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -173,7 +173,7 @@ static struct map_desc omap_sram_io_desc[] __initdata = {
{ /* .length gets filled in at runtime */
.virtual = OMAP1_SRAM_VA,
.pfn = __phys_to_pfn(OMAP1_SRAM_PA),
- .type = MT_MEMORY
+ .type = MT_MEMORY_STRONGLY_ORDERED,
}
};
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
index 7ef3c83..8cb46b7 100644
--- a/include/asm-arm/mach/map.h
+++ b/include/asm-arm/mach/map.h
@@ -19,12 +19,13 @@ struct map_desc {
};
/* types 0-3 are defined in asm/io.h */
-#define MT_CACHECLEAN 4
-#define MT_MINICLEAN 5
-#define MT_LOW_VECTORS 6
-#define MT_HIGH_VECTORS 7
-#define MT_MEMORY 8
-#define MT_ROM 9
+#define MT_CACHECLEAN 4
+#define MT_MINICLEAN 5
+#define MT_LOW_VECTORS 6
+#define MT_HIGH_VECTORS 7
+#define MT_MEMORY 8
+#define MT_ROM 9
+#define MT_MEMORY_STRONGLY_ORDERED 10
#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
#define MT_IXP2000_DEVICE MT_DEVICE_IXP2000
^ permalink raw reply related [flat|nested] 22+ messages in thread* RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-09 1:06 ` Paul Walmsley
@ 2008-07-15 7:58 ` Paul Walmsley
0 siblings, 0 replies; 22+ messages in thread
From: Paul Walmsley @ 2008-07-15 7:58 UTC (permalink / raw)
To: Woodruff, Richard
Cc: Nayak, Rajendra, linux-omap@vger.kernel.org,
'Igor Stoppa'
Hello,
A quick update on the CORE DPLL M2 divider change patches; they seem to
work okay on the BeagleBoard here. (The rate tables need minor tweaks to
match the Beagle DPLL clock rates set up by u-boot.)
Not sure what's going on with the 3430SDP. I suspect there are some PRCM
register contents that are not being properly reset during the FPGA-driven
warm reboots used here.
- Paul
root@(none):~# mount -t debugfs none /mnt
root@(none):~# cd /mnt/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck
root@(none):/mnt/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck#
echo -n 166000000 > rate
clock: clksel_round_rate_div: dpll3_m2_ck target_rate 166000000
clock: new_div = 2, new_rate = 166000000
clock: changing CORE DPLL rate from 332000000 to 166000000
clock: current SDRC timing params: 0004dc01 aa9db4c6 00011517
clock: new SDRC timing params: 00025501 51512283 0001120c
clk: clk_set_rate(dpll3_m2_ck, 166000000) returns 0
root@(none):/mnt/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck#
echo -n 332000000 > rate
clock: clksel_round_rate_div: dpll3_m2_ck target_rate 332000000
clock: new_div = 1, new_rate = 332000000
clock: changing CORE DPLL rate from 166000000 to 332000000
clock: current SDRC timing params: 00025501 51512283 0001120c
clock: new SDRC timing params: 0004dc01 9a9db4c6 00011217
clk: clk_set_rate(dpll3_m2_ck, 332000000) returns 0
root@(none):/mnt/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck#
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-08 23:46 ` Paul Walmsley
2008-07-08 23:55 ` Woodruff, Richard
@ 2008-07-09 4:42 ` Rajendra Nayak
1 sibling, 0 replies; 22+ messages in thread
From: Rajendra Nayak @ 2008-07-09 4:42 UTC (permalink / raw)
To: 'Paul Walmsley', 'Woodruff, Richard'
Cc: linux-omap, 'Igor Stoppa'
> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Wednesday, July 09, 2008 5:17 AM
> To: Woodruff, Richard
> Cc: Nayak, Rajendra; linux-omap@vger.kernel.org; 'Igor Stoppa'
> Subject: RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2
> divider, clean up SDRC
>
> On Tue, 8 Jul 2008, Woodruff, Richard wrote:
>
> > > > SRAM being mapped as cacheable could be a possible
> reason for this.
> >
> > Second this.
>
> Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still
> marked cacheable too, right? Did CORE M2 divider changes work in CDP
> 12.17?
>
> Also still curious why, if it's the cache line eviction
> issue, it only
> locks up on the low- to high-speed transition.
While we saw the issues due to cache line eviction, I remember it used
to pop up both during a low-to-high and high-to-low transitions.
If you are seeing this only during a low-to-high, it probably could be something else.
>
> > Can you ping the board by chance when you are locked? Is only user
> > space locked out or is the board dead. The SRAM thing
> resulted in a dead
> > lock where MPU was done.
>
> The board doesn't respond to pings.
>
>
> - Paul
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC
2008-07-08 2:54 [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Paul Walmsley
` (9 preceding siblings ...)
2008-07-08 4:37 ` [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2 divider, clean up SDRC Rajendra Nayak
@ 2008-08-05 12:13 ` Tony Lindgren
10 siblings, 0 replies; 22+ messages in thread
From: Tony Lindgren @ 2008-08-05 12:13 UTC (permalink / raw)
To: Paul Walmsley; +Cc: linux-omap, Rajendra Nayak, Igor Stoppa
* Paul Walmsley <paul@pwsan.com> [080708 05:56]:
> This patch series has three main objectives:
>
> - connect Rajendra Nayak's existing OMAP3 SRAM code for CORE DPLL M2
> divider reprogramming to the OMAP3 clock tree;
>
> - create a sane method to pass SDRAM timing parameters from board-*.c
> files into the SDRC, to allow optimal timing parameters to be set
> for a given clock rate;
>
> - clean up the existing OMAP2/3 SDRC code.
>
>
> A few notes:
>
> - The M2 divider switch does not seem to work consistently on the
> 3430SDP I use to test. In particular, the switch back to M2=1 results
> in a hung console.
>
> - Four SDRC rates are currently defined for the two SDRAM chip
> registers included in this patch set. The 165MHz and 83MHz rates
> are unusual and are intended to match the TI OPP rates set by the
> u-boot installation on the local 3430SDP. 133MHz and 66MHz rates
> are also present; per CDP 12.17, apparently these are used on Beagle
> and OMAP3EVM - not sure if these rates should also be derated
> slightly?
>
>
> The SDRAM timing parameter infrastructure is currently only used for
> OMAP3, but can be also extended to OMAP2 devices once information on
> the SDRAM parts used on those boards is available.
>
> Thanks to Rajendra Nayak <rnayak@ti.com> and Igor
> Stoppa <igor.stoppa@nokia.com> for finding some of the SDRAM
> datasheets for this patch set.
>
> Compile-tested for N800, 2430SDP, OMAP3430SDP, OMAP3EVM, OMAP3 Beagle.
> Runtime-tested on OMAP3430SDP ES2.
>
> If you have the debugfs set_rate patch, you can test the M2 divider
> code on OMAP3430SDP via:
>
> cd /debug/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck
>
> # Switch to M2 = 2 (assuming DPLL3 at 331MHz)
> echo -n 165941176 > rate
>
> # Switch back to M2 = 1
> echo -n 331882352 > rate
Pushing this series today.
Tony
>
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
>
> ---
>
> size:
> text data bss dec hex filename
> 3404220 159104 108240 3671564 38060c vmlinux.3430sdp
> 3403080 159200 108208 3670488 3801d8 vmlinux.3430sdp.patched
>
> diffstat:
> arch/arm/mach-omap2/Makefile | 6 +
> arch/arm/mach-omap2/board-2430sdp.c | 2
> arch/arm/mach-omap2/board-3430sdp.c | 4
> arch/arm/mach-omap2/board-apollon.c | 2
> arch/arm/mach-omap2/board-generic.c | 2
> arch/arm/mach-omap2/board-h4.c | 2
> arch/arm/mach-omap2/board-ldp.c | 2
> arch/arm/mach-omap2/board-n800.c | 2
> arch/arm/mach-omap2/board-omap2evm.c | 2
> arch/arm/mach-omap2/board-omap3beagle.c | 4
> arch/arm/mach-omap2/board-omap3evm.c | 4
> arch/arm/mach-omap2/clock.c | 2
> arch/arm/mach-omap2/clock24xx.c | 25 +--
> arch/arm/mach-omap2/clock34xx.c | 68 +++++++-
> arch/arm/mach-omap2/clock34xx.h | 9 -
> arch/arm/mach-omap2/gpmc.c | 2
> arch/arm/mach-omap2/io.c | 8 -
> arch/arm/mach-omap2/memory.c | 179 --------------------
> arch/arm/mach-omap2/memory.h | 43 -----
> arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 55 ++++++
> .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h | 55 ++++++
> arch/arm/mach-omap2/sdrc.c | 93 ++++++++++
> arch/arm/mach-omap2/sdrc2xxx.c | 164 ++++++++++++++++++
> arch/arm/mach-omap2/sram34xx.S | 84 +++------
> arch/arm/plat-omap/common.c | 2
> arch/arm/plat-omap/sram.c | 63 ++-----
> include/asm-arm/arch-omap/common.h | 2
> include/asm-arm/arch-omap/gpmc.h | 1
> include/asm-arm/arch-omap/io.h | 4
> include/asm-arm/arch-omap/sdrc.h | 64 ++++++-
> include/asm-arm/arch-omap/sram.h | 25 +--
> 31 files changed, 597 insertions(+), 383 deletions(-)
> delete mode 100644 arch/arm/mach-omap2/memory.c
> delete mode 100644 arch/arm/mach-omap2/memory.h
> create mode 100644 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
> create mode 100644 arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
> create mode 100644 arch/arm/mach-omap2/sdrc.c
> create mode 100644 arch/arm/mach-omap2/sdrc2xxx.c
>
> --
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^ permalink raw reply [flat|nested] 22+ messages in thread