Re: [PATCH] ARM MMU: add strongly-ordered memory type

[Russell King - ARM Linux <linux@arm.linux.org.uk>]

On Thu, Aug 07, 2008 at 06:07:50PM -0500, Woodruff, Richard wrote:
> If I write a series of control register commands to device A, then
> write a go operation to device  B, I would hope all of A's writes
> had completed before B gets the go.  SO gives you this.  DEVICE may
> not with out barriers.

This, I think, is where the problem lies.

Device regions of the same type *are* ordered with respect to each other.

So, shared device accesses occur in program order.  Unshared device
accesses occur in program order.

However, shared device accesses may occur out of order with unshared
device accesses or memory accesses.  Unshared device accesses may
occur out of order with shared device accesses or memory accesses.

So, if both device A and device B are mapped as shared devices, then
accesses to both occur in program order.

If device A is mapped as a shared device and device B as an unshared
device, then you have to use read backs and possibly barriers to
ensure ordering.  Remember, a barrier only affects up to the CPU.
It doesn't affect write posting downstream of the CPU.