* [PATCH 01/12] OMAP2/3 clockdomains: add CM and PRM clkdms
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 02/12] OMAP2/3 clock: convert wkup_clkdm PRM clocks to prm_clkdm Paul Walmsley
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Add clockdomains for the CM and PRM. These will ultimately replace the
"wkup_clkdm", which appears to not actually exist on the hardware.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clockdomains.h | 19 +++++++++++++++++++
arch/arm/plat-omap/include/mach/powerdomain.h | 4 ++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index e17c369..ec5a720 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -14,6 +14,11 @@
/*
* OMAP2/3-common clockdomains
+ *
+ * Even though the 2420 has a single PRCM module from the
+ * interconnect's perspective, internally it does appear to have
+ * separate PRM and CM clockdomains. The usual test case is
+ * sys_clkout/sys_clkout2.
*/
/* This is an implicit clockdomain - it is never defined as such in TRM */
@@ -23,6 +28,18 @@ static struct clockdomain wkup_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};
+static struct clockdomain prm_clkdm = {
+ .name = "prm_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain cm_clkdm = {
+ .name = "cm_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+};
+
/*
* 2420-only clockdomains
*/
@@ -266,6 +283,8 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
static struct clockdomain *clockdomains_omap[] = {
&wkup_clkdm,
+ &cm_clkdm,
+ &prm_clkdm,
#ifdef CONFIG_ARCH_OMAP2420
&mpu_2420_clkdm,
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
index 4948cb7..69c9e67 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -50,9 +50,9 @@
/*
* Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain is probably the worst case.
+ * CORE powerdomain on OMAP3 is the worst case
*/
-#define PWRDM_MAX_CLKDMS 3
+#define PWRDM_MAX_CLKDMS 4
/* XXX A completely arbitrary number. What is reasonable here? */
#define PWRDM_TRANSITION_BAILOUT 100000
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 02/12] OMAP2/3 clock: convert wkup_clkdm PRM clocks to prm_clkdm
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
2008-09-08 16:57 ` [PATCH 01/12] OMAP2/3 clockdomains: add CM and PRM clkdms Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 03/12] OMAP2/3 clock: annotate PRM clocks that are missing clockdomains Paul Walmsley
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Convert existing wkup_clkdm clocks that should be in the PRM clockdomain
to prm_clkdm. (A later patch will add PRM clockdomain associations for
unassociated clocks.)
References for the OMAP2xxx clocks:
OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 TRM Version Q
Figure 4-11:
- alt_ck
Figure 5-7:
- func_32k_ck, osc_ck, sys_ck
Figure 5-8 (assumes that "Level 0" = PRM)
- dpll_ck, apll96_ck, apll54_ck, func_54m_ck
Section 5.4.1.1:
- sys_clkout_src, sys_clkout
Section 29.3.1.1:
- gpios_fck, mpu_wdt_fck, mpu_wdt_ick
References for the OMAP3xxx clocks:
OMAP34xx Multimedia Device Silicon Revision 3.0 Version I TRM
Figure 4-54:
- gpt1_fck, wkup_32k_fck, wdt2_fck, wkup_l4_fck, omap_32ksync_ick,
gpt1_ick
Section 25.3.1.1.3:
- gpio1_fck, gpio1_ick
OMAP34xx Multimedia High Security (HS) Device Silicon Revision 3.0 Security
Addendum Version B TRM
Table 2-5:
- usim_ick
Figure 3-29:
- wdt1_ick, gpt12_ick
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock24xx.h | 29 ++++++++++++++++-------------
arch/arm/mach-omap2/clock34xx.h | 25 ++++++++++++-------------
2 files changed, 28 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 4de6d9b..7224450 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -635,7 +635,7 @@ static struct clk func_32k_ck = {
.rate = 32000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -644,7 +644,7 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
.name = "osc_ck",
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable = &omap2_enable_osc_ck,
.disable = &omap2_disable_osc_ck,
.recalc = &omap2_osc_clk_recalc,
@@ -656,7 +656,7 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_sys_clk_recalc,
};
@@ -665,7 +665,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -697,7 +697,7 @@ static struct clk dpll_ck = {
.dpll_data = &dpll_dd,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_dpllcore_recalc,
.set_rate = &omap2_reprogram_dpllcore,
};
@@ -708,7 +708,7 @@ static struct clk apll96_ck = {
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable,
@@ -722,7 +722,7 @@ static struct clk apll54_ck = {
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable,
@@ -899,7 +899,7 @@ static struct clk sys_clkout_src = {
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -930,7 +930,7 @@ static struct clk sys_clkout = {
.parent = &sys_clkout_src,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
.clksel = sys_clkout_clksel,
@@ -2079,27 +2079,29 @@ static struct clk gpios_fck = {
.name = "gpios_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc,
};
+/* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
};
+/* aka WDT2 */
static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
@@ -2116,11 +2118,12 @@ static struct clk sync_32k_ick = {
.recalc = &followparent_recalc,
};
+/* REVISIT: parent is really wu_l4_iclk */
static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_WDT1_SHIFT,
.recalc = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 4d16f56..c825a37 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2323,7 +2323,7 @@ static struct clk gpt1_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2332,7 +2332,7 @@ static struct clk wkup_32k_fck = {
.init = &omap2_init_clk_clkdm,
.parent = &omap_32k_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2342,7 +2342,7 @@ static struct clk gpio1_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2352,7 +2352,7 @@ static struct clk wdt2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2360,7 +2360,7 @@ static struct clk wkup_l4_ick = {
.name = "wkup_l4_ick",
.parent = &sys_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2372,7 +2372,7 @@ static struct clk usim_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2382,7 +2382,7 @@ static struct clk wdt2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2392,7 +2392,7 @@ static struct clk wdt1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2402,7 +2402,7 @@ static struct clk gpio1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2412,18 +2412,17 @@ static struct clk omap_32ksync_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
-/* XXX This clock no longer exists in 3430 TRM rev F */
static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &wkup_l4_ick,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2433,7 +2432,7 @@ static struct clk gpt1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 03/12] OMAP2/3 clock: annotate PRM clocks that are missing clockdomains
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
2008-09-08 16:57 ` [PATCH 01/12] OMAP2/3 clockdomains: add CM and PRM clkdms Paul Walmsley
2008-09-08 16:57 ` [PATCH 02/12] OMAP2/3 clock: convert wkup_clkdm PRM clocks to prm_clkdm Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 04/12] OMAP2/3 clock: convert wkup_clkdm CM clocks to cm_clkdm Paul Walmsley
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Some PRM clocks are missing clockdomain assignments; add them.
Also, in OMAP2xxx clock tree, standardize the name for wdt1_osc_ck.
References for the OMAP2xxx clocks:
OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 TRM Version Q
Table 18-41:
- wdt1_osc_ck
References for the OMAP3xxx clocks:
OMAP34xx Multimedia Device Silicon Revision 3.0 Version I TRM
Figure 4-13:
- sys_clkout1,
Table 4-37:
- sys_ck
Table 4-38:
- omap_32k_fck, osc_sys_ck,
Figure 4-56:
- sr1_fck, sr2_fck
Figure 4-57:
- omap_96m_alwon_fck
Section 4.7.7.13:
- sr1_fck, sr2_fck
OMAP34xx Multimedia High Security (HS) Device Silicon Revision 3.0 Security
Addendum Version B TRM
Table 2-5:
- usim_fck
Figure 3-29:
- secure_32k_fck, gpt12_fck, wdt1_fck
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock24xx.h | 3 ++-
arch/arm/mach-omap2/clock34xx.h | 18 ++++++++++++++++++
2 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 7224450..8915b52 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -852,9 +852,10 @@ static struct clk func_12m_ck = {
/* Secure timer, only available in secure mode */
static struct clk wdt1_osc_ck = {
- .name = "ck_wdt1_osc",
+ .name = "wdt1_osc_ck",
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c825a37..7bd6f56 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -74,6 +74,7 @@ static struct clk omap_32k_fck = {
.rate = 32768,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -82,6 +83,7 @@ static struct clk secure_32k_fck = {
.rate = 32768,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -91,6 +93,7 @@ static struct clk virt_12m_ck = {
.rate = 12000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -99,6 +102,7 @@ static struct clk virt_13m_ck = {
.rate = 13000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -107,6 +111,7 @@ static struct clk virt_16_8m_ck = {
.rate = 16800000,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -115,6 +120,7 @@ static struct clk virt_19_2m_ck = {
.rate = 19200000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -123,6 +129,7 @@ static struct clk virt_26m_ck = {
.rate = 26000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -131,6 +138,7 @@ static struct clk virt_38_4m_ck = {
.rate = 38400000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -185,6 +193,7 @@ static struct clk osc_sys_ck = {
/* REVISIT: deal with autoextclkmode? */
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -209,6 +218,7 @@ static struct clk sys_ck = {
.clksel_mask = OMAP_SYSCLKDIV_MASK,
.clksel = sys_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -222,6 +232,7 @@ static struct clk sys_altclk = {
static struct clk mcbsp_clks = {
.name = "mcbsp_clks",
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};
@@ -233,6 +244,7 @@ static struct clk sys_clkout1 = {
.enable_reg = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -678,6 +690,7 @@ static struct clk omap_96m_alwon_fck = {
.clksel = omap_96m_alwon_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2310,6 +2323,7 @@ static struct clk usim_fck = {
.clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
.clksel = usim_clksel,
.flags = CLOCK_IN_OMAP3430ES2,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -3036,6 +3050,7 @@ static struct clk sr1_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR1_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -3046,6 +3061,7 @@ static struct clk sr2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR2_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -3064,6 +3080,7 @@ static struct clk gpt12_fck = {
.name = "gpt12_fck",
.parent = &secure_32k_fck,
.flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -3071,6 +3088,7 @@ static struct clk wdt1_fck = {
.name = "wdt1_fck",
.parent = &secure_32k_fck,
.flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 04/12] OMAP2/3 clock: convert wkup_clkdm CM clocks to cm_clkdm
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (2 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 03/12] OMAP2/3 clock: annotate PRM clocks that are missing clockdomains Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 05/12] OMAP2/3 clock: mark the rest of the CM clocks as belonging " Paul Walmsley
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Convert existing wkup_clkdm clocks that should be in the CM clockdomain
to cm_clkdm. (A later patch will add CM clockdomain associations for
unassociated clocks.)
References:
OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 TRM Version Q
Figure 5-9
- func_54m_ck, core_ck, func_96m_ck, func_48m_ck, func_12m_ck
OMAP34xx Multimedia Device Silicon Revision 3.0 Version I TRM
Figure 4-35
- sys_clkout2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock24xx.h | 16 ++++++++--------
arch/arm/mach-omap2/clock34xx.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 8915b52..5845850 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -757,7 +757,7 @@ static struct clk func_54m_ck = {
.parent = &apll54_ck, /* can also be alt_clk */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_54M_SOURCE,
@@ -770,7 +770,7 @@ static struct clk core_ck = {
.parent = &dpll_ck, /* can also be 32k */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -797,7 +797,7 @@ static struct clk func_96m_ck = {
.parent = &apll96_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP2430_96M_SOURCE,
@@ -830,7 +830,7 @@ static struct clk func_48m_ck = {
.parent = &apll96_ck, /* 96M or Alt */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_48M_SOURCE,
@@ -846,7 +846,7 @@ static struct clk func_12m_ck = {
.fixed_div = 4,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};
@@ -945,7 +945,7 @@ static struct clk sys_clkout2_src = {
.name = "sys_clkout2_src",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -968,7 +968,7 @@ static struct clk sys_clkout2 = {
.parent = &sys_clkout2_src,
.flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
@@ -981,7 +981,7 @@ static struct clk emul_ck = {
.name = "emul_ck",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
.enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
.recalc = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 7bd6f56..01414e2 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1023,7 +1023,7 @@ static struct clk clkout2_src_ck = {
.clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
.clksel = clkout2_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 05/12] OMAP2/3 clock: mark the rest of the CM clocks as belonging to cm_clkdm
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (3 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 04/12] OMAP2/3 clock: convert wkup_clkdm CM clocks to cm_clkdm Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 06/12] OMAP2/3 clockdomain: remove wkup_clkdm Paul Walmsley
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Mark CM clocks with no clockdomain as belonging to the CM clockdomain.
References for the OMAP3xxx clocks:
OMAP34xx Multimedia Device Silicon Revision 3.0 Version I TRM
Figure 4-13:
- sys_ck
Figure 4-35:
- sys_clkout2
Figure 4-37:
- corex2_fck, core_ck, dss_tv_fck
Figure 4-38:
- omap_96m_alwon_fck
Figure 4-39:
- corex2_fck, cm_96m_fck, omap_96m_fck, omap_54m_fck, omap_12m_fck,
dpll1_fck, dpll2_fck, rm_ick, dss_tv_fck
Section 4.7.3.2:
- omap_96m_alwon_fck, omap_96m_fck, omap_48m_fck
OMAP34xx Multimedia High Security (HS) Device Silicon Revision 3.0 Security
Addendum Version B TRM
Figure 3-19:
- cpefuse_fck
Table 3-57:
- dss_tv_fck
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.h | 26 ++++++++++++++++++++------
1 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 01414e2..0c2acea 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -225,10 +225,15 @@ static struct clk sys_ck = {
static struct clk sys_altclk = {
.name = "sys_altclk",
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &propagate_rate,
};
-/* Optional external clock input for some McBSPs */
+/*
+ * Optional external clock input for some McBSPs
+ * Apparently this is not really in prm_clkdm, but rather is fed into
+ * both CORE and PER separately.
+ */
static struct clk mcbsp_clks = {
.name = "mcbsp_clks",
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -526,6 +531,7 @@ static struct clk core_ck = {
.clksel = core_ck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -699,6 +705,7 @@ static struct clk cm_96m_fck = {
.parent = &omap_96m_alwon_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -727,6 +734,7 @@ static struct clk omap_96m_fck = {
.clksel = omap_96m_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -769,6 +777,7 @@ static struct clk virt_omap_54m_fck = {
.clksel = virt_omap_54m_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -796,6 +805,7 @@ static struct clk omap_54m_fck = {
.clksel = omap_54m_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -823,6 +833,7 @@ static struct clk omap_48m_fck = {
.clksel = omap_48m_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -832,6 +843,7 @@ static struct clk omap_12m_fck = {
.fixed_div = 4,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};
@@ -1048,6 +1060,7 @@ static struct clk sys_clkout2 = {
.clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1058,6 +1071,7 @@ static struct clk corex2_fck = {
.parent = &dpll3_m2x2_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1075,10 +1089,6 @@ static const struct clksel div4_core_clksel[] = {
{ .parent = NULL }
};
-/*
- * REVISIT: Are these in DPLL power domain or CM power domain? docs
- * may be inconsistent here?
- */
static struct clk dpll1_fck = {
.name = "dpll1_fck",
.parent = &core_ck,
@@ -1088,6 +1098,7 @@ static struct clk dpll1_fck = {
.clksel = div4_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1163,6 +1174,7 @@ static struct clk dpll2_fck = {
.clksel = div4_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1246,6 +1258,7 @@ static struct clk rm_ick = {
.clksel_mask = OMAP3430_CLKSEL_RM_MASK,
.clksel = div2_l4_clksel,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1409,6 +1422,7 @@ static struct clk cpefuse_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2169,7 +2183,7 @@ static struct clk dss_tv_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "dss_clkdm" },
+ .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
.recalc = &followparent_recalc,
};
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 06/12] OMAP2/3 clockdomain: remove wkup_clkdm
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (4 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 05/12] OMAP2/3 clock: mark the rest of the CM clocks as belonging " Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 07/12] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains Paul Walmsley
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Remove wkup_clkdm, as it has been completely replaced by prm_clkdm and
cm_clkdm.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clockdomains.h | 8 --------
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index ec5a720..2156668 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -21,13 +21,6 @@
* sys_clkout/sys_clkout2.
*/
-/* This is an implicit clockdomain - it is never defined as such in TRM */
-static struct clockdomain wkup_clkdm = {
- .name = "wkup_clkdm",
- .pwrdm = { .name = "wkup_pwrdm" },
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
-};
-
static struct clockdomain prm_clkdm = {
.name = "prm_clkdm",
.pwrdm = { .name = "wkup_pwrdm" },
@@ -282,7 +275,6 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
static struct clockdomain *clockdomains_omap[] = {
- &wkup_clkdm,
&cm_clkdm,
&prm_clkdm,
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 07/12] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (5 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 06/12] OMAP2/3 clockdomain: remove wkup_clkdm Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 08/12] OMAP3 clock: mark DPLL clocks with their DPLLx clockdomains Paul Walmsley
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Each DPLL exists in its own powerdomain (cf 34xx TRM figure 4-18) and
clockdomain; so, create powerdomain and clockdomain structures for them.
These are used in a following patch for DPLL-related clocks.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clockdomains.h | 35 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/powerdomains.h | 5 +++++
arch/arm/mach-omap2/powerdomains34xx.h | 31 ++++++++++++++++++++++++++++
3 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index 2156668..5234be1 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -249,6 +249,36 @@ static struct clockdomain emu_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
+static struct clockdomain dpll1_clkdm = {
+ .name = "dpll1_clkdm",
+ .pwrdm = { .name = "dpll1_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll2_clkdm = {
+ .name = "dpll2_clkdm",
+ .pwrdm = { .name = "dpll2_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll3_clkdm = {
+ .name = "dpll3_clkdm",
+ .pwrdm = { .name = "dpll3_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll4_clkdm = {
+ .name = "dpll4_clkdm",
+ .pwrdm = { .name = "dpll4_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll5_clkdm = {
+ .name = "dpll5_clkdm",
+ .pwrdm = { .name = "dpll5_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+};
+
#endif /* CONFIG_ARCH_OMAP34XX */
/*
@@ -310,6 +340,11 @@ static struct clockdomain *clockdomains_omap[] = {
&usbhost_clkdm,
&per_clkdm,
&emu_clkdm,
+ &dpll1_clkdm,
+ &dpll2_clkdm,
+ &dpll3_clkdm,
+ &dpll4_clkdm,
+ &dpll5_clkdm,
#endif
NULL,
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index fba3440..51623e2 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -179,6 +179,11 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
&emu_pwrdm,
&sgx_pwrdm,
&usbhost_pwrdm,
+ &dpll1_pwrdm,
+ &dpll2_pwrdm,
+ &dpll3_pwrdm,
+ &dpll4_pwrdm,
+ &dpll5_pwrdm,
#endif
NULL
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index adbfa91..446a1ed 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -341,6 +341,37 @@ static struct powerdomain usbhost_pwrdm = {
},
};
+static struct powerdomain dpll1_pwrdm = {
+ .name = "dpll1_pwrdm",
+ .prcm_offs = MPU_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll2_pwrdm = {
+ .name = "dpll2_pwrdm",
+ .prcm_offs = OMAP3430_IVA2_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll3_pwrdm = {
+ .name = "dpll3_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll4_pwrdm = {
+ .name = "dpll4_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll5_pwrdm = {
+ .name = "dpll5_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+};
+
+
#endif /* CONFIG_ARCH_OMAP34XX */
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 08/12] OMAP3 clock: mark DPLL clocks with their DPLLx clockdomains
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (6 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 07/12] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 10/12] OMAP2 clockdomain: add virt_opp_clkdm Paul Walmsley
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Mark each DPLL clock as belonging to their respective DPLL clockdomain.
cf. 34xx TRM Table 4-27 (among other references).
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.h | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 0c2acea..682f43a 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -323,6 +323,7 @@ static struct clk dpll1_ck = {
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .clkdm = { .name = "dpll1_clkdm" },
.recalc = &omap3_dpll_recalc,
};
@@ -335,6 +336,7 @@ static struct clk dpll1_x2_ck = {
.parent = &dpll1_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll1_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -357,6 +359,7 @@ static struct clk dpll1_x2m2_ck = {
.clksel = div16_dpll1_x2m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll1_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -394,6 +397,7 @@ static struct clk dpll2_ck = {
.disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .clkdm = { .name = "dpll2_clkdm" },
.recalc = &omap3_dpll_recalc,
};
@@ -416,6 +420,7 @@ static struct clk dpll2_m2_ck = {
.clksel = div16_dpll2_m2x2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll2_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -447,6 +452,7 @@ static struct clk dpll3_ck = {
.dpll_data = &dpll3_dd,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.round_rate = &omap2_dpll_round_rate,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap3_dpll_recalc,
};
@@ -459,6 +465,7 @@ static struct clk dpll3_x2_ck = {
.parent = &dpll3_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -512,6 +519,7 @@ static struct clk dpll3_m2_ck = {
.clksel = div31_dpll3m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap3_core_dpll_m2_set_rate,
.recalc = &omap2_clksel_recalc,
@@ -549,6 +557,7 @@ static struct clk dpll3_m2x2_ck = {
.clksel = dpll3_m2x2_ck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -568,6 +577,7 @@ static struct clk dpll3_m3_ck = {
.clksel = div16_dpll3_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -578,6 +588,7 @@ static struct clk dpll3_m3x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -596,6 +607,7 @@ static struct clk emu_core_alwon_ck = {
.clksel = emu_core_alwon_ck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -631,6 +643,7 @@ static struct clk dpll4_ck = {
.disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_dpll_recalc,
};
@@ -644,6 +657,7 @@ static struct clk dpll4_x2_ck = {
.parent = &dpll4_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -662,6 +676,7 @@ static struct clk dpll4_m2_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -672,6 +687,7 @@ static struct clk dpll4_m2x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_96M_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -748,6 +764,7 @@ static struct clk dpll4_m3_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -759,6 +776,7 @@ static struct clk dpll4_m3x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -857,6 +875,7 @@ static struct clk dpll4_m4_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -867,6 +886,7 @@ static struct clk dpll4_m4x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -880,6 +900,7 @@ static struct clk dpll4_m5_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -890,6 +911,7 @@ static struct clk dpll4_m5x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -903,6 +925,7 @@ static struct clk dpll4_m6_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -914,6 +937,7 @@ static struct clk dpll4_m6x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};
@@ -922,6 +946,7 @@ static struct clk emu_per_alwon_ck = {
.parent = &dpll4_m6x2_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -958,6 +983,7 @@ static struct clk dpll5_ck = {
.disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .clkdm = { .name = "dpll5_clkdm" },
.recalc = &omap3_dpll_recalc,
};
@@ -975,6 +1001,7 @@ static struct clk dpll5_m2_ck = {
.clksel = div16_dpll5_clksel,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll5_clkdm" },
.recalc = &omap2_clksel_recalc,
};
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 10/12] OMAP2 clockdomain: add virt_opp_clkdm
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (7 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 08/12] OMAP3 clock: mark DPLL clocks with their DPLLx clockdomains Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 09/12] OMAP2/3 clock: note clockdomains for remaining clocks Paul Walmsley
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Every OMAP2/3 clock will need to be associated with a clockdomain.
However, the "virt_prcm_set" clock has no clockdomain, since it is a
virtual clock without any hardware referents. So, create a new
clockdomain, "virt_clkdm", for this clock. This clockdomain should be
reusable for OMAP3 virtual clock nodes.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock24xx.h | 1 +
arch/arm/mach-omap2/clockdomains.h | 10 ++++++++++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index e339f6d..63349fa 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -2666,6 +2666,7 @@ static struct clk virt_prcm_set = {
.name = "virt_prcm_set",
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
+ .clkdm = { .name = "virt_opp_clkdm" },
.parent = &mpu_ck, /* Indexed by mpu speed, no parent */
.recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
.set_rate = &omap2_select_table_rate,
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index 5234be1..847e532 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -34,6 +34,15 @@ static struct clockdomain cm_clkdm = {
};
/*
+ * virt_opp_clkdm is intended solely for use with virtual OPP clocks,
+ * e.g., virt_prcm_set, until OPP handling is rationalized.
+ */
+static struct clockdomain virt_opp_clkdm = {
+ .name = "virt_opp_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+};
+
+/*
* 2420-only clockdomains
*/
@@ -307,6 +316,7 @@ static struct clockdomain *clockdomains_omap[] = {
&cm_clkdm,
&prm_clkdm,
+ &virt_opp_clkdm,
#ifdef CONFIG_ARCH_OMAP2420
&mpu_2420_clkdm,
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 09/12] OMAP2/3 clock: note clockdomains for remaining clocks
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (8 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 10/12] OMAP2 clockdomain: add virt_opp_clkdm Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 11/12] OMAP3 clock: remove duplicate call to omap2_init_clk_clkdm() Paul Walmsley
2008-09-08 16:57 ` [PATCH 12/12] OMAP2/3 clock: warn if clock is missing clockdomain Paul Walmsley
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
Fill in clockdomains for all remaining clocks. On OMAP2, these mostly
involve IVA and DSP clocks; on OMAP3, these mostly involve some core_l4_clkdm
devices and the secure peripherals.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock24xx.h | 7 ++++++-
arch/arm/mach-omap2/clock34xx.h | 26 +++++++++++++++++++++++++-
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 5845850..e339f6d 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -1090,12 +1090,13 @@ static struct clk dsp_irate_ick = {
.parent = &dsp_fck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dsp_clkdm" },
.clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_irate_ick_clksel,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
+ .set_rate = &omap2_clksel_set_rate
};
/* 2420 only */
@@ -1103,6 +1104,7 @@ static struct clk dsp_ick = {
.name = "dsp_ick", /* apparently ipi and isp */
.parent = &dsp_irate_ick,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
+ .clkdm = { .name = "dsp_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
.enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
};
@@ -1112,6 +1114,7 @@ static struct clk iva2_1_ick = {
.name = "iva2_1_ick",
.parent = &dsp_irate_ick,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+ .clkdm = { .name = "dsp_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
};
@@ -1691,6 +1694,7 @@ static struct clk gpt7_ick = {
.name = "gpt7_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.recalc = &followparent_recalc,
@@ -2586,6 +2590,7 @@ static struct clk mmchs2_fck = {
.id = 2,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
.recalc = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 682f43a..8fe87e3 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -795,7 +795,7 @@ static struct clk virt_omap_54m_fck = {
.clksel = virt_omap_54m_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1020,6 +1020,7 @@ static struct clk omap_120m_fck = {
.clksel = omap_120m_fck_clksel,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll5_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1175,6 +1176,7 @@ static struct clk arm_fck = {
.clksel = arm_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "mpu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -1189,6 +1191,7 @@ static struct clk emu_mpu_alwon_ck = {
.parent = &mpu_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "mpu_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1306,6 +1309,7 @@ static struct clk gfx_l3_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1459,6 +1463,7 @@ static struct clk ts_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1468,6 +1473,7 @@ static struct clk usbtll_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1624,6 +1630,7 @@ static struct clk mcspi4_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1634,6 +1641,7 @@ static struct clk mcspi3_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1644,6 +1652,7 @@ static struct clk mcspi2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1654,6 +1663,7 @@ static struct clk mcspi1_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1663,6 +1673,7 @@ static struct clk uart2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1672,6 +1683,7 @@ static struct clk uart1_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1681,6 +1693,7 @@ static struct clk fshostusb_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1701,6 +1714,7 @@ static struct clk hdq_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1739,6 +1753,7 @@ static struct clk ssi_sst_fck = {
.parent = &ssi_ssr_fck,
.fixed_div = 2,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};
@@ -1796,6 +1811,7 @@ static struct clk security_l3_ick = {
.parent = &l3_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
@@ -1805,6 +1821,7 @@ static struct clk pka_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_PKA_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2089,6 +2106,7 @@ static struct clk omapctrl_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
.flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2131,6 +2149,7 @@ static struct clk usb_l4_ick = {
.clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
.clksel = usb_l4_clksel,
.flags = CLOCK_IN_OMAP3430ES1,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
@@ -2143,6 +2162,7 @@ static struct clk security_l4_ick2 = {
.parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2152,6 +2172,7 @@ static struct clk aes1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_AES1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2161,6 +2182,7 @@ static struct clk rng_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_RNG_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2170,6 +2192,7 @@ static struct clk sha11_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
@@ -2179,6 +2202,7 @@ static struct clk des1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_DES1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 11/12] OMAP3 clock: remove duplicate call to omap2_init_clk_clkdm()
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (9 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 09/12] OMAP2/3 clock: note clockdomains for remaining clocks Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
2008-09-08 16:57 ` [PATCH 12/12] OMAP2/3 clock: warn if clock is missing clockdomain Paul Walmsley
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
The OMAP3 arch clock init code already calls omap2_init_clk_clkdm(), so there
is no reason to call it again in the per-clock init.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.h | 17 -----------------
1 files changed, 0 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 8fe87e3..65568c3 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1337,7 +1337,6 @@ static struct clk gfx_l3_ick = {
static struct clk gfx_cg1_ck = {
.name = "gfx_cg1_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -1348,7 +1347,6 @@ static struct clk gfx_cg1_ck = {
static struct clk gfx_cg2_ck = {
.name = "gfx_cg2_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -1392,7 +1390,6 @@ static struct clk sgx_fck = {
static struct clk sgx_ick = {
.name = "sgx_ick",
.parent = &l3_ick,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -1405,7 +1402,6 @@ static struct clk sgx_ick = {
static struct clk d2d_26m_fck = {
.name = "d2d_26m_fck",
.parent = &sys_ck,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
@@ -1768,7 +1764,6 @@ static struct clk ssi_sst_fck = {
static struct clk core_l3_ick = {
.name = "core_l3_ick",
.parent = &l3_ick,
- .init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "core_l3_clkdm" },
@@ -1830,7 +1825,6 @@ static struct clk pka_ick = {
static struct clk core_l4_ick = {
.name = "core_l4_ick",
.parent = &l4_ick,
- .init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "core_l4_clkdm" },
@@ -2230,7 +2224,6 @@ static struct clk dss1_alwon_fck = {
static struct clk dss_tv_fck = {
.name = "dss_tv_fck",
.parent = &omap_54m_fck,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2241,7 +2234,6 @@ static struct clk dss_tv_fck = {
static struct clk dss_96m_fck = {
.name = "dss_96m_fck",
.parent = &omap_96m_fck,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2252,7 +2244,6 @@ static struct clk dss_96m_fck = {
static struct clk dss2_alwon_fck = {
.name = "dss2_alwon_fck",
.parent = &sys_ck,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2264,7 +2255,6 @@ static struct clk dss_ick = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
.parent = &l4_ick,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2298,7 +2288,6 @@ static struct clk cam_ick = {
/* Handles both L3 and L4 clocks */
.name = "cam_ick",
.parent = &l4_ick,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
@@ -2322,7 +2311,6 @@ static struct clk csi2_96m_fck = {
static struct clk usbhost_120m_fck = {
.name = "usbhost_120m_fck",
.parent = &omap_120m_fck,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -2333,7 +2321,6 @@ static struct clk usbhost_120m_fck = {
static struct clk usbhost_48m_fck = {
.name = "usbhost_48m_fck",
.parent = &omap_48m_fck,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -2345,7 +2332,6 @@ static struct clk usbhost_ick = {
/* Handles both L3 and L4 clocks */
.name = "usbhost_ick",
.parent = &l4_ick,
- .init = &omap2_init_clk_clkdm,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
@@ -2408,7 +2394,6 @@ static struct clk gpt1_fck = {
static struct clk wkup_32k_fck = {
.name = "wkup_32k_fck",
- .init = &omap2_init_clk_clkdm,
.parent = &omap_32k_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.clkdm = { .name = "prm_clkdm" },
@@ -2522,7 +2507,6 @@ static struct clk gpt1_ick = {
static struct clk per_96m_fck = {
.name = "per_96m_fck",
.parent = &omap_96m_alwon_fck,
- .init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "per_clkdm" },
@@ -2532,7 +2516,6 @@ static struct clk per_96m_fck = {
static struct clk per_48m_fck = {
.name = "per_48m_fck",
.parent = &omap_48m_fck,
- .init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.clkdm = { .name = "per_clkdm" },
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 12/12] OMAP2/3 clock: warn if clock is missing clockdomain
2008-09-08 16:57 [PATCH 00/12] Update OMAP2/3 powerdomains, clockdomains Paul Walmsley
` (10 preceding siblings ...)
2008-09-08 16:57 ` [PATCH 11/12] OMAP3 clock: remove duplicate call to omap2_init_clk_clkdm() Paul Walmsley
@ 2008-09-08 16:57 ` Paul Walmsley
11 siblings, 0 replies; 13+ messages in thread
From: Paul Walmsley @ 2008-09-08 16:57 UTC (permalink / raw)
To: linux-omap; +Cc: Paul Walmsley
At this point, all OMAP2/3 clocks should be associated with a clockdomain.
Warn in clk_register() if any are missing a clockdomain
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock.c | 8 +++++---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index be5c616..b134ca9 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -78,8 +78,10 @@ void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
- if (!clk->clkdm.name)
+ if (!clk->clkdm.name) {
+ pr_err("clock: %s: missing clockdomain", clk->name);
return;
+ }
clkdm = clkdm_lookup(clk->clkdm.name);
if (clkdm) {
@@ -87,8 +89,8 @@ void omap2_init_clk_clkdm(struct clk *clk)
clk->name, clk->clkdm.name);
clk->clkdm.ptr = clkdm;
} else {
- pr_debug("clock: could not associate clk %s to "
- "clkdm %s\n", clk->name, clk->clkdm.name);
+ pr_err("clock: %s: could not associate to clkdm %s\n",
+ clk->name, clk->clkdm.name);
}
}
^ permalink raw reply related [flat|nested] 13+ messages in thread