Re: [RFC] Patch for proper Cortex-A8 cache configuration output

[Tony Lindgren <tony@atomide.com>]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [080911 01:46]:
> On Wed, Sep 10, 2008 at 04:28:07PM -0700, Tony Lindgren wrote:
> > I guess Catalin will submit his patch at some point after 2.6.28 opens.
> > I'll apply it l-o tree, and remove the L2 debug info we had in id.c
> > to clean up id.c in the future patches.
> 
> As I've said on the main ARM lists where I've given reasons, I'm against
> extending this stuff, and it is my intention to remove it completely.
> It was only added because it was relatively simple and easy to print the
> information.
> 
> However, with ARMs attitude of breaking configuration register formats
> willy nilly, it's just not worth having the additional complexity to
> try to work out which format we have, and decode that format.
> 
> For all we know, come the next ARM architecture revision, these registers
> will have completely changed their format again.  So much for providing
> software with an easy way to determine the parameters of the core.
> 
> It's just not worth the complexity and effort to try and decode this
> information for no other purpose than a few printk's.

Hmm, people need to see what's enabled though.

For later ARMs, would it make sense to have some arm_l2_init() function
that would get called from mach specific init to set the timings and enable
L2? That function could then dump the cache configuration too.

Tony