From: Paul Walmsley <paul@pwsan.com>
To: linux-omap@vger.kernel.org
Cc: Paul Walmsley <paul@pwsan.com>
Subject: [PATCH 4/6] OMAP3 clock: omap3_clkoutx2_recalc() should test DPLL IDLEST to determine if DPLL is bypassed
Date: Tue, 16 Sep 2008 06:16:39 -0600 [thread overview]
Message-ID: <20080916121636.4666.73167.stgit@localhost.localdomain> (raw)
In-Reply-To: <20080916121521.4666.61245.stgit@localhost.localdomain>
Convert the DPLL bypass test in omap3_clkoutx2_recalc() to test DPLL IDLEST
bits rather than the CM_CLKEN register.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.c | 7 +++----
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index c5765bf..6963f2e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -577,11 +577,10 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
dd = pclk->dpll_data;
- WARN_ON(!dd->control_reg || !dd->enable_mask);
+ WARN_ON(!dd->idlest_reg || !dd->idlest_mask);
- v = __raw_readl(dd->control_reg) & dd->enable_mask;
- v >>= __ffs(dd->enable_mask);
- if (v != DPLL_LOCKED)
+ v = __raw_readl(dd->idlest_reg) & dd->idlest_mask;
+ if (!v)
clk->rate = clk->parent->rate;
else
clk->rate = clk->parent->rate * 2;
next prev parent reply other threads:[~2008-09-16 12:17 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-16 12:16 [PATCH 0/6] OMAP2/3 clock: revise DPLL bypass handling in clock tree Paul Walmsley
2008-09-16 12:16 ` [PATCH 1/6] OMAP2/3 clock: convert dpll_data.idlest_bit to idlest_mask Paul Walmsley
2008-09-16 12:16 ` [PATCH 2/6] OMAP3 clock: add idlest_reg, idlest_mask for DPLL3 Paul Walmsley
2008-09-16 12:16 ` [PATCH 3/6] OMAP2/3 clock: move DPLL bypass rate calculation into omap2_get_dpll_rate() Paul Walmsley
2008-09-16 12:16 ` Paul Walmsley [this message]
2008-09-16 12:16 ` [PATCH 5/6] OMAP3 clock: DPLLs should enter bypass if new rate is sys_ck Paul Walmsley
2008-09-16 12:16 ` [PATCH 6/6] OMAP3 clock: recalculate DPLL subtree after bypass entry/exit Paul Walmsley
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