[PATCH v2 00/11] OMAP2/3 clock: encode prcm

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* [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk
@ 2008-09-18 17:46 Paul Walmsley
  2008-09-18 17:46 ` [PATCH v2 01/11] OMAP3 clock: split mcbspX_src_fck from mcbspX_fck Paul Walmsley
                   ` (9 more replies)
  0 siblings, 10 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:46 UTC (permalink / raw)
  To: linux-omap

This second revision splits up the final patch into several pieces
and fixes a bug previously introduced in the clksel code.

---

Add a new field, prcm_mod, to the OMAP2/3 struct clk.  Major effects
of this change include:

- the removal of the register rewriting code for OMAP2xxx clock framework,

- the resolution of gcc and sparse warnings for the clock code,

- the removal of many __force void __iomem * casts in the clock tree,

- and the reduction of the register address field size in struct clk by two
  bytes per clk.


This series applies on top of the second version of the 
"OMAP2/3 clock: revise DPLL bypass handling in clock tree"
series.  This series is a prerequisite for the IDLEST handling
revision patches, following shortly.

Boot-tested on 3430SDP and N800.

---

size:
   text    data     bss     dec     hex filename
3443344  158160  105504 3707008  389080 vmlinux.3430sdp.orig
3443440  157712  105504 3706656  388f20 vmlinux.3430sdp


 arch/arm/mach-omap2/clock.c             |  229 +++++------
 arch/arm/mach-omap2/clock.h             |    3 
 arch/arm/mach-omap2/clock24xx.c         |   58 ---
 arch/arm/mach-omap2/clock24xx.h         |  454 +++++++++++++--------
 arch/arm/mach-omap2/clock34xx.c         |   27 +
 arch/arm/mach-omap2/clock34xx.h         |  671 ++++++++++++++++++++-----------
 arch/arm/mach-omap2/cm.h                |    3 
 arch/arm/plat-omap/common.c             |    1 
 arch/arm/plat-omap/include/mach/clock.h |   25 +
 9 files changed, 875 insertions(+), 596 deletions(-)


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH v2 01/11] OMAP3 clock: split mcbspX_src_fck from mcbspX_fck
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
@ 2008-09-18 17:46 ` Paul Walmsley
  2008-09-18 17:46 ` [PATCH v2 02/11] OMAP2/3 clock: shorten some variable names in clock.c for legibility Paul Walmsley
                   ` (8 subsequent siblings)
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:46 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

McBSP clock source control registers are located in the System Control
Module, not the PRCM.  However, the clock enable/disable registers are
in the CM.  Since the following patches require all registers in a
struct clk to be in only one of {CM, PRM, SCM}, we must split the
source clock selection into a separate struct clk from the clock
enable/disable control.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock34xx.h |   82 +++++++++++++++++++++++++++++++--------
 1 files changed, 66 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 92d6903..adfbcb7 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1472,12 +1472,10 @@ static const struct clksel mcbsp_15_clksel[] = {
 	{ .parent = NULL }
 };
 
-static struct clk mcbsp5_fck = {
-	.name		= "mcbsp_fck",
+static struct clk mcbsp5_src_fck = {
+	.name		= "mcbsp_src_fck",
 	.id		= 5,
 	.init		= &omap2_init_clksel_parent,
-	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 	.clksel_mask	= OMAP2_MCBSP5_CLKS_MASK,
 	.clksel		= mcbsp_15_clksel,
@@ -1486,12 +1484,21 @@ static struct clk mcbsp5_fck = {
 	.recalc		= &omap2_clksel_recalc,
 };
 
-static struct clk mcbsp1_fck = {
+static struct clk mcbsp5_fck = {
 	.name		= "mcbsp_fck",
+	.id		= 5,
+	.parent		= &mcbsp5_src_fck,
+	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "core_l4_clkdm" },
+	.recalc		= &followparent_recalc,
+};
+
+static struct clk mcbsp1_src_fck = {
+	.name		= "mcbsp_src_fck",
 	.id		= 1,
 	.init		= &omap2_init_clksel_parent,
-	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 	.clksel_mask	= OMAP2_MCBSP1_CLKS_MASK,
 	.clksel		= mcbsp_15_clksel,
@@ -1500,6 +1507,17 @@ static struct clk mcbsp1_fck = {
 	.recalc		= &omap2_clksel_recalc,
 };
 
+static struct clk mcbsp1_fck = {
+	.name		= "mcbsp_fck",
+	.id		= 1,
+	.parent		= &mcbsp1_src_fck,
+	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "core_l4_clkdm" },
+	.recalc		= &followparent_recalc,
+};
+
 /* CORE_48M_FCK-derived clocks */
 
 static struct clk core_48m_fck = {
@@ -2773,14 +2791,35 @@ static const struct clksel mcbsp_234_clksel[] = {
 	{ .parent = NULL }
 };
 
+static struct clk mcbsp2_src_fck = {
+	.name		= "mcbsp_src_fck",
+	.id		= 2,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
+	.clksel		= mcbsp_234_clksel,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "per_clkdm" },
+	.recalc		= &omap2_clksel_recalc,
+};
+
 static struct clk mcbsp2_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 2,
-	.init		= &omap2_init_clksel_parent,
+	.parent		= &mcbsp2_src_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
-	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "per_clkdm" },
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_src_fck = {
+	.name		= "mcbsp_src_fck",
+	.id		= 3,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+	.clksel_mask	= OMAP2_MCBSP3_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.clkdm		= { .name = "per_clkdm" },
@@ -2790,11 +2829,20 @@ static struct clk mcbsp2_fck = {
 static struct clk mcbsp3_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 3,
-	.init		= &omap2_init_clksel_parent,
+	.parent		= &mcbsp3_src_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "per_clkdm" },
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_src_fck = {
+	.name		= "mcbsp_src_fck",
+	.id		= 4,
+	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-	.clksel_mask	= OMAP2_MCBSP3_CLKS_MASK,
+	.clksel_mask	= OMAP2_MCBSP4_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.clkdm		= { .name = "per_clkdm" },
@@ -2804,12 +2852,9 @@ static struct clk mcbsp3_fck = {
 static struct clk mcbsp4_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 4,
-	.init		= &omap2_init_clksel_parent,
+	.parent		= &mcbsp4_src_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
-	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-	.clksel_mask	= OMAP2_MCBSP4_CLKS_MASK,
-	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.clkdm		= { .name = "per_clkdm" },
 	.recalc		= &omap2_clksel_recalc,
@@ -3091,7 +3136,9 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&i2c3_fck,
 	&i2c2_fck,
 	&i2c1_fck,
+	&mcbsp5_src_fck,
 	&mcbsp5_fck,
+	&mcbsp1_src_fck,
 	&mcbsp1_fck,
 	&core_48m_fck,
 	&mcspi4_fck,
@@ -3207,8 +3254,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&mcbsp2_ick,
 	&mcbsp3_ick,
 	&mcbsp4_ick,
+	&mcbsp2_src_fck,
 	&mcbsp2_fck,
+	&mcbsp3_src_fck,
 	&mcbsp3_fck,
+	&mcbsp4_src_fck,
 	&mcbsp4_fck,
 	&emu_src_ck,
 	&pclk_fck,



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 02/11] OMAP2/3 clock: shorten some variable names in clock.c for legibility
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
  2008-09-18 17:46 ` [PATCH v2 01/11] OMAP3 clock: split mcbspX_src_fck from mcbspX_fck Paul Walmsley
@ 2008-09-18 17:46 ` Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 03/11] OMAP2 clock: add clk.prcm_mod field; annotate OMAP2xxx clocks Paul Walmsley
                   ` (7 subsequent siblings)
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:46 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Some unnecessarily verbose variable names are used in several clock.c
functions; clean these up per CodingStyle.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock.c |   39 +++++++++++++++++++--------------------
 1 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 16cedb2..56065aa 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -219,8 +219,7 @@ void omap2_fixed_divisor_recalc(struct clk *clk)
  */
 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
 {
-	int i = 0;
-	int ena = 0;
+	int i = 0, ena = 0;
 
 	/*
 	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
@@ -351,7 +350,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
  */
 static int _omap2_clk_enable(struct clk *clk)
 {
-	u32 regval32;
+	u32 v;
 
 	if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
 		return 0;
@@ -365,12 +364,12 @@ static int _omap2_clk_enable(struct clk *clk)
 		return 0; /* REVISIT: -EINVAL */
 	}
 
-	regval32 = __raw_readl(clk->enable_reg);
+	v = __raw_readl(clk->enable_reg);
 	if (clk->flags & INVERT_ENABLE)
-		regval32 &= ~(1 << clk->enable_bit);
+		v &= ~(1 << clk->enable_bit);
 	else
-		regval32 |= (1 << clk->enable_bit);
-	__raw_writel(regval32, clk->enable_reg);
+		v |= (1 << clk->enable_bit);
+	__raw_writel(v, clk->enable_reg);
 	wmb();
 
 	omap2_clk_wait_ready(clk);
@@ -381,7 +380,7 @@ static int _omap2_clk_enable(struct clk *clk)
 /* Disables clock without considering parent dependencies or use count */
 static void _omap2_clk_disable(struct clk *clk)
 {
-	u32 regval32;
+	u32 v;
 
 	if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
 		return;
@@ -401,12 +400,12 @@ static void _omap2_clk_disable(struct clk *clk)
 		return;
 	}
 
-	regval32 = __raw_readl(clk->enable_reg);
+	v = __raw_readl(clk->enable_reg);
 	if (clk->flags & INVERT_ENABLE)
-		regval32 |= (1 << clk->enable_bit);
+		v |= (1 << clk->enable_bit);
 	else
-		regval32 &= ~(1 << clk->enable_bit);
-	__raw_writel(regval32, clk->enable_reg);
+		v &= ~(1 << clk->enable_bit);
+	__raw_writel(v, clk->enable_reg);
 	wmb();
 }
 
@@ -701,17 +700,17 @@ static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
  */
 u32 omap2_clksel_get_divisor(struct clk *clk)
 {
-	u32 field_mask, field_val;
+	u32 field_mask, v;
 	void __iomem *div_addr;
 
 	div_addr = omap2_get_clksel(clk, &field_mask);
 	if (div_addr == NULL)
 		return 0;
 
-	field_val = __raw_readl(div_addr) & field_mask;
-	field_val >>= __ffs(field_mask);
+	v = __raw_readl(div_addr) & field_mask;
+	v >>= __ffs(field_mask);
 
-	return omap2_clksel_to_divisor(clk, field_val);
+	return omap2_clksel_to_divisor(clk, v);
 }
 
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
@@ -816,7 +815,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
 	void __iomem *src_addr;
-	u32 field_val, field_mask, reg_val, parent_div;
+	u32 field_val, field_mask, v, parent_div;
 
 	if (clk->flags & CONFIG_PARTICIPANT)
 		return -EINVAL;
@@ -833,9 +832,9 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 		_omap2_clk_disable(clk);
 
 	/* Set new source value (previous dividers if any in effect) */
-	reg_val = __raw_readl(src_addr) & ~field_mask;
-	reg_val |= (field_val << __ffs(field_mask));
-	__raw_writel(reg_val, src_addr);
+	v = __raw_readl(src_addr) & ~field_mask;
+	v |= (field_val << __ffs(field_mask));
+	__raw_writel(v, src_addr);
 	wmb();
 
 	if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 03/11] OMAP2 clock: add clk.prcm_mod field; annotate OMAP2xxx clocks
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
  2008-09-18 17:46 ` [PATCH v2 01/11] OMAP3 clock: split mcbspX_src_fck from mcbspX_fck Paul Walmsley
  2008-09-18 17:46 ` [PATCH v2 02/11] OMAP2/3 clock: shorten some variable names in clock.c for legibility Paul Walmsley
@ 2008-09-18 17:47 ` Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 04/11] OMAP3 clock: add "prcm_mod" field to OMAP3xxx clocks Paul Walmsley
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Add a "prcm_mod" field to the struct clk in OMAP2/3, and annotate each
OMAP2xxx real hardware clock controlled by the PRCM with the PRCM
module offset.  (A subsequent patch will annotate OMAP3 clocks.)

Add flags for this field that allow the registers to
be marked as existing in the PRM, CM, or System Control Module.

A subsequent patch will use this to simplify register addressing in the
struct clk.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock24xx.h         |  128 +++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/mach/clock.h |    8 ++
 2 files changed, 136 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 775d08b..e4630e5 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -696,6 +696,7 @@ static struct dpll_data dpll_dd = {
 static struct clk dpll_ck = {
 	.name		= "dpll_ck",
 	.parent		= &sys_ck,		/* Can be func_32k also */
+	.prcm_mod	= PLL_MOD,
 	.dpll_data	= &dpll_dd,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -707,6 +708,7 @@ static struct clk dpll_ck = {
 static struct clk apll96_ck = {
 	.name		= "apll96_ck",
 	.parent		= &sys_ck,
+	.prcm_mod	= PLL_MOD,
 	.rate		= 96000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
@@ -721,6 +723,7 @@ static struct clk apll96_ck = {
 static struct clk apll54_ck = {
 	.name		= "apll54_ck",
 	.parent		= &sys_ck,
+	.prcm_mod	= PLL_MOD,
 	.rate		= 54000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
@@ -757,6 +760,7 @@ static const struct clksel func_54m_clksel[] = {
 static struct clk func_54m_ck = {
 	.name		= "func_54m_ck",
 	.parent		= &apll54_ck,	/* can also be alt_clk */
+	.prcm_mod	= PLL_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 	.clkdm		= { .name = "cm_clkdm" },
@@ -797,6 +801,7 @@ static const struct clksel func_96m_clksel[] = {
 static struct clk func_96m_ck = {
 	.name		= "func_96m_ck",
 	.parent		= &apll96_ck,
+	.prcm_mod	= PLL_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 	.clkdm		= { .name = "cm_clkdm" },
@@ -830,6 +835,7 @@ static const struct clksel func_48m_clksel[] = {
 static struct clk func_48m_ck = {
 	.name		= "func_48m_ck",
 	.parent		= &apll96_ck,	 /* 96M or Alt */
+	.prcm_mod	= PLL_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 	.clkdm		= { .name = "cm_clkdm" },
@@ -900,6 +906,7 @@ static const struct clksel common_clkout_src_clksel[] = {
 static struct clk sys_clkout_src = {
 	.name		= "sys_clkout_src",
 	.parent		= &func_54m_ck,
+	.prcm_mod	= OMAP24XX_GR_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_PROPAGATES | OFFSET_GR_MOD,
 	.clkdm		= { .name = "prm_clkdm" },
@@ -931,6 +938,7 @@ static const struct clksel sys_clkout_clksel[] = {
 static struct clk sys_clkout = {
 	.name		= "sys_clkout",
 	.parent		= &sys_clkout_src,
+	.prcm_mod	= OMAP24XX_GR_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
 	.clkdm		= { .name = "prm_clkdm" },
@@ -946,6 +954,7 @@ static struct clk sys_clkout = {
 static struct clk sys_clkout2_src = {
 	.name		= "sys_clkout2_src",
 	.parent		= &func_54m_ck,
+	.prcm_mod	= OMAP24XX_GR_MOD,
 	.flags		= CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
 	.clkdm		= { .name = "cm_clkdm" },
 	.enable_reg	= _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
@@ -968,6 +977,7 @@ static const struct clksel sys_clkout2_clksel[] = {
 static struct clk sys_clkout2 = {
 	.name		= "sys_clkout2",
 	.parent		= &sys_clkout2_src,
+	.prcm_mod	= OMAP24XX_GR_MOD,
 	.flags		= CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
 				OFFSET_GR_MOD,
 	.clkdm		= { .name = "cm_clkdm" },
@@ -982,6 +992,7 @@ static struct clk sys_clkout2 = {
 static struct clk emul_ck = {
 	.name		= "emul_ck",
 	.parent		= &func_54m_ck,
+	.prcm_mod	= OMAP24XX_GR_MOD,
 	.flags		= CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
 	.clkdm		= { .name = "cm_clkdm" },
 	.enable_reg	= _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
@@ -1017,6 +1028,7 @@ static const struct clksel mpu_clksel[] = {
 static struct clk mpu_ck = {	/* Control cpu */
 	.name		= "mpu_ck",
 	.parent		= &core_ck,
+	.prcm_mod	= MPU_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				ALWAYS_ENABLED | DELAYED_APP |
 				CONFIG_PARTICIPANT | RATE_PROPAGATES,
@@ -1060,6 +1072,7 @@ static const struct clksel dsp_fck_clksel[] = {
 static struct clk dsp_fck = {
 	.name		= "dsp_fck",
 	.parent		= &core_ck,
+	.prcm_mod	= OMAP24XX_DSP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
 				CONFIG_PARTICIPANT | RATE_PROPAGATES,
 	.clkdm		= { .name = "dsp_clkdm" },
@@ -1090,6 +1103,7 @@ static const struct clksel dsp_irate_ick_clksel[] = {
 static struct clk dsp_irate_ick = {
 	.name		= "dsp_irate_ick",
 	.parent		= &dsp_fck,
+	.prcm_mod	= OMAP24XX_DSP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
 				CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
 	.clkdm		= { .name = "dsp_clkdm" },
@@ -1105,6 +1119,7 @@ static struct clk dsp_irate_ick = {
 static struct clk dsp_ick = {
 	.name		= "dsp_ick",	 /* apparently ipi and isp */
 	.parent		= &dsp_irate_ick,
+	.prcm_mod	= OMAP24XX_DSP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
 	.clkdm		= { .name = "dsp_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_ICLKEN),
@@ -1115,6 +1130,7 @@ static struct clk dsp_ick = {
 static struct clk iva2_1_ick = {
 	.name		= "iva2_1_ick",
 	.parent		= &dsp_irate_ick,
+	.prcm_mod	= OMAP24XX_DSP_MOD,
 	.flags		= CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
 	.clkdm		= { .name = "dsp_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
@@ -1129,6 +1145,7 @@ static struct clk iva2_1_ick = {
 static struct clk iva1_ifck = {
 	.name		= "iva1_ifck",
 	.parent		= &core_ck,
+	.prcm_mod	= OMAP24XX_DSP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
 				RATE_PROPAGATES | DELAYED_APP,
 	.clkdm		= { .name = "iva1_clkdm" },
@@ -1146,6 +1163,7 @@ static struct clk iva1_ifck = {
 static struct clk iva1_mpu_int_ifck = {
 	.name		= "iva1_mpu_int_ifck",
 	.parent		= &iva1_ifck,
+	.prcm_mod	= OMAP24XX_DSP_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "iva1_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
@@ -1192,6 +1210,7 @@ static const struct clksel core_l3_clksel[] = {
 static struct clk core_l3_ck = {	/* Used for ick and fck, interconnect */
 	.name		= "core_l3_ck",
 	.parent		= &core_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				ALWAYS_ENABLED | DELAYED_APP |
 				CONFIG_PARTICIPANT | RATE_PROPAGATES,
@@ -1221,6 +1240,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
 static struct clk usb_l4_ick = {	/* FS-USB interface clock */
 	.name		= "usb_l4_ick",
 	.parent		= &core_l3_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				DELAYED_APP | CONFIG_PARTICIPANT,
 	.clkdm		= { .name = "core_l4_clkdm" },
@@ -1255,6 +1275,7 @@ static const struct clksel l4_clksel[] = {
 static struct clk l4_ck = {		/* used both as an ick and fck */
 	.name		= "l4_ck",
 	.parent		= &core_l3_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
 	.clkdm		= { .name = "core_l4_clkdm" },
@@ -1293,6 +1314,7 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = {
 static struct clk ssi_ssr_sst_fck = {
 	.name		= "ssi_fck",
 	.parent		= &core_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				DELAYED_APP,
 	.clkdm		= { .name = "core_l3_clkdm" },
@@ -1313,6 +1335,7 @@ static struct clk ssi_ssr_sst_fck = {
 static struct clk ssi_l4_ick = {
 	.name		= "ssi_l4_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -1343,6 +1366,7 @@ static const struct clksel gfx_fck_clksel[] = {
 static struct clk gfx_3d_fck = {
 	.name		= "gfx_3d_fck",
 	.parent		= &core_l3_ck,
+	.prcm_mod	= GFX_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "gfx_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
@@ -1358,6 +1382,7 @@ static struct clk gfx_3d_fck = {
 static struct clk gfx_2d_fck = {
 	.name		= "gfx_2d_fck",
 	.parent		= &core_l3_ck,
+	.prcm_mod	= GFX_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "gfx_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
@@ -1373,6 +1398,7 @@ static struct clk gfx_2d_fck = {
 static struct clk gfx_ick = {
 	.name		= "gfx_ick",		/* From l3 */
 	.parent		= &core_l3_ck,
+	.prcm_mod	= GFX_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "gfx_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
@@ -1403,6 +1429,7 @@ static const struct clksel mdm_ick_clksel[] = {
 static struct clk mdm_ick = {		/* used both as a ick and fck */
 	.name		= "mdm_ick",
 	.parent		= &core_ck,
+	.prcm_mod	= OMAP2430_MDM_MOD,
 	.flags		= CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
 	.clkdm		= { .name = "mdm_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
@@ -1418,6 +1445,7 @@ static struct clk mdm_ick = {		/* used both as a ick and fck */
 static struct clk mdm_osc_ck = {
 	.name		= "mdm_osc_ck",
 	.parent		= &osc_ck,
+	.prcm_mod	= OMAP2430_MDM_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "mdm_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
@@ -1463,6 +1491,7 @@ static const struct clksel dss1_fck_clksel[] = {
 static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
 	.name		= "dss_ick",
 	.parent		= &l4_ck,	/* really both l3 and l4 */
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "dss_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1473,6 +1502,7 @@ static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
 static struct clk dss1_fck = {
 	.name		= "dss1_fck",
 	.parent		= &core_ck,		/* Core or sys */
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				DELAYED_APP,
 	.clkdm		= { .name = "dss_clkdm" },
@@ -1506,6 +1536,7 @@ static const struct clksel dss2_fck_clksel[] = {
 static struct clk dss2_fck = {		/* Alt clk used in power management */
 	.name		= "dss2_fck",
 	.parent		= &sys_ck,		/* fixed at sys_ck or 48MHz */
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				DELAYED_APP,
 	.clkdm		= { .name = "dss_clkdm" },
@@ -1521,6 +1552,7 @@ static struct clk dss2_fck = {		/* Alt clk used in power management */
 static struct clk dss_54m_fck = {	/* Alt clk used in power management */
 	.name		= "dss_54m_fck",	/* 54m tv clk */
 	.parent		= &func_54m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "dss_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1549,6 +1581,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
 static struct clk gpt1_ick = {
 	.name		= "gpt1_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -1559,6 +1592,7 @@ static struct clk gpt1_ick = {
 static struct clk gpt1_fck = {
 	.name		= "gpt1_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
@@ -1575,6 +1609,7 @@ static struct clk gpt1_fck = {
 static struct clk gpt2_ick = {
 	.name		= "gpt2_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1585,6 +1620,7 @@ static struct clk gpt2_ick = {
 static struct clk gpt2_fck = {
 	.name		= "gpt2_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1599,6 +1635,7 @@ static struct clk gpt2_fck = {
 static struct clk gpt3_ick = {
 	.name		= "gpt3_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1609,6 +1646,7 @@ static struct clk gpt3_ick = {
 static struct clk gpt3_fck = {
 	.name		= "gpt3_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1623,6 +1661,7 @@ static struct clk gpt3_fck = {
 static struct clk gpt4_ick = {
 	.name		= "gpt4_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1633,6 +1672,7 @@ static struct clk gpt4_ick = {
 static struct clk gpt4_fck = {
 	.name		= "gpt4_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1647,6 +1687,7 @@ static struct clk gpt4_fck = {
 static struct clk gpt5_ick = {
 	.name		= "gpt5_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1657,6 +1698,7 @@ static struct clk gpt5_ick = {
 static struct clk gpt5_fck = {
 	.name		= "gpt5_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1671,6 +1713,7 @@ static struct clk gpt5_fck = {
 static struct clk gpt6_ick = {
 	.name		= "gpt6_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1681,6 +1724,7 @@ static struct clk gpt6_ick = {
 static struct clk gpt6_fck = {
 	.name		= "gpt6_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1695,6 +1739,7 @@ static struct clk gpt6_fck = {
 static struct clk gpt7_ick = {
 	.name		= "gpt7_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1705,6 +1750,7 @@ static struct clk gpt7_ick = {
 static struct clk gpt7_fck = {
 	.name		= "gpt7_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1719,6 +1765,7 @@ static struct clk gpt7_fck = {
 static struct clk gpt8_ick = {
 	.name		= "gpt8_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1729,6 +1776,7 @@ static struct clk gpt8_ick = {
 static struct clk gpt8_fck = {
 	.name		= "gpt8_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1743,6 +1791,7 @@ static struct clk gpt8_fck = {
 static struct clk gpt9_ick = {
 	.name		= "gpt9_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1753,6 +1802,7 @@ static struct clk gpt9_ick = {
 static struct clk gpt9_fck = {
 	.name		= "gpt9_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1767,6 +1817,7 @@ static struct clk gpt9_fck = {
 static struct clk gpt10_ick = {
 	.name		= "gpt10_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1777,6 +1828,7 @@ static struct clk gpt10_ick = {
 static struct clk gpt10_fck = {
 	.name		= "gpt10_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1791,6 +1843,7 @@ static struct clk gpt10_fck = {
 static struct clk gpt11_ick = {
 	.name		= "gpt11_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1801,6 +1854,7 @@ static struct clk gpt11_ick = {
 static struct clk gpt11_fck = {
 	.name		= "gpt11_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1815,6 +1869,7 @@ static struct clk gpt11_fck = {
 static struct clk gpt12_ick = {
 	.name		= "gpt12_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1825,6 +1880,7 @@ static struct clk gpt12_ick = {
 static struct clk gpt12_fck = {
 	.name		= "gpt12_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1840,6 +1896,7 @@ static struct clk mcbsp1_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 1,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1851,6 +1908,7 @@ static struct clk mcbsp1_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 1,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1862,6 +1920,7 @@ static struct clk mcbsp2_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 2,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1873,6 +1932,7 @@ static struct clk mcbsp2_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 2,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1884,6 +1944,7 @@ static struct clk mcbsp3_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 3,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -1895,6 +1956,7 @@ static struct clk mcbsp3_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 3,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1906,6 +1968,7 @@ static struct clk mcbsp4_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 4,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -1917,6 +1980,7 @@ static struct clk mcbsp4_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 4,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1928,6 +1992,7 @@ static struct clk mcbsp5_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 5,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -1939,6 +2004,7 @@ static struct clk mcbsp5_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 5,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1950,6 +2016,7 @@ static struct clk mcspi1_ick = {
 	.name		= "mcspi_ick",
 	.id		= 1,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1961,6 +2028,7 @@ static struct clk mcspi1_fck = {
 	.name		= "mcspi_fck",
 	.id		= 1,
 	.parent		= &func_48m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1972,6 +2040,7 @@ static struct clk mcspi2_ick = {
 	.name		= "mcspi_ick",
 	.id		= 2,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -1983,6 +2052,7 @@ static struct clk mcspi2_fck = {
 	.name		= "mcspi_fck",
 	.id		= 2,
 	.parent		= &func_48m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -1994,6 +2064,7 @@ static struct clk mcspi3_ick = {
 	.name		= "mcspi_ick",
 	.id		= 3,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2005,6 +2076,7 @@ static struct clk mcspi3_fck = {
 	.name		= "mcspi_fck",
 	.id		= 3,
 	.parent		= &func_48m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2015,6 +2087,7 @@ static struct clk mcspi3_fck = {
 static struct clk uart1_ick = {
 	.name		= "uart1_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2025,6 +2098,7 @@ static struct clk uart1_ick = {
 static struct clk uart1_fck = {
 	.name		= "uart1_fck",
 	.parent		= &func_48m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2035,6 +2109,7 @@ static struct clk uart1_fck = {
 static struct clk uart2_ick = {
 	.name		= "uart2_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2045,6 +2120,7 @@ static struct clk uart2_ick = {
 static struct clk uart2_fck = {
 	.name		= "uart2_fck",
 	.parent		= &func_48m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2055,6 +2131,7 @@ static struct clk uart2_fck = {
 static struct clk uart3_ick = {
 	.name		= "uart3_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2065,6 +2142,7 @@ static struct clk uart3_ick = {
 static struct clk uart3_fck = {
 	.name		= "uart3_fck",
 	.parent		= &func_48m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2075,6 +2153,7 @@ static struct clk uart3_fck = {
 static struct clk gpios_ick = {
 	.name		= "gpios_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -2085,6 +2164,7 @@ static struct clk gpios_ick = {
 static struct clk gpios_fck = {
 	.name		= "gpios_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "prm_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
@@ -2096,6 +2176,7 @@ static struct clk gpios_fck = {
 static struct clk mpu_wdt_ick = {
 	.name		= "mpu_wdt_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "prm_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -2107,6 +2188,7 @@ static struct clk mpu_wdt_ick = {
 static struct clk mpu_wdt_fck = {
 	.name		= "mpu_wdt_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "prm_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
@@ -2117,6 +2199,7 @@ static struct clk mpu_wdt_fck = {
 static struct clk sync_32k_ick = {
 	.name		= "sync_32k_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				ENABLE_ON_INIT,
 	.clkdm		= { .name = "core_l4_clkdm" },
@@ -2129,6 +2212,7 @@ static struct clk sync_32k_ick = {
 static struct clk wdt1_ick = {
 	.name		= "wdt1_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "prm_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -2139,6 +2223,7 @@ static struct clk wdt1_ick = {
 static struct clk omapctrl_ick = {
 	.name		= "omapctrl_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				ENABLE_ON_INIT,
 	.clkdm		= { .name = "core_l4_clkdm" },
@@ -2150,6 +2235,7 @@ static struct clk omapctrl_ick = {
 static struct clk icr_ick = {
 	.name		= "icr_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= WKUP_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
@@ -2160,6 +2246,7 @@ static struct clk icr_ick = {
 static struct clk cam_ick = {
 	.name		= "cam_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2175,6 +2262,7 @@ static struct clk cam_ick = {
 static struct clk cam_fck = {
 	.name		= "cam_fck",
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l3_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2185,6 +2273,7 @@ static struct clk cam_fck = {
 static struct clk mailboxes_ick = {
 	.name		= "mailboxes_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2195,6 +2284,7 @@ static struct clk mailboxes_ick = {
 static struct clk wdt4_ick = {
 	.name		= "wdt4_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2205,6 +2295,7 @@ static struct clk wdt4_ick = {
 static struct clk wdt4_fck = {
 	.name		= "wdt4_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2215,6 +2306,7 @@ static struct clk wdt4_fck = {
 static struct clk wdt3_ick = {
 	.name		= "wdt3_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2225,6 +2317,7 @@ static struct clk wdt3_ick = {
 static struct clk wdt3_fck = {
 	.name		= "wdt3_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2235,6 +2328,7 @@ static struct clk wdt3_fck = {
 static struct clk mspro_ick = {
 	.name		= "mspro_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2245,6 +2339,7 @@ static struct clk mspro_ick = {
 static struct clk mspro_fck = {
 	.name		= "mspro_fck",
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2255,6 +2350,7 @@ static struct clk mspro_fck = {
 static struct clk mmc_ick = {
 	.name		= "mmc_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2265,6 +2361,7 @@ static struct clk mmc_ick = {
 static struct clk mmc_fck = {
 	.name		= "mmc_fck",
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2275,6 +2372,7 @@ static struct clk mmc_fck = {
 static struct clk fac_ick = {
 	.name		= "fac_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2285,6 +2383,7 @@ static struct clk fac_ick = {
 static struct clk fac_fck = {
 	.name		= "fac_fck",
 	.parent		= &func_12m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2295,6 +2394,7 @@ static struct clk fac_fck = {
 static struct clk eac_ick = {
 	.name		= "eac_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2305,6 +2405,7 @@ static struct clk eac_ick = {
 static struct clk eac_fck = {
 	.name		= "eac_fck",
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2315,6 +2416,7 @@ static struct clk eac_fck = {
 static struct clk hdq_ick = {
 	.name		= "hdq_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2325,6 +2427,7 @@ static struct clk hdq_ick = {
 static struct clk hdq_fck = {
 	.name		= "hdq_fck",
 	.parent		= &func_12m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2336,6 +2439,7 @@ static struct clk i2c2_ick = {
 	.name		= "i2c_ick",
 	.id		= 2,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2347,6 +2451,7 @@ static struct clk i2c2_fck = {
 	.name		= "i2c_fck",
 	.id		= 2,
 	.parent		= &func_12m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2358,6 +2463,7 @@ static struct clk i2chs2_fck = {
 	.name		= "i2chs_fck",
 	.id		= 2,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2369,6 +2475,7 @@ static struct clk i2c1_ick = {
 	.name		= "i2c_ick",
 	.id		= 1,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2380,6 +2487,7 @@ static struct clk i2c1_fck = {
 	.name		= "i2c_fck",
 	.id		= 1,
 	.parent		= &func_12m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2391,6 +2499,7 @@ static struct clk i2chs1_fck = {
 	.name		= "i2chs_fck",
 	.id		= 1,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2426,6 +2535,7 @@ static struct clk sdma_ick = {
 static struct clk vlynq_ick = {
 	.name		= "vlynq_ick",
 	.parent		= &core_l3_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l3_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
@@ -2461,6 +2571,7 @@ static const struct clksel vlynq_fck_clksel[] = {
 static struct clk vlynq_fck = {
 	.name		= "vlynq_fck",
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP242X | DELAYED_APP,
 	.clkdm		= { .name = "core_l3_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
@@ -2477,6 +2588,7 @@ static struct clk vlynq_fck = {
 static struct clk sdrc_ick = {
 	.name		= "sdrc_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
@@ -2487,6 +2599,7 @@ static struct clk sdrc_ick = {
 static struct clk des_ick = {
 	.name		= "des_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2497,6 +2610,7 @@ static struct clk des_ick = {
 static struct clk sha_ick = {
 	.name		= "sha_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2507,6 +2621,7 @@ static struct clk sha_ick = {
 static struct clk rng_ick = {
 	.name		= "rng_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2517,6 +2632,7 @@ static struct clk rng_ick = {
 static struct clk aes_ick = {
 	.name		= "aes_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2527,6 +2643,7 @@ static struct clk aes_ick = {
 static struct clk pka_ick = {
 	.name		= "pka_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -2537,6 +2654,7 @@ static struct clk pka_ick = {
 static struct clk usb_fck = {
 	.name		= "usb_fck",
 	.parent		= &func_48m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
 	.clkdm		= { .name = "core_l3_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2547,6 +2665,7 @@ static struct clk usb_fck = {
 static struct clk usbhs_ick = {
 	.name		= "usbhs_ick",
 	.parent		= &core_l3_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l3_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2558,6 +2677,7 @@ static struct clk mmchs1_ick = {
 	.name		= "mmchs_ick",
 	.id		= 1,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2569,6 +2689,7 @@ static struct clk mmchs1_fck = {
 	.name		= "mmchs_fck",
 	.id		= 1,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l3_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2580,6 +2701,7 @@ static struct clk mmchs2_ick = {
 	.name		= "mmchs_ick",
 	.id		= 2,
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2591,6 +2713,7 @@ static struct clk mmchs2_fck = {
 	.name		= "mmchs_fck",
 	.id		= 2,
 	.parent		= &func_96m_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2601,6 +2724,7 @@ static struct clk mmchs2_fck = {
 static struct clk gpio5_ick = {
 	.name		= "gpio5_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2611,6 +2735,7 @@ static struct clk gpio5_ick = {
 static struct clk gpio5_fck = {
 	.name		= "gpio5_fck",
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2621,6 +2746,7 @@ static struct clk gpio5_fck = {
 static struct clk mdm_intc_ick = {
 	.name		= "mdm_intc_ick",
 	.parent		= &l4_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
@@ -2632,6 +2758,7 @@ static struct clk mmchsdb1_fck = {
 	.name		= "mmchsdb_fck",
 	.id		= 1,
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2643,6 +2770,7 @@ static struct clk mmchsdb2_fck = {
 	.name		= "mmchsdb_fck",
 	.id		= 2,
 	.parent		= &func_32k_ck,
+	.prcm_mod	= CORE_MOD,
 	.flags		= CLOCK_IN_OMAP243X,
 	.clkdm		= { .name = "core_l4_clkdm" },
 	.enable_reg	= _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 0fb4271..c428cdf 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -86,6 +86,7 @@ struct clk {
 		const char		*name;
 		struct clockdomain	*ptr;
 	} clkdm;
+	s16			prcm_mod;
 #else
 	__u8			rate_offset;
 	__u8			src_offset;
@@ -164,6 +165,13 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 
 #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
 
+/*
+ * clk.prcm_mod flags (possible since only the top byte in clk.prcm_mod
+ * is significant)
+ */
+#define PRCM_MOD_ADDR_MASK	0xff00
+#define CLK_REG_IN_PRM		(1 << 0)
+#define CLK_REG_IN_SCM		(1 << 1)
 
 /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
 #define CORE_CLK_SRC_32K		0



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 04/11] OMAP3 clock: add "prcm_mod" field to OMAP3xxx clocks
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
                   ` (2 preceding siblings ...)
  2008-09-18 17:47 ` [PATCH v2 03/11] OMAP2 clock: add clk.prcm_mod field; annotate OMAP2xxx clocks Paul Walmsley
@ 2008-09-18 17:47 ` Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 05/11] OMAP2/3 clock: add _omap2_clk_{read,write}_reg() Paul Walmsley
                   ` (5 subsequent siblings)
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Annotate each OMAP2xxx real hardware clock controlled by the PRCM with
the PRCM module offset.

A subsequent patch will use this to simplify register addressing in the
struct clk.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock34xx.h |  172 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 172 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index adfbcb7..9727e1d 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -190,6 +190,7 @@ static const struct clksel osc_sys_clksel[] = {
 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 static struct clk osc_sys_ck = {
 	.name		= "osc_sys_ck",
+	.prcm_mod	= OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 	.clksel_mask	= OMAP3430_SYS_CLKIN_SEL_MASK,
@@ -217,6 +218,7 @@ static const struct clksel sys_clksel[] = {
 static struct clk sys_ck = {
 	.name		= "sys_ck",
 	.parent		= &osc_sys_ck,
+	.prcm_mod	= OMAP3430_GR_MOD | CLK_REG_IN_PRM,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 	.clksel_mask	= OMAP_SYSCLKDIV_MASK,
@@ -250,6 +252,7 @@ static struct clk mcbsp_clks = {
 static struct clk sys_clkout1 = {
 	.name		= "sys_clkout1",
 	.parent		= &osc_sys_ck,
+	.prcm_mod	= OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 	.enable_reg	= (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 	.enable_bit	= OMAP3430_CLKOUT_EN_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -314,6 +317,7 @@ static struct dpll_data dpll1_dd = {
 static struct clk dpll1_ck = {
 	.name		= "dpll1_ck",
 	.parent		= &sys_ck,
+	.prcm_mod	= MPU_MOD,
 	.dpll_data	= &dpll1_dd,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.round_rate	= &omap2_dpll_round_rate,
@@ -348,6 +352,7 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = {
 static struct clk dpll1_x2m2_ck = {
 	.name		= "dpll1_x2m2_ck",
 	.parent		= &dpll1_x2_ck,
+	.prcm_mod	= MPU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 	.clksel_mask	= OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
@@ -387,6 +392,7 @@ static struct dpll_data dpll2_dd = {
 static struct clk dpll2_ck = {
 	.name		= "dpll2_ck",
 	.parent		= &sys_ck,
+	.prcm_mod	= OMAP3430_IVA2_MOD,
 	.dpll_data	= &dpll2_dd,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 	.enable		= &omap3_noncore_dpll_enable,
@@ -409,6 +415,7 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = {
 static struct clk dpll2_m2_ck = {
 	.name		= "dpll2_m2_ck",
 	.parent		= &dpll2_ck,
+	.prcm_mod	= OMAP3430_IVA2_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 					  OMAP3430_CM_CLKSEL2_PLL),
@@ -448,6 +455,7 @@ static struct dpll_data dpll3_dd = {
 static struct clk dpll3_ck = {
 	.name		= "dpll3_ck",
 	.parent		= &sys_ck,
+	.prcm_mod	= PLL_MOD,
 	.dpll_data	= &dpll3_dd,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.round_rate	= &omap2_dpll_round_rate,
@@ -512,6 +520,7 @@ static const struct clksel div31_dpll3m2_clksel[] = {
 static struct clk dpll3_m2_ck = {
 	.name		= "dpll3_m2_ck",
 	.parent		= &dpll3_ck,
+	.prcm_mod	= PLL_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
@@ -552,6 +561,7 @@ static const struct clksel div16_dpll3_clksel[] = {
 static struct clk dpll3_m3_ck = {
 	.name		= "dpll3_m3_ck",
 	.parent		= &dpll3_ck,
+	.prcm_mod	= OMAP3430_EMU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_DIV_DPLL3_MASK,
@@ -566,6 +576,7 @@ static struct clk dpll3_m3_ck = {
 static struct clk dpll3_m3x2_ck = {
 	.name		= "dpll3_m3x2_ck",
 	.parent		= &dpll3_m3_ck,
+	.prcm_mod	= PLL_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_EMU_CORE_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
@@ -609,6 +620,7 @@ static struct dpll_data dpll4_dd = {
 static struct clk dpll4_ck = {
 	.name		= "dpll4_ck",
 	.parent		= &sys_ck,
+	.prcm_mod	= PLL_MOD,
 	.dpll_data	= &dpll4_dd,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 	.enable		= &omap3_noncore_dpll_enable,
@@ -642,6 +654,7 @@ static const struct clksel div16_dpll4_clksel[] = {
 static struct clk dpll4_m2_ck = {
 	.name		= "dpll4_m2_ck",
 	.parent		= &dpll4_ck,
+	.prcm_mod	= PLL_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 	.clksel_mask	= OMAP3430_DIV_96M_MASK,
@@ -656,6 +669,7 @@ static struct clk dpll4_m2_ck = {
 static struct clk dpll4_m2x2_ck = {
 	.name		= "dpll4_m2x2_ck",
 	.parent		= &dpll4_m2_ck,
+	.prcm_mod	= PLL_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_96M_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
@@ -706,6 +720,7 @@ static const struct clksel omap_96m_fck_clksel[] = {
 static struct clk omap_96m_fck = {
 	.name		= "omap_96m_fck",
 	.parent		= &sys_ck,
+	.prcm_mod	= PLL_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_SOURCE_96M_MASK,
@@ -720,6 +735,7 @@ static struct clk omap_96m_fck = {
 static struct clk dpll4_m3_ck = {
 	.name		= "dpll4_m3_ck",
 	.parent		= &dpll4_ck,
+	.prcm_mod	= OMAP3430_DSS_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,
@@ -734,6 +750,7 @@ static struct clk dpll4_m3_ck = {
 static struct clk dpll4_m3x2_ck = {
 	.name		= "dpll4_m3x2_ck",
 	.parent		= &dpll4_m3_ck,
+	.prcm_mod	= PLL_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_TV_SHIFT,
@@ -760,6 +777,7 @@ static const struct clksel omap_54m_clksel[] = {
 
 static struct clk omap_54m_fck = {
 	.name		= "omap_54m_fck",
+	.prcm_mod	= PLL_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_SOURCE_54M_MASK,
@@ -788,6 +806,7 @@ static const struct clksel omap_48m_clksel[] = {
 
 static struct clk omap_48m_fck = {
 	.name		= "omap_48m_fck",
+	.prcm_mod	= PLL_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_SOURCE_48M_MASK,
@@ -812,6 +831,7 @@ static struct clk omap_12m_fck = {
 static struct clk dpll4_m4_ck = {
 	.name		= "dpll4_m4_ck",
 	.parent		= &dpll4_ck,
+	.prcm_mod	= OMAP3430_DSS_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,
@@ -826,6 +846,7 @@ static struct clk dpll4_m4_ck = {
 static struct clk dpll4_m4x2_ck = {
 	.name		= "dpll4_m4x2_ck",
 	.parent		= &dpll4_m4_ck,
+	.prcm_mod	= PLL_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_DSS1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
@@ -837,6 +858,7 @@ static struct clk dpll4_m4x2_ck = {
 static struct clk dpll4_m5_ck = {
 	.name		= "dpll4_m5_ck",
 	.parent		= &dpll4_ck,
+	.prcm_mod	= OMAP3430_CAM_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
@@ -851,6 +873,7 @@ static struct clk dpll4_m5_ck = {
 static struct clk dpll4_m5x2_ck = {
 	.name		= "dpll4_m5x2_ck",
 	.parent		= &dpll4_m5_ck,
+	.prcm_mod	= PLL_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_CAM_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
@@ -862,6 +885,7 @@ static struct clk dpll4_m5x2_ck = {
 static struct clk dpll4_m6_ck = {
 	.name		= "dpll4_m6_ck",
 	.parent		= &dpll4_ck,
+	.prcm_mod	= OMAP3430_EMU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,
@@ -876,6 +900,7 @@ static struct clk dpll4_m6_ck = {
 static struct clk dpll4_m6x2_ck = {
 	.name		= "dpll4_m6x2_ck",
 	.parent		= &dpll4_m6_ck,
+	.prcm_mod	= PLL_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
@@ -921,6 +946,7 @@ static struct dpll_data dpll5_dd = {
 static struct clk dpll5_ck = {
 	.name		= "dpll5_ck",
 	.parent		= &sys_ck,
+	.prcm_mod	= PLL_MOD,
 	.dpll_data	= &dpll5_dd,
 	.flags		= CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 	.enable		= &omap3_noncore_dpll_enable,
@@ -939,6 +965,7 @@ static const struct clksel div16_dpll5_clksel[] = {
 static struct clk dpll5_m2_ck = {
 	.name		= "dpll5_m2_ck",
 	.parent		= &dpll5_ck,
+	.prcm_mod	= PLL_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 	.clksel_mask	= OMAP3430ES2_DIV_120M_MASK,
@@ -981,6 +1008,7 @@ static const struct clksel clkout2_src_clksel[] = {
 
 static struct clk clkout2_src_ck = {
 	.name		= "clkout2_src_ck",
+	.prcm_mod	= OMAP3430_CCR_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
 	.enable_bit	= OMAP3430_CLKOUT2_EN_SHIFT,
@@ -1008,6 +1036,7 @@ static const struct clksel sys_clkout2_clksel[] = {
 
 static struct clk sys_clkout2 = {
 	.name		= "sys_clkout2",
+	.prcm_mod	= OMAP3430_CCR_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
 	.clksel_mask	= OMAP3430_CLKOUT2_DIV_MASK,
@@ -1045,6 +1074,7 @@ static const struct clksel div4_core_clksel[] = {
 static struct clk dpll1_fck = {
 	.name		= "dpll1_fck",
 	.parent		= &core_ck,
+	.prcm_mod	= MPU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 	.clksel_mask	= OMAP3430_MPU_CLK_SRC_MASK,
@@ -1079,6 +1109,7 @@ static const struct clksel arm_fck_clksel[] = {
 static struct clk arm_fck = {
 	.name		= "arm_fck",
 	.parent		= &mpu_ck,
+	.prcm_mod	= MPU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 	.clksel_mask	= OMAP3430_ST_MPU_CLK_MASK,
@@ -1107,6 +1138,7 @@ static struct clk emu_mpu_alwon_ck = {
 static struct clk dpll2_fck = {
 	.name		= "dpll2_fck",
 	.parent		= &core_ck,
+	.prcm_mod	= OMAP3430_IVA2_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 	.clksel_mask	= OMAP3430_IVA2_CLK_SRC_MASK,
@@ -1120,6 +1152,7 @@ static struct clk dpll2_fck = {
 static struct clk iva2_ck = {
 	.name		= "iva2_ck",
 	.parent		= &dpll2_m2_ck,
+	.prcm_mod	= OMAP3430_IVA2_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
@@ -1138,6 +1171,7 @@ static const struct clksel div2_core_clksel[] = {
 static struct clk l3_ick = {
 	.name		= "l3_ick",
 	.parent		= &core_ck,
+	.prcm_mod	= CORE_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_L3_MASK,
@@ -1156,6 +1190,7 @@ static const struct clksel div2_l3_clksel[] = {
 static struct clk l4_ick = {
 	.name		= "l4_ick",
 	.parent		= &l3_ick,
+	.prcm_mod	= CORE_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_L4_MASK,
@@ -1175,6 +1210,7 @@ static const struct clksel div2_l4_clksel[] = {
 static struct clk rm_ick = {
 	.name		= "rm_ick",
 	.parent		= &l4_ick,
+	.prcm_mod	= WKUP_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_RM_MASK,
@@ -1197,6 +1233,7 @@ static const struct clksel gfx_l3_clksel[] = {
 static struct clk gfx_l3_ck = {
 	.name		= "gfx_l3_ck",
 	.parent		= &l3_ick,
+	.prcm_mod	= GFX_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP_EN_GFX_SHIFT,
@@ -1208,6 +1245,7 @@ static struct clk gfx_l3_ck = {
 static struct clk gfx_l3_fck = {
 	.name		= "gfx_l3_fck",
 	.parent		= &gfx_l3_ck,
+	.prcm_mod	= GFX_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP_CLKSEL_GFX_MASK,
@@ -1229,6 +1267,7 @@ static struct clk gfx_l3_ick = {
 static struct clk gfx_cg1_ck = {
 	.name		= "gfx_cg1_ck",
 	.parent		= &gfx_l3_fck, /* REVISIT: correct? */
+	.prcm_mod	= GFX_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES1_EN_2D_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES1,
@@ -1239,6 +1278,7 @@ static struct clk gfx_cg1_ck = {
 static struct clk gfx_cg2_ck = {
 	.name		= "gfx_cg2_ck",
 	.parent		= &gfx_l3_fck, /* REVISIT: correct? */
+	.prcm_mod	= GFX_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES1_EN_3D_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES1,
@@ -1269,6 +1309,7 @@ static const struct clksel sgx_clksel[] = {
 static struct clk sgx_fck = {
 	.name		= "sgx_fck",
 	.init		= &omap2_init_clksel_parent,
+	.prcm_mod	= OMAP3430ES2_SGX_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
@@ -1282,6 +1323,7 @@ static struct clk sgx_fck = {
 static struct clk sgx_ick = {
 	.name		= "sgx_ick",
 	.parent		= &l3_ick,
+	.prcm_mod	= OMAP3430ES2_SGX_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -1294,6 +1336,7 @@ static struct clk sgx_ick = {
 static struct clk d2d_26m_fck = {
 	.name		= "d2d_26m_fck",
 	.parent		= &sys_ck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430ES1_EN_D2D_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES1,
@@ -1310,6 +1353,7 @@ static const struct clksel omap343x_gpt_clksel[] = {
 static struct clk gpt10_fck = {
 	.name		= "gpt10_fck",
 	.parent		= &sys_ck,
+	.prcm_mod	= CORE_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_GPT10_SHIFT,
@@ -1324,6 +1368,7 @@ static struct clk gpt10_fck = {
 static struct clk gpt11_fck = {
 	.name		= "gpt11_fck",
 	.parent		= &sys_ck,
+	.prcm_mod	= CORE_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_GPT11_SHIFT,
@@ -1338,6 +1383,7 @@ static struct clk gpt11_fck = {
 static struct clk cpefuse_fck = {
 	.name		= "cpefuse_fck",
 	.parent		= &sys_ck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 	.enable_bit	= OMAP3430ES2_EN_CPEFUSE_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -1348,6 +1394,7 @@ static struct clk cpefuse_fck = {
 static struct clk ts_fck = {
 	.name		= "ts_fck",
 	.parent		= &omap_32k_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 	.enable_bit	= OMAP3430ES2_EN_TS_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -1358,6 +1405,7 @@ static struct clk ts_fck = {
 static struct clk usbtll_fck = {
 	.name		= "usbtll_fck",
 	.parent		= &dpll5_m2_ck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -1380,6 +1428,7 @@ static struct clk mmchs3_fck = {
 	.name		= "mmchs_fck",
 	.id		= 3,
 	.parent		= &core_96m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430ES2_EN_MMC3_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -1391,6 +1440,7 @@ static struct clk mmchs2_fck = {
 	.name		= "mmchs_fck",
 	.id		= 2,
 	.parent		= &core_96m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MMC2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1401,6 +1451,7 @@ static struct clk mmchs2_fck = {
 static struct clk mspro_fck = {
 	.name		= "mspro_fck",
 	.parent		= &core_96m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MSPRO_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1412,6 +1463,7 @@ static struct clk mmchs1_fck = {
 	.name		= "mmchs_fck",
 	.id		= 1,
 	.parent		= &core_96m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MMC1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1423,6 +1475,7 @@ static struct clk i2c3_fck = {
 	.name		= "i2c_fck",
 	.id		= 3,
 	.parent		= &core_96m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1434,6 +1487,7 @@ static struct clk i2c2_fck = {
 	.name		= "i2c_fck",
 	.id		= 2,
 	.parent		= &core_96m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1445,6 +1499,7 @@ static struct clk i2c1_fck = {
 	.name		= "i2c_fck",
 	.id		= 1,
 	.parent		= &core_96m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1475,6 +1530,7 @@ static const struct clksel mcbsp_15_clksel[] = {
 static struct clk mcbsp5_src_fck = {
 	.name		= "mcbsp_src_fck",
 	.id		= 5,
+	.prcm_mod	= CLK_REG_IN_SCM,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 	.clksel_mask	= OMAP2_MCBSP5_CLKS_MASK,
@@ -1488,6 +1544,7 @@ static struct clk mcbsp5_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 5,
 	.parent		= &mcbsp5_src_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1498,6 +1555,7 @@ static struct clk mcbsp5_fck = {
 static struct clk mcbsp1_src_fck = {
 	.name		= "mcbsp_src_fck",
 	.id		= 1,
+	.prcm_mod	= CLK_REG_IN_SCM,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 	.clksel_mask	= OMAP2_MCBSP1_CLKS_MASK,
@@ -1511,6 +1569,7 @@ static struct clk mcbsp1_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 1,
 	.parent		= &mcbsp1_src_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1533,6 +1592,7 @@ static struct clk mcspi4_fck = {
 	.name		= "mcspi_fck",
 	.id		= 4,
 	.parent		= &core_48m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI4_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1544,6 +1604,7 @@ static struct clk mcspi3_fck = {
 	.name		= "mcspi_fck",
 	.id		= 3,
 	.parent		= &core_48m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1555,6 +1616,7 @@ static struct clk mcspi2_fck = {
 	.name		= "mcspi_fck",
 	.id		= 2,
 	.parent		= &core_48m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1566,6 +1628,7 @@ static struct clk mcspi1_fck = {
 	.name		= "mcspi_fck",
 	.id		= 1,
 	.parent		= &core_48m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1576,6 +1639,7 @@ static struct clk mcspi1_fck = {
 static struct clk uart2_fck = {
 	.name		= "uart2_fck",
 	.parent		= &core_48m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_UART2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1586,6 +1650,7 @@ static struct clk uart2_fck = {
 static struct clk uart1_fck = {
 	.name		= "uart1_fck",
 	.parent		= &core_48m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_UART1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1596,6 +1661,7 @@ static struct clk uart1_fck = {
 static struct clk fshostusb_fck = {
 	.name		= "fshostusb_fck",
 	.parent		= &core_48m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES1,
@@ -1617,6 +1683,7 @@ static struct clk core_12m_fck = {
 static struct clk hdq_fck = {
 	.name		= "hdq_fck",
 	.parent		= &core_12m_fck,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_HDQ_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1644,6 +1711,7 @@ static const struct clksel ssi_ssr_clksel[] = {
 static struct clk ssi_ssr_fck = {
 	.name		= "ssi_ssr_fck",
 	.init		= &omap2_init_clksel_parent,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
@@ -1683,6 +1751,7 @@ static struct clk core_l3_ick = {
 static struct clk hsotgusb_ick = {
 	.name		= "hsotgusb_ick",
 	.parent		= &core_l3_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_HSOTGUSB_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1693,6 +1762,7 @@ static struct clk hsotgusb_ick = {
 static struct clk sdrc_ick = {
 	.name		= "sdrc_ick",
 	.parent		= &core_l3_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_SDRC_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
@@ -1723,6 +1793,7 @@ static struct clk security_l3_ick = {
 static struct clk pka_ick = {
 	.name		= "pka_ick",
 	.parent		= &security_l3_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_PKA_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1744,6 +1815,7 @@ static struct clk core_l4_ick = {
 static struct clk usbtll_ick = {
 	.name		= "usbtll_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
 	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -1755,6 +1827,7 @@ static struct clk mmchs3_ick = {
 	.name		= "mmchs_ick",
 	.id		= 3,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430ES2_EN_MMC3_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -1766,6 +1839,7 @@ static struct clk mmchs3_ick = {
 static struct clk icr_ick = {
 	.name		= "icr_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_ICR_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1776,6 +1850,7 @@ static struct clk icr_ick = {
 static struct clk aes2_ick = {
 	.name		= "aes2_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_AES2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1786,6 +1861,7 @@ static struct clk aes2_ick = {
 static struct clk sha12_ick = {
 	.name		= "sha12_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_SHA12_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1796,6 +1872,7 @@ static struct clk sha12_ick = {
 static struct clk des2_ick = {
 	.name		= "des2_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_DES2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1807,6 +1884,7 @@ static struct clk mmchs2_ick = {
 	.name		= "mmchs_ick",
 	.id		= 2,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MMC2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1818,6 +1896,7 @@ static struct clk mmchs1_ick = {
 	.name		= "mmchs_ick",
 	.id		= 1,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MMC1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1828,6 +1907,7 @@ static struct clk mmchs1_ick = {
 static struct clk mspro_ick = {
 	.name		= "mspro_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MSPRO_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1838,6 +1918,7 @@ static struct clk mspro_ick = {
 static struct clk hdq_ick = {
 	.name		= "hdq_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_HDQ_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1849,6 +1930,7 @@ static struct clk mcspi4_ick = {
 	.name		= "mcspi_ick",
 	.id		= 4,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI4_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1860,6 +1942,7 @@ static struct clk mcspi3_ick = {
 	.name		= "mcspi_ick",
 	.id		= 3,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1871,6 +1954,7 @@ static struct clk mcspi2_ick = {
 	.name		= "mcspi_ick",
 	.id		= 2,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1882,6 +1966,7 @@ static struct clk mcspi1_ick = {
 	.name		= "mcspi_ick",
 	.id		= 1,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1893,6 +1978,7 @@ static struct clk i2c3_ick = {
 	.name		= "i2c_ick",
 	.id		= 3,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1904,6 +1990,7 @@ static struct clk i2c2_ick = {
 	.name		= "i2c_ick",
 	.id		= 2,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1915,6 +2002,7 @@ static struct clk i2c1_ick = {
 	.name		= "i2c_ick",
 	.id		= 1,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1925,6 +2013,7 @@ static struct clk i2c1_ick = {
 static struct clk uart2_ick = {
 	.name		= "uart2_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_UART2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1935,6 +2024,7 @@ static struct clk uart2_ick = {
 static struct clk uart1_ick = {
 	.name		= "uart1_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_UART1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1945,6 +2035,7 @@ static struct clk uart1_ick = {
 static struct clk gpt11_ick = {
 	.name		= "gpt11_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_GPT11_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1955,6 +2046,7 @@ static struct clk gpt11_ick = {
 static struct clk gpt10_ick = {
 	.name		= "gpt10_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_GPT10_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1966,6 +2058,7 @@ static struct clk mcbsp5_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 5,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1977,6 +2070,7 @@ static struct clk mcbsp1_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 1,
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -1987,6 +2081,7 @@ static struct clk mcbsp1_ick = {
 static struct clk fac_ick = {
 	.name		= "fac_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430ES1_EN_FAC_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES1,
@@ -1997,6 +2092,7 @@ static struct clk fac_ick = {
 static struct clk mailboxes_ick = {
 	.name		= "mailboxes_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_MAILBOXES_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2007,6 +2103,7 @@ static struct clk mailboxes_ick = {
 static struct clk omapctrl_ick = {
 	.name		= "omapctrl_ick",
 	.parent		= &core_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_OMAPCTRL_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
@@ -2028,6 +2125,7 @@ static struct clk ssi_l4_ick = {
 static struct clk ssi_ick = {
 	.name		= "ssi_ick",
 	.parent		= &ssi_l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2046,6 +2144,7 @@ static const struct clksel usb_l4_clksel[] = {
 static struct clk usb_l4_ick = {
 	.name		= "usb_l4_ick",
 	.parent		= &l4_ick,
+	.prcm_mod	= CORE_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
@@ -2073,6 +2172,7 @@ static struct clk security_l4_ick2 = {
 static struct clk aes1_ick = {
 	.name		= "aes1_ick",
 	.parent		= &security_l4_ick2,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_AES1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2083,6 +2183,7 @@ static struct clk aes1_ick = {
 static struct clk rng_ick = {
 	.name		= "rng_ick",
 	.parent		= &security_l4_ick2,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_RNG_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2093,6 +2194,7 @@ static struct clk rng_ick = {
 static struct clk sha11_ick = {
 	.name		= "sha11_ick",
 	.parent		= &security_l4_ick2,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_SHA11_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2103,6 +2205,7 @@ static struct clk sha11_ick = {
 static struct clk des1_ick = {
 	.name		= "des1_ick",
 	.parent		= &security_l4_ick2,
+	.prcm_mod	= CORE_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= OMAP3430_EN_DES1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2114,6 +2217,7 @@ static struct clk des1_ick = {
 static struct clk dss1_alwon_fck = {
 	.name		= "dss1_alwon_fck",
 	.parent		= &dpll4_m4x2_ck,
+	.prcm_mod	= OMAP3430_DSS_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_DSS1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2124,6 +2228,7 @@ static struct clk dss1_alwon_fck = {
 static struct clk dss_tv_fck = {
 	.name		= "dss_tv_fck",
 	.parent		= &omap_54m_fck,
+	.prcm_mod	= OMAP3430_DSS_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_TV_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2134,6 +2239,7 @@ static struct clk dss_tv_fck = {
 static struct clk dss_96m_fck = {
 	.name		= "dss_96m_fck",
 	.parent		= &omap_96m_fck,
+	.prcm_mod	= OMAP3430_DSS_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_TV_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2144,6 +2250,7 @@ static struct clk dss_96m_fck = {
 static struct clk dss2_alwon_fck = {
 	.name		= "dss2_alwon_fck",
 	.parent		= &sys_ck,
+	.prcm_mod	= OMAP3430_DSS_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_DSS2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2155,6 +2262,7 @@ static struct clk dss_ick = {
 	/* Handles both L3 and L4 clocks */
 	.name		= "dss_ick",
 	.parent		= &l4_ick,
+	.prcm_mod	= OMAP3430_DSS_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2167,6 +2275,7 @@ static struct clk dss_ick = {
 static struct clk cam_mclk = {
 	.name		= "cam_mclk",
 	.parent		= &dpll4_m5x2_ck,
+	.prcm_mod	= OMAP3430_CAM_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_CAM_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2178,6 +2287,7 @@ static struct clk cam_ick = {
 	/* Handles both L3 and L4 clocks */
 	.name		= "cam_ick",
 	.parent		= &l4_ick,
+	.prcm_mod	= OMAP3430_CAM_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_CAM_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2188,6 +2298,7 @@ static struct clk cam_ick = {
 static struct clk csi2_96m_fck = {
 	.name		= "csi2_96m_fck",
 	.parent		= &core_96m_fck,
+	.prcm_mod	= OMAP3430_CAM_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_CSI2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2200,6 +2311,7 @@ static struct clk csi2_96m_fck = {
 static struct clk usbhost_120m_fck = {
 	.name		= "usbhost_120m_fck",
 	.parent		= &dpll5_m2_ck,
+	.prcm_mod	= OMAP3430ES2_USBHOST_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USBHOST2_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -2210,6 +2322,7 @@ static struct clk usbhost_120m_fck = {
 static struct clk usbhost_48m_fck = {
 	.name		= "usbhost_48m_fck",
 	.parent		= &omap_48m_fck,
+	.prcm_mod	= OMAP3430ES2_USBHOST_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USBHOST1_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -2221,6 +2334,7 @@ static struct clk usbhost_ick = {
 	/* Handles both L3 and L4 clocks */
 	.name		= "usbhost_ick",
 	.parent		= &l4_ick,
+	.prcm_mod	= OMAP3430ES2_USBHOST_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USBHOST_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -2256,6 +2370,7 @@ static const struct clksel usim_clksel[] = {
 /* 3430ES2 only */
 static struct clk usim_fck = {
 	.name		= "usim_fck",
+	.prcm_mod	= WKUP_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2270,6 +2385,7 @@ static struct clk usim_fck = {
 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
 static struct clk gpt1_fck = {
 	.name		= "gpt1_fck",
+	.prcm_mod	= WKUP_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT1_SHIFT,
@@ -2292,6 +2408,7 @@ static struct clk wkup_32k_fck = {
 static struct clk gpio1_fck = {
 	.name		= "gpio1_fck",
 	.parent		= &wkup_32k_fck,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2302,6 +2419,7 @@ static struct clk gpio1_fck = {
 static struct clk wdt2_fck = {
 	.name		= "wdt2_fck",
 	.parent		= &wkup_32k_fck,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_WDT2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2322,6 +2440,7 @@ static struct clk wkup_l4_ick = {
 static struct clk usim_ick = {
 	.name		= "usim_ick",
 	.parent		= &wkup_l4_ick,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430ES2_EN_USIMOCP_SHIFT,
 	.flags		= CLOCK_IN_OMAP3430ES2,
@@ -2332,6 +2451,7 @@ static struct clk usim_ick = {
 static struct clk wdt2_ick = {
 	.name		= "wdt2_ick",
 	.parent		= &wkup_l4_ick,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_WDT2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2342,6 +2462,7 @@ static struct clk wdt2_ick = {
 static struct clk wdt1_ick = {
 	.name		= "wdt1_ick",
 	.parent		= &wkup_l4_ick,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_WDT1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2352,6 +2473,7 @@ static struct clk wdt1_ick = {
 static struct clk gpio1_ick = {
 	.name		= "gpio1_ick",
 	.parent		= &wkup_l4_ick,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2362,6 +2484,7 @@ static struct clk gpio1_ick = {
 static struct clk omap_32ksync_ick = {
 	.name		= "omap_32ksync_ick",
 	.parent		= &wkup_l4_ick,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_32KSYNC_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2372,6 +2495,7 @@ static struct clk omap_32ksync_ick = {
 static struct clk gpt12_ick = {
 	.name		= "gpt12_ick",
 	.parent		= &wkup_l4_ick,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT12_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2382,6 +2506,7 @@ static struct clk gpt12_ick = {
 static struct clk gpt1_ick = {
 	.name		= "gpt1_ick",
 	.parent		= &wkup_l4_ick,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2414,6 +2539,7 @@ static struct clk per_48m_fck = {
 static struct clk uart3_fck = {
 	.name		= "uart3_fck",
 	.parent		= &per_48m_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_UART3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2423,6 +2549,7 @@ static struct clk uart3_fck = {
 
 static struct clk gpt2_fck = {
 	.name		= "gpt2_fck",
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT2_SHIFT,
@@ -2436,6 +2563,7 @@ static struct clk gpt2_fck = {
 
 static struct clk gpt3_fck = {
 	.name		= "gpt3_fck",
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT3_SHIFT,
@@ -2449,6 +2577,7 @@ static struct clk gpt3_fck = {
 
 static struct clk gpt4_fck = {
 	.name		= "gpt4_fck",
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT4_SHIFT,
@@ -2462,6 +2591,7 @@ static struct clk gpt4_fck = {
 
 static struct clk gpt5_fck = {
 	.name		= "gpt5_fck",
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT5_SHIFT,
@@ -2475,6 +2605,7 @@ static struct clk gpt5_fck = {
 
 static struct clk gpt6_fck = {
 	.name		= "gpt6_fck",
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT6_SHIFT,
@@ -2488,6 +2619,7 @@ static struct clk gpt6_fck = {
 
 static struct clk gpt7_fck = {
 	.name		= "gpt7_fck",
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT7_SHIFT,
@@ -2501,6 +2633,7 @@ static struct clk gpt7_fck = {
 
 static struct clk gpt8_fck = {
 	.name		= "gpt8_fck",
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT8_SHIFT,
@@ -2514,6 +2647,7 @@ static struct clk gpt8_fck = {
 
 static struct clk gpt9_fck = {
 	.name		= "gpt9_fck",
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPT9_SHIFT,
@@ -2536,6 +2670,7 @@ static struct clk per_32k_alwon_fck = {
 static struct clk gpio6_fck = {
 	.name		= "gpio6_fck",
 	.parent		= &per_32k_alwon_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2546,6 +2681,7 @@ static struct clk gpio6_fck = {
 static struct clk gpio5_fck = {
 	.name		= "gpio5_fck",
 	.parent		= &per_32k_alwon_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2556,6 +2692,7 @@ static struct clk gpio5_fck = {
 static struct clk gpio4_fck = {
 	.name		= "gpio4_fck",
 	.parent		= &per_32k_alwon_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2566,6 +2703,7 @@ static struct clk gpio4_fck = {
 static struct clk gpio3_fck = {
 	.name		= "gpio3_fck",
 	.parent		= &per_32k_alwon_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2576,6 +2714,7 @@ static struct clk gpio3_fck = {
 static struct clk gpio2_fck = {
 	.name		= "gpio2_fck",
 	.parent		= &per_32k_alwon_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2586,6 +2725,7 @@ static struct clk gpio2_fck = {
 static struct clk wdt3_fck = {
 	.name		= "wdt3_fck",
 	.parent		= &per_32k_alwon_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_WDT3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2605,6 +2745,7 @@ static struct clk per_l4_ick = {
 static struct clk gpio6_ick = {
 	.name		= "gpio6_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2615,6 +2756,7 @@ static struct clk gpio6_ick = {
 static struct clk gpio5_ick = {
 	.name		= "gpio5_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2625,6 +2767,7 @@ static struct clk gpio5_ick = {
 static struct clk gpio4_ick = {
 	.name		= "gpio4_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2635,6 +2778,7 @@ static struct clk gpio4_ick = {
 static struct clk gpio3_ick = {
 	.name		= "gpio3_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2645,6 +2789,7 @@ static struct clk gpio3_ick = {
 static struct clk gpio2_ick = {
 	.name		= "gpio2_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2655,6 +2800,7 @@ static struct clk gpio2_ick = {
 static struct clk wdt3_ick = {
 	.name		= "wdt3_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_WDT3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2665,6 +2811,7 @@ static struct clk wdt3_ick = {
 static struct clk uart3_ick = {
 	.name		= "uart3_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_UART3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2675,6 +2822,7 @@ static struct clk uart3_ick = {
 static struct clk gpt9_ick = {
 	.name		= "gpt9_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT9_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2685,6 +2833,7 @@ static struct clk gpt9_ick = {
 static struct clk gpt8_ick = {
 	.name		= "gpt8_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT8_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2695,6 +2844,7 @@ static struct clk gpt8_ick = {
 static struct clk gpt7_ick = {
 	.name		= "gpt7_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT7_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2705,6 +2855,7 @@ static struct clk gpt7_ick = {
 static struct clk gpt6_ick = {
 	.name		= "gpt6_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT6_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2715,6 +2866,7 @@ static struct clk gpt6_ick = {
 static struct clk gpt5_ick = {
 	.name		= "gpt5_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT5_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2725,6 +2877,7 @@ static struct clk gpt5_ick = {
 static struct clk gpt4_ick = {
 	.name		= "gpt4_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT4_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2735,6 +2888,7 @@ static struct clk gpt4_ick = {
 static struct clk gpt3_ick = {
 	.name		= "gpt3_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2745,6 +2899,7 @@ static struct clk gpt3_ick = {
 static struct clk gpt2_ick = {
 	.name		= "gpt2_ick",
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_GPT2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2756,6 +2911,7 @@ static struct clk mcbsp2_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 2,
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2767,6 +2923,7 @@ static struct clk mcbsp3_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 3,
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2778,6 +2935,7 @@ static struct clk mcbsp4_ick = {
 	.name		= "mcbsp_ick",
 	.id		= 4,
 	.parent		= &per_l4_ick,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2794,6 +2952,7 @@ static const struct clksel mcbsp_234_clksel[] = {
 static struct clk mcbsp2_src_fck = {
 	.name		= "mcbsp_src_fck",
 	.id		= 2,
+	.prcm_mod	= CLK_REG_IN_SCM,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
@@ -2807,6 +2966,7 @@ static struct clk mcbsp2_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 2,
 	.parent		= &mcbsp2_src_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2817,6 +2977,7 @@ static struct clk mcbsp2_fck = {
 static struct clk mcbsp3_src_fck = {
 	.name		= "mcbsp_src_fck",
 	.id		= 3,
+	.prcm_mod	= CLK_REG_IN_SCM,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 	.clksel_mask	= OMAP2_MCBSP3_CLKS_MASK,
@@ -2830,6 +2991,7 @@ static struct clk mcbsp3_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 3,
 	.parent		= &mcbsp3_src_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2840,6 +3002,7 @@ static struct clk mcbsp3_fck = {
 static struct clk mcbsp4_src_fck = {
 	.name		= "mcbsp_src_fck",
 	.id		= 4,
+	.prcm_mod	= CLK_REG_IN_SCM,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 	.clksel_mask	= OMAP2_MCBSP4_CLKS_MASK,
@@ -2853,6 +3016,7 @@ static struct clk mcbsp4_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 4,
 	.parent		= &mcbsp4_src_fck,
+	.prcm_mod	= OMAP3430_PER_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X,
@@ -2899,6 +3063,7 @@ static const struct clksel emu_src_clksel[] = {
  */
 static struct clk emu_src_ck = {
 	.name		= "emu_src_ck",
+	.prcm_mod	= OMAP3430_EMU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_MUX_CTRL_MASK,
@@ -2923,6 +3088,7 @@ static const struct clksel pclk_emu_clksel[] = {
 
 static struct clk pclk_fck = {
 	.name		= "pclk_fck",
+	.prcm_mod	= OMAP3430_EMU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CLKSEL_PCLK_MASK,
@@ -2946,6 +3112,7 @@ static const struct clksel pclkx2_emu_clksel[] = {
 
 static struct clk pclkx2_fck = {
 	.name		= "pclkx2_fck",
+	.prcm_mod	= OMAP3430_EMU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CLKSEL_PCLKX2_MASK,
@@ -2962,6 +3129,7 @@ static const struct clksel atclk_emu_clksel[] = {
 
 static struct clk atclk_fck = {
 	.name		= "atclk_fck",
+	.prcm_mod	= OMAP3430_EMU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CLKSEL_ATCLK_MASK,
@@ -2973,6 +3141,7 @@ static struct clk atclk_fck = {
 
 static struct clk traceclk_src_fck = {
 	.name		= "traceclk_src_fck",
+	.prcm_mod	= OMAP3430_EMU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_TRACE_MUX_CTRL_MASK,
@@ -2996,6 +3165,7 @@ static const struct clksel traceclk_clksel[] = {
 
 static struct clk traceclk_fck = {
 	.name		= "traceclk_fck",
+	.prcm_mod	= OMAP3430_EMU_MOD,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CLKSEL_TRACECLK_MASK,
@@ -3011,6 +3181,7 @@ static struct clk traceclk_fck = {
 static struct clk sr1_fck = {
 	.name		= "sr1_fck",
 	.parent		= &sys_ck,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_SR1_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
@@ -3022,6 +3193,7 @@ static struct clk sr1_fck = {
 static struct clk sr2_fck = {
 	.name		= "sr2_fck",
 	.parent		= &sys_ck,
+	.prcm_mod	= WKUP_MOD,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_SR2_SHIFT,
 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 05/11] OMAP2/3 clock: add _omap2_clk_{read,write}_reg()
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
                   ` (3 preceding siblings ...)
  2008-09-18 17:47 ` [PATCH v2 04/11] OMAP3 clock: add "prcm_mod" field to OMAP3xxx clocks Paul Walmsley
@ 2008-09-18 17:47 ` Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 06/11] OMAP2/3 clock: use symbolic constants in omap2_clk_wait_ready() Paul Walmsley
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Create new static functions to read/write registers used in the struct
clk, _omap2_clk_{read,write}_reg().  A subsequent patch will use these
to ensure the correct register read/write instruction is used, which depends
on whether the clock registers are in the CM, PRM, or SCM.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock.c |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 56065aa..2bdd587 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -29,6 +29,7 @@
 #include <mach/sram.h>
 #include <mach/cpu.h>
 #include <mach/prcm.h>
+#include <mach/control.h>
 #include <asm/div64.h>
 
 #include <mach/sdrc.h>
@@ -70,6 +71,43 @@ u8 cpu_mask;
  * OMAP2/3 specific clock functions
  *-------------------------------------------------------------------------*/
 
+/*
+ * _omap2_clk_read_reg - read a clock register
+ * @clk: struct clk *
+ *
+ * Given a struct clk *, returns the value of the clock's register.
+ */
+static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
+{
+	if (clk->prcm_mod & CLK_REG_IN_SCM)
+		return omap_ctrl_readl(reg_offset);
+	else if (clk->prcm_mod & CLK_REG_IN_PRM)
+		return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
+					reg_offset);
+	else
+		return cm_read_mod_reg(clk->prcm_mod, reg_offset);
+}
+
+/*
+ * _omap2_clk_write_reg - write a clock's register
+ * @v: value to write to the clock's enable_reg
+ * @clk: struct clk *
+ *
+ * Given a register value @v and struct clk * @clk, writes the value of @v to
+ * the clock's enable register.  No return value.
+ */
+static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
+{
+	if (clk->prcm_mod & CLK_REG_IN_SCM)
+		omap_ctrl_writel(v, reg_offset);
+	else if (clk->prcm_mod & CLK_REG_IN_PRM)
+		prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
+				  reg_offset);
+	else
+		cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
+}
+
+
 /**
  * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
  * @clk: OMAP clock struct ptr to use



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 06/11] OMAP2/3 clock: use symbolic constants in omap2_clk_wait_ready()
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
                   ` (4 preceding siblings ...)
  2008-09-18 17:47 ` [PATCH v2 05/11] OMAP2/3 clock: add _omap2_clk_{read,write}_reg() Paul Walmsley
@ 2008-09-18 17:47 ` Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 07/11] OMAP2/3 clock: use prcm_mod field " Paul Walmsley
                   ` (3 subsequent siblings)
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Convert the bare constants in the register arithmetic in
omap2_clk_wait_ready() to use meaningful symbolic names.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock.c |   19 ++++++++++++++-----
 1 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 2bdd587..ebf2d7e 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -65,6 +65,13 @@
 #define ST_CORE_CLK_REF			0x1
 #define ST_CORE_CLK_32K			0x3
 
+/* Bitmask to isolate the register type of clk.enable_reg */
+#define PRCM_REGTYPE_MASK		0xf0
+/* various CM register type options */
+#define CM_FCLKEN_REGTYPE		0x00
+#define CM_ICLKEN_REGTYPE		0x10
+#define CM_IDLEST_REGTYPE		0x20
+
 u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
@@ -301,12 +308,13 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	prcm_mod = reg & ~0xff;
 	prcm_regid = reg & 0xff;
 
+	other_reg = reg & ~PRCM_REGTYPE_MASK;
+
+	/* If we are enabling an fclk, also test the iclk; and vice versa */
 	if (prcm_regid >= CM_FCLKEN1 && prcm_regid <= OMAP24XX_CM_FCLKEN2)
-		other_reg = ((reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
-	else if (prcm_regid >= CM_ICLKEN1 && prcm_regid <= OMAP24XX_CM_ICLKEN4)
-		other_reg = ((reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
+		other_reg |= CM_ICLKEN_REGTYPE;
 	else
-		return;
+		other_reg |= CM_FCLKEN_REGTYPE;
 
 	/* Covers most of the cases - a few exceptions are below */
 	other_bit = 1 << clk->enable_bit;
@@ -377,7 +385,8 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	if (!(__raw_readl((void __iomem *)other_reg) & other_bit))
 		return;
 
-	idlest_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+	idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
+	idlest_reg |= CM_IDLEST_REGTYPE;
 
 	omap2_wait_clock_ready((void __iomem *)idlest_reg, idlest_bit,
 			       clk->name);



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 07/11] OMAP2/3 clock: use prcm_mod field in omap2_clk_wait_ready()
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
                   ` (5 preceding siblings ...)
  2008-09-18 17:47 ` [PATCH v2 06/11] OMAP2/3 clock: use symbolic constants in omap2_clk_wait_ready() Paul Walmsley
@ 2008-09-18 17:47 ` Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 08/11] OMAP2/3 clock: convert omap2_wait_clock_ready() to use clk.prcm_mod Paul Walmsley
                   ` (2 subsequent siblings)
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Use the newly-added clk.prcm_mod field in omap2_clk_wait_ready(),
removing some internal register arithmetic.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock.c |   17 +++++++++--------
 1 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ebf2d7e..6433679 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -302,10 +302,13 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
 static void omap2_clk_wait_ready(struct clk *clk)
 {
 	u32 other_bit, idlest_bit;
-	unsigned long reg, other_reg, idlest_reg, prcm_mod, prcm_regid;
+	unsigned long reg, other_reg, idlest_reg, prcm_regid;
+
+	/* Only CM-controlled clocks affect module IDLEST */
+	if (clk->prcm_mod & ~PRCM_MOD_ADDR_MASK)
+		return;
 
 	reg = (unsigned long)clk->enable_reg;
-	prcm_mod = reg & ~0xff;
 	prcm_regid = reg & 0xff;
 
 	other_reg = reg & ~PRCM_REGTYPE_MASK;
@@ -321,9 +324,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	idlest_bit = other_bit;
 
 	/* 24xx: DSS and CAM have no idlest bits for their target agents */
-	if (cpu_is_omap24xx() &&
-	    (prcm_mod == OMAP2420_CM_REGADDR(CORE_MOD, 0) ||
-	     prcm_mod == OMAP2430_CM_REGADDR(CORE_MOD, 0)) &&
+	if (cpu_is_omap24xx() && clk->prcm_mod == CORE_MOD &&
 	    (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
 
 		if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
@@ -337,7 +338,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	if (cpu_is_omap34xx()) {
 
 		/* SSI */
-		if (prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
+		if (clk->prcm_mod == CORE_MOD &&
 		    (reg & 0x0f) == 0 &&
 		    clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
 
@@ -348,7 +349,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
 		}
 
 		/* DSS */
-		if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
+		if (clk->prcm_mod == OMAP3430_DSS_MOD) {
 
 			/* 3430ES1 DSS has no target idlest bits */
 			if (system_rev == OMAP3430_REV_ES1_0)
@@ -366,7 +367,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
 
 		/* USBHOST */
 		if (system_rev > OMAP3430_REV_ES1_0 &&
-		    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, 0)) {
+		    clk->prcm_mod == OMAP3430ES2_USBHOST_MOD) {
 
 			/*
 			 * The 120MHz clock apparently has nothing to do with



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 08/11] OMAP2/3 clock: convert omap2_wait_clock_ready() to use clk.prcm_mod
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
                   ` (6 preceding siblings ...)
  2008-09-18 17:47 ` [PATCH v2 07/11] OMAP2/3 clock: use prcm_mod field " Paul Walmsley
@ 2008-09-18 17:47 ` Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 09/11] OMAP2/3 clock: remove omap2_get_clksel() Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 10/11] OMAP2/3 clock: simplify omap2_clksel_get_src_field() Paul Walmsley
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Convert omap2_wait_clock_ready() to use clk.prcm_mod rather than a
void __iomem *.  This removes some cruft from clock24xx.c and sets
up further cruft removal in a subsequent patch.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock.c     |   13 ++++++++-----
 arch/arm/mach-omap2/clock.h     |    3 ++-
 arch/arm/mach-omap2/clock24xx.c |   10 +---------
 3 files changed, 11 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6433679..b2478b7 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -255,14 +255,16 @@ void omap2_fixed_divisor_recalc(struct clk *clk)
 
 /**
  * omap2_wait_clock_ready - wait for clock to enable
- * @reg: physical address of clock IDLEST register
+ * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
+ * @reg_index: offset of CM register address from prcm_mod
  * @mask: value to mask against to determine if the clock is active
  * @name: name of the clock (for printk)
  *
  * Returns 1 if the clock enabled in time, or 0 if it failed to enable
  * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
  */
-int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
+int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
+			   const char *name)
 {
 	int i = 0, ena = 0;
 
@@ -276,7 +278,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
 		ena = 0;
 
 	/* Wait for lock */
-	while (((__raw_readl(reg) & mask) != ena) &&
+	while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
 	       (i++ < MAX_CLOCK_ENABLE_WAIT)) {
 		udelay(1);
 	}
@@ -287,7 +289,6 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
 		printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
 		       name, MAX_CLOCK_ENABLE_WAIT);
 
-
 	return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
 };
 
@@ -389,7 +390,9 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
 	idlest_reg |= CM_IDLEST_REGTYPE;
 
-	omap2_wait_clock_ready((void __iomem *)idlest_reg, idlest_bit,
+	idlest_reg &= 0xff; /* convert to PRCM register index */
+
+	omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, idlest_bit,
 			       clk->name);
 }
 
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 3fa2e26..bcb0c03 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -48,7 +48,8 @@ void omap2_fixed_divisor_recalc(struct clk *clk);
 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
-int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
+int omap2_wait_clock_ready(s16 prcm_mod, u16 idlest_reg, u32 cval,
+			   const char *name);
 void omap2_clk_prepare_for_reboot(void);
 
 extern u8 cpu_mask;
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index ddb6429..a97d89d 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -93,7 +93,6 @@ static void omap2_disable_osc_ck(struct clk *clk)
 static int omap2_clk_fixed_enable(struct clk *clk)
 {
 	u32 cval, apll_mask;
-	void __iomem *idlest;
 
 	apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 
@@ -111,14 +110,7 @@ static int omap2_clk_fixed_enable(struct clk *clk)
 	else if (clk == &apll54_ck)
 		cval = OMAP24XX_ST_54M_APLL;
 
-	if (cpu_is_omap242x())
-		idlest = (__force void __iomem *)OMAP2420_CM_REGADDR(PLL_MOD,
-								CM_IDLEST);
-	else
-		idlest = (__force void __iomem *)OMAP2430_CM_REGADDR(PLL_MOD,
-								CM_IDLEST);
-
-	omap2_wait_clock_ready(idlest, cval, clk->name);
+	omap2_wait_clock_ready(PLL_MOD, CM_IDLEST, cval, clk->name);
 
 	/*
 	 * REVISIT: Should we return an error code if omap2_wait_clock_ready()



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 09/11] OMAP2/3 clock: remove omap2_get_clksel()
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
                   ` (7 preceding siblings ...)
  2008-09-18 17:47 ` [PATCH v2 08/11] OMAP2/3 clock: convert omap2_wait_clock_ready() to use clk.prcm_mod Paul Walmsley
@ 2008-09-18 17:47 ` Paul Walmsley
  2008-09-18 17:47 ` [PATCH v2 10/11] OMAP2/3 clock: simplify omap2_clksel_get_src_field() Paul Walmsley
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Remove omap2_get_clksel() and just use clk->clksel_reg and
clk->clksel_mask directly.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock.c |   46 +++++++++++--------------------------------
 1 files changed, 12 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index b2478b7..062c034 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -727,23 +727,6 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
 }
 
 /**
- * omap2_get_clksel - find clksel register addr & field mask for a clk
- * @clk: struct clk to use
- * @field_mask: ptr to u32 to store the register field mask
- *
- * Returns the address of the clksel register upon success or NULL on error.
- */
-static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
-{
-	if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
-		return NULL;
-
-	*field_mask = clk->clksel_mask;
-
-	return clk->clksel_reg;
-}
-
-/**
  * omap2_clksel_get_divisor - get current divider applied to parent clock.
  * @clk: OMAP struct clk to use.
  *
@@ -751,41 +734,36 @@ static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
  */
 u32 omap2_clksel_get_divisor(struct clk *clk)
 {
-	u32 field_mask, v;
-	void __iomem *div_addr;
+	u32 v;
 
-	div_addr = omap2_get_clksel(clk, &field_mask);
-	if (div_addr == NULL)
+	if (!clk->clksel_mask)
 		return 0;
 
-	v = __raw_readl(div_addr) & field_mask;
-	v >>= __ffs(field_mask);
+	v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+	v >>= __ffs(clk->clksel_mask);
 
 	return omap2_clksel_to_divisor(clk, v);
 }
 
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 {
-	u32 field_mask, field_val, validrate, new_div = 0;
-	void __iomem *div_addr;
-	u32 v;
+	u32 v, field_val, validrate, new_div = 0;
 
-	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
-	if (validrate != rate)
+	if (!clk->clksel_mask)
 		return -EINVAL;
 
-	div_addr = omap2_get_clksel(clk, &field_mask);
-	if (div_addr == NULL)
+	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+	if (validrate != rate)
 		return -EINVAL;
 
 	field_val = omap2_divisor_to_clksel(clk, new_div);
 	if (field_val == ~0)
 		return -EINVAL;
 
-	v = __raw_readl(div_addr);
-	v &= ~field_mask;
-	v |= field_val << __ffs(field_mask);
-	__raw_writel(v, div_addr);
+	v = __raw_readl(clk->clksel_reg);
+	v &= ~clk->clksel_mask;
+	v |= field_val << __ffs(clk->clksel_mask);
+	__raw_writel(v, clk->clksel_reg);
 
 	wmb();
 



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v2 10/11] OMAP2/3 clock: simplify omap2_clksel_get_src_field()
  2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
                   ` (8 preceding siblings ...)
  2008-09-18 17:47 ` [PATCH v2 09/11] OMAP2/3 clock: remove omap2_get_clksel() Paul Walmsley
@ 2008-09-18 17:47 ` Paul Walmsley
  9 siblings, 0 replies; 11+ messages in thread
From: Paul Walmsley @ 2008-09-18 17:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Paul Walmsley

Get rid of void __iomem * usage in omap2_clksel_get_src_field.
Prepend the function name with an underscore to highlight that it is a
static function.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/clock.c |   31 ++++++++++++-------------------
 1 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 062c034..621babc 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -803,18 +803,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 
 /*
  * Converts encoded control register address into a full address
- * On error, *src_addr will be returned as 0.
+ * On error, the return value (parent_div) will be 0.
  */
-static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
-				      struct clk *src_clk, u32 *field_mask,
-				      struct clk *clk, u32 *parent_div)
+static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
+				       u32 *field_val)
 {
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;
 
-	*parent_div = 0;
-	*src_addr = NULL;
-
 	clks = omap2_get_clksel_by_parent(clk, src_clk);
 	if (!clks)
 		return 0;
@@ -834,17 +830,14 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
 	/* Should never happen.  Add a clksel mask to the struct clk. */
 	WARN_ON(clk->clksel_mask == 0);
 
-	*field_mask = clk->clksel_mask;
-	*src_addr = clk->clksel_reg;
-	*parent_div = clkr->div;
+	*field_val = clkr->val;
 
-	return clkr->val;
+	return clkr->div;
 }
 
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
-	void __iomem *src_addr;
-	u32 field_val, field_mask, v, parent_div;
+	u32 field_val, v, parent_div;
 
 	if (clk->flags & CONFIG_PARTICIPANT)
 		return -EINVAL;
@@ -852,18 +845,18 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 	if (!clk->clksel)
 		return -EINVAL;
 
-	field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
-					       &field_mask, clk, &parent_div);
-	if (src_addr == NULL)
+	parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
+	if (!parent_div)
 		return -EINVAL;
 
 	if (clk->usecount > 0)
 		_omap2_clk_disable(clk);
 
 	/* Set new source value (previous dividers if any in effect) */
-	v = __raw_readl(src_addr) & ~field_mask;
-	v |= (field_val << __ffs(field_mask));
-	__raw_writel(v, src_addr);
+	v = __raw_readl(clk->clksel_reg);
+	v &= ~clk->clksel_mask;
+	v |= field_val << __ffs(clk->clksel_mask);
+	__raw_writel(v, clk->clksel_reg);
 	wmb();
 
 	if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {



^ permalink raw reply related	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2008-09-18 17:48 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-09-18 17:46 [PATCH v2 00/11] OMAP2/3 clock: encode prcm_mod for each struct clk Paul Walmsley
2008-09-18 17:46 ` [PATCH v2 01/11] OMAP3 clock: split mcbspX_src_fck from mcbspX_fck Paul Walmsley
2008-09-18 17:46 ` [PATCH v2 02/11] OMAP2/3 clock: shorten some variable names in clock.c for legibility Paul Walmsley
2008-09-18 17:47 ` [PATCH v2 03/11] OMAP2 clock: add clk.prcm_mod field; annotate OMAP2xxx clocks Paul Walmsley
2008-09-18 17:47 ` [PATCH v2 04/11] OMAP3 clock: add "prcm_mod" field to OMAP3xxx clocks Paul Walmsley
2008-09-18 17:47 ` [PATCH v2 05/11] OMAP2/3 clock: add _omap2_clk_{read,write}_reg() Paul Walmsley
2008-09-18 17:47 ` [PATCH v2 06/11] OMAP2/3 clock: use symbolic constants in omap2_clk_wait_ready() Paul Walmsley
2008-09-18 17:47 ` [PATCH v2 07/11] OMAP2/3 clock: use prcm_mod field " Paul Walmsley
2008-09-18 17:47 ` [PATCH v2 08/11] OMAP2/3 clock: convert omap2_wait_clock_ready() to use clk.prcm_mod Paul Walmsley
2008-09-18 17:47 ` [PATCH v2 09/11] OMAP2/3 clock: remove omap2_get_clksel() Paul Walmsley
2008-09-18 17:47 ` [PATCH v2 10/11] OMAP2/3 clock: simplify omap2_clksel_get_src_field() Paul Walmsley

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