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* [PATCH] OMAP3 DSS: Fixed FIFO buffer register field sizes
@ 2008-10-22  6:47 Kalle Jokiniemi
  2008-10-24 19:24 ` Tony Lindgren
  0 siblings, 1 reply; 2+ messages in thread
From: Kalle Jokiniemi @ 2008-10-22  6:47 UTC (permalink / raw)
  To: linux-omap; +Cc: Kalle Jokiniemi

The size status field in DISPC_[GFX | VID1 | VID2]_FIFO_SIZE_STATUS
register is 11 bits wide in OMAP3, but only 9 bits were read. Similarly,
the threshold field in DISPC_[GFX | VID1 | VID2]_FIFO_THRESHOLD register
is 12 bits wide, while only 9 bits were written in it.

This patch extends the bit field sizes used in setup_plane_fifo to
correspond to ones in OMAP3. In OMAP2 the extra bits are reserved, so no
harm should come from extending the bit fields.

Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
---
 drivers/video/omap/dispc.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
index beda40b..c140c21 100644
--- a/drivers/video/omap/dispc.c
+++ b/drivers/video/omap/dispc.c
@@ -290,7 +290,7 @@ static void setup_plane_fifo(int plane, int ext_mode)
 	BUG_ON(plane > 2);
 
 	l = dispc_read_reg(fsz_reg[plane]);
-	l &= FLD_MASK(0, 9);
+	l &= FLD_MASK(0, 11);
 	if (ext_mode) {
 		low = l * 3 / 4;
 		high = l;
@@ -298,7 +298,7 @@ static void setup_plane_fifo(int plane, int ext_mode)
 		low = l / 4;
 		high = l * 3 / 4;
 	}
-	MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 9) | FLD_MASK(0, 9),
+	MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12),
 			(high << 16) | low);
 }
 
-- 
1.5.4.3


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] OMAP3 DSS: Fixed FIFO buffer register field sizes
  2008-10-22  6:47 [PATCH] OMAP3 DSS: Fixed FIFO buffer register field sizes Kalle Jokiniemi
@ 2008-10-24 19:24 ` Tony Lindgren
  0 siblings, 0 replies; 2+ messages in thread
From: Tony Lindgren @ 2008-10-24 19:24 UTC (permalink / raw)
  To: Kalle Jokiniemi; +Cc: linux-omap

* Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> [081021 23:46]:
> The size status field in DISPC_[GFX | VID1 | VID2]_FIFO_SIZE_STATUS
> register is 11 bits wide in OMAP3, but only 9 bits were read. Similarly,
> the threshold field in DISPC_[GFX | VID1 | VID2]_FIFO_THRESHOLD register
> is 12 bits wide, while only 9 bits were written in it.
> 
> This patch extends the bit field sizes used in setup_plane_fifo to
> correspond to ones in OMAP3. In OMAP2 the extra bits are reserved, so no
> harm should come from extending the bit fields.

Pusing today.

Tony

> 
> Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
> ---
>  drivers/video/omap/dispc.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
> index beda40b..c140c21 100644
> --- a/drivers/video/omap/dispc.c
> +++ b/drivers/video/omap/dispc.c
> @@ -290,7 +290,7 @@ static void setup_plane_fifo(int plane, int ext_mode)
>  	BUG_ON(plane > 2);
>  
>  	l = dispc_read_reg(fsz_reg[plane]);
> -	l &= FLD_MASK(0, 9);
> +	l &= FLD_MASK(0, 11);
>  	if (ext_mode) {
>  		low = l * 3 / 4;
>  		high = l;
> @@ -298,7 +298,7 @@ static void setup_plane_fifo(int plane, int ext_mode)
>  		low = l / 4;
>  		high = l * 3 / 4;
>  	}
> -	MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 9) | FLD_MASK(0, 9),
> +	MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12),
>  			(high << 16) | low);
>  }
>  
> -- 
> 1.5.4.3
> 
> --
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^ permalink raw reply	[flat|nested] 2+ messages in thread

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2008-10-22  6:47 [PATCH] OMAP3 DSS: Fixed FIFO buffer register field sizes Kalle Jokiniemi
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