* Tony Lindgren <tony@atomide.com> [081031 12:21]:
> The only way to ensure write posting to L4 bus is to do a read back
> of the same register right after the write.
> 
> This seems to be mostly needed in interrupt handlers to avoid
> causing spurious interrupts.
> 
> The earlier fix has been to mark the L4 bus as strongly ordered
> memory, which solves the problem, but causes performance penalties.
> 
> Similar fixes may be needed in other interrupt handlers too.

Here's this one updated to say "flush posted write" for easy grepping.

Tony