Re: [PATCH 4/4] DSPBRIDGE: Ensure write posting when acking mailbox irq

[Tony Lindgren <tony@atomide.com>]

* Woodruff, Richard <r-woodruff2@ti.com> [081031 20:44]:
> > owner@vger.kernel.org] On Behalf Of Tony Lindgren
> > Sent: Friday, October 31, 2008 2:21 PM
> 
> > The only way to ensure write posting to L4 bus is to do a read back
> > of the same register right after the write.
> >
> > This seems to be mostly needed in interrupt handlers to avoid
> > causing spurious interrupts.
> >
> > The earlier fix has been to mark the L4 bus as strongly ordered
> > memory, which solves the problem, but causes performance penalties.
> 
> What penalties have you observed?  Can you quantify?

Not yet, I guess we can run some benchmarks though.

> From the L4 perspectives DEVICE and SO are similar.  Long back I was told one difference is DEVICE is allowed to do burst transactions of element size where SO was not. This behavior is only really wanted to a FIFO.
> 
> Really performance sensitive devices will be using DMA to FIFOs.  SO/DEVICE only applies to the ARM's view of things.  DMA is not affected by ARM memory types.

You may be right, and if that's the only difference, then SO might be
even faster as it avoids the extra readbacks.

> Some kind of barrier or read back is needed for sure when dealing with the main interrupt controller.

Yeah. I'm worried that these issues could happen with SO too..

Regards,

Tony