[PATCH] ARM: OMAP3: Enable writing to XCCR and RCCR McBSP registers for OMAP 2430/34xx

[PATCH] ARM: OMAP3: Enable writing to XCCR and RCCR McBSP registers for OMAP 2430/34xx

[Lopez Cruz, Misael]

This patch enables writing to McBSP Transmit Configuration Control
Register (XCCR) and Receive Configuration Control Register (RCCR)
for 2430/34xx platforms. It also adds XCCR, RCCR entries in McBSP
register configuration structure and bit definitions for both
registers.

Signed-off-by: Misael Lopez Cruz <x0052729@ti.com>
---
 arch/arm/plat-omap/include/mach/mcbsp.h |    7 +++++++
 arch/arm/plat-omap/mcbsp.c              |    4 ++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index 6a0d1a0..cc48f2f 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -231,11 +231,16 @@
 #define XPBBLK(value)		((value)<<7)	/* Bits 7:8 */
 
 /*********************** McBSP XCCR bit definitions *************************/
+#define EXTCLKGATE		0x8000
+#define PPCONNECT		0x4000
+#define DXENDLY(value)		((value)<<12)	/* Bits 12:13 */
+#define XFULL_CYCLE		0x0800
 #define DILB			0x0020
 #define XDMAEN			0x0008
 #define XDISABLE		0x0001
 
 /********************** McBSP RCCR bit definitions *************************/
+#define RFULL_CYCLE		0x0800
 #define RDMAEN			0x0008
 #define RDISABLE		0x0001
 
@@ -267,6 +272,8 @@ struct omap_mcbsp_reg_cfg {
 	u16 rcerh;
 	u16 xcerg;
 	u16 xcerh;
+	u16 xccr;
+	u16 rccr;
 };
 
 typedef enum {
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index af33fc7..f2401a8 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -173,6 +173,10 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 	OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 	OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 	OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
+	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+		OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
+		OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
+	}
 }
 EXPORT_SYMBOL(omap_mcbsp_config);
 
-- 
1.5.4.3

RE: [PATCH] ARM: OMAP3: Enable writing to XCCR and RCCR McBSP registers for OMAP 2430/34xx

[Lopez Cruz, Misael]

> This patch enables writing to McBSP Transmit Configuration 
> Control Register (XCCR) and Receive Configuration Control 
> Register (RCCR) for 2430/34xx platforms. It also adds XCCR, 
> RCCR entries in McBSP register configuration structure and 
> bit definitions for both registers.

McBSP changes are now in a separate patch as suggested by Tony and Jarkko.

> +	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
> +		OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
> +		OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
> +	}

Changed to check for 2430 and 34xx platforms as pointed by Jarkko.

-Misa

Re: [PATCH] ARM: OMAP3: Enable writing to XCCR and RCCR McBSP registers for OMAP 2430/34xx

[Tony Lindgren]

* Lopez Cruz, Misael <x0052729@ti.com> [081219 04:53]:
> This patch enables writing to McBSP Transmit Configuration Control
> Register (XCCR) and Receive Configuration Control Register (RCCR)
> for 2430/34xx platforms. It also adds XCCR, RCCR entries in McBSP
> register configuration structure and bit definitions for both
> registers.

Pushing to l-o. Can you briefly describe what happens with ASoC
if these registers are not used? We may be able to send this
as a fix to mainline during the -rc cycle.

Regards,

Tony

> Signed-off-by: Misael Lopez Cruz <x0052729@ti.com>
> ---
>  arch/arm/plat-omap/include/mach/mcbsp.h |    7 +++++++
>  arch/arm/plat-omap/mcbsp.c              |    4 ++++
>  2 files changed, 11 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
> index 6a0d1a0..cc48f2f 100644
> --- a/arch/arm/plat-omap/include/mach/mcbsp.h
> +++ b/arch/arm/plat-omap/include/mach/mcbsp.h
> @@ -231,11 +231,16 @@
>  #define XPBBLK(value)		((value)<<7)	/* Bits 7:8 */
>  
>  /*********************** McBSP XCCR bit definitions *************************/
> +#define EXTCLKGATE		0x8000
> +#define PPCONNECT		0x4000
> +#define DXENDLY(value)		((value)<<12)	/* Bits 12:13 */
> +#define XFULL_CYCLE		0x0800
>  #define DILB			0x0020
>  #define XDMAEN			0x0008
>  #define XDISABLE		0x0001
>  
>  /********************** McBSP RCCR bit definitions *************************/
> +#define RFULL_CYCLE		0x0800
>  #define RDMAEN			0x0008
>  #define RDISABLE		0x0001
>  
> @@ -267,6 +272,8 @@ struct omap_mcbsp_reg_cfg {
>  	u16 rcerh;
>  	u16 xcerg;
>  	u16 xcerh;
> +	u16 xccr;
> +	u16 rccr;
>  };
>  
>  typedef enum {
> diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
> index af33fc7..f2401a8 100644
> --- a/arch/arm/plat-omap/mcbsp.c
> +++ b/arch/arm/plat-omap/mcbsp.c
> @@ -173,6 +173,10 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
>  	OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
>  	OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
>  	OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
> +	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
> +		OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
> +		OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
> +	}
>  }
>  EXPORT_SYMBOL(omap_mcbsp_config);
>  
> -- 
> 1.5.4.3
> --
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RE: [PATCH] ARM: OMAP3: Enable writing to XCCR and RCCR McBSP registers for OMAP 2430/34xx

[Lopez Cruz, Misael]

> * Lopez Cruz, Misael <x0052729@ti.com> [081219 04:53]:
> > This patch enables writing to McBSP Transmit Configuration Control 
> > Register (XCCR) and Receive Configuration Control Register 
> (RCCR) for 
> > 2430/34xx platforms. It also adds XCCR, RCCR entries in 
> McBSP register 
> > configuration structure and bit definitions for both registers.
>
> Pushing to l-o. Can you briefly describe what happens with 
> ASoC if these registers are not used? We may be able to send 
> this as a fix to mainline during the -rc cycle.

If we enable the writing to those registers for 2430/34xx and don't set the default values (setting 0 as a consequence) in ASoC driver, the Transmit/Receive DMA mode gets disabled and the the transmission/reception doesn't happen, ending with a "write error: Input/Output error" when playing with 'aplay'.

-Misa

Re: [PATCH] ARM: OMAP3: Enable writing to XCCR and RCCR McBSP registers for OMAP 2430/34xx

[Tony Lindgren]

* Lopez Cruz, Misael <x0052729@ti.com> [090108 19:43]:
> > * Lopez Cruz, Misael <x0052729@ti.com> [081219 04:53]:
> > > This patch enables writing to McBSP Transmit Configuration Control 
> > > Register (XCCR) and Receive Configuration Control Register 
> > (RCCR) for 
> > > 2430/34xx platforms. It also adds XCCR, RCCR entries in 
> > McBSP register 
> > > configuration structure and bit definitions for both registers.
> >
> > Pushing to l-o. Can you briefly describe what happens with 
> > ASoC if these registers are not used? We may be able to send 
> > this as a fix to mainline during the -rc cycle.
> 
> If we enable the writing to those registers for 2430/34xx and don't set the default values (setting 0 as a consequence) in ASoC driver, the Transmit/Receive DMA mode gets disabled and the the transmission/reception doesn't happen, ending with a "write error: Input/Output error" when playing with 'aplay'.

Thanks, I'll add that to the commit in the omap-fixes queue.

Tony

RE: [PATCH] ARM: OMAP3: Enable writing to XCCR and RCCR McBSP registers for OMAP 2430/34xx

[Paul Walmsley]

On Thu, 8 Jan 2009, Lopez Cruz, Misael wrote:

> > * Lopez Cruz, Misael <x0052729@ti.com> [081219 04:53]:
> > > This patch enables writing to McBSP Transmit Configuration Control 
> > > Register (XCCR) and Receive Configuration Control Register 
> > (RCCR) for 
> > > 2430/34xx platforms. It also adds XCCR, RCCR entries in 
> > McBSP register 
> > > configuration structure and bit definitions for both registers.
> >
> > Pushing to l-o. Can you briefly describe what happens with 
> > ASoC if these registers are not used? We may be able to send 
> > this as a fix to mainline during the -rc cycle.
> 
> If we enable the writing to those registers for 2430/34xx and don't set the default values (setting 0 as a consequence) in ASoC driver, the Transmit/Receive DMA mode gets disabled and the the transmission/reception doesn't happen, ending with a "write error: Input/Output error" when playing with 'aplay'.
> 
> -Misa--

Something is wrong with this patch, at least on Beagle.  When 
starting audio playback, there is a 
several second pause, then a console message:

ALSA sound/core/pcm_native.c:1493: playback drain error (DMA or IRQ 
trouble?)

No audio emerges from the board.

With this patch reverted, a very basic audio test here seems to work.


- Paul