Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Eero Nurkkala]

Feel free to revert this patch.

There appears to be problems with the noised filters
not obeying the i2c standard.

I will come up with a new patch in the future.

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Tony Lindgren]

* Eero Nurkkala <ext-eero.nurkkala@nokia.com> [090112 22:08]:
> Feel free to revert this patch.

OK, reverted from linux-omap master and omap-2.6.28 branches. Also
dropped from omap-fixes queue.

> There appears to be problems with the noised filters
> not obeying the i2c standard.
> 
> I will come up with a new patch in the future.

OK

Tony

[PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[ext-eero.nurkkala]

From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>

The prescalers for 100 kHz and 400 kHz mode
are wrong for omap 3430 and omap 2430. The
internal clock is the fclock divided by the
prescaler. The PSC is an 8 bit field in
omap3430 and omap2430. Moreover, the scll and
sclh values should be adjusted properly.
Having the correct prescaler is important in
the process of getting a finite i2c clock. In
addition, the prescaler is used in the process
of activating the correct noise filter and thus,
lets more error resilient i2c communications.

Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
---
 drivers/i2c/busses/i2c-omap.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 630702c..c21af3f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -337,7 +337,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 
 		/* HSI2C controller internal clk rate should be 19.2 Mhz */
-		internal_clk = 19200;
+		if (dev->speed > 400)
+			internal_clk = 19200;
+		else if (dev->speed > 100)
+			internal_clk = 9600;
+		else
+			internal_clk = 4000;
+
 		fclk_rate = clk_get_rate(dev->fclk) / 1000;
 
 		/* Compute prescaler divisor */
@@ -355,8 +361,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 			hssclh = fclk_rate / (dev->speed * 2) - 6;
 		} else {
 			/* To handle F/S modes */
-			fsscll = internal_clk / (dev->speed * 2) - 6;
-			fssclh = internal_clk / (dev->speed * 2) - 6;
+			fsscll = internal_clk / (dev->speed * 2) - 3;
+			fssclh = internal_clk / (dev->speed * 2) - 9;
 		}
 		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
-- 
1.6.0

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Eero Nurkkala]

We scope-verified these scl and sch values for 100 and 400 kHz busses.
Now they're in the specs.

On Wed, 2008-11-26 at 15:44 +0200, ext-eero.nurkkala@nokia.com wrote:
> From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
> 
> The prescalers for 100 kHz and 400 kHz mode
> are wrong for omap 3430 and omap 2430. The
> internal clock is the fclock divided by the
> prescaler. The PSC is an 8 bit field in
> omap3430 and omap2430. Moreover, the scll and
> sclh values should be adjusted properly.
> Having the correct prescaler is important in
> the process of getting a finite i2c clock. In
> addition, the prescaler is used in the process
> of activating the correct noise filter and thus,
> lets more error resilient i2c communications.
> 
> Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
> ---
>  drivers/i2c/busses/i2c-omap.c |   12 +++++++++---
>  1 files changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 630702c..c21af3f 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -337,7 +337,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
>  
>  		/* HSI2C controller internal clk rate should be 19.2 Mhz */
> -		internal_clk = 19200;
> +		if (dev->speed > 400)
> +			internal_clk = 19200;
> +		else if (dev->speed > 100)
> +			internal_clk = 9600;
> +		else
> +			internal_clk = 4000;
> +
>  		fclk_rate = clk_get_rate(dev->fclk) / 1000;
>  
>  		/* Compute prescaler divisor */
> @@ -355,8 +361,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  			hssclh = fclk_rate / (dev->speed * 2) - 6;
>  		} else {
>  			/* To handle F/S modes */
> -			fsscll = internal_clk / (dev->speed * 2) - 6;
> -			fssclh = internal_clk / (dev->speed * 2) - 6;
> +			fsscll = internal_clk / (dev->speed * 2) - 3;
> +			fssclh = internal_clk / (dev->speed * 2) - 9;
>  		}
>  		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
>  		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Tony Lindgren]

* Eero Nurkkala <ext-eero.nurkkala@nokia.com> [081127 10:39]:
> We scope-verified these scl and sch values for 100 and 400 kHz busses.
> Now they're in the specs.

Pushing to l-o tree and adding to omap-fixes queue for mainline.

Tony

> On Wed, 2008-11-26 at 15:44 +0200, ext-eero.nurkkala@nokia.com wrote:
> > From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
> > 
> > The prescalers for 100 kHz and 400 kHz mode
> > are wrong for omap 3430 and omap 2430. The
> > internal clock is the fclock divided by the
> > prescaler. The PSC is an 8 bit field in
> > omap3430 and omap2430. Moreover, the scll and
> > sclh values should be adjusted properly.
> > Having the correct prescaler is important in
> > the process of getting a finite i2c clock. In
> > addition, the prescaler is used in the process
> > of activating the correct noise filter and thus,
> > lets more error resilient i2c communications.
> > 
> > Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
> > ---
> >  drivers/i2c/busses/i2c-omap.c |   12 +++++++++---
> >  1 files changed, 9 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> > index 630702c..c21af3f 100644
> > --- a/drivers/i2c/busses/i2c-omap.c
> > +++ b/drivers/i2c/busses/i2c-omap.c
> > @@ -337,7 +337,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
> >  	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
> >  
> >  		/* HSI2C controller internal clk rate should be 19.2 Mhz */
> > -		internal_clk = 19200;
> > +		if (dev->speed > 400)
> > +			internal_clk = 19200;
> > +		else if (dev->speed > 100)
> > +			internal_clk = 9600;
> > +		else
> > +			internal_clk = 4000;
> > +
> >  		fclk_rate = clk_get_rate(dev->fclk) / 1000;
> >  
> >  		/* Compute prescaler divisor */
> > @@ -355,8 +361,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
> >  			hssclh = fclk_rate / (dev->speed * 2) - 6;
> >  		} else {
> >  			/* To handle F/S modes */
> > -			fsscll = internal_clk / (dev->speed * 2) - 6;
> > -			fssclh = internal_clk / (dev->speed * 2) - 6;
> > +			fsscll = internal_clk / (dev->speed * 2) - 3;
> > +			fssclh = internal_clk / (dev->speed * 2) - 9;
> >  		}
> >  		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
> >  		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
> 
> --
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Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Kainan Cha]

Eero,

On Wed, Nov 26, 2008 at 7:44 AM,  <ext-eero.nurkkala@nokia.com> wrote:
> From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
>
> The prescalers for 100 kHz and 400 kHz mode
> are wrong for omap 3430 and omap 2430. The
> internal clock is the fclock divided by the
> prescaler. The PSC is an 8 bit field in
> omap3430 and omap2430. Moreover, the scll and
> sclh values should be adjusted properly.
> Having the correct prescaler is important in
> the process of getting a finite i2c clock. In
> addition, the prescaler is used in the process
> of activating the correct noise filter and thus,
> lets more error resilient i2c communications.
>

This patch looks fine for omap3430. But when referring to omap2430
manual, the internal_clk does not seem to depend on the i2c modes. Can
you verify? My brief testing shows that i2c clock is broken for
omap2430 with this patch.

Also, in my manual for both omap2430 and omap3430, scll and sclh
values should be set like so:

                       fsscll = internal_clk / (dev->speed * 2) - 7;
                       fssclh = internal_clk / (dev->speed * 2) - 5;

Could you explain where you got your values from?

Regards,
Kainan Cha

> Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
> ---
>  drivers/i2c/busses/i2c-omap.c |   12 +++++++++---
>  1 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 630702c..c21af3f 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -337,7 +337,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
>
>                /* HSI2C controller internal clk rate should be 19.2 Mhz */
> -               internal_clk = 19200;
> +               if (dev->speed > 400)
> +                       internal_clk = 19200;
> +               else if (dev->speed > 100)
> +                       internal_clk = 9600;
> +               else
> +                       internal_clk = 4000;
> +
>                fclk_rate = clk_get_rate(dev->fclk) / 1000;
>
>                /* Compute prescaler divisor */
> @@ -355,8 +361,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>                        hssclh = fclk_rate / (dev->speed * 2) - 6;
>                } else {
>                        /* To handle F/S modes */
> -                       fsscll = internal_clk / (dev->speed * 2) - 6;
> -                       fssclh = internal_clk / (dev->speed * 2) - 6;
> +                       fsscll = internal_clk / (dev->speed * 2) - 3;
> +                       fssclh = internal_clk / (dev->speed * 2) - 9;
>                }
>                scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
>                sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
> --
> 1.6.0
>
> --
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> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Eero Nurkkala]

On Fri, 2009-01-09 at 14:27 -0600, ext Kainan Cha wrote:
> 
> This patch looks fine for omap3430. But when referring to omap2430
> manual, the internal_clk does not seem to depend on the i2c modes. Can
> you verify? My brief testing shows that i2c clock is broken for
> omap2430 with this patch.
> 
> Also, in my manual for both omap2430 and omap3430, scll and sclh
> values should be set like so:
> 
>                        fsscll = internal_clk / (dev->speed * 2) - 7;
>                        fssclh = internal_clk / (dev->speed * 2) - 5;
> 
> Could you explain where you got your values from?
> 
> Regards,
> Kainan Cha


Hello!

I'm very sorry for breaking the 2430 i2c bus. I have had definitely no
access to 2430 TRM or boards, so all help is much appreciated. That
needs to be fixed.

Our values for fsscll and fssclh (-3, -9) come from the i2c standard. We
scoped out the activity of 100khz and 400khz signals, and by having the
(-6, -6) or TRM's (-7, -5) we found out that the i2c clock signal does
not get into the i2c standard. If I recall correctly, the clock down
time, referred to as "LOW period of the SCL clock, tLOW" in the i2c
standard, was well below the minimum. Taken from the standard, the
400khz mode tLOW is min 1.3uS, and tHIGH is min 0.6uS. You see that
the tLOW needs to be a lot greater than tHIGH, so that would suggest
we're in the right track with the (-3, -9) values ;)

Indeed, with values (-3, -9) we got everything within the i2c standard
for 100 and 400 khz busses, and still having the correct frequency.

If TRM was to be obeyed, and the minimum values were really the (-7,
-5), then it becomes impossible to get the clock frequency to 400 or
100. (I think it went closer to 300 khz, as the tLOW value needed to be
adjusted quite a bit).

However, I would suggest you and everybody who uses the i2c bus, to 
scope the bus, and measure everything (rise/fall times, setup times,
tLOW, tHIGH and everything mentioned in the i2c standard). Just to check
that you actually have a reliable i2c driver.

[PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[ext-eero.nurkkala]

From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>

The prescalers for 100 kHz and 400 kHz mode
are wrong for omap 3430 and omap 2430. The
internal clock is the fclock divided by the
prescaler. The PSC is an 8 bit field in
omap3430 and omap2430. Moreover, the scll and
sclh values should be adjusted properly.
Having the correct prescaler is important in
the process of getting a finite i2c clock. In
addition, the prescaler is used in the process
of activating the correct noise filter and thus,
lets more error resilient i2c communications.

Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
---
 drivers/i2c/busses/i2c-omap.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 630702c..c21af3f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -337,7 +337,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 
 		/* HSI2C controller internal clk rate should be 19.2 Mhz */
-		internal_clk = 19200;
+		if (dev->speed > 400)
+			internal_clk = 19200;
+		else if (dev->speed > 100)
+			internal_clk = 9600;
+		else
+			internal_clk = 4000;
+
 		fclk_rate = clk_get_rate(dev->fclk) / 1000;
 
 		/* Compute prescaler divisor */
@@ -355,8 +361,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 			hssclh = fclk_rate / (dev->speed * 2) - 6;
 		} else {
 			/* To handle F/S modes */
-			fsscll = internal_clk / (dev->speed * 2) - 6;
-			fssclh = internal_clk / (dev->speed * 2) - 6;
+			fsscll = internal_clk / (dev->speed * 2) - 7;
+			fssclh = internal_clk / (dev->speed * 2) - 5;
 		}
 		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
-- 
1.6.0

[PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[ext-eero.nurkkala]

From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>

The prescalers for 100 kHz and 400 kHz mode
are wrong. The internal clock is the fclock
divided by the prescaler. The PSC is an 8 bit
field in omap3430. Moreover, the scll and
sclh values should be adjusted properly.
Having the correct prescaler is important in
the process of getting a finite i2c clock. In
addition, the prescaler is used in the process
of activating the correct noise filter and thus,
lets more error resilient i2c communications.

Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
---
 drivers/i2c/busses/i2c-omap.c |   21 ++++++++++++++++++---
 1 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e708ebd..a42003a 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -288,7 +288,17 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 
 		/* HSI2C controller internal clk rate should be 19.2 Mhz */
-		internal_clk = 19200;
+		if (cpu_is_omap34xx()) {
+			if (dev->speed > 400)
+				internal_clk = 19200;
+			else if (dev->speed > 100)
+				internal_clk = 9600;
+			else
+				internal_clk = 4000;
+		} else {
+			internal_clk = 19200;
+		}
+
 		fclk_rate = clk_get_rate(dev->fclk) / 1000;
 
 		/* Compute prescaler divisor */
@@ -306,8 +316,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 			hssclh = fclk_rate / (dev->speed * 2) - 6;
 		} else {
 			/* To handle F/S modes */
-			fsscll = internal_clk / (dev->speed * 2) - 6;
-			fssclh = internal_clk / (dev->speed * 2) - 6;
+			if (cpu_is_omap34xx()) {
+				fsscll = internal_clk / (dev->speed * 2) - 7;
+				fssclh = internal_clk / (dev->speed * 2) - 5;
+			} else {
+				fsscll = internal_clk / (dev->speed * 2) - 6;
+				fssclh = internal_clk / (dev->speed * 2) - 6;
+			}
 		}
 		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
-- 
1.6.0

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[David Brownell]

On Friday 14 November 2008, ext-eero.nurkkala@nokia.com wrote:
> The prescalers for 100 kHz and 400 kHz mode
> are wrong. The internal clock is the fclock
> divided by the prescaler. The PSC is an 8 bit
> field in omap3430. Moreover, the scll and
> sclh values should be adjusted properly.
> Having the correct prescaler is important in
> the process of getting a finite i2c clock. In
> addition, the prescaler is used in the process
> of activating the correct noise filter and thus,
> lets more error resilient i2c communications.

Should this fix the bug causing the need for that
recent ZOOM patch slowing down twl4030 communication
to 400 MHz?

And should it let at least some boards talk to their
TWL chips at 3.4 MBit/sec (top speed for standard
highspeed I2C) instead of 2.6 Mbit/sec (pokey slow)?
I've always wondered why all the boards configured
those links to be seemingly slower than allowed ...

- Dave

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Felipe Balbi]

On Fri, Nov 14, 2008 at 11:45:30AM -0800, David Brownell wrote:
> And should it let at least some boards talk to their
> TWL chips at 3.4 MBit/sec (top speed for standard
> highspeed I2C) instead of 2.6 Mbit/sec (pokey slow)?
> I've always wondered why all the boards configured
> those links to be seemingly slower than allowed ...

I think it came from board-3430sdp.c

All other board files are based on that so is kind of a brainless
change.

Just change a few stuff in the MACHINE_START and some function names.
Remove some unneded functions and that's about it ;-)

-- 
balbi

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[David Brownell]

On Friday 14 November 2008, Felipe Balbi wrote:
> On Fri, Nov 14, 2008 at 11:45:30AM -0800, David Brownell wrote:
> > And should it let at least some boards talk to their
> > TWL chips at 3.4 MBit/sec (top speed for standard
> > highspeed I2C) instead of 2.6 Mbit/sec (pokey slow)?
> > I've always wondered why all the boards configured
> > those links to be seemingly slower than allowed ...
> 
> I think it came from board-3430sdp.c

So you're saying there was *never* a need for that slowdown,
and everyone was just copying an existing buglet?

I know I didn't make time to test whether faster speeds
would work ... but had expected there was a reason, at
some point, for that detuning.


> All other board files are based on that so is kind of a brainless
> change.
> 
> Just change a few stuff in the MACHINE_START and some function names.
> Remove some unneded functions and that's about it ;-)

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Felipe Balbi]

On Fri, Nov 14, 2008 at 12:08:10PM -0800, David Brownell wrote:
> On Friday 14 November 2008, Felipe Balbi wrote:
> > On Fri, Nov 14, 2008 at 11:45:30AM -0800, David Brownell wrote:
> > > And should it let at least some boards talk to their
> > > TWL chips at 3.4 MBit/sec (top speed for standard
> > > highspeed I2C) instead of 2.6 Mbit/sec (pokey slow)?
> > > I've always wondered why all the boards configured
> > > those links to be seemingly slower than allowed ...
> > 
> > I think it came from board-3430sdp.c
> 
> So you're saying there was *never* a need for that slowdown,
> and everyone was just copying an existing buglet?
> 
> I know I didn't make time to test whether faster speeds
> would work ... but had expected there was a reason, at
> some point, for that detuning.

There was a need. But I think it should be fixed by now. I shall test
tw5030 with 3.4Mbit/sec on monday. Will report.

-- 
balbi

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[shekhar, chandra]

I had tested twl4030 at 3.4 Mbps couple of months back and it was working fine 
with current settings. It wasn't a rigorous testing though.

----- Original Message ----- 
From: "Felipe Balbi" <me@felipebalbi.com>
To: "David Brownell" <david-b@pacbell.net>
Cc: <me@felipebalbi.com>; <ext-eero.nurkkala@nokia.com>; 
<linux-omap@vger.kernel.org>
Sent: Saturday, November 15, 2008 3:16 AM
Subject: Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers


> On Fri, Nov 14, 2008 at 12:08:10PM -0800, David Brownell wrote:
>> On Friday 14 November 2008, Felipe Balbi wrote:
>> > On Fri, Nov 14, 2008 at 11:45:30AM -0800, David Brownell wrote:
>> > > And should it let at least some boards talk to their
>> > > TWL chips at 3.4 MBit/sec (top speed for standard
>> > > highspeed I2C) instead of 2.6 Mbit/sec (pokey slow)?
>> > > I've always wondered why all the boards configured
>> > > those links to be seemingly slower than allowed ...
>> >
>> > I think it came from board-3430sdp.c
>>
>> So you're saying there was *never* a need for that slowdown,
>> and everyone was just copying an existing buglet?
>>
>> I know I didn't make time to test whether faster speeds
>> would work ... but had expected there was a reason, at
>> some point, for that detuning.
>
> There was a need. But I think it should be fixed by now. I shall test
> tw5030 with 3.4Mbit/sec on monday. Will report.
>
> -- 
> balbi
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Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[David Brownell]

On Sunday 16 November 2008, shekhar, chandra wrote:
> I had tested twl4030 at 3.4 Mbps couple of months back and it was working fine 
> with current settings. It wasn't a rigorous testing though.

My Beagle booted 2.6.28-rc5-omap with that speed,
and it worked fine too.  No errors even though I'm
using the pmu_stat LED (on a TWL LED) for the MMC
activity indicator ... so it got a decent amount
of traffic.

(Oh, and this is *with* the $SUBJECT patch too.)

- Dave

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Steve Sakoman]

On Fri, Nov 14, 2008 at 11:45 AM, David Brownell <david-b@pacbell.net> wrote:
> On Friday 14 November 2008, ext-eero.nurkkala@nokia.com wrote:
>> The prescalers for 100 kHz and 400 kHz mode
>> are wrong. The internal clock is the fclock
>> divided by the prescaler. The PSC is an 8 bit
>> field in omap3430. Moreover, the scll and
>> sclh values should be adjusted properly.
>> Having the correct prescaler is important in
>> the process of getting a finite i2c clock. In
>> addition, the prescaler is used in the process
>> of activating the correct noise filter and thus,
>> lets more error resilient i2c communications.
>
> Should this fix the bug causing the need for that
> recent ZOOM patch slowing down twl4030 communication
> to 400 MHz?
>
> And should it let at least some boards talk to their
> TWL chips at 3.4 MBit/sec (top speed for standard
> highspeed I2C) instead of 2.6 Mbit/sec (pokey slow)?
> I've always wondered why all the boards configured
> those links to be seemingly slower than allowed ...

When I put a scope to Beagle and Overo a couple of months back it
looked to me like the i2c signals were just *barely* in spec for
2.6Mbit/sec, so I think that hardware might have been the limiting
factor in the decision to choose 2.6 Mit/sec

Steve

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Eero Nurkkala]

On Fri, 2008-11-14 at 11:45 -0800, ext David Brownell wrote:
> On Friday 14 November 2008, ext-eero.nurkkala@nokia.com wrote:
> > The prescalers for 100 kHz and 400 kHz mode
> > are wrong. The internal clock is the fclock
> > divided by the prescaler. The PSC is an 8 bit
> > field in omap3430. Moreover, the scll and
> > sclh values should be adjusted properly.
> > Having the correct prescaler is important in
> > the process of getting a finite i2c clock. In
> > addition, the prescaler is used in the process
> > of activating the correct noise filter and thus,
> > lets more error resilient i2c communications.
> 
> Should this fix the bug causing the need for that
> recent ZOOM patch slowing down twl4030 communication
> to 400 MHz?
> 
> And should it let at least some boards talk to their
> TWL chips at 3.4 MBit/sec (top speed for standard
> highspeed I2C) instead of 2.6 Mbit/sec (pokey slow)?
> I've always wondered why all the boards configured
> those links to be seemingly slower than allowed ...
> 
> - Dave
> 

Well, this should not affect the High speed I2C at all.
Only fast and slow I2C (100 and 400 khz).

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[Tony Lindgren]

* ext-eero.nurkkala@nokia.com <ext-eero.nurkkala@nokia.com> [081114 00:43]:
> From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
> 
> The prescalers for 100 kHz and 400 kHz mode
> are wrong. The internal clock is the fclock
> divided by the prescaler. The PSC is an 8 bit
> field in omap3430. Moreover, the scll and
> sclh values should be adjusted properly.
> Having the correct prescaler is important in
> the process of getting a finite i2c clock. In
> addition, the prescaler is used in the process
> of activating the correct noise filter and thus,
> lets more error resilient i2c communications.

I guess this should be also updated to use dev->rev so it works on
2430 too?

Tony

> Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
> ---
>  drivers/i2c/busses/i2c-omap.c |   21 ++++++++++++++++++---
>  1 files changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index e708ebd..a42003a 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -288,7 +288,17 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
>  
>  		/* HSI2C controller internal clk rate should be 19.2 Mhz */
> -		internal_clk = 19200;
> +		if (cpu_is_omap34xx()) {
> +			if (dev->speed > 400)
> +				internal_clk = 19200;
> +			else if (dev->speed > 100)
> +				internal_clk = 9600;
> +			else
> +				internal_clk = 4000;
> +		} else {
> +			internal_clk = 19200;
> +		}
> +
>  		fclk_rate = clk_get_rate(dev->fclk) / 1000;
>  
>  		/* Compute prescaler divisor */
> @@ -306,8 +316,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  			hssclh = fclk_rate / (dev->speed * 2) - 6;
>  		} else {
>  			/* To handle F/S modes */
> -			fsscll = internal_clk / (dev->speed * 2) - 6;
> -			fssclh = internal_clk / (dev->speed * 2) - 6;
> +			if (cpu_is_omap34xx()) {
> +				fsscll = internal_clk / (dev->speed * 2) - 7;
> +				fssclh = internal_clk / (dev->speed * 2) - 5;
> +			} else {
> +				fsscll = internal_clk / (dev->speed * 2) - 6;
> +				fssclh = internal_clk / (dev->speed * 2) - 6;
> +			}
>  		}
>  		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
>  		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
> -- 
> 1.6.0
> 
> --
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[PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[ext-eero.nurkkala]

From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>

The prescalers for 100 kHz and 400 kHz mode
are wrong. The internal clock is the fclock
divided by the prescaler. Also, the scll and
sclh values should be adjusted correctly.
Having the correct prescaler is important in
the process of getting standard i2c clock. In
addition, it (psc) is used to get the correct
noise filter and thus, lets more error resilient
i2c communications.

Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
---
 drivers/i2c/busses/i2c-omap.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index f15668d..cee2f2d 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -288,7 +288,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 
 		/* HSI2C controller internal clk rate should be 19.2 Mhz */
-		internal_clk = 19200;
+		if (dev->speed > 400)
+			internal_clk = 19200;
+		else if (dev->speed > 100)
+			internal_clk = 9600;
+		else
+			internal_clk = 4000;
+
 		fclk_rate = clk_get_rate(dev->fclk) / 1000;
 
 		/* Compute prescaler divisor */
@@ -306,8 +312,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 			hssclh = fclk_rate / (dev->speed * 2) - 6;
 		} else {
 			/* To handle F/S modes */
-			fsscll = internal_clk / (dev->speed * 2) - 6;
-			fssclh = internal_clk / (dev->speed * 2) - 6;
+			fsscll = internal_clk / (dev->speed * 2) - 7;
+			fssclh = internal_clk / (dev->speed * 2) - 5;
 		}
 		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
-- 
1.6.0

Re: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[shekhar, chandra]

----- Original Message ----- 
From: <ext-eero.nurkkala@nokia.com>
To: <linux-omap@vger.kernel.org>
Cc: "Eero Nurkkala" <ext-eero.nurkkala@nokia.com>
Sent: Tuesday, November 11, 2008 12:22 PM
Subject: [PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers


> From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
>
> The prescalers for 100 kHz and 400 kHz mode
> are wrong. The internal clock is the fclock
> divided by the prescaler. Also, the scll and
> sclh values should be adjusted correctly.
> Having the correct prescaler is important in
> the process of getting standard i2c clock. In
> addition, it (psc) is used to get the correct
> noise filter and thus, lets more error resilient
> i2c communications.
>
> Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
> ---
> drivers/i2c/busses/i2c-omap.c |   12 +++++++++---
> 1 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index f15668d..cee2f2d 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -288,7 +288,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  if (cpu_is_omap2430() || cpu_is_omap34xx()) {
>
>  /* HSI2C controller internal clk rate should be 19.2 Mhz */
> - internal_clk = 19200;
> + if (dev->speed > 400)
> + internal_clk = 19200;
> + else if (dev->speed > 100)
> + internal_clk = 9600;
> + else
> + internal_clk = 4000;

Is internal clk 4000 valid??  PSC_REG  field cannot encompass ( its 4 bit field) 
the calculated psc if internal_clk is 4000.

> +
>  fclk_rate = clk_get_rate(dev->fclk) / 1000;
>
>  /* Compute prescaler divisor */
> @@ -306,8 +312,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
>  hssclh = fclk_rate / (dev->speed * 2) - 6;
>  } else {
>  /* To handle F/S modes */
> - fsscll = internal_clk / (dev->speed * 2) - 6;
> - fssclh = internal_clk / (dev->speed * 2) - 6;
> + fsscll = internal_clk / (dev->speed * 2) - 7;
> + fssclh = internal_clk / (dev->speed * 2) - 5;
>  }
>  scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
>  sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
> -- 
> 1.6.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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> 

[PATCH] i2c: i2c-omap: Fix standard and fast mode prescalers

[ext-eero.nurkkala]

From: Eero Nurkkala <ext-eero.nurkkala@nokia.com>


Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
---
 drivers/i2c/busses/i2c-omap.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 9ae3ad3..92653ce 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -304,7 +304,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 
 		/* HSI2C controller internal clk rate should be 19.2 Mhz */
-		internal_clk = 19200;
+		if (dev->speed > 400)
+			internal_clk = 19200;
+		else if (dev->speed > 100)
+			internal_clk = 9600;
+		else
+			internal_clk = 4000;
+
 		fclk_rate = clk_get_rate(dev->fclk) / 1000;
 
 		/* Compute prescaler divisor */
@@ -322,8 +328,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 			hssclh = fclk_rate / (dev->speed * 2) - 6;
 		} else {
 			/* To handle F/S modes */
-			fsscll = internal_clk / (dev->speed * 2) - 6;
-			fssclh = internal_clk / (dev->speed * 2) - 6;
+			fsscll = internal_clk / (dev->speed * 2) - 7;
+			fssclh = internal_clk / (dev->speed * 2) - 5;
 		}
 		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
-- 
1.5.2