Beagleboard rev C memory timings & suspend/resume

Beagleboard rev C memory timings & suspend/resume

[Jean Pihet]

Hi,

The suspend/resume on Beagleboard has some problem due to bad memory timings.
Suspending for more than 5 to 10 seconds shows memory corruption.

The new chips on rev Cx boards are using 2 DDR chip selects and it looks like 
the 2nd memory part is not correctly put into self refresh. As an 
experimentation I tried the same kernel with 'mem=128M' and it resumes 
correctly after 1 min in suspend.

I could not find the latest DDR detailed specs from Micron. The part number is 
MT29C2G48MAKLCJI-6 IT. Are those available? Is this part identical to 2 1Gb 
parts?

Now for the code in the kernel, there are some changes needed to support 2 
CS'es:
- the SDRC parameters need to be updated for the new memory part
- the SDRC parameters need to include the ACTIM_CTRL_A_0, ACTIM_CTRL_A_1, 
ACTIM_CTRL_B_0, ACTIM_CTRL_B_1, RFR_CTRL_0 and RFR_CTRL_1 registers. Since 
the parameters for the 2nd CS are the same, this can be avoided by writing 
the same values to the 2 sets of registers
- is there a need to differentiate between 1Gb and 2Gb chips, or can we just 
write the same params for both CS'es even if only one is being used?
- the 'configure_sdrc' function in arch/arm/mach-omap2/sram34xx.S needs to 
program the 2 sets of registers. Here is a patch excerpt below. This patch 
only does not help the suspend/resume though.

Any idea or suggestion?

Regards,
Jean

---
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 487fa86..6d5843a 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -175,15 +175,24 @@ wait_dll_unlock:
        bne     wait_dll_unlock
        bx      lr
 configure_sdrc:
-       ldr     r11, omap3_sdrc_rfr_ctrl
+       ldr     r11, omap3_sdrc_rfr_ctrl_0
        str     r0, [r11]
-       ldr     r11, omap3_sdrc_actim_ctrla
+       ldr     r11, omap3_sdrc_rfr_ctrl_1
+       str     r0, [r11]
+       ldr     r11, omap3_sdrc_actim_ctrla_0
+       str     r1, [r11]
+       ldr     r11, omap3_sdrc_actim_ctrla_1
        str     r1, [r11]
-       ldr     r11, omap3_sdrc_actim_ctrlb
+       ldr     r11, omap3_sdrc_actim_ctrlb_0
+       str     r2, [r11]
+       ldr     r11, omap3_sdrc_actim_ctrlb_1
        str     r2, [r11]
        ldr     r11, omap3_sdrc_mr_0
        str     r6, [r11]
        ldr     r6, [r11]               @ posted-write barrier for SDRC
+       ldr     r11, omap3_sdrc_mr_1
+       str     r6, [r11]
+       ldr     r6, [r11]               @ posted-write barrier for SDRC
        bx      lr

 omap3_sdrc_power:
@@ -194,14 +203,22 @@ omap3_cm_idlest1_core:
        .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 omap3_cm_iclken1_core:
        .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
-omap3_sdrc_rfr_ctrl:
+omap3_sdrc_rfr_ctrl_0:
        .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap3_sdrc_actim_ctrla:
+omap3_sdrc_rfr_ctrl_1:
+       .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
+omap3_sdrc_actim_ctrla_0:
        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
-omap3_sdrc_actim_ctrlb:
+omap3_sdrc_actim_ctrla_1:
+       .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
+omap3_sdrc_actim_ctrlb_0:
        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_actim_ctrlb_1:
+       .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 omap3_sdrc_mr_0:
        .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
+omap3_sdrc_mr_1:
+       .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
 omap3_sdrc_dlla_status:
        .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:

Re: Beagleboard rev C memory timings & suspend/resume

[Paul Walmsley]

Hello Jean,

sorry about the delay,

On Wed, 29 Apr 2009, Jean Pihet wrote:

> The suspend/resume on Beagleboard has some problem due to bad memory timings.
> Suspending for more than 5 to 10 seconds shows memory corruption.
> 
> The new chips on rev Cx boards are using 2 DDR chip selects and it looks like 
> the 2nd memory part is not correctly put into self refresh. As an 
> experimentation I tried the same kernel with 'mem=128M' and it resumes 
> correctly after 1 min in suspend.

Nice work, this seems likely to be the cause.

> I could not find the latest DDR detailed specs from Micron. The part number is 
> MT29C2G48MAKLCJI-6 IT. Are those available? Is this part identical to 2 1Gb 
> parts?

The combined part's web page is:

http://www.micron.com/products/partdetail?part=MT29C2G48MAKLCJI-6%20IT

The SDRAM datasheet is the same that is used for all the other Micron 
parts that we've run across so far:

http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdram_t48m.pdf

> Now for the code in the kernel, there are some changes needed to support 2 
> CS'es:
> - the SDRC parameters need to be updated for the new memory part
> - the SDRC parameters need to include the ACTIM_CTRL_A_0, ACTIM_CTRL_A_1, 
> ACTIM_CTRL_B_0, ACTIM_CTRL_B_1, RFR_CTRL_0 and RFR_CTRL_1 registers. Since 
> the parameters for the 2nd CS are the same, this can be avoided by writing 
> the same values to the 2 sets of registers
> - is there a need to differentiate between 1Gb and 2Gb chips, or can we just 
> write the same params for both CS'es even if only one is being used?
> - the 'configure_sdrc' function in arch/arm/mach-omap2/sram34xx.S needs to 
> program the 2 sets of registers. Here is a patch excerpt below. This patch 
> only does not help the suspend/resume though.
> 
> Any idea or suggestion?

Looks like a good start.  Since the two SDRC chip-selects can technically 
address parts with different timings, we should not assume that the two 
chip selects will be the same.  Admittedly this seems like an unlikely 
situation, but it's not impossible for non-POP OMAPs.

Re: suspend/resume, if you're talking about the code in sleep34xx.S, it 
looks like this is already in good shape.

Re: board & SDRC changes: would suggest modifying omap2_sdrc_init() to 
take either two struct omap_sdrc_params pointers, or one struct with two 
pointers.  omap2_init_common_hw() will also need to be updated for that, 
and all of the board-*.c files also.

Sound reasonable?

>         ldr     r11, omap3_sdrc_mr_0
>         str     r6, [r11]
>         ldr     r6, [r11]               @ posted-write barrier for SDRC
> +       ldr     r11, omap3_sdrc_mr_1
> +       str     r6, [r11]
> +       ldr     r6, [r11]               @ posted-write barrier for SDRC
>         bx      lr

By the way, there's no need to duplicate the posted-write barrier.  There 
should only be one, appearing right before the 'bx lr'.

regards,

- Paul

Re: Beagleboard rev C memory timings & suspend/resume

[Jean Pihet]

Hi Paul,

On Thursday 07 May 2009 01:39:02 Paul Walmsley wrote:
> Hello Jean,
>
> sorry about the delay,
Thanks for replying!

> On Wed, 29 Apr 2009, Jean Pihet wrote:
> > The suspend/resume on Beagleboard has some problem due to bad memory
> > timings. Suspending for more than 5 to 10 seconds shows memory
> > corruption.
> >
> > The new chips on rev Cx boards are using 2 DDR chip selects and it looks
> > like the 2nd memory part is not correctly put into self refresh. As an
> > experimentation I tried the same kernel with 'mem=128M' and it resumes
> > correctly after 1 min in suspend.
>
> Nice work, this seems likely to be the cause.
>
> > I could not find the latest DDR detailed specs from Micron. The part
> > number is MT29C2G48MAKLCJI-6 IT. Are those available? Is this part
> > identical to 2 1Gb parts?
>
> The combined part's web page is:
>
> http://www.micron.com/products/partdetail?part=MT29C2G48MAKLCJI-6%20IT
>
> The SDRAM datasheet is the same that is used for all the other Micron
> parts that we've run across so far:
>
> http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdram_
>t48m.pdf
Ok so we have 2 DDRs combined.
That does not explain why the self-refresh is ok with only 1 part while it 
fails with the 2 parts.
Could it be that the timings are too tight? Is there something special for the 
SDRC to support the 2 CSes correctly?

We already have used the self refresh with 2 parts hooked on a 3430, not 
Micron parts though, so the code looks correct.

I think we need help from the HW vendors here to identify the root cause: 
SDRC, DDR parts, connections?
 
> > Now for the code in the kernel, there are some changes needed to support
> > 2 CS'es:
> > - the SDRC parameters need to be updated for the new memory part
> > - the SDRC parameters need to include the ACTIM_CTRL_A_0, ACTIM_CTRL_A_1,
> > ACTIM_CTRL_B_0, ACTIM_CTRL_B_1, RFR_CTRL_0 and RFR_CTRL_1 registers.
> > Since the parameters for the 2nd CS are the same, this can be avoided by
> > writing the same values to the 2 sets of registers
> > - is there a need to differentiate between 1Gb and 2Gb chips, or can we
> > just write the same params for both CS'es even if only one is being used?
> > - the 'configure_sdrc' function in arch/arm/mach-omap2/sram34xx.S needs
> > to program the 2 sets of registers. Here is a patch excerpt below. This
> > patch only does not help the suspend/resume though.
> >
> > Any idea or suggestion?
>
> Looks like a good start.  Since the two SDRC chip-selects can technically
> address parts with different timings, we should not assume that the two
> chip selects will be the same.  Admittedly this seems like an unlikely
> situation, but it's not impossible for non-POP OMAPs.
Makes sense. It is better to have correct and generic code.

> Re: suspend/resume, if you're talking about the code in sleep34xx.S, it
> looks like this is already in good shape.
>
> Re: board & SDRC changes: would suggest modifying omap2_sdrc_init() to
> take either two struct omap_sdrc_params pointers, or one struct with two
> pointers.  omap2_init_common_hw() will also need to be updated for that,
> and all of the board-*.c files also.
>
> Sound reasonable?
Sure. I can write the new code, but I prefer to have the self refresh working 
first.

> >         ldr     r11, omap3_sdrc_mr_0
> >         str     r6, [r11]
> >         ldr     r6, [r11]               @ posted-write barrier for SDRC
> > +       ldr     r11, omap3_sdrc_mr_1
> > +       str     r6, [r11]
> > +       ldr     r6, [r11]               @ posted-write barrier for SDRC
> >         bx      lr
>
> By the way, there's no need to duplicate the posted-write barrier.  There
> should only be one, appearing right before the 'bx lr'.
Ok I will take it into account.

>
> regards,
>
> - Paul

Regards,
Jean

Re: Beagleboard rev C memory timings & suspend/resume

[Jean Pihet]

Hi,

FYI I tried to relax the DDR timings (mainly tRC, tWTR, tXP, tXSR, ARCV) but 
that did not help.

>From the OMAP datasheet it looks like the ARCV setting is off: shouldn't it be 
(tREFI/tCK)+50=(7800/6)+50=0x546?

Is there a way to know if the self refresh works on both parts?

Regards,
Jean

On Thursday 07 May 2009 13:18:30 Jean Pihet wrote:
> Hi Paul,
>
> On Thursday 07 May 2009 01:39:02 Paul Walmsley wrote:
> > Hello Jean,
> >
> > sorry about the delay,
>
> Thanks for replying!
>
> > On Wed, 29 Apr 2009, Jean Pihet wrote:
> > > The suspend/resume on Beagleboard has some problem due to bad memory
> > > timings. Suspending for more than 5 to 10 seconds shows memory
> > > corruption.
> > >
> > > The new chips on rev Cx boards are using 2 DDR chip selects and it
> > > looks like the 2nd memory part is not correctly put into self refresh.
> > > As an experimentation I tried the same kernel with 'mem=128M' and it
> > > resumes correctly after 1 min in suspend.
> >
> > Nice work, this seems likely to be the cause.
> >
> > > I could not find the latest DDR detailed specs from Micron. The part
> > > number is MT29C2G48MAKLCJI-6 IT. Are those available? Is this part
> > > identical to 2 1Gb parts?
> >
> > The combined part's web page is:
> >
> > http://www.micron.com/products/partdetail?part=MT29C2G48MAKLCJI-6%20IT
> >
> > The SDRAM datasheet is the same that is used for all the other Micron
> > parts that we've run across so far:
> >
> > http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdra
> >m_ t48m.pdf
>
> Ok so we have 2 DDRs combined.
> That does not explain why the self-refresh is ok with only 1 part while it
> fails with the 2 parts.
> Could it be that the timings are too tight? Is there something special for
> the SDRC to support the 2 CSes correctly?
>
> We already have used the self refresh with 2 parts hooked on a 3430, not
> Micron parts though, so the code looks correct.
>
> I think we need help from the HW vendors here to identify the root cause:
> SDRC, DDR parts, connections?
>
> > > Now for the code in the kernel, there are some changes needed to
> > > support 2 CS'es:
> > > - the SDRC parameters need to be updated for the new memory part
> > > - the SDRC parameters need to include the ACTIM_CTRL_A_0,
> > > ACTIM_CTRL_A_1, ACTIM_CTRL_B_0, ACTIM_CTRL_B_1, RFR_CTRL_0 and
> > > RFR_CTRL_1 registers. Since the parameters for the 2nd CS are the same,
> > > this can be avoided by writing the same values to the 2 sets of
> > > registers
> > > - is there a need to differentiate between 1Gb and 2Gb chips, or can we
> > > just write the same params for both CS'es even if only one is being
> > > used? - the 'configure_sdrc' function in arch/arm/mach-omap2/sram34xx.S
> > > needs to program the 2 sets of registers. Here is a patch excerpt
> > > below. This patch only does not help the suspend/resume though.
> > >
> > > Any idea or suggestion?
> >
> > Looks like a good start.  Since the two SDRC chip-selects can technically
> > address parts with different timings, we should not assume that the two
> > chip selects will be the same.  Admittedly this seems like an unlikely
> > situation, but it's not impossible for non-POP OMAPs.
>
> Makes sense. It is better to have correct and generic code.
>
> > Re: suspend/resume, if you're talking about the code in sleep34xx.S, it
> > looks like this is already in good shape.
> >
> > Re: board & SDRC changes: would suggest modifying omap2_sdrc_init() to
> > take either two struct omap_sdrc_params pointers, or one struct with two
> > pointers.  omap2_init_common_hw() will also need to be updated for that,
> > and all of the board-*.c files also.
> >
> > Sound reasonable?
>
> Sure. I can write the new code, but I prefer to have the self refresh
> working first.
>
> > >         ldr     r11, omap3_sdrc_mr_0
> > >         str     r6, [r11]
> > >         ldr     r6, [r11]               @ posted-write barrier for SDRC
> > > +       ldr     r11, omap3_sdrc_mr_1
> > > +       str     r6, [r11]
> > > +       ldr     r6, [r11]               @ posted-write barrier for SDRC
> > >         bx      lr
> >
> > By the way, there's no need to duplicate the posted-write barrier.  There
> > should only be one, appearing right before the 'bx lr'.
>
> Ok I will take it into account.
>
> > regards,
> >
> > - Paul
>
> Regards,
> Jean
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: Beagleboard rev C memory timings & suspend/resume

[Paul Walmsley]

Hello Jean

On Thu, 7 May 2009, Jean Pihet wrote:

> From the OMAP datasheet it looks like the ARCV setting is off: shouldn't it be 
> (tREFI/tCK)+50=(7800/6)+50=0x546?

Could you elaborate further what you're seeing?  It would help to 
see the register value that you're using to come to this conclusion.

- Paul

> 
> Is there a way to know if the self refresh works on both parts?
> 
> Regards,
> Jean
> 
> On Thursday 07 May 2009 13:18:30 Jean Pihet wrote:
> > Hi Paul,
> >
> > On Thursday 07 May 2009 01:39:02 Paul Walmsley wrote:
> > > Hello Jean,
> > >
> > > sorry about the delay,
> >
> > Thanks for replying!
> >
> > > On Wed, 29 Apr 2009, Jean Pihet wrote:
> > > > The suspend/resume on Beagleboard has some problem due to bad memory
> > > > timings. Suspending for more than 5 to 10 seconds shows memory
> > > > corruption.
> > > >
> > > > The new chips on rev Cx boards are using 2 DDR chip selects and it
> > > > looks like the 2nd memory part is not correctly put into self refresh.
> > > > As an experimentation I tried the same kernel with 'mem=128M' and it
> > > > resumes correctly after 1 min in suspend.
> > >
> > > Nice work, this seems likely to be the cause.
> > >
> > > > I could not find the latest DDR detailed specs from Micron. The part
> > > > number is MT29C2G48MAKLCJI-6 IT. Are those available? Is this part
> > > > identical to 2 1Gb parts?
> > >
> > > The combined part's web page is:
> > >
> > > http://www.micron.com/products/partdetail?part=MT29C2G48MAKLCJI-6%20IT
> > >
> > > The SDRAM datasheet is the same that is used for all the other Micron
> > > parts that we've run across so far:
> > >
> > > http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdra
> > >m_ t48m.pdf
> >
> > Ok so we have 2 DDRs combined.
> > That does not explain why the self-refresh is ok with only 1 part while it
> > fails with the 2 parts.
> > Could it be that the timings are too tight? Is there something special for
> > the SDRC to support the 2 CSes correctly?
> >
> > We already have used the self refresh with 2 parts hooked on a 3430, not
> > Micron parts though, so the code looks correct.
> >
> > I think we need help from the HW vendors here to identify the root cause:
> > SDRC, DDR parts, connections?
> >
> > > > Now for the code in the kernel, there are some changes needed to
> > > > support 2 CS'es:
> > > > - the SDRC parameters need to be updated for the new memory part
> > > > - the SDRC parameters need to include the ACTIM_CTRL_A_0,
> > > > ACTIM_CTRL_A_1, ACTIM_CTRL_B_0, ACTIM_CTRL_B_1, RFR_CTRL_0 and
> > > > RFR_CTRL_1 registers. Since the parameters for the 2nd CS are the same,
> > > > this can be avoided by writing the same values to the 2 sets of
> > > > registers
> > > > - is there a need to differentiate between 1Gb and 2Gb chips, or can we
> > > > just write the same params for both CS'es even if only one is being
> > > > used? - the 'configure_sdrc' function in arch/arm/mach-omap2/sram34xx.S
> > > > needs to program the 2 sets of registers. Here is a patch excerpt
> > > > below. This patch only does not help the suspend/resume though.
> > > >
> > > > Any idea or suggestion?
> > >
> > > Looks like a good start.  Since the two SDRC chip-selects can technically
> > > address parts with different timings, we should not assume that the two
> > > chip selects will be the same.  Admittedly this seems like an unlikely
> > > situation, but it's not impossible for non-POP OMAPs.
> >
> > Makes sense. It is better to have correct and generic code.
> >
> > > Re: suspend/resume, if you're talking about the code in sleep34xx.S, it
> > > looks like this is already in good shape.
> > >
> > > Re: board & SDRC changes: would suggest modifying omap2_sdrc_init() to
> > > take either two struct omap_sdrc_params pointers, or one struct with two
> > > pointers.  omap2_init_common_hw() will also need to be updated for that,
> > > and all of the board-*.c files also.
> > >
> > > Sound reasonable?
> >
> > Sure. I can write the new code, but I prefer to have the self refresh
> > working first.
> >
> > > >         ldr     r11, omap3_sdrc_mr_0
> > > >         str     r6, [r11]
> > > >         ldr     r6, [r11]               @ posted-write barrier for SDRC
> > > > +       ldr     r11, omap3_sdrc_mr_1
> > > > +       str     r6, [r11]
> > > > +       ldr     r6, [r11]               @ posted-write barrier for SDRC
> > > >         bx      lr
> > >
> > > By the way, there's no need to duplicate the posted-write barrier.  There
> > > should only be one, appearing right before the 'bx lr'.
> >
> > Ok I will take it into account.
> >
> > > regards,
> > >
> > > - Paul
> >
> > Regards,
> > Jean
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 


- Paul

Re: Beagleboard rev C memory timings & suspend/resume

[Jean Pihet]

Paul,

On Thursday 07 May 2009 20:59:43 Paul Walmsley wrote:
> Hello Jean
>
> On Thu, 7 May 2009, Jean Pihet wrote:
> > From the OMAP datasheet it looks like the ARCV setting is off: shouldn't
> > it be (tREFI/tCK)+50=(7800/6)+50=0x546?
>
> Could you elaborate further what you're seeing?  It would help to
> see the register value that you're using to come to this conclusion.
The SDRC_RFR_CTRL_p registers are now programmed with 0x4dc01, which means the 
fiel ARCV has the value 0x4dc=1244.
>From the DDR datasheet we need an average refresh period of 7.8us and a clock 
period of 6ns (166MHz). From the definition of the ARCV field in the OMAP TRM 
I need to program ARCV with: (tREFI/tCK)+50 = (7800/6)+50=1350=0x546.
The SDRC_RFR_CTRL_p registers would then have the value of 0x54601.

Does that make sense? Am I wrong with the calculation?

>
> - Paul
Regards,
Jean
>
> > Is there a way to know if the self refresh works on both parts?
> >
> > Regards,
> > Jean
> >
> > On Thursday 07 May 2009 13:18:30 Jean Pihet wrote:
> > > Hi Paul,
> > >
> > > On Thursday 07 May 2009 01:39:02 Paul Walmsley wrote:
> > > > Hello Jean,
> > > >
> > > > sorry about the delay,
> > >
> > > Thanks for replying!
> > >
> > > > On Wed, 29 Apr 2009, Jean Pihet wrote:
> > > > > The suspend/resume on Beagleboard has some problem due to bad
> > > > > memory timings. Suspending for more than 5 to 10 seconds shows
> > > > > memory corruption.
> > > > >
> > > > > The new chips on rev Cx boards are using 2 DDR chip selects and it
> > > > > looks like the 2nd memory part is not correctly put into self
> > > > > refresh. As an experimentation I tried the same kernel with
> > > > > 'mem=128M' and it resumes correctly after 1 min in suspend.
> > > >
> > > > Nice work, this seems likely to be the cause.
> > > >
> > > > > I could not find the latest DDR detailed specs from Micron. The
> > > > > part number is MT29C2G48MAKLCJI-6 IT. Are those available? Is this
> > > > > part identical to 2 1Gb parts?
> > > >
> > > > The combined part's web page is:
> > > >
> > > > http://www.micron.com/products/partdetail?part=MT29C2G48MAKLCJI-6%20I
> > > >T
> > > >
> > > > The SDRAM datasheet is the same that is used for all the other Micron
> > > > parts that we've run across so far:
> > > >
> > > > http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_
> > > >sdra m_ t48m.pdf
> > >
> > > Ok so we have 2 DDRs combined.
> > > That does not explain why the self-refresh is ok with only 1 part while
> > > it fails with the 2 parts.
> > > Could it be that the timings are too tight? Is there something special
> > > for the SDRC to support the 2 CSes correctly?
> > >
> > > We already have used the self refresh with 2 parts hooked on a 3430,
> > > not Micron parts though, so the code looks correct.
> > >
> > > I think we need help from the HW vendors here to identify the root
> > > cause: SDRC, DDR parts, connections?
> > >
> > > > > Now for the code in the kernel, there are some changes needed to
> > > > > support 2 CS'es:
> > > > > - the SDRC parameters need to be updated for the new memory part
> > > > > - the SDRC parameters need to include the ACTIM_CTRL_A_0,
> > > > > ACTIM_CTRL_A_1, ACTIM_CTRL_B_0, ACTIM_CTRL_B_1, RFR_CTRL_0 and
> > > > > RFR_CTRL_1 registers. Since the parameters for the 2nd CS are the
> > > > > same, this can be avoided by writing the same values to the 2 sets
> > > > > of registers
> > > > > - is there a need to differentiate between 1Gb and 2Gb chips, or
> > > > > can we just write the same params for both CS'es even if only one
> > > > > is being used? - the 'configure_sdrc' function in
> > > > > arch/arm/mach-omap2/sram34xx.S needs to program the 2 sets of
> > > > > registers. Here is a patch excerpt below. This patch only does not
> > > > > help the suspend/resume though.
> > > > >
> > > > > Any idea or suggestion?
> > > >
> > > > Looks like a good start.  Since the two SDRC chip-selects can
> > > > technically address parts with different timings, we should not
> > > > assume that the two chip selects will be the same.  Admittedly this
> > > > seems like an unlikely situation, but it's not impossible for non-POP
> > > > OMAPs.
> > >
> > > Makes sense. It is better to have correct and generic code.
> > >
> > > > Re: suspend/resume, if you're talking about the code in sleep34xx.S,
> > > > it looks like this is already in good shape.
> > > >
> > > > Re: board & SDRC changes: would suggest modifying omap2_sdrc_init()
> > > > to take either two struct omap_sdrc_params pointers, or one struct
> > > > with two pointers.  omap2_init_common_hw() will also need to be
> > > > updated for that, and all of the board-*.c files also.
> > > >
> > > > Sound reasonable?
> > >
> > > Sure. I can write the new code, but I prefer to have the self refresh
> > > working first.
> > >
> > > > >         ldr     r11, omap3_sdrc_mr_0
> > > > >         str     r6, [r11]
> > > > >         ldr     r6, [r11]               @ posted-write barrier for
> > > > > SDRC +       ldr     r11, omap3_sdrc_mr_1
> > > > > +       str     r6, [r11]
> > > > > +       ldr     r6, [r11]               @ posted-write barrier for
> > > > > SDRC bx      lr
> > > >
> > > > By the way, there's no need to duplicate the posted-write barrier. 
> > > > There should only be one, appearing right before the 'bx lr'.
> > >
> > > Ok I will take it into account.
> > >
> > > > regards,
> > > >
> > > > - Paul
> > >
> > > Regards,
> > > Jean
> > >
> > > --
> > > To unsubscribe from this list: send the line "unsubscribe linux-omap"
> > > in the body of a message to majordomo@vger.kernel.org
> > > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> - Paul

Re: Beagleboard rev C memory timings & suspend/resume

[Paul Walmsley]

Hello Jean,

On Fri, 8 May 2009, Jean Pihet wrote:

> On Thursday 07 May 2009 20:59:43 Paul Walmsley wrote:
> > On Thu, 7 May 2009, Jean Pihet wrote:
> > > From the OMAP datasheet it looks like the ARCV setting is off: shouldn't
> > > it be (tREFI/tCK)+50=(7800/6)+50=0x546?
> >
> > Could you elaborate further what you're seeing?  It would help to
> > see the register value that you're using to come to this conclusion.
> The SDRC_RFR_CTRL_p registers are now programmed with 0x4dc01, which means the 
> fiel ARCV has the value 0x4dc=1244.
> From the DDR datasheet we need an average refresh period of 7.8us and a clock 
> period of 6ns (166MHz). From the definition of the ARCV field in the OMAP TRM 
> I need to program ARCV with: (tREFI/tCK)+50 = (7800/6)+50=1350=0x546.
> The SDRC_RFR_CTRL_p registers would then have the value of 0x54601.
> 
> Does that make sense? Am I wrong with the calculation?

According to the TRM, the 50 cycles should be subtracted rather than added 
(section 11.2.6.3.3.4).  One other thing is that the bootloaders I've seen 
program DPLL3 such that the SDRC clock is 166000000 Hz, rather than 
166666666 Hz, so tCK winds up being something like 6.024... ns.

Auto-refresh is only used while the SDRC is active, though.  So unless 
memory corruption is evident outside of suspend, the ARCV value is 
unlikely to be the problem.  

It sounds like the problem is related to self-refresh, that the SDRAM bank 
on one of the chipselects either can't enter or exit self-refresh.  You 
have self-refresh working on a different board with both SDRC CS0 and CS1 
in use, correct?  Is that with an ES2 or ES3 chip?

One possibility: perhaps the problem is with Beagle's pin mux settings.  
You might want to boot with mem=128M and make sure 
CONTROL_PADCONF_SAD2D_SBUSFLAG and CONTROL_PADCONF_SDRC_CKE1 are in mode 0 
before suspend and after resume.

Another thought: it could be that the ROM code on Beagle is not 
programming the correct SDRC register values after resume.  You might try 
booting with mem=128M and dumping the SDRC register values before suspend 
and after resume.


- Paul

Re: Beagleboard rev C memory timings & suspend/resume

[Jean Pihet]

Hi Paul,

On Saturday 09 May 2009 00:43:43 Paul Walmsley wrote:
> Hello Jean,
>
> On Fri, 8 May 2009, Jean Pihet wrote:
> > On Thursday 07 May 2009 20:59:43 Paul Walmsley wrote:
> > > On Thu, 7 May 2009, Jean Pihet wrote:
> > > > From the OMAP datasheet it looks like the ARCV setting is off:
> > > > shouldn't it be (tREFI/tCK)+50=(7800/6)+50=0x546?
> > >
> > > Could you elaborate further what you're seeing?  It would help to
> > > see the register value that you're using to come to this conclusion.
> >
> > The SDRC_RFR_CTRL_p registers are now programmed with 0x4dc01, which
> > means the fiel ARCV has the value 0x4dc=1244.
> > From the DDR datasheet we need an average refresh period of 7.8us and a
> > clock period of 6ns (166MHz). From the definition of the ARCV field in
> > the OMAP TRM I need to program ARCV with: (tREFI/tCK)+50 =
> > (7800/6)+50=1350=0x546. The SDRC_RFR_CTRL_p registers would then have the
> > value of 0x54601.
> >
> > Does that make sense? Am I wrong with the calculation?
>
> According to the TRM, the 50 cycles should be subtracted rather than added
> (section 11.2.6.3.3.4).  One other thing is that the bootloaders I've seen
> program DPLL3 such that the SDRC clock is 166000000 Hz, rather than
> 166666666 Hz, so tCK winds up being something like 6.024... ns.
The settings should be ok with tCK=6.024ns

> Auto-refresh is only used while the SDRC is active, though.  So unless
> memory corruption is evident outside of suspend, the ARCV value is
> unlikely to be the problem.
Ok

> It sounds like the problem is related to self-refresh, that the SDRAM bank
> on one of the chipselects either can't enter or exit self-refresh.  You
> have self-refresh working on a different board with both SDRC CS0 and CS1
> in use, correct?  Is that with an ES2 or ES3 chip?
>
> One possibility: perhaps the problem is with Beagle's pin mux settings.
> You might want to boot with mem=128M and make sure
> CONTROL_PADCONF_SAD2D_SBUSFLAG and CONTROL_PADCONF_SDRC_CKE1 are in mode 0
> before suspend and after resume.
Yes that definitely is the root cause. I should have checked this first ;-(
The U-Boot change is committed, cf. 
http://gitorious.org/u-boot-omap3/mainline/commit/c6f01ad390308800693c62dbdb096ab59e03630b
and
http://gitorious.org/u-boot-omap3/mainline/commit/4025cfbde3611b14c0d4831a5524e5e061128e30

> Another thought: it could be that the ROM code on Beagle is not
> programming the correct SDRC register values after resume.  You might try
> booting with mem=128M and dumping the SDRC register values before suspend
> and after resume.
Those are OK.

I am looking at a fix for the SDRC setup with 2 CSes. I will propose the 
changes asap.

>
> - Paul

Thx & regards,
Jean

Re: Beagleboard rev C memory timings & suspend/resume

[Paul Walmsley]

Hi Jean,

On Mon, 11 May 2009, Jean Pihet wrote:

> On Saturday 09 May 2009 00:43:43 Paul Walmsley wrote:
> > One possibility: perhaps the problem is with Beagle's pin mux settings.
> > You might want to boot with mem=128M and make sure
> > CONTROL_PADCONF_SAD2D_SBUSFLAG and CONTROL_PADCONF_SDRC_CKE1 are in mode 0
> > before suspend and after resume.
> Yes that definitely is the root cause. I should have checked this first ;-(
> The U-Boot change is committed, cf. 
> http://gitorious.org/u-boot-omap3/mainline/commit/c6f01ad390308800693c62dbdb096ab59e03630b
> and
> http://gitorious.org/u-boot-omap3/mainline/commit/4025cfbde3611b14c0d4831a5524e5e061128e30

Nice work!

Sounds like we should also patch mach-omap2/sdrc.c:omap2_sdrc_init() to 
warn if the sdrc_cke1 pin mux is wrong if a second struct omap_sdrc_params 
* is passed.  Probably board-omap3beagle.c should also remux the pad if 
it's wrong.  Otherwise there will be a lot of unhappy Rev C BeagleBoard 
users.

> I am looking at a fix for the SDRC setup with 2 CSes. I will propose the 
> changes asap.

Excellent, thanks Jean.


- Paul

[RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Jean Pihet]

[-- Attachment #1: Type: text/plain, Size: 2404 bytes --]

Hi Paul, Kevin,

Here is a patch for the SDRC 2nd CS support. It applies on top of the current 
pm branch.

I have some questions:
- Is it OK to copy the micron sdram params file to a new file with the 2 CSes 
params? One could use a unique file with #ifdef SDRC_SUPPORT_2_CSES.
- Does the RX51 board have 2 sdram parts? If so I need to update the board 
file as well.

Comments are welcome.

Regards,
Jean

From 517f52f4bef8225c5921b55ecd96eda2e0c4b697 Mon Sep 17 00:00:00 2001
From: Jean Pihet <jpihet@mvista.com>
Date: Tue, 26 May 2009 14:55:57 +0200
Subject: [PATCH] OMAP3: add support for 2 SDRAM chip selects

Some boards (Beagle Cx, Overo) have 2 SDRAM parts
connected to the SDRC.

This patch adds the following:
- ensure that the CKE signals mux settings are correct
- extend the omap_sdrc_params struct with the 2nd CS params
- add a new file for the micron sdram params for 2 CSes
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Thanks to Paul Walmsley and Kevin Hilman for the suggestions
and code reviews.

Tested on Beagleboard rev C2 and B5.

Signed-off-by: Jean Pihet <jpihet@mvista.com>

On Monday 11 May 2009 22:27:50 Paul Walmsley wrote:
> Hi Jean,
>
> On Mon, 11 May 2009, Jean Pihet wrote:
> > On Saturday 09 May 2009 00:43:43 Paul Walmsley wrote:
> > > One possibility: perhaps the problem is with Beagle's pin mux settings.
> > > You might want to boot with mem=128M and make sure
> > > CONTROL_PADCONF_SAD2D_SBUSFLAG and CONTROL_PADCONF_SDRC_CKE1 are in
> > > mode 0 before suspend and after resume.
> >
> > Yes that definitely is the root cause. I should have checked this first
> > ;-( The U-Boot change is committed, cf.
> > http://gitorious.org/u-boot-omap3/mainline/commit/c6f01ad390308800693c62d
> >bdb096ab59e03630b and
> > http://gitorious.org/u-boot-omap3/mainline/commit/4025cfbde3611b14c0d4831
> >a5524e5e061128e30
>
> Nice work!
>
> Sounds like we should also patch mach-omap2/sdrc.c:omap2_sdrc_init() to
> warn if the sdrc_cke1 pin mux is wrong if a second struct omap_sdrc_params
> * is passed.  Probably board-omap3beagle.c should also remux the pad if
> it's wrong.  Otherwise there will be a lot of unhappy Rev C BeagleBoard
> users.
>
> > I am looking at a fix for the SDRC setup with 2 CSes. I will propose the
> > changes asap.
>
> Excellent, thanks Jean.
>
>
> - Paul



[-- Attachment #2: 0001-OMAP3-add-support-for-2-SDRAM-chip-selects.patch --]
[-- Type: text/x-diff, Size: 25924 bytes --]

From 517f52f4bef8225c5921b55ecd96eda2e0c4b697 Mon Sep 17 00:00:00 2001
From: Jean Pihet <jpihet@mvista.com>
Date: Tue, 26 May 2009 14:55:57 +0200
Subject: [PATCH] OMAP3: add support for 2 SDRAM chip selects

Some boards (Beagle Cx, Overo) have 2 SDRAM parts
connected to the SDRC.

This patch adds the following:
- ensure that the CKE signals mux settings are correct
- extend the omap_sdrc_params struct with the 2nd CS params
- add a new file for the micron sdram params for 2 CSes
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Thanks to Paul Walmsley and Kevin Hilman for the suggestions
and code reviews.

Tested on Beagleboard rev C2 and B5.

Signed-off-by: Jean Pihet <jpihet@mvista.com>
---
 arch/arm/mach-omap2/board-omap3beagle.c            |    6 +-
 arch/arm/mach-omap2/board-overo.c                  |    6 +-
 arch/arm/mach-omap2/board-rx51-sdram.c             |    8 +-
 arch/arm/mach-omap2/clock34xx.c                    |   18 ++-
 arch/arm/mach-omap2/mux.c                          |    6 +
 .../mach-omap2/sdram-micron-mt46h32m32lf-6-2cses.h |   93 ++++++++++++++
 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h  |   60 +++++-----
 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |   40 +++---
 arch/arm/mach-omap2/sdrc.c                         |   15 ++-
 arch/arm/mach-omap2/sram34xx.S                     |  128 +++++++++++++++-----
 arch/arm/plat-omap/include/mach/mux.h              |    4 +
 arch/arm/plat-omap/include/mach/sdrc.h             |   23 +++--
 arch/arm/plat-omap/include/mach/sram.h             |   12 +-
 arch/arm/plat-omap/sram.c                          |   34 +++--
 14 files changed, 329 insertions(+), 124 deletions(-)
 create mode 100644 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6-2cses.h

diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7294dbf..7128213 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -110,7 +110,7 @@ static struct platform_device omap3beagle_nand_device = {
 	.resource	= &omap3beagle_nand_resource,
 };
 
-#include "sdram-micron-mt46h32m32lf-6.h"
+#include "sdram-micron-mt46h32m32lf-6-2cses.h"
 
 static struct omap_uart_config omap3_beagle_uart_config __initdata = {
 	.enabled_uarts	= ((1 << 0) | (1 << 1) | (1 << 2)),
@@ -441,6 +441,10 @@ static void __init omap3_beagle_init(void)
 	usb_musb_init();
 	usb_ehci_init();
 	omap3beagle_flash_init();
+
+	/* Ensure SDRC pins are mux'd for self-refresh */
+	omap_cfg_reg(H16_34XX_SDRC_CKE0);
+	omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 9eae608..a6ac353 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -47,7 +47,7 @@
 #include <mach/nand.h>
 #include <mach/usb.h>
 
-#include "sdram-micron-mt46h32m32lf-6.h"
+#include "sdram-micron-mt46h32m32lf-6-2cses.h"
 #include "twl4030-generic-scripts.h"
 #include "mmc-twl4030.h"
 
@@ -391,6 +391,10 @@ static void __init overo_init(void)
 	overo_init_smsc911x();
 	overo_ads7846_init();
 
+	/* Ensure SDRC pins are mux'd for self-refresh */
+	omap_cfg_reg(H16_34XX_SDRC_CKE0);
+	omap_cfg_reg(H17_34XX_SDRC_CKE1);
+
 	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
 			  "OVERO_GPIO_W2W_NRESET") == 0) &&
 	    (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c
index 32b5da4..2e37b0f 100644
--- a/arch/arm/mach-omap2/board-rx51-sdram.c
+++ b/arch/arm/mach-omap2/board-rx51-sdram.c
@@ -204,10 +204,10 @@ struct omap_sdrc_params *rx51_get_sdram_timings(void)
 	rfr_ctrl = l | 0x3; /* autorefresh, reload counter with 8xARCV */
 
 	rx51_sdrc_params[0].rate = 133333333;
-	rx51_sdrc_params[0].actim_ctrla = actim_ctrla;
-	rx51_sdrc_params[0].actim_ctrlb = actim_ctrlb;
-	rx51_sdrc_params[0].rfr_ctrl = rfr_ctrl;
-	rx51_sdrc_params[0].mr = 0x32;
+	rx51_sdrc_params[0].actim_ctrl_a_0 = actim_ctrla;
+	rx51_sdrc_params[0].actim_ctrl_b_0 = actim_ctrlb;
+	rx51_sdrc_params[0].rfr_ctrl_0 = rfr_ctrl;
+	rx51_sdrc_params[0].mr_0 = 0x32;
 
 	rx51_sdrc_params[1].rate = 0;
 
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 3cee6b4..a019711 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -518,12 +518,18 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
 	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 		 validrate);
-	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
-		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
-
-	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-				  sp->actim_ctrlb, new_div, unlock_dll, c,
-				  sp->mr, rate > clk->rate);
+	pr_debug("Clock: SDRC timing params used: "
+		 "CS0 %08x %08x %08x %08x, CS1 %08x %08x %08x %08x\n",
+		 sp->rfr_ctrl_0, sp->actim_ctrl_a_0,
+		 sp->actim_ctrl_b_0, sp->mr_0,
+		 sp->rfr_ctrl_1, sp->actim_ctrl_a_1,
+		 sp->actim_ctrl_b_1, sp->mr_1);
+
+	omap3_configure_core_dpll(new_div, unlock_dll, c, rate > clk->rate,
+				  sp->rfr_ctrl_0, sp->actim_ctrl_a_0,
+				  sp->actim_ctrl_b_0, sp->mr_0,
+				  sp->rfr_ctrl_1, sp->actim_ctrl_a_1,
+				  sp->actim_ctrl_b_1, sp->mr_1);
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc..43d6b92 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
 		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
 		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+
+/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
+		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
+		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
 };
 
 #define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6-2cses.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6-2cses.h
new file mode 100644
index 0000000..5b9be9e
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6-2cses.h
@@ -0,0 +1,93 @@
+/*
+ * SDRC register values for the Micron MT46H32M32LF-6
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
+#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
+
+#include <mach/sdrc.h>
+
+/* Micron MT46H32M32LF-6, using 2 parts on CS0 and CS1 */
+/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
+static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
+	[0] = {
+		.rate			= 166000000,
+		.actim_ctrl_a_0		= 0x9a9db4c6,
+		.actim_ctrl_b_0 	= 0x00011217,
+		.rfr_ctrl_0		= 0x0004dc01,
+		.mr_0			= 0x00000032,
+		.actim_ctrl_a_1		= 0x9a9db4c6,
+		.actim_ctrl_b_1 	= 0x00011217,
+		.rfr_ctrl_1		= 0x0004dc01,
+		.mr_1			= 0x00000032,
+	},
+	[1] = {
+		.rate			= 165941176,
+		.actim_ctrl_a_0		= 0x9a9db4c6,
+		.actim_ctrl_b_0		= 0x00011217,
+		.rfr_ctrl_0		= 0x0004dc01,
+		.mr_0			= 0x00000032,
+		.actim_ctrl_a_1		= 0x9a9db4c6,
+		.actim_ctrl_b_1		= 0x00011217,
+		.rfr_ctrl_1		= 0x0004dc01,
+		.mr_1			= 0x00000032,
+	},
+	[2] = {
+		.rate			= 133333333,
+		.actim_ctrl_a_0		= 0x7a19b485,
+		.actim_ctrl_b_0		= 0x00011213,
+		.rfr_ctrl_0		= 0x0003de01,
+		.mr_0			= 0x00000032,
+		.actim_ctrl_a_1		= 0x7a19b485,
+		.actim_ctrl_b_1		= 0x00011213,
+		.rfr_ctrl_1		= 0x0003de01,
+		.mr_1			= 0x00000032,
+	},
+	[3] = {
+		.rate			= 83000000,
+		.actim_ctrl_a_0		= 0x51512283,
+		.actim_ctrl_b_0		= 0x0001120c,
+		.rfr_ctrl_0		= 0x00025501,
+		.mr_0			= 0x00000032,
+		.actim_ctrl_a_1		= 0x51512283,
+		.actim_ctrl_b_1		= 0x0001120c,
+		.rfr_ctrl_1		= 0x00025501,
+		.mr_1			= 0x00000032,
+	},
+	[4] = {
+		.rate			= 82970588,
+		.actim_ctrl_a_0		= 0x51512283,
+		.actim_ctrl_b_0		= 0x0001120c,
+		.rfr_ctrl_0		= 0x00025501,
+		.mr_0			= 0x00000032,
+		.actim_ctrl_a_1		= 0x51512283,
+		.actim_ctrl_b_1		= 0x0001120c,
+		.rfr_ctrl_1		= 0x00025501,
+		.mr_1			= 0x00000032,
+	},
+	[5] = {
+		.rate			= 66666666,
+		.actim_ctrl_a_0		= 0x410d2243,
+		.actim_ctrl_b_0		= 0x0001120a,
+		.rfr_ctrl_0		= 0x0001d601,
+		.mr_0			= 0x00000032,
+		.actim_ctrl_a_1		= 0x410d2243,
+		.actim_ctrl_b_1		= 0x0001120a,
+		.rfr_ctrl_1		= 0x0001d601,
+		.mr_1			= 0x00000032,
+	},
+	[6] = {
+		.rate	     = 0
+	},
+};
+
+#endif
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
index b6c1db3..3b0dce4 100644
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -20,46 +20,46 @@
 /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
 static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
 	[0] = {
-		.rate	     = 166000000,
-		.actim_ctrla = 0x9a9db4c6,
-		.actim_ctrlb = 0x00011217,
-		.rfr_ctrl    = 0x0004dc01,
-		.mr	     = 0x00000032,
+		.rate		= 166000000,
+		.actim_ctrl_a_0	= 0x9a9db4c6,
+		.actim_ctrl_b_0	= 0x00011217,
+		.rfr_ctrl_0	= 0x0004dc01,
+		.mr_0		= 0x00000032,
 	},
 	[1] = {
-		.rate	     = 165941176,
-		.actim_ctrla = 0x9a9db4c6,
-		.actim_ctrlb = 0x00011217,
-		.rfr_ctrl    = 0x0004dc01,
-		.mr	     = 0x00000032,
+		.rate		= 165941176,
+		.actim_ctrl_a_0	= 0x9a9db4c6,
+		.actim_ctrl_b_0	= 0x00011217,
+		.rfr_ctrl_0	= 0x0004dc01,
+		.mr_0		= 0x00000032,
 	},
 	[2] = {
-		.rate	     = 133333333,
-		.actim_ctrla = 0x7a19b485,
-		.actim_ctrlb = 0x00011213,
-		.rfr_ctrl    = 0x0003de01,
-		.mr	     = 0x00000032,
+		.rate		= 133333333,
+		.actim_ctrl_a_0	= 0x7a19b485,
+		.actim_ctrl_b_0	= 0x00011213,
+		.rfr_ctrl_0	= 0x0003de01,
+		.mr_0		= 0x00000032,
 	},
 	[3] = {
-		.rate	     = 83000000,
-		.actim_ctrla = 0x51512283,
-		.actim_ctrlb = 0x0001120c,
-		.rfr_ctrl    = 0x00025501,
-		.mr	     = 0x00000032,
+		.rate		= 83000000,
+		.actim_ctrl_a_0	= 0x51512283,
+		.actim_ctrl_b_0	= 0x0001120c,
+		.rfr_ctrl_0	= 0x00025501,
+		.mr_0		= 0x00000032,
 	},
 	[4] = {
-		.rate	     = 82970588,
-		.actim_ctrla = 0x51512283,
-		.actim_ctrlb = 0x0001120c,
-		.rfr_ctrl    = 0x00025501,
-		.mr	     = 0x00000032,
+		.rate		= 82970588,
+		.actim_ctrl_a_0	= 0x51512283,
+		.actim_ctrl_b_0	= 0x0001120c,
+		.rfr_ctrl_0	= 0x00025501,
+		.mr_0		= 0x00000032,
 	},
 	[5] = {
-		.rate	     = 66666666,
-		.actim_ctrla = 0x410d2243,
-		.actim_ctrlb = 0x0001120a,
-		.rfr_ctrl    = 0x0001d601,
-		.mr	     = 0x00000032,
+		.rate		= 66666666,
+		.actim_ctrl_a_0	= 0x410d2243,
+		.actim_ctrl_b_0	= 0x0001120a,
+		.rfr_ctrl_0	= 0x0001d601,
+		.mr_0		= 0x00000032,
 	},
 	[6] = {
 		.rate	     = 0
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
index 74a92c8..b637460 100644
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -20,32 +20,32 @@
 /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
 static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
 	[0] = {
-		.rate	     = 165941176,
-		.actim_ctrla = 0x629db4c6,
-		.actim_ctrlb = 0x00012214,
-		.rfr_ctrl    = 0x0004dc01,
-		.mr	     = 0x00000032,
+		.rate		= 165941176,
+		.actim_ctrl_a_0	= 0x629db4c6,
+		.actim_ctrl_b_0	= 0x00012214,
+		.rfr_ctrl_0	= 0x0004dc01,
+		.mr_0		= 0x00000032,
 	},
 	[1] = {
-		.rate	     = 133333333,
-		.actim_ctrla = 0x5219b485,
-		.actim_ctrlb = 0x00012210,
-		.rfr_ctrl    = 0x0003de01,
-		.mr	     = 0x00000032,
+		.rate		= 133333333,
+		.actim_ctrl_a_0	= 0x5219b485,
+		.actim_ctrl_b_0	= 0x00012210,
+		.rfr_ctrl_0	= 0x0003de01,
+		.mr_0		= 0x00000032,
 	},
 	[2] = {
-		.rate	     = 82970588,
-		.actim_ctrla = 0x31512283,
-		.actim_ctrlb = 0x0001220a,
-		.rfr_ctrl    = 0x00025501,
-		.mr	     = 0x00000022,
+		.rate		= 82970588,
+		.actim_ctrl_a_0	= 0x31512283,
+		.actim_ctrl_b_0	= 0x0001220a,
+		.rfr_ctrl_0	= 0x00025501,
+		.mr_0		= 0x00000022,
 	},
 	[3] = {
-		.rate	     = 66666666,
-		.actim_ctrla = 0x290d2243,
-		.actim_ctrlb = 0x00012208,
-		.rfr_ctrl    = 0x0001d601,
-		.mr	     = 0x00000022,
+		.rate		= 66666666,
+		.actim_ctrl_a_0	= 0x290d2243,
+		.actim_ctrl_b_0	= 0x00012208,
+		.rfr_ctrl_0	= 0x0001d601,
+		.mr_0		= 0x00000022,
 	},
 	[4] = {
 		.rate	     = 0
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index c832d83..072dcc9 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -72,14 +72,19 @@ void omap2_sms_restore_context(void)
  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  * @r: SDRC clock rate (in Hz)
  *
- * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
- * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
- * SDRC clock rate 'r'.  These parameters control various timing
+ * Return pre-calculated values for the SDRC_ACTIM_CTRL_A_[01],
+ * SDRC_ACTIM_CTRL_B_[01], SDRC_RFR_CTRL_[01], and SDRC_MR_[01] registers,
+ * for a given SDRC clock rate 'r'.
+ * These parameters control various timing
  * delays in the SDRAM controller that are expressed in terms of the
  * number of SDRC clock cycles to wait; hence the clock rate
  * dependency. Note that sdrc_init_params must be sorted rate
- * descending.  Also assumes that both chip-selects use the same
- * timing parameters.  Returns a struct omap_sdrc_params * upon
+ * descending.
+ *
+ * The omap_sdrc_params struct supports different timing parameters
+ * for 2 chip selects.
+ *
+ * Returns a struct omap_sdrc_params * upon
  * success, or NULL upon failure.
  */
 struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index f41f8d9..ccfc008 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -36,7 +36,7 @@
 
 	.text
 
-/* r4 parameters */
+/* r1 parameters */
 #define SDRC_NO_UNLOCK_DLL		0x0
 #define SDRC_UNLOCK_DLL			0x1
 
@@ -71,40 +71,65 @@
 
 /*
  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
- * r0 = new SDRC_RFR_CTRL register contents
- * r1 = new SDRC_ACTIM_CTRLA register contents
- * r2 = new SDRC_ACTIM_CTRLB register contents
- * r3 = new M2 divider setting (only 1 and 2 supported right now)
- * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
+ *
+ * Params passed in registers:
+ *  r0 = new M2 divider setting (only 1 and 2 supported right now)
+ *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  *      SDRC rates < 83MHz
- * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
- * r6 = new SDRC_MR_0 register value
- * r7 = increasing SDRC rate? (1 = yes, 0 = no)
+ *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
  *
+ * Params passed via the stack. Those will be copied in SRAM before use
+ *  by the code in SRAM (SDRAM is not accessible during SDRC
+ *  reconfiguration):
+ *  new SDRC_RFR_CTRL_0 register contents
+ *  new SDRC_ACTIM_CTRL_A_0 register contents
+ *  new SDRC_ACTIM_CTRL_B_0 register contents
+ *  new SDRC_MR_0 register value
+ *  new SDRC_RFR_CTRL_1 register contents
+ *  new SDRC_ACTIM_CTRL_A_1 register contents
+ *  new SDRC_ACTIM_CTRL_B_1 register contents
+ *  new SDRC_MR_1 register value
  */
 ENTRY(omap3_sram_configure_core_dpll)
 	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
-	ldr	r4, [sp, #52]		@ pull extra args off the stack
-	ldr	r5, [sp, #56]		@ load extra args from the stack
-	ldr	r6, [sp, #60]		@ load extra args from the stack
-	ldr	r7, [sp, #64]		@ load extra args from the stack
+
+					@ pull the extra args off the stack
+					@  and store them in SRAM
+	ldr	r4, [sp, #52]
+	str     r4, omap_sdrc_rfr_ctrl_0_val
+	ldr	r4, [sp, #56]
+	str     r4, omap_sdrc_actim_ctrl_a_0_val
+	ldr	r4, [sp, #60]
+	str     r4, omap_sdrc_actim_ctrl_b_0_val
+	ldr	r4, [sp, #64]
+	str     r4, omap_sdrc_mr_0_val
+	ldr	r4, [sp, #68]
+	str     r4, omap_sdrc_rfr_ctrl_1_val
+	ldr	r4, [sp, #72]
+	str     r4, omap_sdrc_actim_ctrl_a_1_val
+	ldr	r4, [sp, #76]
+	str     r4, omap_sdrc_actim_ctrl_b_1_val
+	ldr	r4, [sp, #80]
+	str     r4, omap_sdrc_mr_1_val
 	dsb				@ flush buffered writes to interconnect
-	cmp	r7, #1			@ if increasing SDRC clk rate,
+
+	cmp	r3, #1			@ if increasing SDRC clk rate,
 	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
-	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
+	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
 	bleq	unlock_dll
 	blne	lock_dll
 	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
 	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
 	bl	enable_sdrc		@ take SDRC out of idle
-	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
+	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
 	bleq	wait_dll_unlock
 	blne	wait_dll_lock
-	cmp	r7, #1			@ if increasing SDRC clk rate,
+	cmp	r3, #1			@ if increasing SDRC clk rate,
 	beq	return_to_sdram		@ return to SDRAM code, otherwise,
 	bl	configure_sdrc		@ reprogram SDRC regs now
-	mov	r12, r5
+	mov	r12, r2
 	bl	wait_clk_stable		@ wait for SDRC to stabilize
 return_to_sdram:
 	isb				@ prevent speculative exec past here
@@ -149,7 +174,7 @@ configure_core_dpll:
 	ldr	r12, [r11]
 	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
 	and	r12, r12, r10
-	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
+	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
 	str	r12, [r11]
 	ldr	r12, [r11]		@ posted-write barrier for CM
 	bx	lr
@@ -187,15 +212,31 @@ wait_dll_unlock:
 	bne	wait_dll_unlock
 	bx	lr
 configure_sdrc:
-	ldr	r11, omap3_sdrc_rfr_ctrl
-	str	r0, [r11]
-	ldr	r11, omap3_sdrc_actim_ctrla
-	str	r1, [r11]
-	ldr	r11, omap3_sdrc_actim_ctrlb
-	str	r2, [r11]
+	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
+	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
+	str	r12, [r11]			@ store
+	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
+	ldr	r11, omap3_sdrc_actim_ctrl_a_0
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
+	ldr	r11, omap3_sdrc_actim_ctrl_b_0
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_mr_0_val
 	ldr	r11, omap3_sdrc_mr_0
-	str	r6, [r11]
-	ldr	r6, [r11]		@ posted-write barrier for SDRC
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_rfr_ctrl_1_val
+	ldr	r11, omap3_sdrc_rfr_ctrl_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
+	ldr	r11, omap3_sdrc_actim_ctrl_a_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
+	ldr	r11, omap3_sdrc_actim_ctrl_b_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_mr_1_val
+	ldr	r11, omap3_sdrc_mr_1
+	str	r12, [r11]
+	ldr	r12, [r11]		@ posted-write barrier for SDRC
 	bx	lr
 
 omap3_sdrc_power:
@@ -206,14 +247,40 @@ omap3_cm_idlest1_core:
 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 omap3_cm_iclken1_core:
 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
-omap3_sdrc_rfr_ctrl:
+
+omap3_sdrc_rfr_ctrl_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap3_sdrc_actim_ctrla:
+omap3_sdrc_rfr_ctrl_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
+omap3_sdrc_actim_ctrl_a_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
-omap3_sdrc_actim_ctrlb:
+omap3_sdrc_actim_ctrl_a_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
+omap3_sdrc_actim_ctrl_b_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_actim_ctrl_b_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 omap3_sdrc_mr_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
+omap3_sdrc_mr_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
+omap_sdrc_rfr_ctrl_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_rfr_ctrl_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_mr_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_mr_1_val:
+	.word 0xDEADBEEF
+
 omap3_sdrc_dlla_status:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:
@@ -223,3 +290,4 @@ core_m2_mask_val:
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
 	.word	. - omap3_sram_configure_core_dpll
+
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index f7e298a..7368aba 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -803,6 +803,10 @@ enum omap34xx_index {
 	AE5_34XX_GPIO143,
 	H19_34XX_GPIO164_OUT,
 	J25_34XX_GPIO170,
+
+	/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+	H16_34XX_SDRC_CKE0,
+	H17_34XX_SDRC_CKE1,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index a678bc8..e14204c 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -94,22 +94,29 @@
 /**
  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
  * @rate: SDRC clock rate (in Hz)
- * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
- * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
- * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
- * @mr: Value to program to SDRC_MR for this rate
+ * @actim_ctrl_a_[01]: Value to program to SDRC_ACTIM_CTRL_A_[01] for this rate
+ * @actim_ctrl_b_[01]: Value to program to SDRC_ACTIM_CTRL_B_[01] for this rate
+ * @rfr_ctrl_[01]: Value to program to SDRC_RFR_CTRL_[01] for this rate
+ * @mr_[01]: Value to program to SDRC_MR_[01] for this rate
  *
  * This structure holds a pre-computed set of register values for the
  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
  * intended to be pre-computed and specified in an array in the board-*.c
  * files.  The structure is keyed off the 'rate' field.
+ *
+ * The struct supports up to 2 CSes. The fields *_0 are used for the 1st
+ * CS, the fields *_1 are used for the 2nd one.
  */
 struct omap_sdrc_params {
 	unsigned long rate;
-	u32 actim_ctrla;
-	u32 actim_ctrlb;
-	u32 rfr_ctrl;
-	u32 mr;
+	u32 actim_ctrl_a_0;
+	u32 actim_ctrl_b_0;
+	u32 rfr_ctrl_0;
+	u32 mr_0;
+	u32 actim_ctrl_a_1;
+	u32 actim_ctrl_b_1;
+	u32 rfr_ctrl_1;
+	u32 mr_1;
 };
 
 void omap2_sms_save_context(void);
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index ad0a600..2194b04 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
 				      u32 mem_type);
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 
-extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
-				     u32 sdrc_actim_ctrla,
-				     u32 sdrc_actim_ctrlb, u32 m2,
-				     u32 unlock_dll, u32 f, u32 sdrc_mr,
-				     u32 inc);
+extern u32 omap3_configure_core_dpll(
+			u32 m2, u32 unlock_dll, u32 f, u32 inc,
+			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
 extern void omap3_sram_restore_context(void);
 
 /* Do not use these */
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a2e60e7..517f45b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
 
 #ifdef CONFIG_ARCH_OMAP3
 
-static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
-					      u32 sdrc_actim_ctrla,
-					      u32 sdrc_actim_ctrlb,
-					      u32 m2, u32 unlock_dll,
-					      u32 f, u32 sdrc_mr, u32 inc);
-u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-			      u32 f, u32 sdrc_mr, u32 inc)
- {
+static u32 (*_omap3_sram_configure_core_dpll)(
+				u32 m2, u32 unlock_dll, u32 f, u32 inc,
+				u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+				u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+				u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+				u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+			      u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+			      u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+			      u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+			      u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
+{
 	if (!_omap3_sram_configure_core_dpll)
 		omap_sram_error();
 
-	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
-					       sdrc_actim_ctrla,
-					       sdrc_actim_ctrlb, m2,
-					       unlock_dll, f, sdrc_mr, inc);
- }
+	return _omap3_sram_configure_core_dpll(
+				m2, unlock_dll, f, inc,
+				sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+				sdrc_actim_ctrl_b_0, sdrc_mr_0,
+				sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+				sdrc_actim_ctrl_b_1, sdrc_mr_1);
+}
 
 #ifdef CONFIG_PM
 void omap3_sram_restore_context(void)
-- 
1.6.1.2.MVISTA.50.gdf8fd

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Paul Walmsley]

Hi Jean,

a minor request: it is easier to comment on these patches if they are 
included inline in the E-mail message, rather than attached.  That way 
code comments can be inlined in the reply.

On Tue, 26 May 2009, Jean Pihet wrote:

> Here is a patch for the SDRC 2nd CS support. It applies on top of the current 
> pm branch.

Thanks for doing this work.

> I have some questions:
> - Is it OK to copy the micron sdram params file to a new file with the 2 CSes 
> params? One could use a unique file with #ifdef SDRC_SUPPORT_2_CSES.

Is it possible for the SDRAM parameter files to remain unchanged, and to 
simply pass two struct omap_sdrc_params * to omap2_init_common_hw() and 
then to omap2_sdrc_init()?  Boards with only CS0 in use should pass NULL 
for the second omap_sdrc_params *.

So something like this (I realize the PM branch has additional parameters 
here also):

void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                                 struct omap_sdrc_params *sdrc_cs1)

Then:

void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                            struct omap_sdrc_params *sdrc_cs1)

I would prefer that approach.

It would also be good to avoid changing the SDRC CS1 parameters in the 
SRAM code if the board does not use CS1.  Maybe pass in a flag that 
indicates whether CS1 is in use, and if not, avoid programming those 
registers?  The (admittedly minor) overhead of loading the CS1 registers 
off the stack would be nice to avoid also.

> - Does the RX51 board have 2 sdram parts? If so I need to update the board 
> file as well.

Probably best if someone from Nokia handles this.


- Paul

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Jean Pihet]

Hi Paul,

OK I will rework the code and send a patch when done.

Regards,
Jean

On Wednesday 03 June 2009 01:40:13 Paul Walmsley wrote:
> Hi Jean,
>
> a minor request: it is easier to comment on these patches if they are
> included inline in the E-mail message, rather than attached.  That way
> code comments can be inlined in the reply.
>
> On Tue, 26 May 2009, Jean Pihet wrote:
> > Here is a patch for the SDRC 2nd CS support. It applies on top of the
> > current pm branch.
>
> Thanks for doing this work.
>
> > I have some questions:
> > - Is it OK to copy the micron sdram params file to a new file with the 2
> > CSes params? One could use a unique file with #ifdef SDRC_SUPPORT_2_CSES.
>
> Is it possible for the SDRAM parameter files to remain unchanged, and to
> simply pass two struct omap_sdrc_params * to omap2_init_common_hw() and
> then to omap2_sdrc_init()?  Boards with only CS0 in use should pass NULL
> for the second omap_sdrc_params *.
>
> So something like this (I realize the PM branch has additional parameters
> here also):
>
> void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
>                                  struct omap_sdrc_params *sdrc_cs1)
>
> Then:
>
> void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>                             struct omap_sdrc_params *sdrc_cs1)
>
> I would prefer that approach.
>
> It would also be good to avoid changing the SDRC CS1 parameters in the
> SRAM code if the board does not use CS1.  Maybe pass in a flag that
> indicates whether CS1 is in use, and if not, avoid programming those
> registers?  The (admittedly minor) overhead of loading the CS1 registers
> off the stack would be nice to avoid also.
>
> > - Does the RX51 board have 2 sdram parts? If so I need to update the
> > board file as well.
>
> Probably best if someone from Nokia handles this.
>
>
> - Paul

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Jean Pihet]

Hi Paul, Kevin,

Here is the new patch that includes all the remarks and suggestion. The 
description is here below.

Some notes:
- all calls to omap2_init_common_hw have been adapted in the board files. it 
looks like 2430SDP and Pandora board files are broken since they use only one 
param. Can that be checked on those boards?
- it is assumed that RX51 only uses 1 CS. Is that correct?

Can you review it and possibly merge?

Thanks & regards,
Jean

--
>From 097a640997b74638e0e7200ecd5834205204c956 Mon Sep 17 00:00:00 2001
From: Jean Pihet <jpihet@mvista.com>
Date: Fri, 5 Jun 2009 17:19:00 +0200
Subject: [PATCH] [PATCH] OMAP3: add support for 2 SDRAM chip selects

Some boards (Beagle Cx, Overo) have 2 SDRAM parts
connected to the SDRC.

This patch adds the following:
- ensure that the CKE signals mux settings are correct
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw. Only Beagle and Overo are using the 2 CS'es
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers

Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).

Thanks to Paul Walmsley and Kevin Hilman for the suggestions
and code reviews.

Signed-off-by: Jean Pihet <jpihet@mvista.com>
---
 arch/arm/mach-omap2/board-2430sdp.c      |    2 +-
 arch/arm/mach-omap2/board-3430sdp.c      |    6 +-
 arch/arm/mach-omap2/board-apollon.c      |    2 +-
 arch/arm/mach-omap2/board-generic.c      |    2 +-
 arch/arm/mach-omap2/board-h4.c           |    2 +-
 arch/arm/mach-omap2/board-ldp.c          |    2 +-
 arch/arm/mach-omap2/board-n800.c         |    2 +-
 arch/arm/mach-omap2/board-omap2evm.c     |    2 +-
 arch/arm/mach-omap2/board-omap3beagle.c  |   11 ++-
 arch/arm/mach-omap2/board-omap3evm.c     |    6 +-
 arch/arm/mach-omap2/board-omap3pandora.c |    3 +-
 arch/arm/mach-omap2/board-overo.c        |    8 ++-
 arch/arm/mach-omap2/board-rx51.c         |    6 +-
 arch/arm/mach-omap2/clock34xx.c          |   37 ++++++--
 arch/arm/mach-omap2/io.c                 |    5 +-
 arch/arm/mach-omap2/mux.c                |    6 ++
 arch/arm/mach-omap2/sdrc.c               |   63 +++++++++-----
 arch/arm/mach-omap2/sram34xx.S           |  137 
+++++++++++++++++++++++-------
 arch/arm/plat-omap/include/mach/io.h     |    3 +-
 arch/arm/plat-omap/include/mach/mux.h    |    4 +
 arch/arm/plat-omap/include/mach/sdrc.h   |    8 +-
 arch/arm/plat-omap/include/mach/sram.h   |   23 +++--
 arch/arm/plat-omap/sram.c                |   34 +++++---
 23 files changed, 266 insertions(+), 108 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c 
b/arch/arm/mach-omap2/board-2430sdp.c
index aa5df72..4cb7bc5 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -322,7 +322,7 @@ out:
 
 static void __init omap_2430sdp_init_irq(void)
 {
-	omap2_init_common_hw(NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	sdp2430_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-3430sdp.c 
b/arch/arm/mach-omap2/board-3430sdp.c
index 195b749..24e2728 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -302,8 +302,10 @@ static inline void __init sdp3430_init_smc91x(void)
 
 static void __init omap_3430sdp_init_irq(void)
 {
-	omap2_init_common_hw(hyb18m512160af6_sdrc_params, omap3_mpu_rate_table,
-			     omap3_dsp_rate_table, omap3_l3_rate_table);
+	omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL,
+			     omap3_mpu_rate_table,
+			     omap3_dsp_rate_table,
+			     omap3_l3_rate_table);
 	omap_init_irq();
 	omap_gpio_init();
 	sdp3430_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-apollon.c 
b/arch/arm/mach-omap2/board-apollon.c
index 2e24812..2dd1350 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -323,7 +323,7 @@ out:
 
 static void __init omap_apollon_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c 
b/arch/arm/mach-omap2/board-generic.c
index be763a9..763329b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
 
 static void __init omap_generic_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8f54939..17c3599 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -348,7 +348,7 @@ static void __init h4_init_flash(void)
 
 static void __init omap_h4_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 9f41dc9..b012806 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -344,7 +344,7 @@ static inline void __init ldp_init_smc911x(void)
 
 static void __init omap_ldp_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	ldp_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-n800.c 
b/arch/arm/mach-omap2/board-n800.c
index ac7cf3f..ad53f4a 100644
--- a/arch/arm/mach-omap2/board-n800.c
+++ b/arch/arm/mach-omap2/board-n800.c
@@ -127,7 +127,7 @@ static struct lm8323_platform_data lm8323_pdata = {
 
 void __init nokia_n800_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 
diff --git a/arch/arm/mach-omap2/board-omap2evm.c 
b/arch/arm/mach-omap2/board-omap2evm.c
index 4fac1be..56a26d4 100644
--- a/arch/arm/mach-omap2/board-omap2evm.c
+++ b/arch/arm/mach-omap2/board-omap2evm.c
@@ -276,7 +276,7 @@ static struct twl4030_keypad_data omap2evm_kp_data = {
 
 static void __init omap2_evm_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	omap2evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c 
b/arch/arm/mach-omap2/board-omap3beagle.c
index 7294dbf..872beb6 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -312,8 +312,11 @@ static int __init omap3_beagle_i2c_init(void)
 
 static void __init omap3_beagle_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
-			     omap3_dsp_rate_table, omap3_l3_rate_table);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+			     mt46h32m32lf6_sdrc_params,
+			     omap3_mpu_rate_table,
+			     omap3_dsp_rate_table,
+			     omap3_l3_rate_table);
 	omap_init_irq();
 	omap_gpio_init();
 }
@@ -441,6 +444,10 @@ static void __init omap3_beagle_init(void)
 	usb_musb_init();
 	usb_ehci_init();
 	omap3beagle_flash_init();
+
+	/* Ensure SDRC pins are mux'd for self-refresh */
+	omap_cfg_reg(H16_34XX_SDRC_CKE0);
+	omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c 
b/arch/arm/mach-omap2/board-omap3evm.c
index f017f0d..3b9c96a 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -276,8 +276,10 @@ struct spi_board_info omap3evm_spi_board_info[] = {
 
 static void __init omap3_evm_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
-	                     omap3_dsp_rate_table, omap3_l3_rate_table);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
+			     omap3_mpu_rate_table,
+			     omap3_dsp_rate_table,
+			     omap3_l3_rate_table);
 	omap_init_irq();
 	omap_gpio_init();
 	omap3evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c 
b/arch/arm/mach-omap2/board-omap3pandora.c
index c67f62f..05ab99e 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -220,7 +220,8 @@ static int __init omap3pandora_i2c_init(void)
 
 static void __init omap3pandora_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
+			     NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/board-overo.c 
b/arch/arm/mach-omap2/board-overo.c
index 9eae608..2c6d2c5 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -355,7 +355,9 @@ static int __init overo_i2c_init(void)
 
 static void __init overo_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL, NULL, NULL);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+			     mt46h32m32lf6_sdrc_params,
+			     NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 }
@@ -391,6 +393,10 @@ static void __init overo_init(void)
 	overo_init_smsc911x();
 	overo_ads7846_init();
 
+	/* Ensure SDRC pins are mux'd for self-refresh */
+	omap_cfg_reg(H16_34XX_SDRC_CKE0);
+	omap_cfg_reg(H17_34XX_SDRC_CKE1);
+
 	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
 			  "OVERO_GPIO_W2W_NRESET") == 0) &&
 	    (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
diff --git a/arch/arm/mach-omap2/board-rx51.c 
b/arch/arm/mach-omap2/board-rx51.c
index 09035b0..d48459f 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -64,8 +64,10 @@ static struct omap_board_config_kernel rx51_config[] = {
 
 static void __init rx51_init_irq(void)
 {
-	omap2_init_common_hw(rx51_get_sdram_timings(), omap3_mpu_rate_table,
-			     omap3_dsp_rate_table, omap3_l3_rate_table);
+	omap2_init_common_hw(rx51_get_sdram_timings(), NULL,
+			     omap3_mpu_rate_table,
+			     omap3_dsp_rate_table,
+			     omap3_l3_rate_table);
 	omap_init_irq();
 	omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 3cee6b4..f262787 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -478,7 +478,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
unsigned long rate)
 	u32 unlock_dll = 0;
 	u32 c;
 	unsigned long validrate, sdrcrate, mpurate;
-	struct omap_sdrc_params *sp;
+	struct omap_sdrc_params *sdrc_cs0;
+	struct omap_sdrc_params *sdrc_cs1;
+	int ret;
 
 	if (!clk || !rate)
 		return -EINVAL;
@@ -496,8 +498,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
unsigned long rate)
 	else
 		sdrcrate >>= ((clk->rate / rate) >> 1);
 
-	sp = omap2_sdrc_get_params(sdrcrate);
-	if (!sp)
+	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
+	if (ret)
 		return -EINVAL;
 
 	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
@@ -518,12 +520,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
unsigned long rate)
 
 	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 		 validrate);
-	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
-		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
-
-	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-				  sp->actim_ctrlb, new_div, unlock_dll, c,
-				  sp->mr, rate > clk->rate);
+	pr_debug("clock: SDRC CS0 timing params used:"
+		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
+	if (sdrc_cs1)
+		pr_debug("clock: SDRC CS1 timing params used: "
+		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+		 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+		 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+
+	if (sdrc_cs1)
+		omap3_configure_core_dpll(
+				  new_div, unlock_dll, c, rate > clk->rate,
+				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+	else
+		omap3_configure_core_dpll(
+				  new_div, unlock_dll, c, rate > clk->rate,
+				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+				  0, 0, 0, 0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 6fb6c29..aa000b4 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -231,7 +231,8 @@ static int __init _omap2_init_reprogram_sdrc(void)
 	return v;
 }
 
-void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
+void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+				 struct omap_sdrc_params *sdrc_cs1,
 				 struct omap_opp *mpu_opps,
 				 struct omap_opp *dsp_opps,
 				 struct omap_opp *l3_opps)
@@ -244,7 +245,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params 
*sp,
 	omapdev_init(omapdevs);
 	omap2_clk_init();
 	omap_pm_if_init();
-	omap2_sdrc_init(sp);
+	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
 
 	_omap2_init_reprogram_sdrc();
 
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc..43d6b92 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
 		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
 		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+
+/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
+		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
+		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
 };
 
 #define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index c832d83..b42f5ae 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -32,7 +32,7 @@
 #include <mach/sdrc.h>
 #include "sdrc.h"
 
-static struct omap_sdrc_params *sdrc_init_params;
+static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
 
 void __iomem *omap2_sdrc_base;
 void __iomem *omap2_sms_base;
@@ -71,33 +71,49 @@ void omap2_sms_restore_context(void)
 /**
  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  * @r: SDRC clock rate (in Hz)
+ * @sdrc_cs0: chip select 0 ram timings **
+ * @sdrc_cs1: chip select 1 ram timings **
  *
  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
- * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
- * SDRC clock rate 'r'.  These parameters control various timing
- * delays in the SDRAM controller that are expressed in terms of the
- * number of SDRC clock cycles to wait; hence the clock rate
- * dependency. Note that sdrc_init_params must be sorted rate
- * descending.  Also assumes that both chip-selects use the same
- * timing parameters.  Returns a struct omap_sdrc_params * upon
- * success, or NULL upon failure.
+ *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
+ *  structs,for a given SDRC clock rate 'r'.
+ * These parameters control various timing delays in the SDRAM controller
+ *  that are expressed in terms of the number of SDRC clock cycles to
+ *  wait; hence the clock rate dependency.
+ *
+ * Supports 2 different timing parameters for both chip selects.
+ *
+ * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
+ * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
+ *  as sdrc_init_params_cs_0.
+ *
+ * Fills in the struct omap_sdrc_params * for each chip select.
+ * Returns 0 upon success or -1 upon failure.
  */
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
+int omap2_sdrc_get_params(unsigned long r,
+			  struct omap_sdrc_params **sdrc_cs0,
+			  struct omap_sdrc_params **sdrc_cs1)
 {
-	struct omap_sdrc_params *sp;
+	struct omap_sdrc_params *sp0, *sp1;
 
-	if (!sdrc_init_params)
-		return NULL;
+	if (!sdrc_init_params_cs0)
+		return -1;
 
-	sp = sdrc_init_params;
+	sp0 = sdrc_init_params_cs0;
+	sp1 = sdrc_init_params_cs1;
 
-	while (sp->rate && sp->rate != r)
-		sp++;
+	while (sp0->rate && sp0->rate != r) {
+		sp0++;
+		if (sdrc_init_params_cs1)
+			sp1++;
+	}
 
-	if (!sp->rate)
-		return NULL;
+	if (!sp0->rate)
+		return -1;
 
-	return sp;
+	*sdrc_cs0 = sp0;
+	*sdrc_cs1 = sp1;
+	return 0;
 }
 
 
@@ -109,13 +125,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals 
*omap2_globals)
 
 /**
  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
- * @sp: pointer to a null-terminated list of struct omap_sdrc_params
+ * @sdrc_cs[01]: pointers to a null-terminated list of struct 
omap_sdrc_params
+ *  Support for 2 chip selects timings
  *
  * Turn on smart idle modes for SDRAM scheduler and controller.
  * Program a known-good configuration for the SDRC to deal with buggy
  * bootloaders.
  */
-void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+			    struct omap_sdrc_params *sdrc_cs1)
 {
 	u32 l;
 
@@ -129,7 +147,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
 	l |= (0x2 << 3);
 	sdrc_write_reg(l, SDRC_SYSCONFIG);
 
-	sdrc_init_params = sp;
+	sdrc_init_params_cs0 = sdrc_cs0;
+	sdrc_init_params_cs1 = sdrc_cs1;
 
 	/* XXX Enable SRFRONIDLEREQ here also? */
 	l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index f41f8d9..3aef744 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -36,7 +36,7 @@
 
 	.text
 
-/* r4 parameters */
+/* r1 parameters */
 #define SDRC_NO_UNLOCK_DLL		0x0
 #define SDRC_UNLOCK_DLL			0x1
 
@@ -71,40 +71,71 @@
 
 /*
  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
- * r0 = new SDRC_RFR_CTRL register contents
- * r1 = new SDRC_ACTIM_CTRLA register contents
- * r2 = new SDRC_ACTIM_CTRLB register contents
- * r3 = new M2 divider setting (only 1 and 2 supported right now)
- * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
+ *
+ * Params passed in registers:
+ *  r0 = new M2 divider setting (only 1 and 2 supported right now)
+ *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  *      SDRC rates < 83MHz
- * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
- * r6 = new SDRC_MR_0 register value
- * r7 = increasing SDRC rate? (1 = yes, 0 = no)
+ *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
+ *
+ * Params passed via the stack. The needed params will be copied in SRAM
+ *  before use by the code in SRAM (SDRAM is not accessible during SDRC
+ *  reconfiguration):
+ *  new SDRC_RFR_CTRL_0 register contents
+ *  new SDRC_ACTIM_CTRL_A_0 register contents
+ *  new SDRC_ACTIM_CTRL_B_0 register contents
+ *  new SDRC_MR_0 register value
+ *  new SDRC_RFR_CTRL_1 register contents
+ *  new SDRC_ACTIM_CTRL_A_1 register contents
+ *  new SDRC_ACTIM_CTRL_B_1 register contents
+ *  new SDRC_MR_1 register value
  *
+ * If the param SDRC_RFR_CTRL_1 is 0, the parameters
+ *  are not programmed into the SDRC CS1 registers
  */
 ENTRY(omap3_sram_configure_core_dpll)
 	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
-	ldr	r4, [sp, #52]		@ pull extra args off the stack
-	ldr	r5, [sp, #56]		@ load extra args from the stack
-	ldr	r6, [sp, #60]		@ load extra args from the stack
-	ldr	r7, [sp, #64]		@ load extra args from the stack
+
+					@ pull the extra args off the stack
+					@  and store them in SRAM
+	ldr	r4, [sp, #52]
+	str     r4, omap_sdrc_rfr_ctrl_0_val
+	ldr	r4, [sp, #56]
+	str     r4, omap_sdrc_actim_ctrl_a_0_val
+	ldr	r4, [sp, #60]
+	str     r4, omap_sdrc_actim_ctrl_b_0_val
+	ldr	r4, [sp, #64]
+	str     r4, omap_sdrc_mr_0_val
+	ldr	r4, [sp, #68]
+	str     r4, omap_sdrc_rfr_ctrl_1_val
+	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
+	beq	skip_cs1_params		@  do not use cs1 params
+	ldr	r4, [sp, #72]
+	str     r4, omap_sdrc_actim_ctrl_a_1_val
+	ldr	r4, [sp, #76]
+	str     r4, omap_sdrc_actim_ctrl_b_1_val
+	ldr	r4, [sp, #80]
+	str     r4, omap_sdrc_mr_1_val
+skip_cs1_params:
 	dsb				@ flush buffered writes to interconnect
-	cmp	r7, #1			@ if increasing SDRC clk rate,
+
+	cmp	r3, #1			@ if increasing SDRC clk rate,
 	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
-	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
+	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
 	bleq	unlock_dll
 	blne	lock_dll
 	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
 	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
 	bl	enable_sdrc		@ take SDRC out of idle
-	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
+	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
 	bleq	wait_dll_unlock
 	blne	wait_dll_lock
-	cmp	r7, #1			@ if increasing SDRC clk rate,
+	cmp	r3, #1			@ if increasing SDRC clk rate,
 	beq	return_to_sdram		@ return to SDRAM code, otherwise,
 	bl	configure_sdrc		@ reprogram SDRC regs now
-	mov	r12, r5
+	mov	r12, r2
 	bl	wait_clk_stable		@ wait for SDRC to stabilize
 return_to_sdram:
 	isb				@ prevent speculative exec past here
@@ -149,7 +180,7 @@ configure_core_dpll:
 	ldr	r12, [r11]
 	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
 	and	r12, r12, r10
-	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
+	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
 	str	r12, [r11]
 	ldr	r12, [r11]		@ posted-write barrier for CM
 	bx	lr
@@ -187,15 +218,34 @@ wait_dll_unlock:
 	bne	wait_dll_unlock
 	bx	lr
 configure_sdrc:
-	ldr	r11, omap3_sdrc_rfr_ctrl
-	str	r0, [r11]
-	ldr	r11, omap3_sdrc_actim_ctrla
-	str	r1, [r11]
-	ldr	r11, omap3_sdrc_actim_ctrlb
-	str	r2, [r11]
+	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
+	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
+	str	r12, [r11]			@ store
+	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
+	ldr	r11, omap3_sdrc_actim_ctrl_a_0
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
+	ldr	r11, omap3_sdrc_actim_ctrl_b_0
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_mr_0_val
 	ldr	r11, omap3_sdrc_mr_0
-	str	r6, [r11]
-	ldr	r6, [r11]		@ posted-write barrier for SDRC
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_rfr_ctrl_1_val
+	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
+	beq	skip_cs1_prog		@  do not program cs1 params
+	ldr	r11, omap3_sdrc_rfr_ctrl_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
+	ldr	r11, omap3_sdrc_actim_ctrl_a_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
+	ldr	r11, omap3_sdrc_actim_ctrl_b_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_mr_1_val
+	ldr	r11, omap3_sdrc_mr_1
+	str	r12, [r11]
+skip_cs1_prog:
+	ldr	r12, [r11]		@ posted-write barrier for SDRC
 	bx	lr
 
 omap3_sdrc_power:
@@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 omap3_cm_iclken1_core:
 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
-omap3_sdrc_rfr_ctrl:
+
+omap3_sdrc_rfr_ctrl_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap3_sdrc_actim_ctrla:
+omap3_sdrc_rfr_ctrl_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
+omap3_sdrc_actim_ctrl_a_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
-omap3_sdrc_actim_ctrlb:
+omap3_sdrc_actim_ctrl_a_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
+omap3_sdrc_actim_ctrl_b_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_actim_ctrl_b_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 omap3_sdrc_mr_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
+omap3_sdrc_mr_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
+omap_sdrc_rfr_ctrl_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_rfr_ctrl_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_mr_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_mr_1_val:
+	.word 0xDEADBEEF
+
 omap3_sdrc_dlla_status:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:
@@ -223,3 +299,4 @@ core_m2_mask_val:
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
 	.word	. - omap3_sram_configure_core_dpll
+
diff --git a/arch/arm/plat-omap/include/mach/io.h 
b/arch/arm/plat-omap/include/mach/io.h
index 54c159b..d4c78b4 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -192,7 +192,8 @@ extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
 extern void omap2_map_common_io(void);
-extern void omap2_init_common_hw(struct omap_sdrc_params *sp,
+extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+				 struct omap_sdrc_params *sdrc_cs1,
 				 struct omap_opp *mpu_opps,
 				 struct omap_opp *dsp_opps,
 				 struct omap_opp *l3_opps);
diff --git a/arch/arm/plat-omap/include/mach/mux.h 
b/arch/arm/plat-omap/include/mach/mux.h
index f7e298a..7368aba 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -803,6 +803,10 @@ enum omap34xx_index {
 	AE5_34XX_GPIO143,
 	H19_34XX_GPIO164_OUT,
 	J25_34XX_GPIO170,
+
+	/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+	H16_34XX_SDRC_CKE0,
+	H17_34XX_SDRC_CKE1,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h 
b/arch/arm/plat-omap/include/mach/sdrc.h
index a678bc8..7e22143 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -114,9 +114,11 @@ struct omap_sdrc_params {
 
 void omap2_sms_save_context(void);
 void omap2_sms_restore_context(void);
-void __init omap2_sdrc_init(struct omap_sdrc_params *);
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
-
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+			    struct omap_sdrc_params *sdrc_cs1);
+int omap2_sdrc_get_params(unsigned long r,
+			  struct omap_sdrc_params **sdrc_cs0,
+			  struct omap_sdrc_params **sdrc_cs1);
 #ifdef CONFIG_ARCH_OMAP2
 
 struct memory_timings {
diff --git a/arch/arm/plat-omap/include/mach/sram.h 
b/arch/arm/plat-omap/include/mach/sram.h
index ad0a600..98906ea 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 
dll_val,
 				      u32 mem_type);
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 
-extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
-				     u32 sdrc_actim_ctrla,
-				     u32 sdrc_actim_ctrlb, u32 m2,
-				     u32 unlock_dll, u32 f, u32 sdrc_mr,
-				     u32 inc);
+extern u32 omap3_configure_core_dpll(
+			u32 m2, u32 unlock_dll, u32 f, u32 inc,
+			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
 extern void omap3_sram_restore_context(void);
 
 /* Do not use these */
@@ -61,11 +63,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, 
u32 dll_val,
 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 
 
-extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
-					  u32 sdrc_actim_ctrla,
-					  u32 sdrc_actim_ctrlb, u32 m2,
-					  u32 unlock_dll, u32 f, u32 sdrc_mr,
-					  u32 inc);
+extern u32 omap3_sram_configure_core_dpll(
+			u32 m2, u32 unlock_dll, u32 f, u32 inc,
+			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a2e60e7..517f45b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
 
 #ifdef CONFIG_ARCH_OMAP3
 
-static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
-					      u32 sdrc_actim_ctrla,
-					      u32 sdrc_actim_ctrlb,
-					      u32 m2, u32 unlock_dll,
-					      u32 f, u32 sdrc_mr, u32 inc);
-u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-			      u32 f, u32 sdrc_mr, u32 inc)
- {
+static u32 (*_omap3_sram_configure_core_dpll)(
+				u32 m2, u32 unlock_dll, u32 f, u32 inc,
+				u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+				u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+				u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+				u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+			      u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+			      u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+			      u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+			      u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
+{
 	if (!_omap3_sram_configure_core_dpll)
 		omap_sram_error();
 
-	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
-					       sdrc_actim_ctrla,
-					       sdrc_actim_ctrlb, m2,
-					       unlock_dll, f, sdrc_mr, inc);
- }
+	return _omap3_sram_configure_core_dpll(
+				m2, unlock_dll, f, inc,
+				sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+				sdrc_actim_ctrl_b_0, sdrc_mr_0,
+				sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+				sdrc_actim_ctrl_b_1, sdrc_mr_1);
+}
 
 #ifdef CONFIG_PM
 void omap3_sram_restore_context(void)
-- 
1.6.2.5.168.g3823



On Wednesday 03 June 2009 01:40:13 Paul Walmsley wrote:
> Hi Jean,
>
> a minor request: it is easier to comment on these patches if they are
> included inline in the E-mail message, rather than attached.  That way
> code comments can be inlined in the reply.
>
> On Tue, 26 May 2009, Jean Pihet wrote:
> > Here is a patch for the SDRC 2nd CS support. It applies on top of the
> > current pm branch.
>
> Thanks for doing this work.
>
> > I have some questions:
> > - Is it OK to copy the micron sdram params file to a new file with the 2
> > CSes params? One could use a unique file with #ifdef SDRC_SUPPORT_2_CSES.
>
> Is it possible for the SDRAM parameter files to remain unchanged, and to
> simply pass two struct omap_sdrc_params * to omap2_init_common_hw() and
> then to omap2_sdrc_init()?  Boards with only CS0 in use should pass NULL
> for the second omap_sdrc_params *.
>
> So something like this (I realize the PM branch has additional parameters
> here also):
>
> void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
>                                  struct omap_sdrc_params *sdrc_cs1)
>
> Then:
>
> void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>                             struct omap_sdrc_params *sdrc_cs1)
>
> I would prefer that approach.
>
> It would also be good to avoid changing the SDRC CS1 parameters in the
> SRAM code if the board does not use CS1.  Maybe pass in a flag that
> indicates whether CS1 is in use, and if not, avoid programming those
> registers?  The (admittedly minor) overhead of loading the CS1 registers
> off the stack would be nice to avoid also.
>
> > - Does the RX51 board have 2 sdram parts? If so I need to update the
> > board file as well.
>
> Probably best if someone from Nokia handles this.
>
>
> - Paul

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Paul Walmsley]

Hi Jean,

On Fri, 5 Jun 2009, Jean Pihet wrote:

> Here is the new patch that includes all the remarks and suggestion. The 
> description is here below.
> 
> Some notes:
> - all calls to omap2_init_common_hw have been adapted in the board files. it 
> looks like 2430SDP and Pandora board files are broken since they use only one 
> param. Can that be checked on those boards?
> - it is assumed that RX51 only uses 1 CS. Is that correct?
> 
> Can you review it and possibly merge?

Looks great.

Tero, does RX51 use two SDRC chipselects!

Acked-by: Paul Walmsley <paul@pwsan.com>


> 
> Thanks & regards,
> Jean
> 
> --
> From 097a640997b74638e0e7200ecd5834205204c956 Mon Sep 17 00:00:00 2001
> From: Jean Pihet <jpihet@mvista.com>
> Date: Fri, 5 Jun 2009 17:19:00 +0200
> Subject: [PATCH] [PATCH] OMAP3: add support for 2 SDRAM chip selects
> 
> Some boards (Beagle Cx, Overo) have 2 SDRAM parts
> connected to the SDRC.
> 
> This patch adds the following:
> - ensure that the CKE signals mux settings are correct
> - add a new argument of type omap_sdrc_params struct*
> to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
> - adapted the OMAP boards files to the new prototype of
> omap2_init_common_hw. Only Beagle and Overo are using the 2 CS'es
> - adapt the sram sleep code to configure the SDRC for the 2nd CS
> 
> Note: If the 2nd param to omap2_init_common_hw is NULL, then the
> parameters are not programmed into the SDRC CS1 registers
> 
> Tested on 3430 SDP and Beagleboard rev C2 and B5, with
> suspend/resume and frequency changes (cpufreq).
> 
> Thanks to Paul Walmsley and Kevin Hilman for the suggestions
> and code reviews.
> 
> Signed-off-by: Jean Pihet <jpihet@mvista.com>
> ---
>  arch/arm/mach-omap2/board-2430sdp.c      |    2 +-
>  arch/arm/mach-omap2/board-3430sdp.c      |    6 +-
>  arch/arm/mach-omap2/board-apollon.c      |    2 +-
>  arch/arm/mach-omap2/board-generic.c      |    2 +-
>  arch/arm/mach-omap2/board-h4.c           |    2 +-
>  arch/arm/mach-omap2/board-ldp.c          |    2 +-
>  arch/arm/mach-omap2/board-n800.c         |    2 +-
>  arch/arm/mach-omap2/board-omap2evm.c     |    2 +-
>  arch/arm/mach-omap2/board-omap3beagle.c  |   11 ++-
>  arch/arm/mach-omap2/board-omap3evm.c     |    6 +-
>  arch/arm/mach-omap2/board-omap3pandora.c |    3 +-
>  arch/arm/mach-omap2/board-overo.c        |    8 ++-
>  arch/arm/mach-omap2/board-rx51.c         |    6 +-
>  arch/arm/mach-omap2/clock34xx.c          |   37 ++++++--
>  arch/arm/mach-omap2/io.c                 |    5 +-
>  arch/arm/mach-omap2/mux.c                |    6 ++
>  arch/arm/mach-omap2/sdrc.c               |   63 +++++++++-----
>  arch/arm/mach-omap2/sram34xx.S           |  137 
> +++++++++++++++++++++++-------
>  arch/arm/plat-omap/include/mach/io.h     |    3 +-
>  arch/arm/plat-omap/include/mach/mux.h    |    4 +
>  arch/arm/plat-omap/include/mach/sdrc.h   |    8 +-
>  arch/arm/plat-omap/include/mach/sram.h   |   23 +++--
>  arch/arm/plat-omap/sram.c                |   34 +++++---
>  23 files changed, 266 insertions(+), 108 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-2430sdp.c 
> b/arch/arm/mach-omap2/board-2430sdp.c
> index aa5df72..4cb7bc5 100644
> --- a/arch/arm/mach-omap2/board-2430sdp.c
> +++ b/arch/arm/mach-omap2/board-2430sdp.c
> @@ -322,7 +322,7 @@ out:
>  
>  static void __init omap_2430sdp_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	sdp2430_init_smc91x();
> diff --git a/arch/arm/mach-omap2/board-3430sdp.c 
> b/arch/arm/mach-omap2/board-3430sdp.c
> index 195b749..24e2728 100644
> --- a/arch/arm/mach-omap2/board-3430sdp.c
> +++ b/arch/arm/mach-omap2/board-3430sdp.c
> @@ -302,8 +302,10 @@ static inline void __init sdp3430_init_smc91x(void)
>  
>  static void __init omap_3430sdp_init_irq(void)
>  {
> -	omap2_init_common_hw(hyb18m512160af6_sdrc_params, omap3_mpu_rate_table,
> -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> +	omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL,
> +			     omap3_mpu_rate_table,
> +			     omap3_dsp_rate_table,
> +			     omap3_l3_rate_table);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	sdp3430_init_smc91x();
> diff --git a/arch/arm/mach-omap2/board-apollon.c 
> b/arch/arm/mach-omap2/board-apollon.c
> index 2e24812..2dd1350 100644
> --- a/arch/arm/mach-omap2/board-apollon.c
> +++ b/arch/arm/mach-omap2/board-apollon.c
> @@ -323,7 +323,7 @@ out:
>  
>  static void __init omap_apollon_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	apollon_init_smc91x();
> diff --git a/arch/arm/mach-omap2/board-generic.c 
> b/arch/arm/mach-omap2/board-generic.c
> index be763a9..763329b 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -33,7 +33,7 @@
>  
>  static void __init omap_generic_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  }
>  
> diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
> index 8f54939..17c3599 100644
> --- a/arch/arm/mach-omap2/board-h4.c
> +++ b/arch/arm/mach-omap2/board-h4.c
> @@ -348,7 +348,7 @@ static void __init h4_init_flash(void)
>  
>  static void __init omap_h4_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	h4_init_flash();
> diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
> index 9f41dc9..b012806 100644
> --- a/arch/arm/mach-omap2/board-ldp.c
> +++ b/arch/arm/mach-omap2/board-ldp.c
> @@ -344,7 +344,7 @@ static inline void __init ldp_init_smc911x(void)
>  
>  static void __init omap_ldp_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	ldp_init_smc911x();
> diff --git a/arch/arm/mach-omap2/board-n800.c 
> b/arch/arm/mach-omap2/board-n800.c
> index ac7cf3f..ad53f4a 100644
> --- a/arch/arm/mach-omap2/board-n800.c
> +++ b/arch/arm/mach-omap2/board-n800.c
> @@ -127,7 +127,7 @@ static struct lm8323_platform_data lm8323_pdata = {
>  
>  void __init nokia_n800_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  
> diff --git a/arch/arm/mach-omap2/board-omap2evm.c 
> b/arch/arm/mach-omap2/board-omap2evm.c
> index 4fac1be..56a26d4 100644
> --- a/arch/arm/mach-omap2/board-omap2evm.c
> +++ b/arch/arm/mach-omap2/board-omap2evm.c
> @@ -276,7 +276,7 @@ static struct twl4030_keypad_data omap2evm_kp_data = {
>  
>  static void __init omap2_evm_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	omap2evm_init_smc911x();
> diff --git a/arch/arm/mach-omap2/board-omap3beagle.c 
> b/arch/arm/mach-omap2/board-omap3beagle.c
> index 7294dbf..872beb6 100644
> --- a/arch/arm/mach-omap2/board-omap3beagle.c
> +++ b/arch/arm/mach-omap2/board-omap3beagle.c
> @@ -312,8 +312,11 @@ static int __init omap3_beagle_i2c_init(void)
>  
>  static void __init omap3_beagle_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
> -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> +			     mt46h32m32lf6_sdrc_params,
> +			     omap3_mpu_rate_table,
> +			     omap3_dsp_rate_table,
> +			     omap3_l3_rate_table);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> @@ -441,6 +444,10 @@ static void __init omap3_beagle_init(void)
>  	usb_musb_init();
>  	usb_ehci_init();
>  	omap3beagle_flash_init();
> +
> +	/* Ensure SDRC pins are mux'd for self-refresh */
> +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
> +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
>  }
>  
>  static void __init omap3_beagle_map_io(void)
> diff --git a/arch/arm/mach-omap2/board-omap3evm.c 
> b/arch/arm/mach-omap2/board-omap3evm.c
> index f017f0d..3b9c96a 100644
> --- a/arch/arm/mach-omap2/board-omap3evm.c
> +++ b/arch/arm/mach-omap2/board-omap3evm.c
> @@ -276,8 +276,10 @@ struct spi_board_info omap3evm_spi_board_info[] = {
>  
>  static void __init omap3_evm_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
> -	                     omap3_dsp_rate_table, omap3_l3_rate_table);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
> +			     omap3_mpu_rate_table,
> +			     omap3_dsp_rate_table,
> +			     omap3_l3_rate_table);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	omap3evm_init_smc911x();
> diff --git a/arch/arm/mach-omap2/board-omap3pandora.c 
> b/arch/arm/mach-omap2/board-omap3pandora.c
> index c67f62f..05ab99e 100644
> --- a/arch/arm/mach-omap2/board-omap3pandora.c
> +++ b/arch/arm/mach-omap2/board-omap3pandora.c
> @@ -220,7 +220,8 @@ static int __init omap3pandora_i2c_init(void)
>  
>  static void __init omap3pandora_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
> +			     NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> diff --git a/arch/arm/mach-omap2/board-overo.c 
> b/arch/arm/mach-omap2/board-overo.c
> index 9eae608..2c6d2c5 100644
> --- a/arch/arm/mach-omap2/board-overo.c
> +++ b/arch/arm/mach-omap2/board-overo.c
> @@ -355,7 +355,9 @@ static int __init overo_i2c_init(void)
>  
>  static void __init overo_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL, NULL, NULL);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> +			     mt46h32m32lf6_sdrc_params,
> +			     NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> @@ -391,6 +393,10 @@ static void __init overo_init(void)
>  	overo_init_smsc911x();
>  	overo_ads7846_init();
>  
> +	/* Ensure SDRC pins are mux'd for self-refresh */
> +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
> +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
> +
>  	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
>  			  "OVERO_GPIO_W2W_NRESET") == 0) &&
>  	    (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
> diff --git a/arch/arm/mach-omap2/board-rx51.c 
> b/arch/arm/mach-omap2/board-rx51.c
> index 09035b0..d48459f 100644
> --- a/arch/arm/mach-omap2/board-rx51.c
> +++ b/arch/arm/mach-omap2/board-rx51.c
> @@ -64,8 +64,10 @@ static struct omap_board_config_kernel rx51_config[] = {
>  
>  static void __init rx51_init_irq(void)
>  {
> -	omap2_init_common_hw(rx51_get_sdram_timings(), omap3_mpu_rate_table,
> -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> +	omap2_init_common_hw(rx51_get_sdram_timings(), NULL,
> +			     omap3_mpu_rate_table,
> +			     omap3_dsp_rate_table,
> +			     omap3_l3_rate_table);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index 3cee6b4..f262787 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -478,7 +478,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
> unsigned long rate)
>  	u32 unlock_dll = 0;
>  	u32 c;
>  	unsigned long validrate, sdrcrate, mpurate;
> -	struct omap_sdrc_params *sp;
> +	struct omap_sdrc_params *sdrc_cs0;
> +	struct omap_sdrc_params *sdrc_cs1;
> +	int ret;
>  
>  	if (!clk || !rate)
>  		return -EINVAL;
> @@ -496,8 +498,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
> unsigned long rate)
>  	else
>  		sdrcrate >>= ((clk->rate / rate) >> 1);
>  
> -	sp = omap2_sdrc_get_params(sdrcrate);
> -	if (!sp)
> +	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
> +	if (ret)
>  		return -EINVAL;
>  
>  	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
> @@ -518,12 +520,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
> unsigned long rate)
>  
>  	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
>  		 validrate);
> -	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
> -		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
> -
> -	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
> -				  sp->actim_ctrlb, new_div, unlock_dll, c,
> -				  sp->mr, rate > clk->rate);
> +	pr_debug("clock: SDRC CS0 timing params used:"
> +		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
> +		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> +		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
> +	if (sdrc_cs1)
> +		pr_debug("clock: SDRC CS1 timing params used: "
> +		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
> +		 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
> +		 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
> +
> +	if (sdrc_cs1)
> +		omap3_configure_core_dpll(
> +				  new_div, unlock_dll, c, rate > clk->rate,
> +				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> +				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
> +				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
> +				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
> +	else
> +		omap3_configure_core_dpll(
> +				  new_div, unlock_dll, c, rate > clk->rate,
> +				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> +				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
> +				  0, 0, 0, 0);
>  
>  	return 0;
>  }
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 6fb6c29..aa000b4 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -231,7 +231,8 @@ static int __init _omap2_init_reprogram_sdrc(void)
>  	return v;
>  }
>  
> -void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
> +void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
> +				 struct omap_sdrc_params *sdrc_cs1,
>  				 struct omap_opp *mpu_opps,
>  				 struct omap_opp *dsp_opps,
>  				 struct omap_opp *l3_opps)
> @@ -244,7 +245,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params 
> *sp,
>  	omapdev_init(omapdevs);
>  	omap2_clk_init();
>  	omap_pm_if_init();
> -	omap2_sdrc_init(sp);
> +	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
>  
>  	_omap2_init_reprogram_sdrc();
>  
> diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
> index 026c4fc..43d6b92 100644
> --- a/arch/arm/mach-omap2/mux.c
> +++ b/arch/arm/mach-omap2/mux.c
> @@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
>  		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
>  MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
>  		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
> +
> +/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
> +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
> +		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
> +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
> +		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
>  };
>  
>  #define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)
> diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
> index c832d83..b42f5ae 100644
> --- a/arch/arm/mach-omap2/sdrc.c
> +++ b/arch/arm/mach-omap2/sdrc.c
> @@ -32,7 +32,7 @@
>  #include <mach/sdrc.h>
>  #include "sdrc.h"
>  
> -static struct omap_sdrc_params *sdrc_init_params;
> +static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
>  
>  void __iomem *omap2_sdrc_base;
>  void __iomem *omap2_sms_base;
> @@ -71,33 +71,49 @@ void omap2_sms_restore_context(void)
>  /**
>   * omap2_sdrc_get_params - return SDRC register values for a given clock rate
>   * @r: SDRC clock rate (in Hz)
> + * @sdrc_cs0: chip select 0 ram timings **
> + * @sdrc_cs1: chip select 1 ram timings **
>   *
>   * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
> - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
> - * SDRC clock rate 'r'.  These parameters control various timing
> - * delays in the SDRAM controller that are expressed in terms of the
> - * number of SDRC clock cycles to wait; hence the clock rate
> - * dependency. Note that sdrc_init_params must be sorted rate
> - * descending.  Also assumes that both chip-selects use the same
> - * timing parameters.  Returns a struct omap_sdrc_params * upon
> - * success, or NULL upon failure.
> + *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
> + *  structs,for a given SDRC clock rate 'r'.
> + * These parameters control various timing delays in the SDRAM controller
> + *  that are expressed in terms of the number of SDRC clock cycles to
> + *  wait; hence the clock rate dependency.
> + *
> + * Supports 2 different timing parameters for both chip selects.
> + *
> + * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
> + * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
> + *  as sdrc_init_params_cs_0.
> + *
> + * Fills in the struct omap_sdrc_params * for each chip select.
> + * Returns 0 upon success or -1 upon failure.
>   */
> -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
> +int omap2_sdrc_get_params(unsigned long r,
> +			  struct omap_sdrc_params **sdrc_cs0,
> +			  struct omap_sdrc_params **sdrc_cs1)
>  {
> -	struct omap_sdrc_params *sp;
> +	struct omap_sdrc_params *sp0, *sp1;
>  
> -	if (!sdrc_init_params)
> -		return NULL;
> +	if (!sdrc_init_params_cs0)
> +		return -1;
>  
> -	sp = sdrc_init_params;
> +	sp0 = sdrc_init_params_cs0;
> +	sp1 = sdrc_init_params_cs1;
>  
> -	while (sp->rate && sp->rate != r)
> -		sp++;
> +	while (sp0->rate && sp0->rate != r) {
> +		sp0++;
> +		if (sdrc_init_params_cs1)
> +			sp1++;
> +	}
>  
> -	if (!sp->rate)
> -		return NULL;
> +	if (!sp0->rate)
> +		return -1;
>  
> -	return sp;
> +	*sdrc_cs0 = sp0;
> +	*sdrc_cs1 = sp1;
> +	return 0;
>  }
>  
>  
> @@ -109,13 +125,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals 
> *omap2_globals)
>  
>  /**
>   * omap2_sdrc_init - initialize SMS, SDRC devices on boot
> - * @sp: pointer to a null-terminated list of struct omap_sdrc_params
> + * @sdrc_cs[01]: pointers to a null-terminated list of struct 
> omap_sdrc_params
> + *  Support for 2 chip selects timings
>   *
>   * Turn on smart idle modes for SDRAM scheduler and controller.
>   * Program a known-good configuration for the SDRC to deal with buggy
>   * bootloaders.
>   */
> -void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
> +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> +			    struct omap_sdrc_params *sdrc_cs1)
>  {
>  	u32 l;
>  
> @@ -129,7 +147,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
>  	l |= (0x2 << 3);
>  	sdrc_write_reg(l, SDRC_SYSCONFIG);
>  
> -	sdrc_init_params = sp;
> +	sdrc_init_params_cs0 = sdrc_cs0;
> +	sdrc_init_params_cs1 = sdrc_cs1;
>  
>  	/* XXX Enable SRFRONIDLEREQ here also? */
>  	l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
> diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
> index f41f8d9..3aef744 100644
> --- a/arch/arm/mach-omap2/sram34xx.S
> +++ b/arch/arm/mach-omap2/sram34xx.S
> @@ -36,7 +36,7 @@
>  
>  	.text
>  
> -/* r4 parameters */
> +/* r1 parameters */
>  #define SDRC_NO_UNLOCK_DLL		0x0
>  #define SDRC_UNLOCK_DLL			0x1
>  
> @@ -71,40 +71,71 @@
>  
>  /*
>   * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
> - * r0 = new SDRC_RFR_CTRL register contents
> - * r1 = new SDRC_ACTIM_CTRLA register contents
> - * r2 = new SDRC_ACTIM_CTRLB register contents
> - * r3 = new M2 divider setting (only 1 and 2 supported right now)
> - * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
> + *
> + * Params passed in registers:
> + *  r0 = new M2 divider setting (only 1 and 2 supported right now)
> + *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
>   *      SDRC rates < 83MHz
> - * r5 = number of MPU cycles to wait for SDRC to stabilize after
> + *  r2 = number of MPU cycles to wait for SDRC to stabilize after
>   *      reprogramming the SDRC when switching to a slower MPU speed
> - * r6 = new SDRC_MR_0 register value
> - * r7 = increasing SDRC rate? (1 = yes, 0 = no)
> + *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
> + *
> + * Params passed via the stack. The needed params will be copied in SRAM
> + *  before use by the code in SRAM (SDRAM is not accessible during SDRC
> + *  reconfiguration):
> + *  new SDRC_RFR_CTRL_0 register contents
> + *  new SDRC_ACTIM_CTRL_A_0 register contents
> + *  new SDRC_ACTIM_CTRL_B_0 register contents
> + *  new SDRC_MR_0 register value
> + *  new SDRC_RFR_CTRL_1 register contents
> + *  new SDRC_ACTIM_CTRL_A_1 register contents
> + *  new SDRC_ACTIM_CTRL_B_1 register contents
> + *  new SDRC_MR_1 register value
>   *
> + * If the param SDRC_RFR_CTRL_1 is 0, the parameters
> + *  are not programmed into the SDRC CS1 registers
>   */
>  ENTRY(omap3_sram_configure_core_dpll)
>  	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
> -	ldr	r4, [sp, #52]		@ pull extra args off the stack
> -	ldr	r5, [sp, #56]		@ load extra args from the stack
> -	ldr	r6, [sp, #60]		@ load extra args from the stack
> -	ldr	r7, [sp, #64]		@ load extra args from the stack
> +
> +					@ pull the extra args off the stack
> +					@  and store them in SRAM
> +	ldr	r4, [sp, #52]
> +	str     r4, omap_sdrc_rfr_ctrl_0_val
> +	ldr	r4, [sp, #56]
> +	str     r4, omap_sdrc_actim_ctrl_a_0_val
> +	ldr	r4, [sp, #60]
> +	str     r4, omap_sdrc_actim_ctrl_b_0_val
> +	ldr	r4, [sp, #64]
> +	str     r4, omap_sdrc_mr_0_val
> +	ldr	r4, [sp, #68]
> +	str     r4, omap_sdrc_rfr_ctrl_1_val
> +	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
> +	beq	skip_cs1_params		@  do not use cs1 params
> +	ldr	r4, [sp, #72]
> +	str     r4, omap_sdrc_actim_ctrl_a_1_val
> +	ldr	r4, [sp, #76]
> +	str     r4, omap_sdrc_actim_ctrl_b_1_val
> +	ldr	r4, [sp, #80]
> +	str     r4, omap_sdrc_mr_1_val
> +skip_cs1_params:
>  	dsb				@ flush buffered writes to interconnect
> -	cmp	r7, #1			@ if increasing SDRC clk rate,
> +
> +	cmp	r3, #1			@ if increasing SDRC clk rate,
>  	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
> -	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
> +	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
>  	bleq	unlock_dll
>  	blne	lock_dll
>  	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
>  	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
>  	bl	enable_sdrc		@ take SDRC out of idle
> -	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
> +	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
>  	bleq	wait_dll_unlock
>  	blne	wait_dll_lock
> -	cmp	r7, #1			@ if increasing SDRC clk rate,
> +	cmp	r3, #1			@ if increasing SDRC clk rate,
>  	beq	return_to_sdram		@ return to SDRAM code, otherwise,
>  	bl	configure_sdrc		@ reprogram SDRC regs now
> -	mov	r12, r5
> +	mov	r12, r2
>  	bl	wait_clk_stable		@ wait for SDRC to stabilize
>  return_to_sdram:
>  	isb				@ prevent speculative exec past here
> @@ -149,7 +180,7 @@ configure_core_dpll:
>  	ldr	r12, [r11]
>  	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
>  	and	r12, r12, r10
> -	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
> +	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
>  	str	r12, [r11]
>  	ldr	r12, [r11]		@ posted-write barrier for CM
>  	bx	lr
> @@ -187,15 +218,34 @@ wait_dll_unlock:
>  	bne	wait_dll_unlock
>  	bx	lr
>  configure_sdrc:
> -	ldr	r11, omap3_sdrc_rfr_ctrl
> -	str	r0, [r11]
> -	ldr	r11, omap3_sdrc_actim_ctrla
> -	str	r1, [r11]
> -	ldr	r11, omap3_sdrc_actim_ctrlb
> -	str	r2, [r11]
> +	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
> +	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
> +	str	r12, [r11]			@ store
> +	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
> +	ldr	r11, omap3_sdrc_actim_ctrl_a_0
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
> +	ldr	r11, omap3_sdrc_actim_ctrl_b_0
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_mr_0_val
>  	ldr	r11, omap3_sdrc_mr_0
> -	str	r6, [r11]
> -	ldr	r6, [r11]		@ posted-write barrier for SDRC
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_rfr_ctrl_1_val
> +	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
> +	beq	skip_cs1_prog		@  do not program cs1 params
> +	ldr	r11, omap3_sdrc_rfr_ctrl_1
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
> +	ldr	r11, omap3_sdrc_actim_ctrl_a_1
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
> +	ldr	r11, omap3_sdrc_actim_ctrl_b_1
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_mr_1_val
> +	ldr	r11, omap3_sdrc_mr_1
> +	str	r12, [r11]
> +skip_cs1_prog:
> +	ldr	r12, [r11]		@ posted-write barrier for SDRC
>  	bx	lr
>  
>  omap3_sdrc_power:
> @@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
>  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
>  omap3_cm_iclken1_core:
>  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
> -omap3_sdrc_rfr_ctrl:
> +
> +omap3_sdrc_rfr_ctrl_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
> -omap3_sdrc_actim_ctrla:
> +omap3_sdrc_rfr_ctrl_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
> +omap3_sdrc_actim_ctrl_a_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
> -omap3_sdrc_actim_ctrlb:
> +omap3_sdrc_actim_ctrl_a_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
> +omap3_sdrc_actim_ctrl_b_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
> +omap3_sdrc_actim_ctrl_b_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
>  omap3_sdrc_mr_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
> +omap3_sdrc_mr_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
> +omap_sdrc_rfr_ctrl_0_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_rfr_ctrl_1_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_actim_ctrl_a_0_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_actim_ctrl_a_1_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_actim_ctrl_b_0_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_actim_ctrl_b_1_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_mr_0_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_mr_1_val:
> +	.word 0xDEADBEEF
> +
>  omap3_sdrc_dlla_status:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  omap3_sdrc_dlla_ctrl:
> @@ -223,3 +299,4 @@ core_m2_mask_val:
>  
>  ENTRY(omap3_sram_configure_core_dpll_sz)
>  	.word	. - omap3_sram_configure_core_dpll
> +
> diff --git a/arch/arm/plat-omap/include/mach/io.h 
> b/arch/arm/plat-omap/include/mach/io.h
> index 54c159b..d4c78b4 100644
> --- a/arch/arm/plat-omap/include/mach/io.h
> +++ b/arch/arm/plat-omap/include/mach/io.h
> @@ -192,7 +192,8 @@ extern void omap1_map_common_io(void);
>  extern void omap1_init_common_hw(void);
>  
>  extern void omap2_map_common_io(void);
> -extern void omap2_init_common_hw(struct omap_sdrc_params *sp,
> +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
> +				 struct omap_sdrc_params *sdrc_cs1,
>  				 struct omap_opp *mpu_opps,
>  				 struct omap_opp *dsp_opps,
>  				 struct omap_opp *l3_opps);
> diff --git a/arch/arm/plat-omap/include/mach/mux.h 
> b/arch/arm/plat-omap/include/mach/mux.h
> index f7e298a..7368aba 100644
> --- a/arch/arm/plat-omap/include/mach/mux.h
> +++ b/arch/arm/plat-omap/include/mach/mux.h
> @@ -803,6 +803,10 @@ enum omap34xx_index {
>  	AE5_34XX_GPIO143,
>  	H19_34XX_GPIO164_OUT,
>  	J25_34XX_GPIO170,
> +
> +	/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
> +	H16_34XX_SDRC_CKE0,
> +	H17_34XX_SDRC_CKE1,
>  };
>  
>  struct omap_mux_cfg {
> diff --git a/arch/arm/plat-omap/include/mach/sdrc.h 
> b/arch/arm/plat-omap/include/mach/sdrc.h
> index a678bc8..7e22143 100644
> --- a/arch/arm/plat-omap/include/mach/sdrc.h
> +++ b/arch/arm/plat-omap/include/mach/sdrc.h
> @@ -114,9 +114,11 @@ struct omap_sdrc_params {
>  
>  void omap2_sms_save_context(void);
>  void omap2_sms_restore_context(void);
> -void __init omap2_sdrc_init(struct omap_sdrc_params *);
> -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
> -
> +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> +			    struct omap_sdrc_params *sdrc_cs1);
> +int omap2_sdrc_get_params(unsigned long r,
> +			  struct omap_sdrc_params **sdrc_cs0,
> +			  struct omap_sdrc_params **sdrc_cs1);
>  #ifdef CONFIG_ARCH_OMAP2
>  
>  struct memory_timings {
> diff --git a/arch/arm/plat-omap/include/mach/sram.h 
> b/arch/arm/plat-omap/include/mach/sram.h
> index ad0a600..98906ea 100644
> --- a/arch/arm/plat-omap/include/mach/sram.h
> +++ b/arch/arm/plat-omap/include/mach/sram.h
> @@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 
> dll_val,
>  				      u32 mem_type);
>  extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
>  
> -extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
> -				     u32 sdrc_actim_ctrla,
> -				     u32 sdrc_actim_ctrlb, u32 m2,
> -				     u32 unlock_dll, u32 f, u32 sdrc_mr,
> -				     u32 inc);
> +extern u32 omap3_configure_core_dpll(
> +			u32 m2, u32 unlock_dll, u32 f, u32 inc,
> +			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> +			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> +			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> +			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
> +
>  extern void omap3_sram_restore_context(void);
>  
>  /* Do not use these */
> @@ -61,11 +63,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, 
> u32 dll_val,
>  extern unsigned long omap243x_sram_reprogram_sdrc_sz;
>  
>  
> -extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
> -					  u32 sdrc_actim_ctrla,
> -					  u32 sdrc_actim_ctrlb, u32 m2,
> -					  u32 unlock_dll, u32 f, u32 sdrc_mr,
> -					  u32 inc);
> +extern u32 omap3_sram_configure_core_dpll(
> +			u32 m2, u32 unlock_dll, u32 f, u32 inc,
> +			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> +			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> +			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> +			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>  extern unsigned long omap3_sram_configure_core_dpll_sz;
>  
>  #ifdef CONFIG_PM
> diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
> index a2e60e7..517f45b 100644
> --- a/arch/arm/plat-omap/sram.c
> +++ b/arch/arm/plat-omap/sram.c
> @@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
>  
>  #ifdef CONFIG_ARCH_OMAP3
>  
> -static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
> -					      u32 sdrc_actim_ctrla,
> -					      u32 sdrc_actim_ctrlb,
> -					      u32 m2, u32 unlock_dll,
> -					      u32 f, u32 sdrc_mr, u32 inc);
> -u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
> -			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
> -			      u32 f, u32 sdrc_mr, u32 inc)
> - {
> +static u32 (*_omap3_sram_configure_core_dpll)(
> +				u32 m2, u32 unlock_dll, u32 f, u32 inc,
> +				u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> +				u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> +				u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> +				u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
> +
> +u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
> +			      u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> +			      u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> +			      u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> +			      u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
> +{
>  	if (!_omap3_sram_configure_core_dpll)
>  		omap_sram_error();
>  
> -	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
> -					       sdrc_actim_ctrla,
> -					       sdrc_actim_ctrlb, m2,
> -					       unlock_dll, f, sdrc_mr, inc);
> - }
> +	return _omap3_sram_configure_core_dpll(
> +				m2, unlock_dll, f, inc,
> +				sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
> +				sdrc_actim_ctrl_b_0, sdrc_mr_0,
> +				sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
> +				sdrc_actim_ctrl_b_1, sdrc_mr_1);
> +}
>  
>  #ifdef CONFIG_PM
>  void omap3_sram_restore_context(void)
> -- 
> 1.6.2.5.168.g3823
> 
> 
> 
> On Wednesday 03 June 2009 01:40:13 Paul Walmsley wrote:
> > Hi Jean,
> >
> > a minor request: it is easier to comment on these patches if they are
> > included inline in the E-mail message, rather than attached.  That way
> > code comments can be inlined in the reply.
> >
> > On Tue, 26 May 2009, Jean Pihet wrote:
> > > Here is a patch for the SDRC 2nd CS support. It applies on top of the
> > > current pm branch.
> >
> > Thanks for doing this work.
> >
> > > I have some questions:
> > > - Is it OK to copy the micron sdram params file to a new file with the 2
> > > CSes params? One could use a unique file with #ifdef SDRC_SUPPORT_2_CSES.
> >
> > Is it possible for the SDRAM parameter files to remain unchanged, and to
> > simply pass two struct omap_sdrc_params * to omap2_init_common_hw() and
> > then to omap2_sdrc_init()?  Boards with only CS0 in use should pass NULL
> > for the second omap_sdrc_params *.
> >
> > So something like this (I realize the PM branch has additional parameters
> > here also):
> >
> > void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
> >                                  struct omap_sdrc_params *sdrc_cs1)
> >
> > Then:
> >
> > void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> >                             struct omap_sdrc_params *sdrc_cs1)
> >
> > I would prefer that approach.
> >
> > It would also be good to avoid changing the SDRC CS1 parameters in the
> > SRAM code if the board does not use CS1.  Maybe pass in a flag that
> > indicates whether CS1 is in use, and if not, avoid programming those
> > registers?  The (admittedly minor) overhead of loading the CS1 registers
> > off the stack would be nice to avoid also.
> >
> > > - Does the RX51 board have 2 sdram parts? If so I need to update the
> > > board file as well.
> >
> > Probably best if someone from Nokia handles this.
> >
> >
> > - Paul
> 
> 


- Paul

RE: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Tero.Kristo]

>-----Original Message-----
>From: ext Paul Walmsley [mailto:paul@pwsan.com]
>Sent: 05 June, 2009 21:11
>To: Jean Pihet; Kristo Tero (Nokia-D/Tampere)
>Cc: Kevin Hilman; linux-omap
>Subject: Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip
>selects (was: Re: Beagleboard rev C memory timings & suspend/resume)
>
>Hi Jean,
>
>On Fri, 5 Jun 2009, Jean Pihet wrote:
>
>> Here is the new patch that includes all the remarks and suggestion.
>> The description is here below.
>>
>> Some notes:
>> - all calls to omap2_init_common_hw have been adapted in the board
>> files. it looks like 2430SDP and Pandora board files are
>broken since
>> they use only one param. Can that be checked on those boards?
>> - it is assumed that RX51 only uses 1 CS. Is that correct?
>>
>> Can you review it and possibly merge?
>
>Looks great.
>
>Tero, does RX51 use two SDRC chipselects!

Yes, I'll take a look at this and post a patch on top of this. I did this for the earlier version already, but need to re-check this one.

-Tero

>
>Acked-by: Paul Walmsley <paul@pwsan.com>
>
>
>>
>> Thanks & regards,
>> Jean
>>
>> --
>> From 097a640997b74638e0e7200ecd5834205204c956 Mon Sep 17
>00:00:00 2001
>> From: Jean Pihet <jpihet@mvista.com>
>> Date: Fri, 5 Jun 2009 17:19:00 +0200
>> Subject: [PATCH] [PATCH] OMAP3: add support for 2 SDRAM chip selects
>>
>> Some boards (Beagle Cx, Overo) have 2 SDRAM parts connected to the
>> SDRC.
>>
>> This patch adds the following:
>> - ensure that the CKE signals mux settings are correct
>> - add a new argument of type omap_sdrc_params struct* to
>> omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
>> - adapted the OMAP boards files to the new prototype of
>> omap2_init_common_hw. Only Beagle and Overo are using the 2 CS'es
>> - adapt the sram sleep code to configure the SDRC for the 2nd CS
>>
>> Note: If the 2nd param to omap2_init_common_hw is NULL, then the
>> parameters are not programmed into the SDRC CS1 registers
>>
>> Tested on 3430 SDP and Beagleboard rev C2 and B5, with
>suspend/resume
>> and frequency changes (cpufreq).
>>
>> Thanks to Paul Walmsley and Kevin Hilman for the suggestions
>and code
>> reviews.
>>
>> Signed-off-by: Jean Pihet <jpihet@mvista.com>
>> ---
>>  arch/arm/mach-omap2/board-2430sdp.c      |    2 +-
>>  arch/arm/mach-omap2/board-3430sdp.c      |    6 +-
>>  arch/arm/mach-omap2/board-apollon.c      |    2 +-
>>  arch/arm/mach-omap2/board-generic.c      |    2 +-
>>  arch/arm/mach-omap2/board-h4.c           |    2 +-
>>  arch/arm/mach-omap2/board-ldp.c          |    2 +-
>>  arch/arm/mach-omap2/board-n800.c         |    2 +-
>>  arch/arm/mach-omap2/board-omap2evm.c     |    2 +-
>>  arch/arm/mach-omap2/board-omap3beagle.c  |   11 ++-
>>  arch/arm/mach-omap2/board-omap3evm.c     |    6 +-
>>  arch/arm/mach-omap2/board-omap3pandora.c |    3 +-
>>  arch/arm/mach-omap2/board-overo.c        |    8 ++-
>>  arch/arm/mach-omap2/board-rx51.c         |    6 +-
>>  arch/arm/mach-omap2/clock34xx.c          |   37 ++++++--
>>  arch/arm/mach-omap2/io.c                 |    5 +-
>>  arch/arm/mach-omap2/mux.c                |    6 ++
>>  arch/arm/mach-omap2/sdrc.c               |   63 +++++++++-----
>>  arch/arm/mach-omap2/sram34xx.S           |  137
>> +++++++++++++++++++++++-------
>>  arch/arm/plat-omap/include/mach/io.h     |    3 +-
>>  arch/arm/plat-omap/include/mach/mux.h    |    4 +
>>  arch/arm/plat-omap/include/mach/sdrc.h   |    8 +-
>>  arch/arm/plat-omap/include/mach/sram.h   |   23 +++--
>>  arch/arm/plat-omap/sram.c                |   34 +++++---
>>  23 files changed, 266 insertions(+), 108 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/board-2430sdp.c
>> b/arch/arm/mach-omap2/board-2430sdp.c
>> index aa5df72..4cb7bc5 100644
>> --- a/arch/arm/mach-omap2/board-2430sdp.c
>> +++ b/arch/arm/mach-omap2/board-2430sdp.c
>> @@ -322,7 +322,7 @@ out:
>>
>>  static void __init omap_2430sdp_init_irq(void)  {
>> -    omap2_init_common_hw(NULL);
>> +    omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>      omap_init_irq();
>>      omap_gpio_init();
>>      sdp2430_init_smc91x();
>> diff --git a/arch/arm/mach-omap2/board-3430sdp.c
>> b/arch/arm/mach-omap2/board-3430sdp.c
>> index 195b749..24e2728 100644
>> --- a/arch/arm/mach-omap2/board-3430sdp.c
>> +++ b/arch/arm/mach-omap2/board-3430sdp.c
>> @@ -302,8 +302,10 @@ static inline void __init
>> sdp3430_init_smc91x(void)
>>
>>  static void __init omap_3430sdp_init_irq(void)  {
>> -    omap2_init_common_hw(hyb18m512160af6_sdrc_params,
>omap3_mpu_rate_table,
>> -                         omap3_dsp_rate_table, omap3_l3_rate_table);
>> +    omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL,
>> +                         omap3_mpu_rate_table,
>> +                         omap3_dsp_rate_table,
>> +                         omap3_l3_rate_table);
>>      omap_init_irq();
>>      omap_gpio_init();
>>      sdp3430_init_smc91x();
>> diff --git a/arch/arm/mach-omap2/board-apollon.c
>> b/arch/arm/mach-omap2/board-apollon.c
>> index 2e24812..2dd1350 100644
>> --- a/arch/arm/mach-omap2/board-apollon.c
>> +++ b/arch/arm/mach-omap2/board-apollon.c
>> @@ -323,7 +323,7 @@ out:
>>
>>  static void __init omap_apollon_init_irq(void)  {
>> -    omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> +    omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>      omap_init_irq();
>>      omap_gpio_init();
>>      apollon_init_smc91x();
>> diff --git a/arch/arm/mach-omap2/board-generic.c
>> b/arch/arm/mach-omap2/board-generic.c
>> index be763a9..763329b 100644
>> --- a/arch/arm/mach-omap2/board-generic.c
>> +++ b/arch/arm/mach-omap2/board-generic.c
>> @@ -33,7 +33,7 @@
>>
>>  static void __init omap_generic_init_irq(void)  {
>> -    omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> +    omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>      omap_init_irq();
>>  }
>>
>> diff --git a/arch/arm/mach-omap2/board-h4.c
>> b/arch/arm/mach-omap2/board-h4.c index 8f54939..17c3599 100644
>> --- a/arch/arm/mach-omap2/board-h4.c
>> +++ b/arch/arm/mach-omap2/board-h4.c
>> @@ -348,7 +348,7 @@ static void __init h4_init_flash(void)
>>
>>  static void __init omap_h4_init_irq(void)  {
>> -    omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> +    omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>      omap_init_irq();
>>      omap_gpio_init();
>>      h4_init_flash();
>> diff --git a/arch/arm/mach-omap2/board-ldp.c
>> b/arch/arm/mach-omap2/board-ldp.c index 9f41dc9..b012806 100644
>> --- a/arch/arm/mach-omap2/board-ldp.c
>> +++ b/arch/arm/mach-omap2/board-ldp.c
>> @@ -344,7 +344,7 @@ static inline void __init ldp_init_smc911x(void)
>>
>>  static void __init omap_ldp_init_irq(void)  {
>> -    omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> +    omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>      omap_init_irq();
>>      omap_gpio_init();
>>      ldp_init_smc911x();
>> diff --git a/arch/arm/mach-omap2/board-n800.c
>> b/arch/arm/mach-omap2/board-n800.c
>> index ac7cf3f..ad53f4a 100644
>> --- a/arch/arm/mach-omap2/board-n800.c
>> +++ b/arch/arm/mach-omap2/board-n800.c
>> @@ -127,7 +127,7 @@ static struct lm8323_platform_data
>lm8323_pdata =
>> {
>>
>>  void __init nokia_n800_init_irq(void)  {
>> -    omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> +    omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>      omap_init_irq();
>>      omap_gpio_init();
>>
>> diff --git a/arch/arm/mach-omap2/board-omap2evm.c
>> b/arch/arm/mach-omap2/board-omap2evm.c
>> index 4fac1be..56a26d4 100644
>> --- a/arch/arm/mach-omap2/board-omap2evm.c
>> +++ b/arch/arm/mach-omap2/board-omap2evm.c
>> @@ -276,7 +276,7 @@ static struct twl4030_keypad_data
>omap2evm_kp_data
>> = {
>>
>>  static void __init omap2_evm_init_irq(void)  {
>> -    omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> +    omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>      omap_init_irq();
>>      omap_gpio_init();
>>      omap2evm_init_smc911x();
>> diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
>> b/arch/arm/mach-omap2/board-omap3beagle.c
>> index 7294dbf..872beb6 100644
>> --- a/arch/arm/mach-omap2/board-omap3beagle.c
>> +++ b/arch/arm/mach-omap2/board-omap3beagle.c
>> @@ -312,8 +312,11 @@ static int __init omap3_beagle_i2c_init(void)
>>
>>  static void __init omap3_beagle_init_irq(void)  {
>> -    omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>omap3_mpu_rate_table,
>> -                         omap3_dsp_rate_table, omap3_l3_rate_table);
>> +    omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>> +                         mt46h32m32lf6_sdrc_params,
>> +                         omap3_mpu_rate_table,
>> +                         omap3_dsp_rate_table,
>> +                         omap3_l3_rate_table);
>>      omap_init_irq();
>>      omap_gpio_init();
>>  }
>> @@ -441,6 +444,10 @@ static void __init omap3_beagle_init(void)
>>      usb_musb_init();
>>      usb_ehci_init();
>>      omap3beagle_flash_init();
>> +
>> +    /* Ensure SDRC pins are mux'd for self-refresh */
>> +    omap_cfg_reg(H16_34XX_SDRC_CKE0);
>> +    omap_cfg_reg(H17_34XX_SDRC_CKE1);
>>  }
>>
>>  static void __init omap3_beagle_map_io(void) diff --git
>> a/arch/arm/mach-omap2/board-omap3evm.c
>> b/arch/arm/mach-omap2/board-omap3evm.c
>> index f017f0d..3b9c96a 100644
>> --- a/arch/arm/mach-omap2/board-omap3evm.c
>> +++ b/arch/arm/mach-omap2/board-omap3evm.c
>> @@ -276,8 +276,10 @@ struct spi_board_info
>omap3evm_spi_board_info[] =
>> {
>>
>>  static void __init omap3_evm_init_irq(void)  {
>> -    omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>omap3_mpu_rate_table,
>> -                         omap3_dsp_rate_table, omap3_l3_rate_table);
>> +    omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>> +                         omap3_mpu_rate_table,
>> +                         omap3_dsp_rate_table,
>> +                         omap3_l3_rate_table);
>>      omap_init_irq();
>>      omap_gpio_init();
>>      omap3evm_init_smc911x();
>> diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
>> b/arch/arm/mach-omap2/board-omap3pandora.c
>> index c67f62f..05ab99e 100644
>> --- a/arch/arm/mach-omap2/board-omap3pandora.c
>> +++ b/arch/arm/mach-omap2/board-omap3pandora.c
>> @@ -220,7 +220,8 @@ static int __init omap3pandora_i2c_init(void)
>>
>>  static void __init omap3pandora_init_irq(void)  {
>> -    omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
>> +    omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>> +                         NULL, NULL, NULL);
>>      omap_init_irq();
>>      omap_gpio_init();
>>  }
>> diff --git a/arch/arm/mach-omap2/board-overo.c
>> b/arch/arm/mach-omap2/board-overo.c
>> index 9eae608..2c6d2c5 100644
>> --- a/arch/arm/mach-omap2/board-overo.c
>> +++ b/arch/arm/mach-omap2/board-overo.c
>> @@ -355,7 +355,9 @@ static int __init overo_i2c_init(void)
>>
>>  static void __init overo_init_irq(void)  {
>> -    omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>NULL, NULL);
>> +    omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>> +                         mt46h32m32lf6_sdrc_params,
>> +                         NULL, NULL, NULL);
>>      omap_init_irq();
>>      omap_gpio_init();
>>  }
>> @@ -391,6 +393,10 @@ static void __init overo_init(void)
>>      overo_init_smsc911x();
>>      overo_ads7846_init();
>>
>> +    /* Ensure SDRC pins are mux'd for self-refresh */
>> +    omap_cfg_reg(H16_34XX_SDRC_CKE0);
>> +    omap_cfg_reg(H17_34XX_SDRC_CKE1);
>> +
>>      if ((gpio_request(OVERO_GPIO_W2W_NRESET,
>>                        "OVERO_GPIO_W2W_NRESET") == 0) &&
>>          (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) ==
>0)) { diff
>> --git a/arch/arm/mach-omap2/board-rx51.c
>> b/arch/arm/mach-omap2/board-rx51.c
>> index 09035b0..d48459f 100644
>> --- a/arch/arm/mach-omap2/board-rx51.c
>> +++ b/arch/arm/mach-omap2/board-rx51.c
>> @@ -64,8 +64,10 @@ static struct omap_board_config_kernel
>> rx51_config[] = {
>>
>>  static void __init rx51_init_irq(void)  {
>> -    omap2_init_common_hw(rx51_get_sdram_timings(),
>omap3_mpu_rate_table,
>> -                         omap3_dsp_rate_table, omap3_l3_rate_table);
>> +    omap2_init_common_hw(rx51_get_sdram_timings(), NULL,
>> +                         omap3_mpu_rate_table,
>> +                         omap3_dsp_rate_table,
>> +                         omap3_l3_rate_table);
>>      omap_init_irq();
>>      omap_gpio_init();
>>  }
>> diff --git a/arch/arm/mach-omap2/clock34xx.c
>> b/arch/arm/mach-omap2/clock34xx.c index 3cee6b4..f262787 100644
>> --- a/arch/arm/mach-omap2/clock34xx.c
>> +++ b/arch/arm/mach-omap2/clock34xx.c
>> @@ -478,7 +478,9 @@ static int
>omap3_core_dpll_m2_set_rate(struct clk
>> *clk, unsigned long rate)
>>      u32 unlock_dll = 0;
>>      u32 c;
>>      unsigned long validrate, sdrcrate, mpurate;
>> -    struct omap_sdrc_params *sp;
>> +    struct omap_sdrc_params *sdrc_cs0;
>> +    struct omap_sdrc_params *sdrc_cs1;
>> +    int ret;
>>
>>      if (!clk || !rate)
>>              return -EINVAL;
>> @@ -496,8 +498,8 @@ static int
>omap3_core_dpll_m2_set_rate(struct clk
>> *clk, unsigned long rate)
>>      else
>>              sdrcrate >>= ((clk->rate / rate) >> 1);
>>
>> -    sp = omap2_sdrc_get_params(sdrcrate);
>> -    if (!sp)
>> +    ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
>> +    if (ret)
>>              return -EINVAL;
>>
>>      if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { @@ -518,12 +520,29 @@
>> static int omap3_core_dpll_m2_set_rate(struct clk *clk,
>unsigned long
>> rate)
>>
>>      pr_debug("clock: changing CORE DPLL rate from %lu to
>%lu\n", clk->rate,
>>               validrate);
>> -    pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
>> -             sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
>> -
>> -    omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
>> -                              sp->actim_ctrlb, new_div,
>unlock_dll, c,
>> -                              sp->mr, rate > clk->rate);
>> +    pr_debug("clock: SDRC CS0 timing params used:"
>> +             " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
>> +             sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
>> +             sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
>> +    if (sdrc_cs1)
>> +            pr_debug("clock: SDRC CS1 timing params used: "
>> +             " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
>> +             sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
>> +             sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
>> +
>> +    if (sdrc_cs1)
>> +            omap3_configure_core_dpll(
>> +                              new_div, unlock_dll, c, rate
>> clk->rate,
>> +                              sdrc_cs0->rfr_ctrl,
>sdrc_cs0->actim_ctrla,
>> +                              sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
>> +                              sdrc_cs1->rfr_ctrl,
>sdrc_cs1->actim_ctrla,
>> +                              sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
>> +    else
>> +            omap3_configure_core_dpll(
>> +                              new_div, unlock_dll, c, rate
>> clk->rate,
>> +                              sdrc_cs0->rfr_ctrl,
>sdrc_cs0->actim_ctrla,
>> +                              sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
>> +                              0, 0, 0, 0);
>>
>>      return 0;
>>  }
>> diff --git a/arch/arm/mach-omap2/io.c
>b/arch/arm/mach-omap2/io.c index
>> 6fb6c29..aa000b4 100644
>> --- a/arch/arm/mach-omap2/io.c
>> +++ b/arch/arm/mach-omap2/io.c
>> @@ -231,7 +231,8 @@ static int __init
>_omap2_init_reprogram_sdrc(void)
>>      return v;
>>  }
>>
>> -void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
>> +void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
>> +                             struct omap_sdrc_params *sdrc_cs1,
>>                               struct omap_opp *mpu_opps,
>>                               struct omap_opp *dsp_opps,
>>                               struct omap_opp *l3_opps)
>> @@ -244,7 +245,7 @@ void __init omap2_init_common_hw(struct
>> omap_sdrc_params *sp,
>>      omapdev_init(omapdevs);
>>      omap2_clk_init();
>>      omap_pm_if_init();
>> -    omap2_sdrc_init(sp);
>> +    omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
>>
>>      _omap2_init_reprogram_sdrc();
>>
>> diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
>> index 026c4fc..43d6b92 100644
>> --- a/arch/arm/mach-omap2/mux.c
>> +++ b/arch/arm/mach-omap2/mux.c
>> @@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
>>              OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
>> MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
>>              OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
>> +
>> +/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
>> +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
>> +            OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
>> +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
>> +            OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
>>  };
>>
>>  #define OMAP34XX_PINS_SZ    ARRAY_SIZE(omap34xx_pins)
>> diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
>> index c832d83..b42f5ae 100644
>> --- a/arch/arm/mach-omap2/sdrc.c
>> +++ b/arch/arm/mach-omap2/sdrc.c
>> @@ -32,7 +32,7 @@
>>  #include <mach/sdrc.h>
>>  #include "sdrc.h"
>>
>> -static struct omap_sdrc_params *sdrc_init_params;
>> +static struct omap_sdrc_params *sdrc_init_params_cs0,
>> +*sdrc_init_params_cs1;
>>
>>  void __iomem *omap2_sdrc_base;
>>  void __iomem *omap2_sms_base;
>> @@ -71,33 +71,49 @@ void omap2_sms_restore_context(void)
>>  /**
>>   * omap2_sdrc_get_params - return SDRC register values for
>a given clock rate
>>   * @r: SDRC clock rate (in Hz)
>> + * @sdrc_cs0: chip select 0 ram timings **
>> + * @sdrc_cs1: chip select 1 ram timings **
>>   *
>>   * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
>> - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a
>> given
>> - * SDRC clock rate 'r'.  These parameters control various timing
>> - * delays in the SDRAM controller that are expressed in terms of the
>> - * number of SDRC clock cycles to wait; hence the clock rate
>> - * dependency. Note that sdrc_init_params must be sorted rate
>> - * descending.  Also assumes that both chip-selects use the same
>> - * timing parameters.  Returns a struct omap_sdrc_params * upon
>> - * success, or NULL upon failure.
>> + *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in
>> + sdrc_cs[01]
>> + *  structs,for a given SDRC clock rate 'r'.
>> + * These parameters control various timing delays in the SDRAM
>> + controller
>> + *  that are expressed in terms of the number of SDRC clock
>cycles to
>> + *  wait; hence the clock rate dependency.
>> + *
>> + * Supports 2 different timing parameters for both chip selects.
>> + *
>> + * Note 1: the sdrc_init_params_cs[01] must be sorted rate
>descending.
>> + * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same
>> + size
>> + *  as sdrc_init_params_cs_0.
>> + *
>> + * Fills in the struct omap_sdrc_params * for each chip select.
>> + * Returns 0 upon success or -1 upon failure.
>>   */
>> -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
>> +int omap2_sdrc_get_params(unsigned long r,
>> +                      struct omap_sdrc_params **sdrc_cs0,
>> +                      struct omap_sdrc_params **sdrc_cs1)
>>  {
>> -    struct omap_sdrc_params *sp;
>> +    struct omap_sdrc_params *sp0, *sp1;
>>
>> -    if (!sdrc_init_params)
>> -            return NULL;
>> +    if (!sdrc_init_params_cs0)
>> +            return -1;
>>
>> -    sp = sdrc_init_params;
>> +    sp0 = sdrc_init_params_cs0;
>> +    sp1 = sdrc_init_params_cs1;
>>
>> -    while (sp->rate && sp->rate != r)
>> -            sp++;
>> +    while (sp0->rate && sp0->rate != r) {
>> +            sp0++;
>> +            if (sdrc_init_params_cs1)
>> +                    sp1++;
>> +    }
>>
>> -    if (!sp->rate)
>> -            return NULL;
>> +    if (!sp0->rate)
>> +            return -1;
>>
>> -    return sp;
>> +    *sdrc_cs0 = sp0;
>> +    *sdrc_cs1 = sp1;
>> +    return 0;
>>  }
>>
>>
>> @@ -109,13 +125,15 @@ void __init omap2_set_globals_sdrc(struct
>> omap_globals
>> *omap2_globals)
>>
>>  /**
>>   * omap2_sdrc_init - initialize SMS, SDRC devices on boot
>> - * @sp: pointer to a null-terminated list of struct omap_sdrc_params
>> + * @sdrc_cs[01]: pointers to a null-terminated list of struct
>> omap_sdrc_params
>> + *  Support for 2 chip selects timings
>>   *
>>   * Turn on smart idle modes for SDRAM scheduler and controller.
>>   * Program a known-good configuration for the SDRC to deal
>with buggy
>>   * bootloaders.
>>   */
>> -void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
>> +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>> +                        struct omap_sdrc_params *sdrc_cs1)
>>  {
>>      u32 l;
>>
>> @@ -129,7 +147,8 @@ void __init omap2_sdrc_init(struct
>omap_sdrc_params *sp)
>>      l |= (0x2 << 3);
>>      sdrc_write_reg(l, SDRC_SYSCONFIG);
>>
>> -    sdrc_init_params = sp;
>> +    sdrc_init_params_cs0 = sdrc_cs0;
>> +    sdrc_init_params_cs1 = sdrc_cs1;
>>
>>      /* XXX Enable SRFRONIDLEREQ here also? */
>>      l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | diff --git
>> a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
>> index f41f8d9..3aef744 100644
>> --- a/arch/arm/mach-omap2/sram34xx.S
>> +++ b/arch/arm/mach-omap2/sram34xx.S
>> @@ -36,7 +36,7 @@
>>
>>      .text
>>
>> -/* r4 parameters */
>> +/* r1 parameters */
>>  #define SDRC_NO_UNLOCK_DLL          0x0
>>  #define SDRC_UNLOCK_DLL                     0x1
>>
>> @@ -71,40 +71,71 @@
>>
>>  /*
>>   * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
>> - * r0 = new SDRC_RFR_CTRL register contents
>> - * r1 = new SDRC_ACTIM_CTRLA register contents
>> - * r2 = new SDRC_ACTIM_CTRLB register contents
>> - * r3 = new M2 divider setting (only 1 and 2 supported right now)
>> - * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
>> + *
>> + * Params passed in registers:
>> + *  r0 = new M2 divider setting (only 1 and 2 supported right now)
>> + *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
>>   *      SDRC rates < 83MHz
>> - * r5 = number of MPU cycles to wait for SDRC to stabilize after
>> + *  r2 = number of MPU cycles to wait for SDRC to stabilize after
>>   *      reprogramming the SDRC when switching to a slower MPU speed
>> - * r6 = new SDRC_MR_0 register value
>> - * r7 = increasing SDRC rate? (1 = yes, 0 = no)
>> + *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
>> + *
>> + * Params passed via the stack. The needed params will be copied in
>> + SRAM
>> + *  before use by the code in SRAM (SDRAM is not accessible during
>> + SDRC
>> + *  reconfiguration):
>> + *  new SDRC_RFR_CTRL_0 register contents
>> + *  new SDRC_ACTIM_CTRL_A_0 register contents
>> + *  new SDRC_ACTIM_CTRL_B_0 register contents
>> + *  new SDRC_MR_0 register value
>> + *  new SDRC_RFR_CTRL_1 register contents
>> + *  new SDRC_ACTIM_CTRL_A_1 register contents
>> + *  new SDRC_ACTIM_CTRL_B_1 register contents
>> + *  new SDRC_MR_1 register value
>>   *
>> + * If the param SDRC_RFR_CTRL_1 is 0, the parameters
>> + *  are not programmed into the SDRC CS1 registers
>>   */
>>  ENTRY(omap3_sram_configure_core_dpll)
>>      stmfd   sp!, {r1-r12, lr}       @ store regs to stack
>> -    ldr     r4, [sp, #52]           @ pull extra args off the stack
>> -    ldr     r5, [sp, #56]           @ load extra args from the stack
>> -    ldr     r6, [sp, #60]           @ load extra args from the stack
>> -    ldr     r7, [sp, #64]           @ load extra args from the stack
>> +
>> +                                    @ pull the extra args
>off the stack
>> +                                    @  and store them in SRAM
>> +    ldr     r4, [sp, #52]
>> +    str     r4, omap_sdrc_rfr_ctrl_0_val
>> +    ldr     r4, [sp, #56]
>> +    str     r4, omap_sdrc_actim_ctrl_a_0_val
>> +    ldr     r4, [sp, #60]
>> +    str     r4, omap_sdrc_actim_ctrl_b_0_val
>> +    ldr     r4, [sp, #64]
>> +    str     r4, omap_sdrc_mr_0_val
>> +    ldr     r4, [sp, #68]
>> +    str     r4, omap_sdrc_rfr_ctrl_1_val
>> +    cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
>> +    beq     skip_cs1_params         @  do not use cs1 params
>> +    ldr     r4, [sp, #72]
>> +    str     r4, omap_sdrc_actim_ctrl_a_1_val
>> +    ldr     r4, [sp, #76]
>> +    str     r4, omap_sdrc_actim_ctrl_b_1_val
>> +    ldr     r4, [sp, #80]
>> +    str     r4, omap_sdrc_mr_1_val
>> +skip_cs1_params:
>>      dsb                             @ flush buffered writes
>to interconnect
>> -    cmp     r7, #1                  @ if increasing SDRC clk rate,
>> +
>> +    cmp     r3, #1                  @ if increasing SDRC clk rate,
>>      bleq    configure_sdrc          @ program the SDRC regs
>early (for RFR)
>> -    cmp     r4, #SDRC_UNLOCK_DLL    @ set the intended DLL state
>> +    cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
>>      bleq    unlock_dll
>>      blne    lock_dll
>>      bl      sdram_in_selfrefresh    @ put SDRAM in self
>refresh, idle SDRC
>>      bl      configure_core_dpll     @ change the DPLL3 M2 divider
>>      bl      enable_sdrc             @ take SDRC out of idle
>> -    cmp     r4, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
>> +    cmp     r1, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
>>      bleq    wait_dll_unlock
>>      blne    wait_dll_lock
>> -    cmp     r7, #1                  @ if increasing SDRC clk rate,
>> +    cmp     r3, #1                  @ if increasing SDRC clk rate,
>>      beq     return_to_sdram         @ return to SDRAM code,
>otherwise,
>>      bl      configure_sdrc          @ reprogram SDRC regs now
>> -    mov     r12, r5
>> +    mov     r12, r2
>>      bl      wait_clk_stable         @ wait for SDRC to stabilize
>>  return_to_sdram:
>>      isb                             @ prevent speculative
>exec past here
>> @@ -149,7 +180,7 @@ configure_core_dpll:
>>      ldr     r12, [r11]
>>      ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
>>      and     r12, r12, r10
>> -    orr     r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
>> +    orr     r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
>>      str     r12, [r11]
>>      ldr     r12, [r11]              @ posted-write barrier for CM
>>      bx      lr
>> @@ -187,15 +218,34 @@ wait_dll_unlock:
>>      bne     wait_dll_unlock
>>      bx      lr
>>  configure_sdrc:
>> -    ldr     r11, omap3_sdrc_rfr_ctrl
>> -    str     r0, [r11]
>> -    ldr     r11, omap3_sdrc_actim_ctrla
>> -    str     r1, [r11]
>> -    ldr     r11, omap3_sdrc_actim_ctrlb
>> -    str     r2, [r11]
>> +    ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
>> +    ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
>> +    str     r12, [r11]                      @ store
>> +    ldr     r12, omap_sdrc_actim_ctrl_a_0_val
>> +    ldr     r11, omap3_sdrc_actim_ctrl_a_0
>> +    str     r12, [r11]
>> +    ldr     r12, omap_sdrc_actim_ctrl_b_0_val
>> +    ldr     r11, omap3_sdrc_actim_ctrl_b_0
>> +    str     r12, [r11]
>> +    ldr     r12, omap_sdrc_mr_0_val
>>      ldr     r11, omap3_sdrc_mr_0
>> -    str     r6, [r11]
>> -    ldr     r6, [r11]               @ posted-write barrier for SDRC
>> +    str     r12, [r11]
>> +    ldr     r12, omap_sdrc_rfr_ctrl_1_val
>> +    cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
>> +    beq     skip_cs1_prog           @  do not program cs1 params
>> +    ldr     r11, omap3_sdrc_rfr_ctrl_1
>> +    str     r12, [r11]
>> +    ldr     r12, omap_sdrc_actim_ctrl_a_1_val
>> +    ldr     r11, omap3_sdrc_actim_ctrl_a_1
>> +    str     r12, [r11]
>> +    ldr     r12, omap_sdrc_actim_ctrl_b_1_val
>> +    ldr     r11, omap3_sdrc_actim_ctrl_b_1
>> +    str     r12, [r11]
>> +    ldr     r12, omap_sdrc_mr_1_val
>> +    ldr     r11, omap3_sdrc_mr_1
>> +    str     r12, [r11]
>> +skip_cs1_prog:
>> +    ldr     r12, [r11]              @ posted-write barrier for SDRC
>>      bx      lr
>>
>>  omap3_sdrc_power:
>> @@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
>>      .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
>>  omap3_cm_iclken1_core:
>>      .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
>> -omap3_sdrc_rfr_ctrl:
>> +
>> +omap3_sdrc_rfr_ctrl_0:
>>      .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
>> -omap3_sdrc_actim_ctrla:
>> +omap3_sdrc_rfr_ctrl_1:
>> +    .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
>> +omap3_sdrc_actim_ctrl_a_0:
>>      .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
>> -omap3_sdrc_actim_ctrlb:
>> +omap3_sdrc_actim_ctrl_a_1:
>> +    .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
>> +omap3_sdrc_actim_ctrl_b_0:
>>      .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
>> +omap3_sdrc_actim_ctrl_b_1:
>> +    .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
>>  omap3_sdrc_mr_0:
>>      .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
>> +omap3_sdrc_mr_1:
>> +    .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
>> +omap_sdrc_rfr_ctrl_0_val:
>> +    .word 0xDEADBEEF
>> +omap_sdrc_rfr_ctrl_1_val:
>> +    .word 0xDEADBEEF
>> +omap_sdrc_actim_ctrl_a_0_val:
>> +    .word 0xDEADBEEF
>> +omap_sdrc_actim_ctrl_a_1_val:
>> +    .word 0xDEADBEEF
>> +omap_sdrc_actim_ctrl_b_0_val:
>> +    .word 0xDEADBEEF
>> +omap_sdrc_actim_ctrl_b_1_val:
>> +    .word 0xDEADBEEF
>> +omap_sdrc_mr_0_val:
>> +    .word 0xDEADBEEF
>> +omap_sdrc_mr_1_val:
>> +    .word 0xDEADBEEF
>> +
>>  omap3_sdrc_dlla_status:
>>      .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>>  omap3_sdrc_dlla_ctrl:
>> @@ -223,3 +299,4 @@ core_m2_mask_val:
>>
>>  ENTRY(omap3_sram_configure_core_dpll_sz)
>>      .word   . - omap3_sram_configure_core_dpll
>> +
>> diff --git a/arch/arm/plat-omap/include/mach/io.h
>> b/arch/arm/plat-omap/include/mach/io.h
>> index 54c159b..d4c78b4 100644
>> --- a/arch/arm/plat-omap/include/mach/io.h
>> +++ b/arch/arm/plat-omap/include/mach/io.h
>> @@ -192,7 +192,8 @@ extern void omap1_map_common_io(void);  extern
>> void omap1_init_common_hw(void);
>>
>>  extern void omap2_map_common_io(void); -extern void
>> omap2_init_common_hw(struct omap_sdrc_params *sp,
>> +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
>> +                             struct omap_sdrc_params *sdrc_cs1,
>>                               struct omap_opp *mpu_opps,
>>                               struct omap_opp *dsp_opps,
>>                               struct omap_opp *l3_opps);
>> diff --git a/arch/arm/plat-omap/include/mach/mux.h
>> b/arch/arm/plat-omap/include/mach/mux.h
>> index f7e298a..7368aba 100644
>> --- a/arch/arm/plat-omap/include/mach/mux.h
>> +++ b/arch/arm/plat-omap/include/mach/mux.h
>> @@ -803,6 +803,10 @@ enum omap34xx_index {
>>      AE5_34XX_GPIO143,
>>      H19_34XX_GPIO164_OUT,
>>      J25_34XX_GPIO170,
>> +
>> +    /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
>> +    H16_34XX_SDRC_CKE0,
>> +    H17_34XX_SDRC_CKE1,
>>  };
>>
>>  struct omap_mux_cfg {
>> diff --git a/arch/arm/plat-omap/include/mach/sdrc.h
>> b/arch/arm/plat-omap/include/mach/sdrc.h
>> index a678bc8..7e22143 100644
>> --- a/arch/arm/plat-omap/include/mach/sdrc.h
>> +++ b/arch/arm/plat-omap/include/mach/sdrc.h
>> @@ -114,9 +114,11 @@ struct omap_sdrc_params {
>>
>>  void omap2_sms_save_context(void);
>>  void omap2_sms_restore_context(void); -void __init
>> omap2_sdrc_init(struct omap_sdrc_params *); -struct omap_sdrc_params
>> *omap2_sdrc_get_params(unsigned long r);
>> -
>> +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>> +                        struct omap_sdrc_params *sdrc_cs1); int
>> +omap2_sdrc_get_params(unsigned long r,
>> +                      struct omap_sdrc_params **sdrc_cs0,
>> +                      struct omap_sdrc_params **sdrc_cs1);
>>  #ifdef CONFIG_ARCH_OMAP2
>>
>>  struct memory_timings {
>> diff --git a/arch/arm/plat-omap/include/mach/sram.h
>> b/arch/arm/plat-omap/include/mach/sram.h
>> index ad0a600..98906ea 100644
>> --- a/arch/arm/plat-omap/include/mach/sram.h
>> +++ b/arch/arm/plat-omap/include/mach/sram.h
>> @@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32
>> perf_level, u32 dll_val,
>>                                    u32 mem_type);
>>  extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int
>> bypass);
>>
>> -extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
>> -                                 u32 sdrc_actim_ctrla,
>> -                                 u32 sdrc_actim_ctrlb, u32 m2,
>> -                                 u32 unlock_dll, u32 f, u32 sdrc_mr,
>> -                                 u32 inc);
>> +extern u32 omap3_configure_core_dpll(
>> +                    u32 m2, u32 unlock_dll, u32 f, u32 inc,
>> +                    u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
>> +                    u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>> +                    u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
>> +                    u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>> +
>>  extern void omap3_sram_restore_context(void);
>>
>>  /* Do not use these */
>> @@ -61,11 +63,12 @@ extern void omap243x_sram_reprogram_sdrc(u32
>> perf_level,
>> u32 dll_val,
>>  extern unsigned long omap243x_sram_reprogram_sdrc_sz;
>>
>>
>> -extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
>> -                                      u32 sdrc_actim_ctrla,
>> -                                      u32 sdrc_actim_ctrlb, u32 m2,
>> -                                      u32 unlock_dll, u32
>f, u32 sdrc_mr,
>> -                                      u32 inc);
>> +extern u32 omap3_sram_configure_core_dpll(
>> +                    u32 m2, u32 unlock_dll, u32 f, u32 inc,
>> +                    u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
>> +                    u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>> +                    u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
>> +                    u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>>  extern unsigned long omap3_sram_configure_core_dpll_sz;
>>
>>  #ifdef CONFIG_PM
>> diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
>> index a2e60e7..517f45b 100644
>> --- a/arch/arm/plat-omap/sram.c
>> +++ b/arch/arm/plat-omap/sram.c
>> @@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
>>
>>  #ifdef CONFIG_ARCH_OMAP3
>>
>> -static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
>> -                                          u32 sdrc_actim_ctrla,
>> -                                          u32 sdrc_actim_ctrlb,
>> -                                          u32 m2, u32 unlock_dll,
>> -                                          u32 f, u32
>sdrc_mr, u32 inc);
>> -u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32
>sdrc_actim_ctrla,
>> -                          u32 sdrc_actim_ctrlb, u32 m2, u32
>unlock_dll,
>> -                          u32 f, u32 sdrc_mr, u32 inc)
>> - {
>> +static u32 (*_omap3_sram_configure_core_dpll)(
>> +                            u32 m2, u32 unlock_dll, u32 f, u32 inc,
>> +                            u32 sdrc_rfr_ctrl_0, u32
>sdrc_actim_ctrl_a_0,
>> +                            u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>> +                            u32 sdrc_rfr_ctrl_1, u32
>sdrc_actim_ctrl_a_1,
>> +                            u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>> +
>> +u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32
>f, u32 inc,
>> +                          u32 sdrc_rfr_ctrl_0, u32
>sdrc_actim_ctrl_a_0,
>> +                          u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>> +                          u32 sdrc_rfr_ctrl_1, u32
>sdrc_actim_ctrl_a_1,
>> +                          u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1) {
>>      if (!_omap3_sram_configure_core_dpll)
>>              omap_sram_error();
>>
>> -    return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
>> -                                           sdrc_actim_ctrla,
>> -                                           sdrc_actim_ctrlb, m2,
>> -                                           unlock_dll, f,
>sdrc_mr, inc);
>> - }
>> +    return _omap3_sram_configure_core_dpll(
>> +                            m2, unlock_dll, f, inc,
>> +                            sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
>> +                            sdrc_actim_ctrl_b_0, sdrc_mr_0,
>> +                            sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
>> +                            sdrc_actim_ctrl_b_1, sdrc_mr_1);
>> +}
>>
>>  #ifdef CONFIG_PM
>>  void omap3_sram_restore_context(void)
>> --
>> 1.6.2.5.168.g3823
>>
>>
>>
>> On Wednesday 03 June 2009 01:40:13 Paul Walmsley wrote:
>> > Hi Jean,
>> >
>> > a minor request: it is easier to comment on these patches if they
>> > are included inline in the E-mail message, rather than attached.
>> > That way code comments can be inlined in the reply.
>> >
>> > On Tue, 26 May 2009, Jean Pihet wrote:
>> > > Here is a patch for the SDRC 2nd CS support. It applies
>on top of
>> > > the current pm branch.
>> >
>> > Thanks for doing this work.
>> >
>> > > I have some questions:
>> > > - Is it OK to copy the micron sdram params file to a new
>file with
>> > > the 2 CSes params? One could use a unique file with
>#ifdef SDRC_SUPPORT_2_CSES.
>> >
>> > Is it possible for the SDRAM parameter files to remain unchanged,
>> > and to simply pass two struct omap_sdrc_params * to
>> > omap2_init_common_hw() and then to omap2_sdrc_init()?  Boards with
>> > only CS0 in use should pass NULL for the second omap_sdrc_params *.
>> >
>> > So something like this (I realize the PM branch has additional
>> > parameters here also):
>> >
>> > void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
>> >                                  struct omap_sdrc_params *sdrc_cs1)
>> >
>> > Then:
>> >
>> > void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>> >                             struct omap_sdrc_params *sdrc_cs1)
>> >
>> > I would prefer that approach.
>> >
>> > It would also be good to avoid changing the SDRC CS1 parameters in
>> > the SRAM code if the board does not use CS1.  Maybe pass in a flag
>> > that indicates whether CS1 is in use, and if not, avoid
>programming
>> > those registers?  The (admittedly minor) overhead of
>loading the CS1
>> > registers off the stack would be nice to avoid also.
>> >
>> > > - Does the RX51 board have 2 sdram parts? If so I need to update
>> > > the board file as well.
>> >
>> > Probably best if someone from Nokia handles this.
>> >
>> >
>> > - Paul
>>
>>
>
>
>- Paul
>

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Jean Pihet]

Paul,

Here is the updated patch that fixes the Overo build as well.
Can you check it?

Kevin, can you push it if it is correct?

Regards,
Jean

>From ebe57354b04444de059e1f042e0c488f761853f0 Mon Sep 17 00:00:00 2001
From: Jean Pihet <jpihet@mvista.com>
Date: Fri, 5 Jun 2009 17:19:00 +0200
Subject: OMAP3: add support for 2 SDRAM chip selects

Some boards (Beagle Cx, Overo) have 2 SDRAM parts
connected to the SDRC.

This patch adds the following:
- ensure that the CKE signals mux settings are correct
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw. Only Beagle and Overo are using the 2 CS'es
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers

Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).

Thanks to Paul Walmsley and Kevin Hilman for the suggestions
and code reviews.

Signed-off-by: Jean Pihet <jpihet@mvista.com>
---
 arch/arm/mach-omap2/board-2430sdp.c      |    2 +-
 arch/arm/mach-omap2/board-3430sdp.c      |    6 +-
 arch/arm/mach-omap2/board-apollon.c      |    2 +-
 arch/arm/mach-omap2/board-generic.c      |    2 +-
 arch/arm/mach-omap2/board-h4.c           |    2 +-
 arch/arm/mach-omap2/board-ldp.c          |    2 +-
 arch/arm/mach-omap2/board-n800.c         |    2 +-
 arch/arm/mach-omap2/board-omap2evm.c     |    2 +-
 arch/arm/mach-omap2/board-omap3beagle.c  |   11 ++-
 arch/arm/mach-omap2/board-omap3evm.c     |    6 +-
 arch/arm/mach-omap2/board-omap3pandora.c |    3 +-
 arch/arm/mach-omap2/board-overo.c        |    9 ++-
 arch/arm/mach-omap2/board-rx51.c         |    6 +-
 arch/arm/mach-omap2/clock34xx.c          |   37 ++++++--
 arch/arm/mach-omap2/io.c                 |    5 +-
 arch/arm/mach-omap2/mux.c                |    6 ++
 arch/arm/mach-omap2/sdrc.c               |   63 +++++++++-----
 arch/arm/mach-omap2/sram34xx.S           |  137 
+++++++++++++++++++++++-------
 arch/arm/plat-omap/include/mach/io.h     |    3 +-
 arch/arm/plat-omap/include/mach/mux.h    |    4 +
 arch/arm/plat-omap/include/mach/sdrc.h   |    8 +-
 arch/arm/plat-omap/include/mach/sram.h   |   23 +++--
 arch/arm/plat-omap/sram.c                |   34 +++++---
 23 files changed, 267 insertions(+), 108 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c 
b/arch/arm/mach-omap2/board-2430sdp.c
index aa5df72..4cb7bc5 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -322,7 +322,7 @@ out:
 
 static void __init omap_2430sdp_init_irq(void)
 {
-	omap2_init_common_hw(NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	sdp2430_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-3430sdp.c 
b/arch/arm/mach-omap2/board-3430sdp.c
index 195b749..24e2728 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -302,8 +302,10 @@ static inline void __init sdp3430_init_smc91x(void)
 
 static void __init omap_3430sdp_init_irq(void)
 {
-	omap2_init_common_hw(hyb18m512160af6_sdrc_params, omap3_mpu_rate_table,
-			     omap3_dsp_rate_table, omap3_l3_rate_table);
+	omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL,
+			     omap3_mpu_rate_table,
+			     omap3_dsp_rate_table,
+			     omap3_l3_rate_table);
 	omap_init_irq();
 	omap_gpio_init();
 	sdp3430_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-apollon.c 
b/arch/arm/mach-omap2/board-apollon.c
index 2e24812..2dd1350 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -323,7 +323,7 @@ out:
 
 static void __init omap_apollon_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c 
b/arch/arm/mach-omap2/board-generic.c
index be763a9..763329b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
 
 static void __init omap_generic_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8f54939..17c3599 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -348,7 +348,7 @@ static void __init h4_init_flash(void)
 
 static void __init omap_h4_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 9f41dc9..b012806 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -344,7 +344,7 @@ static inline void __init ldp_init_smc911x(void)
 
 static void __init omap_ldp_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	ldp_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-n800.c 
b/arch/arm/mach-omap2/board-n800.c
index ac7cf3f..ad53f4a 100644
--- a/arch/arm/mach-omap2/board-n800.c
+++ b/arch/arm/mach-omap2/board-n800.c
@@ -127,7 +127,7 @@ static struct lm8323_platform_data lm8323_pdata = {
 
 void __init nokia_n800_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 
diff --git a/arch/arm/mach-omap2/board-omap2evm.c 
b/arch/arm/mach-omap2/board-omap2evm.c
index 4fac1be..56a26d4 100644
--- a/arch/arm/mach-omap2/board-omap2evm.c
+++ b/arch/arm/mach-omap2/board-omap2evm.c
@@ -276,7 +276,7 @@ static struct twl4030_keypad_data omap2evm_kp_data = {
 
 static void __init omap2_evm_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL, NULL, NULL);
+	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 	omap2evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c 
b/arch/arm/mach-omap2/board-omap3beagle.c
index 7294dbf..872beb6 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -312,8 +312,11 @@ static int __init omap3_beagle_i2c_init(void)
 
 static void __init omap3_beagle_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
-			     omap3_dsp_rate_table, omap3_l3_rate_table);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+			     mt46h32m32lf6_sdrc_params,
+			     omap3_mpu_rate_table,
+			     omap3_dsp_rate_table,
+			     omap3_l3_rate_table);
 	omap_init_irq();
 	omap_gpio_init();
 }
@@ -441,6 +444,10 @@ static void __init omap3_beagle_init(void)
 	usb_musb_init();
 	usb_ehci_init();
 	omap3beagle_flash_init();
+
+	/* Ensure SDRC pins are mux'd for self-refresh */
+	omap_cfg_reg(H16_34XX_SDRC_CKE0);
+	omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c 
b/arch/arm/mach-omap2/board-omap3evm.c
index f017f0d..3b9c96a 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -276,8 +276,10 @@ struct spi_board_info omap3evm_spi_board_info[] = {
 
 static void __init omap3_evm_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
-	                     omap3_dsp_rate_table, omap3_l3_rate_table);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
+			     omap3_mpu_rate_table,
+			     omap3_dsp_rate_table,
+			     omap3_l3_rate_table);
 	omap_init_irq();
 	omap_gpio_init();
 	omap3evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c 
b/arch/arm/mach-omap2/board-omap3pandora.c
index c67f62f..05ab99e 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -220,7 +220,8 @@ static int __init omap3pandora_i2c_init(void)
 
 static void __init omap3pandora_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
+			     NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/board-overo.c 
b/arch/arm/mach-omap2/board-overo.c
index 9eae608..50902d4 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -45,6 +45,7 @@
 #include <mach/gpmc.h>
 #include <mach/hardware.h>
 #include <mach/nand.h>
+#include <mach/mux.h>
 #include <mach/usb.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -355,7 +356,9 @@ static int __init overo_i2c_init(void)
 
 static void __init overo_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL, NULL, NULL);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+			     mt46h32m32lf6_sdrc_params,
+			     NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
 }
@@ -391,6 +394,10 @@ static void __init overo_init(void)
 	overo_init_smsc911x();
 	overo_ads7846_init();
 
+	/* Ensure SDRC pins are mux'd for self-refresh */
+	omap_cfg_reg(H16_34XX_SDRC_CKE0);
+	omap_cfg_reg(H17_34XX_SDRC_CKE1);
+
 	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
 			  "OVERO_GPIO_W2W_NRESET") == 0) &&
 	    (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
diff --git a/arch/arm/mach-omap2/board-rx51.c 
b/arch/arm/mach-omap2/board-rx51.c
index 09035b0..d48459f 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -64,8 +64,10 @@ static struct omap_board_config_kernel rx51_config[] = {
 
 static void __init rx51_init_irq(void)
 {
-	omap2_init_common_hw(rx51_get_sdram_timings(), omap3_mpu_rate_table,
-			     omap3_dsp_rate_table, omap3_l3_rate_table);
+	omap2_init_common_hw(rx51_get_sdram_timings(), NULL,
+			     omap3_mpu_rate_table,
+			     omap3_dsp_rate_table,
+			     omap3_l3_rate_table);
 	omap_init_irq();
 	omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 3cee6b4..f262787 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -478,7 +478,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
unsigned long rate)
 	u32 unlock_dll = 0;
 	u32 c;
 	unsigned long validrate, sdrcrate, mpurate;
-	struct omap_sdrc_params *sp;
+	struct omap_sdrc_params *sdrc_cs0;
+	struct omap_sdrc_params *sdrc_cs1;
+	int ret;
 
 	if (!clk || !rate)
 		return -EINVAL;
@@ -496,8 +498,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
unsigned long rate)
 	else
 		sdrcrate >>= ((clk->rate / rate) >> 1);
 
-	sp = omap2_sdrc_get_params(sdrcrate);
-	if (!sp)
+	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
+	if (ret)
 		return -EINVAL;
 
 	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
@@ -518,12 +520,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
unsigned long rate)
 
 	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 		 validrate);
-	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
-		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
-
-	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-				  sp->actim_ctrlb, new_div, unlock_dll, c,
-				  sp->mr, rate > clk->rate);
+	pr_debug("clock: SDRC CS0 timing params used:"
+		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
+	if (sdrc_cs1)
+		pr_debug("clock: SDRC CS1 timing params used: "
+		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+		 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+		 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+
+	if (sdrc_cs1)
+		omap3_configure_core_dpll(
+				  new_div, unlock_dll, c, rate > clk->rate,
+				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+	else
+		omap3_configure_core_dpll(
+				  new_div, unlock_dll, c, rate > clk->rate,
+				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+				  0, 0, 0, 0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 6fb6c29..aa000b4 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -231,7 +231,8 @@ static int __init _omap2_init_reprogram_sdrc(void)
 	return v;
 }
 
-void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
+void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+				 struct omap_sdrc_params *sdrc_cs1,
 				 struct omap_opp *mpu_opps,
 				 struct omap_opp *dsp_opps,
 				 struct omap_opp *l3_opps)
@@ -244,7 +245,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params 
*sp,
 	omapdev_init(omapdevs);
 	omap2_clk_init();
 	omap_pm_if_init();
-	omap2_sdrc_init(sp);
+	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
 
 	_omap2_init_reprogram_sdrc();
 
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc..43d6b92 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
 		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
 		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+
+/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
+		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
+		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
 };
 
 #define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index c832d83..b42f5ae 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -32,7 +32,7 @@
 #include <mach/sdrc.h>
 #include "sdrc.h"
 
-static struct omap_sdrc_params *sdrc_init_params;
+static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
 
 void __iomem *omap2_sdrc_base;
 void __iomem *omap2_sms_base;
@@ -71,33 +71,49 @@ void omap2_sms_restore_context(void)
 /**
  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  * @r: SDRC clock rate (in Hz)
+ * @sdrc_cs0: chip select 0 ram timings **
+ * @sdrc_cs1: chip select 1 ram timings **
  *
  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
- * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
- * SDRC clock rate 'r'.  These parameters control various timing
- * delays in the SDRAM controller that are expressed in terms of the
- * number of SDRC clock cycles to wait; hence the clock rate
- * dependency. Note that sdrc_init_params must be sorted rate
- * descending.  Also assumes that both chip-selects use the same
- * timing parameters.  Returns a struct omap_sdrc_params * upon
- * success, or NULL upon failure.
+ *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
+ *  structs,for a given SDRC clock rate 'r'.
+ * These parameters control various timing delays in the SDRAM controller
+ *  that are expressed in terms of the number of SDRC clock cycles to
+ *  wait; hence the clock rate dependency.
+ *
+ * Supports 2 different timing parameters for both chip selects.
+ *
+ * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
+ * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
+ *  as sdrc_init_params_cs_0.
+ *
+ * Fills in the struct omap_sdrc_params * for each chip select.
+ * Returns 0 upon success or -1 upon failure.
  */
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
+int omap2_sdrc_get_params(unsigned long r,
+			  struct omap_sdrc_params **sdrc_cs0,
+			  struct omap_sdrc_params **sdrc_cs1)
 {
-	struct omap_sdrc_params *sp;
+	struct omap_sdrc_params *sp0, *sp1;
 
-	if (!sdrc_init_params)
-		return NULL;
+	if (!sdrc_init_params_cs0)
+		return -1;
 
-	sp = sdrc_init_params;
+	sp0 = sdrc_init_params_cs0;
+	sp1 = sdrc_init_params_cs1;
 
-	while (sp->rate && sp->rate != r)
-		sp++;
+	while (sp0->rate && sp0->rate != r) {
+		sp0++;
+		if (sdrc_init_params_cs1)
+			sp1++;
+	}
 
-	if (!sp->rate)
-		return NULL;
+	if (!sp0->rate)
+		return -1;
 
-	return sp;
+	*sdrc_cs0 = sp0;
+	*sdrc_cs1 = sp1;
+	return 0;
 }
 
 
@@ -109,13 +125,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals 
*omap2_globals)
 
 /**
  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
- * @sp: pointer to a null-terminated list of struct omap_sdrc_params
+ * @sdrc_cs[01]: pointers to a null-terminated list of struct 
omap_sdrc_params
+ *  Support for 2 chip selects timings
  *
  * Turn on smart idle modes for SDRAM scheduler and controller.
  * Program a known-good configuration for the SDRC to deal with buggy
  * bootloaders.
  */
-void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+			    struct omap_sdrc_params *sdrc_cs1)
 {
 	u32 l;
 
@@ -129,7 +147,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
 	l |= (0x2 << 3);
 	sdrc_write_reg(l, SDRC_SYSCONFIG);
 
-	sdrc_init_params = sp;
+	sdrc_init_params_cs0 = sdrc_cs0;
+	sdrc_init_params_cs1 = sdrc_cs1;
 
 	/* XXX Enable SRFRONIDLEREQ here also? */
 	l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index f41f8d9..3aef744 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -36,7 +36,7 @@
 
 	.text
 
-/* r4 parameters */
+/* r1 parameters */
 #define SDRC_NO_UNLOCK_DLL		0x0
 #define SDRC_UNLOCK_DLL			0x1
 
@@ -71,40 +71,71 @@
 
 /*
  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
- * r0 = new SDRC_RFR_CTRL register contents
- * r1 = new SDRC_ACTIM_CTRLA register contents
- * r2 = new SDRC_ACTIM_CTRLB register contents
- * r3 = new M2 divider setting (only 1 and 2 supported right now)
- * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
+ *
+ * Params passed in registers:
+ *  r0 = new M2 divider setting (only 1 and 2 supported right now)
+ *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  *      SDRC rates < 83MHz
- * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
- * r6 = new SDRC_MR_0 register value
- * r7 = increasing SDRC rate? (1 = yes, 0 = no)
+ *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
+ *
+ * Params passed via the stack. The needed params will be copied in SRAM
+ *  before use by the code in SRAM (SDRAM is not accessible during SDRC
+ *  reconfiguration):
+ *  new SDRC_RFR_CTRL_0 register contents
+ *  new SDRC_ACTIM_CTRL_A_0 register contents
+ *  new SDRC_ACTIM_CTRL_B_0 register contents
+ *  new SDRC_MR_0 register value
+ *  new SDRC_RFR_CTRL_1 register contents
+ *  new SDRC_ACTIM_CTRL_A_1 register contents
+ *  new SDRC_ACTIM_CTRL_B_1 register contents
+ *  new SDRC_MR_1 register value
  *
+ * If the param SDRC_RFR_CTRL_1 is 0, the parameters
+ *  are not programmed into the SDRC CS1 registers
  */
 ENTRY(omap3_sram_configure_core_dpll)
 	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
-	ldr	r4, [sp, #52]		@ pull extra args off the stack
-	ldr	r5, [sp, #56]		@ load extra args from the stack
-	ldr	r6, [sp, #60]		@ load extra args from the stack
-	ldr	r7, [sp, #64]		@ load extra args from the stack
+
+					@ pull the extra args off the stack
+					@  and store them in SRAM
+	ldr	r4, [sp, #52]
+	str     r4, omap_sdrc_rfr_ctrl_0_val
+	ldr	r4, [sp, #56]
+	str     r4, omap_sdrc_actim_ctrl_a_0_val
+	ldr	r4, [sp, #60]
+	str     r4, omap_sdrc_actim_ctrl_b_0_val
+	ldr	r4, [sp, #64]
+	str     r4, omap_sdrc_mr_0_val
+	ldr	r4, [sp, #68]
+	str     r4, omap_sdrc_rfr_ctrl_1_val
+	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
+	beq	skip_cs1_params		@  do not use cs1 params
+	ldr	r4, [sp, #72]
+	str     r4, omap_sdrc_actim_ctrl_a_1_val
+	ldr	r4, [sp, #76]
+	str     r4, omap_sdrc_actim_ctrl_b_1_val
+	ldr	r4, [sp, #80]
+	str     r4, omap_sdrc_mr_1_val
+skip_cs1_params:
 	dsb				@ flush buffered writes to interconnect
-	cmp	r7, #1			@ if increasing SDRC clk rate,
+
+	cmp	r3, #1			@ if increasing SDRC clk rate,
 	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
-	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
+	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
 	bleq	unlock_dll
 	blne	lock_dll
 	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
 	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
 	bl	enable_sdrc		@ take SDRC out of idle
-	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
+	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
 	bleq	wait_dll_unlock
 	blne	wait_dll_lock
-	cmp	r7, #1			@ if increasing SDRC clk rate,
+	cmp	r3, #1			@ if increasing SDRC clk rate,
 	beq	return_to_sdram		@ return to SDRAM code, otherwise,
 	bl	configure_sdrc		@ reprogram SDRC regs now
-	mov	r12, r5
+	mov	r12, r2
 	bl	wait_clk_stable		@ wait for SDRC to stabilize
 return_to_sdram:
 	isb				@ prevent speculative exec past here
@@ -149,7 +180,7 @@ configure_core_dpll:
 	ldr	r12, [r11]
 	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
 	and	r12, r12, r10
-	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
+	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
 	str	r12, [r11]
 	ldr	r12, [r11]		@ posted-write barrier for CM
 	bx	lr
@@ -187,15 +218,34 @@ wait_dll_unlock:
 	bne	wait_dll_unlock
 	bx	lr
 configure_sdrc:
-	ldr	r11, omap3_sdrc_rfr_ctrl
-	str	r0, [r11]
-	ldr	r11, omap3_sdrc_actim_ctrla
-	str	r1, [r11]
-	ldr	r11, omap3_sdrc_actim_ctrlb
-	str	r2, [r11]
+	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
+	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
+	str	r12, [r11]			@ store
+	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
+	ldr	r11, omap3_sdrc_actim_ctrl_a_0
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
+	ldr	r11, omap3_sdrc_actim_ctrl_b_0
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_mr_0_val
 	ldr	r11, omap3_sdrc_mr_0
-	str	r6, [r11]
-	ldr	r6, [r11]		@ posted-write barrier for SDRC
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_rfr_ctrl_1_val
+	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
+	beq	skip_cs1_prog		@  do not program cs1 params
+	ldr	r11, omap3_sdrc_rfr_ctrl_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
+	ldr	r11, omap3_sdrc_actim_ctrl_a_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
+	ldr	r11, omap3_sdrc_actim_ctrl_b_1
+	str	r12, [r11]
+	ldr	r12, omap_sdrc_mr_1_val
+	ldr	r11, omap3_sdrc_mr_1
+	str	r12, [r11]
+skip_cs1_prog:
+	ldr	r12, [r11]		@ posted-write barrier for SDRC
 	bx	lr
 
 omap3_sdrc_power:
@@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 omap3_cm_iclken1_core:
 	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
-omap3_sdrc_rfr_ctrl:
+
+omap3_sdrc_rfr_ctrl_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap3_sdrc_actim_ctrla:
+omap3_sdrc_rfr_ctrl_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
+omap3_sdrc_actim_ctrl_a_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
-omap3_sdrc_actim_ctrlb:
+omap3_sdrc_actim_ctrl_a_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
+omap3_sdrc_actim_ctrl_b_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_actim_ctrl_b_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 omap3_sdrc_mr_0:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
+omap3_sdrc_mr_1:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
+omap_sdrc_rfr_ctrl_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_rfr_ctrl_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_1_val:
+	.word 0xDEADBEEF
+omap_sdrc_mr_0_val:
+	.word 0xDEADBEEF
+omap_sdrc_mr_1_val:
+	.word 0xDEADBEEF
+
 omap3_sdrc_dlla_status:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:
@@ -223,3 +299,4 @@ core_m2_mask_val:
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
 	.word	. - omap3_sram_configure_core_dpll
+
diff --git a/arch/arm/plat-omap/include/mach/io.h 
b/arch/arm/plat-omap/include/mach/io.h
index 54c159b..d4c78b4 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -192,7 +192,8 @@ extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
 extern void omap2_map_common_io(void);
-extern void omap2_init_common_hw(struct omap_sdrc_params *sp,
+extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+				 struct omap_sdrc_params *sdrc_cs1,
 				 struct omap_opp *mpu_opps,
 				 struct omap_opp *dsp_opps,
 				 struct omap_opp *l3_opps);
diff --git a/arch/arm/plat-omap/include/mach/mux.h 
b/arch/arm/plat-omap/include/mach/mux.h
index f7e298a..7368aba 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -803,6 +803,10 @@ enum omap34xx_index {
 	AE5_34XX_GPIO143,
 	H19_34XX_GPIO164_OUT,
 	J25_34XX_GPIO170,
+
+	/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+	H16_34XX_SDRC_CKE0,
+	H17_34XX_SDRC_CKE1,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h 
b/arch/arm/plat-omap/include/mach/sdrc.h
index a678bc8..7e22143 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -114,9 +114,11 @@ struct omap_sdrc_params {
 
 void omap2_sms_save_context(void);
 void omap2_sms_restore_context(void);
-void __init omap2_sdrc_init(struct omap_sdrc_params *);
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
-
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+			    struct omap_sdrc_params *sdrc_cs1);
+int omap2_sdrc_get_params(unsigned long r,
+			  struct omap_sdrc_params **sdrc_cs0,
+			  struct omap_sdrc_params **sdrc_cs1);
 #ifdef CONFIG_ARCH_OMAP2
 
 struct memory_timings {
diff --git a/arch/arm/plat-omap/include/mach/sram.h 
b/arch/arm/plat-omap/include/mach/sram.h
index ad0a600..98906ea 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 
dll_val,
 				      u32 mem_type);
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 
-extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
-				     u32 sdrc_actim_ctrla,
-				     u32 sdrc_actim_ctrlb, u32 m2,
-				     u32 unlock_dll, u32 f, u32 sdrc_mr,
-				     u32 inc);
+extern u32 omap3_configure_core_dpll(
+			u32 m2, u32 unlock_dll, u32 f, u32 inc,
+			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
 extern void omap3_sram_restore_context(void);
 
 /* Do not use these */
@@ -61,11 +63,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, 
u32 dll_val,
 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 
 
-extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
-					  u32 sdrc_actim_ctrla,
-					  u32 sdrc_actim_ctrlb, u32 m2,
-					  u32 unlock_dll, u32 f, u32 sdrc_mr,
-					  u32 inc);
+extern u32 omap3_sram_configure_core_dpll(
+			u32 m2, u32 unlock_dll, u32 f, u32 inc,
+			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a2e60e7..517f45b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
 
 #ifdef CONFIG_ARCH_OMAP3
 
-static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
-					      u32 sdrc_actim_ctrla,
-					      u32 sdrc_actim_ctrlb,
-					      u32 m2, u32 unlock_dll,
-					      u32 f, u32 sdrc_mr, u32 inc);
-u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-			      u32 f, u32 sdrc_mr, u32 inc)
- {
+static u32 (*_omap3_sram_configure_core_dpll)(
+				u32 m2, u32 unlock_dll, u32 f, u32 inc,
+				u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+				u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+				u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+				u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+			      u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+			      u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+			      u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+			      u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
+{
 	if (!_omap3_sram_configure_core_dpll)
 		omap_sram_error();
 
-	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
-					       sdrc_actim_ctrla,
-					       sdrc_actim_ctrlb, m2,
-					       unlock_dll, f, sdrc_mr, inc);
- }
+	return _omap3_sram_configure_core_dpll(
+				m2, unlock_dll, f, inc,
+				sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+				sdrc_actim_ctrl_b_0, sdrc_mr_0,
+				sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+				sdrc_actim_ctrl_b_1, sdrc_mr_1);
+}
 
 #ifdef CONFIG_PM
 void omap3_sram_restore_context(void)
-- 
1.6.2.5.168.g3823


On Friday 05 June 2009 20:10:40 Paul Walmsley wrote:
> Hi Jean,
>
> On Fri, 5 Jun 2009, Jean Pihet wrote:
> > Here is the new patch that includes all the remarks and suggestion. The
> > description is here below.
> >
> > Some notes:
> > - all calls to omap2_init_common_hw have been adapted in the board files.
> > it looks like 2430SDP and Pandora board files are broken since they use
> > only one param. Can that be checked on those boards?
> > - it is assumed that RX51 only uses 1 CS. Is that correct?
> >
> > Can you review it and possibly merge?
>
> Looks great.
>
> Tero, does RX51 use two SDRC chipselects!
>
> Acked-by: Paul Walmsley <paul@pwsan.com>
>
> > Thanks & regards,
> > Jean
> >

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Kevin Hilman]

Jean Pihet <jpihet@mvista.com> writes:

> Paul,
>
> Here is the updated patch that fixes the Overo build as well.
> Can you check it?
>
> Kevin, can you push it if it is correct?

Can you run it through checkpatch, fix the errors and also merge Tero's
RX51 patch if it looks good to you.

Below are the checkpatch errors I get:  looks lik your mailer is
probably wrapping the patch and there is also one error to fix.

Kevin

ERROR: patch seems to be corrupt (line wrapped?)
#306: FILE: arch/arm/mach-omap2/clock34xx.c:477:
unsigned long rate)

ERROR: trailing whitespace
#494: FILE: arch/arm/mach-omap2/sdrc.c:128:
+ * @sdrc_cs[01]: pointers to a null-terminated list of struct $

total: 2 errors, 0 warnings, 648 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.


>
> Regards,
> Jean
>
> From ebe57354b04444de059e1f042e0c488f761853f0 Mon Sep 17 00:00:00 2001
> From: Jean Pihet <jpihet@mvista.com>
> Date: Fri, 5 Jun 2009 17:19:00 +0200
> Subject: OMAP3: add support for 2 SDRAM chip selects
>
> Some boards (Beagle Cx, Overo) have 2 SDRAM parts
> connected to the SDRC.
>
> This patch adds the following:
> - ensure that the CKE signals mux settings are correct
> - add a new argument of type omap_sdrc_params struct*
> to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
> - adapted the OMAP boards files to the new prototype of
> omap2_init_common_hw. Only Beagle and Overo are using the 2 CS'es
> - adapt the sram sleep code to configure the SDRC for the 2nd CS
>
> Note: If the 2nd param to omap2_init_common_hw is NULL, then the
> parameters are not programmed into the SDRC CS1 registers
>
> Tested on 3430 SDP and Beagleboard rev C2 and B5, with
> suspend/resume and frequency changes (cpufreq).
>
> Thanks to Paul Walmsley and Kevin Hilman for the suggestions
> and code reviews.
>
> Signed-off-by: Jean Pihet <jpihet@mvista.com>
> ---
>  arch/arm/mach-omap2/board-2430sdp.c      |    2 +-
>  arch/arm/mach-omap2/board-3430sdp.c      |    6 +-
>  arch/arm/mach-omap2/board-apollon.c      |    2 +-
>  arch/arm/mach-omap2/board-generic.c      |    2 +-
>  arch/arm/mach-omap2/board-h4.c           |    2 +-
>  arch/arm/mach-omap2/board-ldp.c          |    2 +-
>  arch/arm/mach-omap2/board-n800.c         |    2 +-
>  arch/arm/mach-omap2/board-omap2evm.c     |    2 +-
>  arch/arm/mach-omap2/board-omap3beagle.c  |   11 ++-
>  arch/arm/mach-omap2/board-omap3evm.c     |    6 +-
>  arch/arm/mach-omap2/board-omap3pandora.c |    3 +-
>  arch/arm/mach-omap2/board-overo.c        |    9 ++-
>  arch/arm/mach-omap2/board-rx51.c         |    6 +-
>  arch/arm/mach-omap2/clock34xx.c          |   37 ++++++--
>  arch/arm/mach-omap2/io.c                 |    5 +-
>  arch/arm/mach-omap2/mux.c                |    6 ++
>  arch/arm/mach-omap2/sdrc.c               |   63 +++++++++-----
>  arch/arm/mach-omap2/sram34xx.S           |  137 
> +++++++++++++++++++++++-------
>  arch/arm/plat-omap/include/mach/io.h     |    3 +-
>  arch/arm/plat-omap/include/mach/mux.h    |    4 +
>  arch/arm/plat-omap/include/mach/sdrc.h   |    8 +-
>  arch/arm/plat-omap/include/mach/sram.h   |   23 +++--
>  arch/arm/plat-omap/sram.c                |   34 +++++---
>  23 files changed, 267 insertions(+), 108 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-2430sdp.c 
> b/arch/arm/mach-omap2/board-2430sdp.c
> index aa5df72..4cb7bc5 100644
> --- a/arch/arm/mach-omap2/board-2430sdp.c
> +++ b/arch/arm/mach-omap2/board-2430sdp.c
> @@ -322,7 +322,7 @@ out:
>  
>  static void __init omap_2430sdp_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	sdp2430_init_smc91x();
> diff --git a/arch/arm/mach-omap2/board-3430sdp.c 
> b/arch/arm/mach-omap2/board-3430sdp.c
> index 195b749..24e2728 100644
> --- a/arch/arm/mach-omap2/board-3430sdp.c
> +++ b/arch/arm/mach-omap2/board-3430sdp.c
> @@ -302,8 +302,10 @@ static inline void __init sdp3430_init_smc91x(void)
>  
>  static void __init omap_3430sdp_init_irq(void)
>  {
> -	omap2_init_common_hw(hyb18m512160af6_sdrc_params, omap3_mpu_rate_table,
> -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> +	omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL,
> +			     omap3_mpu_rate_table,
> +			     omap3_dsp_rate_table,
> +			     omap3_l3_rate_table);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	sdp3430_init_smc91x();
> diff --git a/arch/arm/mach-omap2/board-apollon.c 
> b/arch/arm/mach-omap2/board-apollon.c
> index 2e24812..2dd1350 100644
> --- a/arch/arm/mach-omap2/board-apollon.c
> +++ b/arch/arm/mach-omap2/board-apollon.c
> @@ -323,7 +323,7 @@ out:
>  
>  static void __init omap_apollon_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	apollon_init_smc91x();
> diff --git a/arch/arm/mach-omap2/board-generic.c 
> b/arch/arm/mach-omap2/board-generic.c
> index be763a9..763329b 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -33,7 +33,7 @@
>  
>  static void __init omap_generic_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  }
>  
> diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
> index 8f54939..17c3599 100644
> --- a/arch/arm/mach-omap2/board-h4.c
> +++ b/arch/arm/mach-omap2/board-h4.c
> @@ -348,7 +348,7 @@ static void __init h4_init_flash(void)
>  
>  static void __init omap_h4_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	h4_init_flash();
> diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
> index 9f41dc9..b012806 100644
> --- a/arch/arm/mach-omap2/board-ldp.c
> +++ b/arch/arm/mach-omap2/board-ldp.c
> @@ -344,7 +344,7 @@ static inline void __init ldp_init_smc911x(void)
>  
>  static void __init omap_ldp_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	ldp_init_smc911x();
> diff --git a/arch/arm/mach-omap2/board-n800.c 
> b/arch/arm/mach-omap2/board-n800.c
> index ac7cf3f..ad53f4a 100644
> --- a/arch/arm/mach-omap2/board-n800.c
> +++ b/arch/arm/mach-omap2/board-n800.c
> @@ -127,7 +127,7 @@ static struct lm8323_platform_data lm8323_pdata = {
>  
>  void __init nokia_n800_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  
> diff --git a/arch/arm/mach-omap2/board-omap2evm.c 
> b/arch/arm/mach-omap2/board-omap2evm.c
> index 4fac1be..56a26d4 100644
> --- a/arch/arm/mach-omap2/board-omap2evm.c
> +++ b/arch/arm/mach-omap2/board-omap2evm.c
> @@ -276,7 +276,7 @@ static struct twl4030_keypad_data omap2evm_kp_data = {
>  
>  static void __init omap2_evm_init_irq(void)
>  {
> -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	omap2evm_init_smc911x();
> diff --git a/arch/arm/mach-omap2/board-omap3beagle.c 
> b/arch/arm/mach-omap2/board-omap3beagle.c
> index 7294dbf..872beb6 100644
> --- a/arch/arm/mach-omap2/board-omap3beagle.c
> +++ b/arch/arm/mach-omap2/board-omap3beagle.c
> @@ -312,8 +312,11 @@ static int __init omap3_beagle_i2c_init(void)
>  
>  static void __init omap3_beagle_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
> -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> +			     mt46h32m32lf6_sdrc_params,
> +			     omap3_mpu_rate_table,
> +			     omap3_dsp_rate_table,
> +			     omap3_l3_rate_table);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> @@ -441,6 +444,10 @@ static void __init omap3_beagle_init(void)
>  	usb_musb_init();
>  	usb_ehci_init();
>  	omap3beagle_flash_init();
> +
> +	/* Ensure SDRC pins are mux'd for self-refresh */
> +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
> +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
>  }
>  
>  static void __init omap3_beagle_map_io(void)
> diff --git a/arch/arm/mach-omap2/board-omap3evm.c 
> b/arch/arm/mach-omap2/board-omap3evm.c
> index f017f0d..3b9c96a 100644
> --- a/arch/arm/mach-omap2/board-omap3evm.c
> +++ b/arch/arm/mach-omap2/board-omap3evm.c
> @@ -276,8 +276,10 @@ struct spi_board_info omap3evm_spi_board_info[] = {
>  
>  static void __init omap3_evm_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
> -	                     omap3_dsp_rate_table, omap3_l3_rate_table);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
> +			     omap3_mpu_rate_table,
> +			     omap3_dsp_rate_table,
> +			     omap3_l3_rate_table);
>  	omap_init_irq();
>  	omap_gpio_init();
>  	omap3evm_init_smc911x();
> diff --git a/arch/arm/mach-omap2/board-omap3pandora.c 
> b/arch/arm/mach-omap2/board-omap3pandora.c
> index c67f62f..05ab99e 100644
> --- a/arch/arm/mach-omap2/board-omap3pandora.c
> +++ b/arch/arm/mach-omap2/board-omap3pandora.c
> @@ -220,7 +220,8 @@ static int __init omap3pandora_i2c_init(void)
>  
>  static void __init omap3pandora_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
> +			     NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> diff --git a/arch/arm/mach-omap2/board-overo.c 
> b/arch/arm/mach-omap2/board-overo.c
> index 9eae608..50902d4 100644
> --- a/arch/arm/mach-omap2/board-overo.c
> +++ b/arch/arm/mach-omap2/board-overo.c
> @@ -45,6 +45,7 @@
>  #include <mach/gpmc.h>
>  #include <mach/hardware.h>
>  #include <mach/nand.h>
> +#include <mach/mux.h>
>  #include <mach/usb.h>
>  
>  #include "sdram-micron-mt46h32m32lf-6.h"
> @@ -355,7 +356,9 @@ static int __init overo_i2c_init(void)
>  
>  static void __init overo_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL, NULL, NULL);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> +			     mt46h32m32lf6_sdrc_params,
> +			     NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> @@ -391,6 +394,10 @@ static void __init overo_init(void)
>  	overo_init_smsc911x();
>  	overo_ads7846_init();
>  
> +	/* Ensure SDRC pins are mux'd for self-refresh */
> +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
> +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
> +
>  	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
>  			  "OVERO_GPIO_W2W_NRESET") == 0) &&
>  	    (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
> diff --git a/arch/arm/mach-omap2/board-rx51.c 
> b/arch/arm/mach-omap2/board-rx51.c
> index 09035b0..d48459f 100644
> --- a/arch/arm/mach-omap2/board-rx51.c
> +++ b/arch/arm/mach-omap2/board-rx51.c
> @@ -64,8 +64,10 @@ static struct omap_board_config_kernel rx51_config[] = {
>  
>  static void __init rx51_init_irq(void)
>  {
> -	omap2_init_common_hw(rx51_get_sdram_timings(), omap3_mpu_rate_table,
> -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> +	omap2_init_common_hw(rx51_get_sdram_timings(), NULL,
> +			     omap3_mpu_rate_table,
> +			     omap3_dsp_rate_table,
> +			     omap3_l3_rate_table);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index 3cee6b4..f262787 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -478,7 +478,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
> unsigned long rate)
>  	u32 unlock_dll = 0;
>  	u32 c;
>  	unsigned long validrate, sdrcrate, mpurate;
> -	struct omap_sdrc_params *sp;
> +	struct omap_sdrc_params *sdrc_cs0;
> +	struct omap_sdrc_params *sdrc_cs1;
> +	int ret;
>  
>  	if (!clk || !rate)
>  		return -EINVAL;
> @@ -496,8 +498,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
> unsigned long rate)
>  	else
>  		sdrcrate >>= ((clk->rate / rate) >> 1);
>  
> -	sp = omap2_sdrc_get_params(sdrcrate);
> -	if (!sp)
> +	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
> +	if (ret)
>  		return -EINVAL;
>  
>  	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
> @@ -518,12 +520,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, 
> unsigned long rate)
>  
>  	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
>  		 validrate);
> -	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
> -		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
> -
> -	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
> -				  sp->actim_ctrlb, new_div, unlock_dll, c,
> -				  sp->mr, rate > clk->rate);
> +	pr_debug("clock: SDRC CS0 timing params used:"
> +		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
> +		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> +		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
> +	if (sdrc_cs1)
> +		pr_debug("clock: SDRC CS1 timing params used: "
> +		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
> +		 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
> +		 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
> +
> +	if (sdrc_cs1)
> +		omap3_configure_core_dpll(
> +				  new_div, unlock_dll, c, rate > clk->rate,
> +				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> +				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
> +				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
> +				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
> +	else
> +		omap3_configure_core_dpll(
> +				  new_div, unlock_dll, c, rate > clk->rate,
> +				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> +				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
> +				  0, 0, 0, 0);
>  
>  	return 0;
>  }
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 6fb6c29..aa000b4 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -231,7 +231,8 @@ static int __init _omap2_init_reprogram_sdrc(void)
>  	return v;
>  }
>  
> -void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
> +void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
> +				 struct omap_sdrc_params *sdrc_cs1,
>  				 struct omap_opp *mpu_opps,
>  				 struct omap_opp *dsp_opps,
>  				 struct omap_opp *l3_opps)
> @@ -244,7 +245,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params 
> *sp,
>  	omapdev_init(omapdevs);
>  	omap2_clk_init();
>  	omap_pm_if_init();
> -	omap2_sdrc_init(sp);
> +	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
>  
>  	_omap2_init_reprogram_sdrc();
>  
> diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
> index 026c4fc..43d6b92 100644
> --- a/arch/arm/mach-omap2/mux.c
> +++ b/arch/arm/mach-omap2/mux.c
> @@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
>  		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
>  MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
>  		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
> +
> +/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
> +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
> +		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
> +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
> +		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
>  };
>  
>  #define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)
> diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
> index c832d83..b42f5ae 100644
> --- a/arch/arm/mach-omap2/sdrc.c
> +++ b/arch/arm/mach-omap2/sdrc.c
> @@ -32,7 +32,7 @@
>  #include <mach/sdrc.h>
>  #include "sdrc.h"
>  
> -static struct omap_sdrc_params *sdrc_init_params;
> +static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
>  
>  void __iomem *omap2_sdrc_base;
>  void __iomem *omap2_sms_base;
> @@ -71,33 +71,49 @@ void omap2_sms_restore_context(void)
>  /**
>   * omap2_sdrc_get_params - return SDRC register values for a given clock rate
>   * @r: SDRC clock rate (in Hz)
> + * @sdrc_cs0: chip select 0 ram timings **
> + * @sdrc_cs1: chip select 1 ram timings **
>   *
>   * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
> - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
> - * SDRC clock rate 'r'.  These parameters control various timing
> - * delays in the SDRAM controller that are expressed in terms of the
> - * number of SDRC clock cycles to wait; hence the clock rate
> - * dependency. Note that sdrc_init_params must be sorted rate
> - * descending.  Also assumes that both chip-selects use the same
> - * timing parameters.  Returns a struct omap_sdrc_params * upon
> - * success, or NULL upon failure.
> + *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
> + *  structs,for a given SDRC clock rate 'r'.
> + * These parameters control various timing delays in the SDRAM controller
> + *  that are expressed in terms of the number of SDRC clock cycles to
> + *  wait; hence the clock rate dependency.
> + *
> + * Supports 2 different timing parameters for both chip selects.
> + *
> + * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
> + * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
> + *  as sdrc_init_params_cs_0.
> + *
> + * Fills in the struct omap_sdrc_params * for each chip select.
> + * Returns 0 upon success or -1 upon failure.
>   */
> -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
> +int omap2_sdrc_get_params(unsigned long r,
> +			  struct omap_sdrc_params **sdrc_cs0,
> +			  struct omap_sdrc_params **sdrc_cs1)
>  {
> -	struct omap_sdrc_params *sp;
> +	struct omap_sdrc_params *sp0, *sp1;
>  
> -	if (!sdrc_init_params)
> -		return NULL;
> +	if (!sdrc_init_params_cs0)
> +		return -1;
>  
> -	sp = sdrc_init_params;
> +	sp0 = sdrc_init_params_cs0;
> +	sp1 = sdrc_init_params_cs1;
>  
> -	while (sp->rate && sp->rate != r)
> -		sp++;
> +	while (sp0->rate && sp0->rate != r) {
> +		sp0++;
> +		if (sdrc_init_params_cs1)
> +			sp1++;
> +	}
>  
> -	if (!sp->rate)
> -		return NULL;
> +	if (!sp0->rate)
> +		return -1;
>  
> -	return sp;
> +	*sdrc_cs0 = sp0;
> +	*sdrc_cs1 = sp1;
> +	return 0;
>  }
>  
>  
> @@ -109,13 +125,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals 
> *omap2_globals)
>  
>  /**
>   * omap2_sdrc_init - initialize SMS, SDRC devices on boot
> - * @sp: pointer to a null-terminated list of struct omap_sdrc_params
> + * @sdrc_cs[01]: pointers to a null-terminated list of struct 
> omap_sdrc_params
> + *  Support for 2 chip selects timings
>   *
>   * Turn on smart idle modes for SDRAM scheduler and controller.
>   * Program a known-good configuration for the SDRC to deal with buggy
>   * bootloaders.
>   */
> -void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
> +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> +			    struct omap_sdrc_params *sdrc_cs1)
>  {
>  	u32 l;
>  
> @@ -129,7 +147,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
>  	l |= (0x2 << 3);
>  	sdrc_write_reg(l, SDRC_SYSCONFIG);
>  
> -	sdrc_init_params = sp;
> +	sdrc_init_params_cs0 = sdrc_cs0;
> +	sdrc_init_params_cs1 = sdrc_cs1;
>  
>  	/* XXX Enable SRFRONIDLEREQ here also? */
>  	l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
> diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
> index f41f8d9..3aef744 100644
> --- a/arch/arm/mach-omap2/sram34xx.S
> +++ b/arch/arm/mach-omap2/sram34xx.S
> @@ -36,7 +36,7 @@
>  
>  	.text
>  
> -/* r4 parameters */
> +/* r1 parameters */
>  #define SDRC_NO_UNLOCK_DLL		0x0
>  #define SDRC_UNLOCK_DLL			0x1
>  
> @@ -71,40 +71,71 @@
>  
>  /*
>   * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
> - * r0 = new SDRC_RFR_CTRL register contents
> - * r1 = new SDRC_ACTIM_CTRLA register contents
> - * r2 = new SDRC_ACTIM_CTRLB register contents
> - * r3 = new M2 divider setting (only 1 and 2 supported right now)
> - * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
> + *
> + * Params passed in registers:
> + *  r0 = new M2 divider setting (only 1 and 2 supported right now)
> + *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
>   *      SDRC rates < 83MHz
> - * r5 = number of MPU cycles to wait for SDRC to stabilize after
> + *  r2 = number of MPU cycles to wait for SDRC to stabilize after
>   *      reprogramming the SDRC when switching to a slower MPU speed
> - * r6 = new SDRC_MR_0 register value
> - * r7 = increasing SDRC rate? (1 = yes, 0 = no)
> + *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
> + *
> + * Params passed via the stack. The needed params will be copied in SRAM
> + *  before use by the code in SRAM (SDRAM is not accessible during SDRC
> + *  reconfiguration):
> + *  new SDRC_RFR_CTRL_0 register contents
> + *  new SDRC_ACTIM_CTRL_A_0 register contents
> + *  new SDRC_ACTIM_CTRL_B_0 register contents
> + *  new SDRC_MR_0 register value
> + *  new SDRC_RFR_CTRL_1 register contents
> + *  new SDRC_ACTIM_CTRL_A_1 register contents
> + *  new SDRC_ACTIM_CTRL_B_1 register contents
> + *  new SDRC_MR_1 register value
>   *
> + * If the param SDRC_RFR_CTRL_1 is 0, the parameters
> + *  are not programmed into the SDRC CS1 registers
>   */
>  ENTRY(omap3_sram_configure_core_dpll)
>  	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
> -	ldr	r4, [sp, #52]		@ pull extra args off the stack
> -	ldr	r5, [sp, #56]		@ load extra args from the stack
> -	ldr	r6, [sp, #60]		@ load extra args from the stack
> -	ldr	r7, [sp, #64]		@ load extra args from the stack
> +
> +					@ pull the extra args off the stack
> +					@  and store them in SRAM
> +	ldr	r4, [sp, #52]
> +	str     r4, omap_sdrc_rfr_ctrl_0_val
> +	ldr	r4, [sp, #56]
> +	str     r4, omap_sdrc_actim_ctrl_a_0_val
> +	ldr	r4, [sp, #60]
> +	str     r4, omap_sdrc_actim_ctrl_b_0_val
> +	ldr	r4, [sp, #64]
> +	str     r4, omap_sdrc_mr_0_val
> +	ldr	r4, [sp, #68]
> +	str     r4, omap_sdrc_rfr_ctrl_1_val
> +	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
> +	beq	skip_cs1_params		@  do not use cs1 params
> +	ldr	r4, [sp, #72]
> +	str     r4, omap_sdrc_actim_ctrl_a_1_val
> +	ldr	r4, [sp, #76]
> +	str     r4, omap_sdrc_actim_ctrl_b_1_val
> +	ldr	r4, [sp, #80]
> +	str     r4, omap_sdrc_mr_1_val
> +skip_cs1_params:
>  	dsb				@ flush buffered writes to interconnect
> -	cmp	r7, #1			@ if increasing SDRC clk rate,
> +
> +	cmp	r3, #1			@ if increasing SDRC clk rate,
>  	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
> -	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
> +	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
>  	bleq	unlock_dll
>  	blne	lock_dll
>  	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
>  	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
>  	bl	enable_sdrc		@ take SDRC out of idle
> -	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
> +	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
>  	bleq	wait_dll_unlock
>  	blne	wait_dll_lock
> -	cmp	r7, #1			@ if increasing SDRC clk rate,
> +	cmp	r3, #1			@ if increasing SDRC clk rate,
>  	beq	return_to_sdram		@ return to SDRAM code, otherwise,
>  	bl	configure_sdrc		@ reprogram SDRC regs now
> -	mov	r12, r5
> +	mov	r12, r2
>  	bl	wait_clk_stable		@ wait for SDRC to stabilize
>  return_to_sdram:
>  	isb				@ prevent speculative exec past here
> @@ -149,7 +180,7 @@ configure_core_dpll:
>  	ldr	r12, [r11]
>  	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
>  	and	r12, r12, r10
> -	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
> +	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
>  	str	r12, [r11]
>  	ldr	r12, [r11]		@ posted-write barrier for CM
>  	bx	lr
> @@ -187,15 +218,34 @@ wait_dll_unlock:
>  	bne	wait_dll_unlock
>  	bx	lr
>  configure_sdrc:
> -	ldr	r11, omap3_sdrc_rfr_ctrl
> -	str	r0, [r11]
> -	ldr	r11, omap3_sdrc_actim_ctrla
> -	str	r1, [r11]
> -	ldr	r11, omap3_sdrc_actim_ctrlb
> -	str	r2, [r11]
> +	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
> +	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
> +	str	r12, [r11]			@ store
> +	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
> +	ldr	r11, omap3_sdrc_actim_ctrl_a_0
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
> +	ldr	r11, omap3_sdrc_actim_ctrl_b_0
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_mr_0_val
>  	ldr	r11, omap3_sdrc_mr_0
> -	str	r6, [r11]
> -	ldr	r6, [r11]		@ posted-write barrier for SDRC
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_rfr_ctrl_1_val
> +	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
> +	beq	skip_cs1_prog		@  do not program cs1 params
> +	ldr	r11, omap3_sdrc_rfr_ctrl_1
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
> +	ldr	r11, omap3_sdrc_actim_ctrl_a_1
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
> +	ldr	r11, omap3_sdrc_actim_ctrl_b_1
> +	str	r12, [r11]
> +	ldr	r12, omap_sdrc_mr_1_val
> +	ldr	r11, omap3_sdrc_mr_1
> +	str	r12, [r11]
> +skip_cs1_prog:
> +	ldr	r12, [r11]		@ posted-write barrier for SDRC
>  	bx	lr
>  
>  omap3_sdrc_power:
> @@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
>  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
>  omap3_cm_iclken1_core:
>  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
> -omap3_sdrc_rfr_ctrl:
> +
> +omap3_sdrc_rfr_ctrl_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
> -omap3_sdrc_actim_ctrla:
> +omap3_sdrc_rfr_ctrl_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
> +omap3_sdrc_actim_ctrl_a_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
> -omap3_sdrc_actim_ctrlb:
> +omap3_sdrc_actim_ctrl_a_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
> +omap3_sdrc_actim_ctrl_b_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
> +omap3_sdrc_actim_ctrl_b_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
>  omap3_sdrc_mr_0:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
> +omap3_sdrc_mr_1:
> +	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
> +omap_sdrc_rfr_ctrl_0_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_rfr_ctrl_1_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_actim_ctrl_a_0_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_actim_ctrl_a_1_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_actim_ctrl_b_0_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_actim_ctrl_b_1_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_mr_0_val:
> +	.word 0xDEADBEEF
> +omap_sdrc_mr_1_val:
> +	.word 0xDEADBEEF
> +
>  omap3_sdrc_dlla_status:
>  	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  omap3_sdrc_dlla_ctrl:
> @@ -223,3 +299,4 @@ core_m2_mask_val:
>  
>  ENTRY(omap3_sram_configure_core_dpll_sz)
>  	.word	. - omap3_sram_configure_core_dpll
> +
> diff --git a/arch/arm/plat-omap/include/mach/io.h 
> b/arch/arm/plat-omap/include/mach/io.h
> index 54c159b..d4c78b4 100644
> --- a/arch/arm/plat-omap/include/mach/io.h
> +++ b/arch/arm/plat-omap/include/mach/io.h
> @@ -192,7 +192,8 @@ extern void omap1_map_common_io(void);
>  extern void omap1_init_common_hw(void);
>  
>  extern void omap2_map_common_io(void);
> -extern void omap2_init_common_hw(struct omap_sdrc_params *sp,
> +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
> +				 struct omap_sdrc_params *sdrc_cs1,
>  				 struct omap_opp *mpu_opps,
>  				 struct omap_opp *dsp_opps,
>  				 struct omap_opp *l3_opps);
> diff --git a/arch/arm/plat-omap/include/mach/mux.h 
> b/arch/arm/plat-omap/include/mach/mux.h
> index f7e298a..7368aba 100644
> --- a/arch/arm/plat-omap/include/mach/mux.h
> +++ b/arch/arm/plat-omap/include/mach/mux.h
> @@ -803,6 +803,10 @@ enum omap34xx_index {
>  	AE5_34XX_GPIO143,
>  	H19_34XX_GPIO164_OUT,
>  	J25_34XX_GPIO170,
> +
> +	/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
> +	H16_34XX_SDRC_CKE0,
> +	H17_34XX_SDRC_CKE1,
>  };
>  
>  struct omap_mux_cfg {
> diff --git a/arch/arm/plat-omap/include/mach/sdrc.h 
> b/arch/arm/plat-omap/include/mach/sdrc.h
> index a678bc8..7e22143 100644
> --- a/arch/arm/plat-omap/include/mach/sdrc.h
> +++ b/arch/arm/plat-omap/include/mach/sdrc.h
> @@ -114,9 +114,11 @@ struct omap_sdrc_params {
>  
>  void omap2_sms_save_context(void);
>  void omap2_sms_restore_context(void);
> -void __init omap2_sdrc_init(struct omap_sdrc_params *);
> -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
> -
> +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> +			    struct omap_sdrc_params *sdrc_cs1);
> +int omap2_sdrc_get_params(unsigned long r,
> +			  struct omap_sdrc_params **sdrc_cs0,
> +			  struct omap_sdrc_params **sdrc_cs1);
>  #ifdef CONFIG_ARCH_OMAP2
>  
>  struct memory_timings {
> diff --git a/arch/arm/plat-omap/include/mach/sram.h 
> b/arch/arm/plat-omap/include/mach/sram.h
> index ad0a600..98906ea 100644
> --- a/arch/arm/plat-omap/include/mach/sram.h
> +++ b/arch/arm/plat-omap/include/mach/sram.h
> @@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 
> dll_val,
>  				      u32 mem_type);
>  extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
>  
> -extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
> -				     u32 sdrc_actim_ctrla,
> -				     u32 sdrc_actim_ctrlb, u32 m2,
> -				     u32 unlock_dll, u32 f, u32 sdrc_mr,
> -				     u32 inc);
> +extern u32 omap3_configure_core_dpll(
> +			u32 m2, u32 unlock_dll, u32 f, u32 inc,
> +			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> +			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> +			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> +			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
> +
>  extern void omap3_sram_restore_context(void);
>  
>  /* Do not use these */
> @@ -61,11 +63,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, 
> u32 dll_val,
>  extern unsigned long omap243x_sram_reprogram_sdrc_sz;
>  
>  
> -extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
> -					  u32 sdrc_actim_ctrla,
> -					  u32 sdrc_actim_ctrlb, u32 m2,
> -					  u32 unlock_dll, u32 f, u32 sdrc_mr,
> -					  u32 inc);
> +extern u32 omap3_sram_configure_core_dpll(
> +			u32 m2, u32 unlock_dll, u32 f, u32 inc,
> +			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> +			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> +			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> +			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>  extern unsigned long omap3_sram_configure_core_dpll_sz;
>  
>  #ifdef CONFIG_PM
> diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
> index a2e60e7..517f45b 100644
> --- a/arch/arm/plat-omap/sram.c
> +++ b/arch/arm/plat-omap/sram.c
> @@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
>  
>  #ifdef CONFIG_ARCH_OMAP3
>  
> -static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
> -					      u32 sdrc_actim_ctrla,
> -					      u32 sdrc_actim_ctrlb,
> -					      u32 m2, u32 unlock_dll,
> -					      u32 f, u32 sdrc_mr, u32 inc);
> -u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
> -			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
> -			      u32 f, u32 sdrc_mr, u32 inc)
> - {
> +static u32 (*_omap3_sram_configure_core_dpll)(
> +				u32 m2, u32 unlock_dll, u32 f, u32 inc,
> +				u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> +				u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> +				u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> +				u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
> +
> +u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
> +			      u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> +			      u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> +			      u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> +			      u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
> +{
>  	if (!_omap3_sram_configure_core_dpll)
>  		omap_sram_error();
>  
> -	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
> -					       sdrc_actim_ctrla,
> -					       sdrc_actim_ctrlb, m2,
> -					       unlock_dll, f, sdrc_mr, inc);
> - }
> +	return _omap3_sram_configure_core_dpll(
> +				m2, unlock_dll, f, inc,
> +				sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
> +				sdrc_actim_ctrl_b_0, sdrc_mr_0,
> +				sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
> +				sdrc_actim_ctrl_b_1, sdrc_mr_1);
> +}
>  
>  #ifdef CONFIG_PM
>  void omap3_sram_restore_context(void)
> -- 
> 1.6.2.5.168.g3823
>
>
> On Friday 05 June 2009 20:10:40 Paul Walmsley wrote:
>> Hi Jean,
>>
>> On Fri, 5 Jun 2009, Jean Pihet wrote:
>> > Here is the new patch that includes all the remarks and suggestion. The
>> > description is here below.
>> >
>> > Some notes:
>> > - all calls to omap2_init_common_hw have been adapted in the board files.
>> > it looks like 2430SDP and Pandora board files are broken since they use
>> > only one param. Can that be checked on those boards?
>> > - it is assumed that RX51 only uses 1 CS. Is that correct?
>> >
>> > Can you review it and possibly merge?
>>
>> Looks great.
>>
>> Tero, does RX51 use two SDRC chipselects!
>>
>> Acked-by: Paul Walmsley <paul@pwsan.com>
>>
>> > Thanks & regards,
>> > Jean
>> >

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Jean Pihet]

On Monday 08 June 2009 16:59:36 Kevin Hilman wrote:
> Jean Pihet <jpihet@mvista.com> writes:
> > Paul,
> >
> > Here is the updated patch that fixes the Overo build as well.
> > Can you check it?
> >
> > Kevin, can you push it if it is correct?
>
> Can you run it through checkpatch, fix the errors and also merge Tero's
> RX51 patch if it looks good to you.
Ok. I will check. The cause might be the mailer.

I think we need the omap_cfg_reg calls in the RX51 board file as well, even if 
the bootloader has the mux setting already right. That way a warning will be 
issued in case of a faulty bootloader. Do you agree?

>
> Below are the checkpatch errors I get:  looks lik your mailer is
> probably wrapping the patch and there is also one error to fix.
>
> Kevin

Regards,
Jean
>
> ERROR: patch seems to be corrupt (line wrapped?)
> #306: FILE: arch/arm/mach-omap2/clock34xx.c:477:
> unsigned long rate)
>
> ERROR: trailing whitespace
> #494: FILE: arch/arm/mach-omap2/sdrc.c:128:
> + * @sdrc_cs[01]: pointers to a null-terminated list of struct $
>
> total: 2 errors, 0 warnings, 648 lines checked
>
> Your patch has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
>
> > Regards,
> > Jean
> >
> > From ebe57354b04444de059e1f042e0c488f761853f0 Mon Sep 17 00:00:00 2001
> > From: Jean Pihet <jpihet@mvista.com>
> > Date: Fri, 5 Jun 2009 17:19:00 +0200
> > Subject: OMAP3: add support for 2 SDRAM chip selects
> >
> > Some boards (Beagle Cx, Overo) have 2 SDRAM parts
> > connected to the SDRC.
> >
> > This patch adds the following:
> > - ensure that the CKE signals mux settings are correct
> > - add a new argument of type omap_sdrc_params struct*
> > to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
> > - adapted the OMAP boards files to the new prototype of
> > omap2_init_common_hw. Only Beagle and Overo are using the 2 CS'es
> > - adapt the sram sleep code to configure the SDRC for the 2nd CS
> >
> > Note: If the 2nd param to omap2_init_common_hw is NULL, then the
> > parameters are not programmed into the SDRC CS1 registers
> >
> > Tested on 3430 SDP and Beagleboard rev C2 and B5, with
> > suspend/resume and frequency changes (cpufreq).
> >
> > Thanks to Paul Walmsley and Kevin Hilman for the suggestions
> > and code reviews.
> >
> > Signed-off-by: Jean Pihet <jpihet@mvista.com>
> > ---
> >  arch/arm/mach-omap2/board-2430sdp.c      |    2 +-
> >  arch/arm/mach-omap2/board-3430sdp.c      |    6 +-
> >  arch/arm/mach-omap2/board-apollon.c      |    2 +-
> >  arch/arm/mach-omap2/board-generic.c      |    2 +-
> >  arch/arm/mach-omap2/board-h4.c           |    2 +-
> >  arch/arm/mach-omap2/board-ldp.c          |    2 +-
> >  arch/arm/mach-omap2/board-n800.c         |    2 +-
> >  arch/arm/mach-omap2/board-omap2evm.c     |    2 +-
> >  arch/arm/mach-omap2/board-omap3beagle.c  |   11 ++-
> >  arch/arm/mach-omap2/board-omap3evm.c     |    6 +-
> >  arch/arm/mach-omap2/board-omap3pandora.c |    3 +-
> >  arch/arm/mach-omap2/board-overo.c        |    9 ++-
> >  arch/arm/mach-omap2/board-rx51.c         |    6 +-
> >  arch/arm/mach-omap2/clock34xx.c          |   37 ++++++--
> >  arch/arm/mach-omap2/io.c                 |    5 +-
> >  arch/arm/mach-omap2/mux.c                |    6 ++
> >  arch/arm/mach-omap2/sdrc.c               |   63 +++++++++-----
> >  arch/arm/mach-omap2/sram34xx.S           |  137
> > +++++++++++++++++++++++-------
> >  arch/arm/plat-omap/include/mach/io.h     |    3 +-
> >  arch/arm/plat-omap/include/mach/mux.h    |    4 +
> >  arch/arm/plat-omap/include/mach/sdrc.h   |    8 +-
> >  arch/arm/plat-omap/include/mach/sram.h   |   23 +++--
> >  arch/arm/plat-omap/sram.c                |   34 +++++---
> >  23 files changed, 267 insertions(+), 108 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/board-2430sdp.c
> > b/arch/arm/mach-omap2/board-2430sdp.c
> > index aa5df72..4cb7bc5 100644
> > --- a/arch/arm/mach-omap2/board-2430sdp.c
> > +++ b/arch/arm/mach-omap2/board-2430sdp.c
> > @@ -322,7 +322,7 @@ out:
> >
> >  static void __init omap_2430sdp_init_irq(void)
> >  {
> > -	omap2_init_common_hw(NULL);
> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  	sdp2430_init_smc91x();
> > diff --git a/arch/arm/mach-omap2/board-3430sdp.c
> > b/arch/arm/mach-omap2/board-3430sdp.c
> > index 195b749..24e2728 100644
> > --- a/arch/arm/mach-omap2/board-3430sdp.c
> > +++ b/arch/arm/mach-omap2/board-3430sdp.c
> > @@ -302,8 +302,10 @@ static inline void __init sdp3430_init_smc91x(void)
> >
> >  static void __init omap_3430sdp_init_irq(void)
> >  {
> > -	omap2_init_common_hw(hyb18m512160af6_sdrc_params, omap3_mpu_rate_table,
> > -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> > +	omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL,
> > +			     omap3_mpu_rate_table,
> > +			     omap3_dsp_rate_table,
> > +			     omap3_l3_rate_table);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  	sdp3430_init_smc91x();
> > diff --git a/arch/arm/mach-omap2/board-apollon.c
> > b/arch/arm/mach-omap2/board-apollon.c
> > index 2e24812..2dd1350 100644
> > --- a/arch/arm/mach-omap2/board-apollon.c
> > +++ b/arch/arm/mach-omap2/board-apollon.c
> > @@ -323,7 +323,7 @@ out:
> >
> >  static void __init omap_apollon_init_irq(void)
> >  {
> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  	apollon_init_smc91x();
> > diff --git a/arch/arm/mach-omap2/board-generic.c
> > b/arch/arm/mach-omap2/board-generic.c
> > index be763a9..763329b 100644
> > --- a/arch/arm/mach-omap2/board-generic.c
> > +++ b/arch/arm/mach-omap2/board-generic.c
> > @@ -33,7 +33,7 @@
> >
> >  static void __init omap_generic_init_irq(void)
> >  {
> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
> >  	omap_init_irq();
> >  }
> >
> > diff --git a/arch/arm/mach-omap2/board-h4.c
> > b/arch/arm/mach-omap2/board-h4.c index 8f54939..17c3599 100644
> > --- a/arch/arm/mach-omap2/board-h4.c
> > +++ b/arch/arm/mach-omap2/board-h4.c
> > @@ -348,7 +348,7 @@ static void __init h4_init_flash(void)
> >
> >  static void __init omap_h4_init_irq(void)
> >  {
> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  	h4_init_flash();
> > diff --git a/arch/arm/mach-omap2/board-ldp.c
> > b/arch/arm/mach-omap2/board-ldp.c index 9f41dc9..b012806 100644
> > --- a/arch/arm/mach-omap2/board-ldp.c
> > +++ b/arch/arm/mach-omap2/board-ldp.c
> > @@ -344,7 +344,7 @@ static inline void __init ldp_init_smc911x(void)
> >
> >  static void __init omap_ldp_init_irq(void)
> >  {
> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  	ldp_init_smc911x();
> > diff --git a/arch/arm/mach-omap2/board-n800.c
> > b/arch/arm/mach-omap2/board-n800.c
> > index ac7cf3f..ad53f4a 100644
> > --- a/arch/arm/mach-omap2/board-n800.c
> > +++ b/arch/arm/mach-omap2/board-n800.c
> > @@ -127,7 +127,7 @@ static struct lm8323_platform_data lm8323_pdata = {
> >
> >  void __init nokia_n800_init_irq(void)
> >  {
> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >
> > diff --git a/arch/arm/mach-omap2/board-omap2evm.c
> > b/arch/arm/mach-omap2/board-omap2evm.c
> > index 4fac1be..56a26d4 100644
> > --- a/arch/arm/mach-omap2/board-omap2evm.c
> > +++ b/arch/arm/mach-omap2/board-omap2evm.c
> > @@ -276,7 +276,7 @@ static struct twl4030_keypad_data omap2evm_kp_data =
> > {
> >
> >  static void __init omap2_evm_init_irq(void)
> >  {
> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  	omap2evm_init_smc911x();
> > diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
> > b/arch/arm/mach-omap2/board-omap3beagle.c
> > index 7294dbf..872beb6 100644
> > --- a/arch/arm/mach-omap2/board-omap3beagle.c
> > +++ b/arch/arm/mach-omap2/board-omap3beagle.c
> > @@ -312,8 +312,11 @@ static int __init omap3_beagle_i2c_init(void)
> >
> >  static void __init omap3_beagle_init_irq(void)
> >  {
> > -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
> > -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> > +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> > +			     mt46h32m32lf6_sdrc_params,
> > +			     omap3_mpu_rate_table,
> > +			     omap3_dsp_rate_table,
> > +			     omap3_l3_rate_table);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  }
> > @@ -441,6 +444,10 @@ static void __init omap3_beagle_init(void)
> >  	usb_musb_init();
> >  	usb_ehci_init();
> >  	omap3beagle_flash_init();
> > +
> > +	/* Ensure SDRC pins are mux'd for self-refresh */
> > +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
> > +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
> >  }
> >
> >  static void __init omap3_beagle_map_io(void)
> > diff --git a/arch/arm/mach-omap2/board-omap3evm.c
> > b/arch/arm/mach-omap2/board-omap3evm.c
> > index f017f0d..3b9c96a 100644
> > --- a/arch/arm/mach-omap2/board-omap3evm.c
> > +++ b/arch/arm/mach-omap2/board-omap3evm.c
> > @@ -276,8 +276,10 @@ struct spi_board_info omap3evm_spi_board_info[] = {
> >
> >  static void __init omap3_evm_init_irq(void)
> >  {
> > -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
> > -	                     omap3_dsp_rate_table, omap3_l3_rate_table);
> > +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
> > +			     omap3_mpu_rate_table,
> > +			     omap3_dsp_rate_table,
> > +			     omap3_l3_rate_table);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  	omap3evm_init_smc911x();
> > diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
> > b/arch/arm/mach-omap2/board-omap3pandora.c
> > index c67f62f..05ab99e 100644
> > --- a/arch/arm/mach-omap2/board-omap3pandora.c
> > +++ b/arch/arm/mach-omap2/board-omap3pandora.c
> > @@ -220,7 +220,8 @@ static int __init omap3pandora_i2c_init(void)
> >
> >  static void __init omap3pandora_init_irq(void)
> >  {
> > -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
> > +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
> > +			     NULL, NULL, NULL);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  }
> > diff --git a/arch/arm/mach-omap2/board-overo.c
> > b/arch/arm/mach-omap2/board-overo.c
> > index 9eae608..50902d4 100644
> > --- a/arch/arm/mach-omap2/board-overo.c
> > +++ b/arch/arm/mach-omap2/board-overo.c
> > @@ -45,6 +45,7 @@
> >  #include <mach/gpmc.h>
> >  #include <mach/hardware.h>
> >  #include <mach/nand.h>
> > +#include <mach/mux.h>
> >  #include <mach/usb.h>
> >
> >  #include "sdram-micron-mt46h32m32lf-6.h"
> > @@ -355,7 +356,9 @@ static int __init overo_i2c_init(void)
> >
> >  static void __init overo_init_irq(void)
> >  {
> > -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL, NULL, NULL);
> > +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> > +			     mt46h32m32lf6_sdrc_params,
> > +			     NULL, NULL, NULL);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  }
> > @@ -391,6 +394,10 @@ static void __init overo_init(void)
> >  	overo_init_smsc911x();
> >  	overo_ads7846_init();
> >
> > +	/* Ensure SDRC pins are mux'd for self-refresh */
> > +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
> > +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
> > +
> >  	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
> >  			  "OVERO_GPIO_W2W_NRESET") == 0) &&
> >  	    (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
> > diff --git a/arch/arm/mach-omap2/board-rx51.c
> > b/arch/arm/mach-omap2/board-rx51.c
> > index 09035b0..d48459f 100644
> > --- a/arch/arm/mach-omap2/board-rx51.c
> > +++ b/arch/arm/mach-omap2/board-rx51.c
> > @@ -64,8 +64,10 @@ static struct omap_board_config_kernel rx51_config[] =
> > {
> >
> >  static void __init rx51_init_irq(void)
> >  {
> > -	omap2_init_common_hw(rx51_get_sdram_timings(), omap3_mpu_rate_table,
> > -			     omap3_dsp_rate_table, omap3_l3_rate_table);
> > +	omap2_init_common_hw(rx51_get_sdram_timings(), NULL,
> > +			     omap3_mpu_rate_table,
> > +			     omap3_dsp_rate_table,
> > +			     omap3_l3_rate_table);
> >  	omap_init_irq();
> >  	omap_gpio_init();
> >  }
> > diff --git a/arch/arm/mach-omap2/clock34xx.c
> > b/arch/arm/mach-omap2/clock34xx.c index 3cee6b4..f262787 100644
> > --- a/arch/arm/mach-omap2/clock34xx.c
> > +++ b/arch/arm/mach-omap2/clock34xx.c
> > @@ -478,7 +478,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk
> > *clk, unsigned long rate)
> >  	u32 unlock_dll = 0;
> >  	u32 c;
> >  	unsigned long validrate, sdrcrate, mpurate;
> > -	struct omap_sdrc_params *sp;
> > +	struct omap_sdrc_params *sdrc_cs0;
> > +	struct omap_sdrc_params *sdrc_cs1;
> > +	int ret;
> >
> >  	if (!clk || !rate)
> >  		return -EINVAL;
> > @@ -496,8 +498,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk
> > *clk, unsigned long rate)
> >  	else
> >  		sdrcrate >>= ((clk->rate / rate) >> 1);
> >
> > -	sp = omap2_sdrc_get_params(sdrcrate);
> > -	if (!sp)
> > +	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
> > +	if (ret)
> >  		return -EINVAL;
> >
> >  	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
> > @@ -518,12 +520,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk
> > *clk, unsigned long rate)
> >
> >  	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
> >  		 validrate);
> > -	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
> > -		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
> > -
> > -	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
> > -				  sp->actim_ctrlb, new_div, unlock_dll, c,
> > -				  sp->mr, rate > clk->rate);
> > +	pr_debug("clock: SDRC CS0 timing params used:"
> > +		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
> > +		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> > +		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
> > +	if (sdrc_cs1)
> > +		pr_debug("clock: SDRC CS1 timing params used: "
> > +		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
> > +		 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
> > +		 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
> > +
> > +	if (sdrc_cs1)
> > +		omap3_configure_core_dpll(
> > +				  new_div, unlock_dll, c, rate > clk->rate,
> > +				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> > +				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
> > +				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
> > +				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
> > +	else
> > +		omap3_configure_core_dpll(
> > +				  new_div, unlock_dll, c, rate > clk->rate,
> > +				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
> > +				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
> > +				  0, 0, 0, 0);
> >
> >  	return 0;
> >  }
> > diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> > index 6fb6c29..aa000b4 100644
> > --- a/arch/arm/mach-omap2/io.c
> > +++ b/arch/arm/mach-omap2/io.c
> > @@ -231,7 +231,8 @@ static int __init _omap2_init_reprogram_sdrc(void)
> >  	return v;
> >  }
> >
> > -void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
> > +void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
> > +				 struct omap_sdrc_params *sdrc_cs1,
> >  				 struct omap_opp *mpu_opps,
> >  				 struct omap_opp *dsp_opps,
> >  				 struct omap_opp *l3_opps)
> > @@ -244,7 +245,7 @@ void __init omap2_init_common_hw(struct
> > omap_sdrc_params *sp,
> >  	omapdev_init(omapdevs);
> >  	omap2_clk_init();
> >  	omap_pm_if_init();
> > -	omap2_sdrc_init(sp);
> > +	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
> >
> >  	_omap2_init_reprogram_sdrc();
> >
> > diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
> > index 026c4fc..43d6b92 100644
> > --- a/arch/arm/mach-omap2/mux.c
> > +++ b/arch/arm/mach-omap2/mux.c
> > @@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
> >  		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
> >  MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
> >  		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
> > +
> > +/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
> > +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
> > +		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
> > +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
> > +		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
> >  };
> >
> >  #define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)
> > diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
> > index c832d83..b42f5ae 100644
> > --- a/arch/arm/mach-omap2/sdrc.c
> > +++ b/arch/arm/mach-omap2/sdrc.c
> > @@ -32,7 +32,7 @@
> >  #include <mach/sdrc.h>
> >  #include "sdrc.h"
> >
> > -static struct omap_sdrc_params *sdrc_init_params;
> > +static struct omap_sdrc_params *sdrc_init_params_cs0,
> > *sdrc_init_params_cs1;
> >
> >  void __iomem *omap2_sdrc_base;
> >  void __iomem *omap2_sms_base;
> > @@ -71,33 +71,49 @@ void omap2_sms_restore_context(void)
> >  /**
> >   * omap2_sdrc_get_params - return SDRC register values for a given clock
> > rate * @r: SDRC clock rate (in Hz)
> > + * @sdrc_cs0: chip select 0 ram timings **
> > + * @sdrc_cs1: chip select 1 ram timings **
> >   *
> >   * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
> > - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
> > - * SDRC clock rate 'r'.  These parameters control various timing
> > - * delays in the SDRAM controller that are expressed in terms of the
> > - * number of SDRC clock cycles to wait; hence the clock rate
> > - * dependency. Note that sdrc_init_params must be sorted rate
> > - * descending.  Also assumes that both chip-selects use the same
> > - * timing parameters.  Returns a struct omap_sdrc_params * upon
> > - * success, or NULL upon failure.
> > + *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
> > + *  structs,for a given SDRC clock rate 'r'.
> > + * These parameters control various timing delays in the SDRAM
> > controller + *  that are expressed in terms of the number of SDRC clock
> > cycles to + *  wait; hence the clock rate dependency.
> > + *
> > + * Supports 2 different timing parameters for both chip selects.
> > + *
> > + * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
> > + * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
> > + *  as sdrc_init_params_cs_0.
> > + *
> > + * Fills in the struct omap_sdrc_params * for each chip select.
> > + * Returns 0 upon success or -1 upon failure.
> >   */
> > -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
> > +int omap2_sdrc_get_params(unsigned long r,
> > +			  struct omap_sdrc_params **sdrc_cs0,
> > +			  struct omap_sdrc_params **sdrc_cs1)
> >  {
> > -	struct omap_sdrc_params *sp;
> > +	struct omap_sdrc_params *sp0, *sp1;
> >
> > -	if (!sdrc_init_params)
> > -		return NULL;
> > +	if (!sdrc_init_params_cs0)
> > +		return -1;
> >
> > -	sp = sdrc_init_params;
> > +	sp0 = sdrc_init_params_cs0;
> > +	sp1 = sdrc_init_params_cs1;
> >
> > -	while (sp->rate && sp->rate != r)
> > -		sp++;
> > +	while (sp0->rate && sp0->rate != r) {
> > +		sp0++;
> > +		if (sdrc_init_params_cs1)
> > +			sp1++;
> > +	}
> >
> > -	if (!sp->rate)
> > -		return NULL;
> > +	if (!sp0->rate)
> > +		return -1;
> >
> > -	return sp;
> > +	*sdrc_cs0 = sp0;
> > +	*sdrc_cs1 = sp1;
> > +	return 0;
> >  }
> >
> >
> > @@ -109,13 +125,15 @@ void __init omap2_set_globals_sdrc(struct
> > omap_globals *omap2_globals)
> >
> >  /**
> >   * omap2_sdrc_init - initialize SMS, SDRC devices on boot
> > - * @sp: pointer to a null-terminated list of struct omap_sdrc_params
> > + * @sdrc_cs[01]: pointers to a null-terminated list of struct
> > omap_sdrc_params
> > + *  Support for 2 chip selects timings
> >   *
> >   * Turn on smart idle modes for SDRAM scheduler and controller.
> >   * Program a known-good configuration for the SDRC to deal with buggy
> >   * bootloaders.
> >   */
> > -void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
> > +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> > +			    struct omap_sdrc_params *sdrc_cs1)
> >  {
> >  	u32 l;
> >
> > @@ -129,7 +147,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params
> > *sp) l |= (0x2 << 3);
> >  	sdrc_write_reg(l, SDRC_SYSCONFIG);
> >
> > -	sdrc_init_params = sp;
> > +	sdrc_init_params_cs0 = sdrc_cs0;
> > +	sdrc_init_params_cs1 = sdrc_cs1;
> >
> >  	/* XXX Enable SRFRONIDLEREQ here also? */
> >  	l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
> > diff --git a/arch/arm/mach-omap2/sram34xx.S
> > b/arch/arm/mach-omap2/sram34xx.S index f41f8d9..3aef744 100644
> > --- a/arch/arm/mach-omap2/sram34xx.S
> > +++ b/arch/arm/mach-omap2/sram34xx.S
> > @@ -36,7 +36,7 @@
> >
> >  	.text
> >
> > -/* r4 parameters */
> > +/* r1 parameters */
> >  #define SDRC_NO_UNLOCK_DLL		0x0
> >  #define SDRC_UNLOCK_DLL			0x1
> >
> > @@ -71,40 +71,71 @@
> >
> >  /*
> >   * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
> > - * r0 = new SDRC_RFR_CTRL register contents
> > - * r1 = new SDRC_ACTIM_CTRLA register contents
> > - * r2 = new SDRC_ACTIM_CTRLB register contents
> > - * r3 = new M2 divider setting (only 1 and 2 supported right now)
> > - * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
> > + *
> > + * Params passed in registers:
> > + *  r0 = new M2 divider setting (only 1 and 2 supported right now)
> > + *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
> >   *      SDRC rates < 83MHz
> > - * r5 = number of MPU cycles to wait for SDRC to stabilize after
> > + *  r2 = number of MPU cycles to wait for SDRC to stabilize after
> >   *      reprogramming the SDRC when switching to a slower MPU speed
> > - * r6 = new SDRC_MR_0 register value
> > - * r7 = increasing SDRC rate? (1 = yes, 0 = no)
> > + *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
> > + *
> > + * Params passed via the stack. The needed params will be copied in SRAM
> > + *  before use by the code in SRAM (SDRAM is not accessible during SDRC
> > + *  reconfiguration):
> > + *  new SDRC_RFR_CTRL_0 register contents
> > + *  new SDRC_ACTIM_CTRL_A_0 register contents
> > + *  new SDRC_ACTIM_CTRL_B_0 register contents
> > + *  new SDRC_MR_0 register value
> > + *  new SDRC_RFR_CTRL_1 register contents
> > + *  new SDRC_ACTIM_CTRL_A_1 register contents
> > + *  new SDRC_ACTIM_CTRL_B_1 register contents
> > + *  new SDRC_MR_1 register value
> >   *
> > + * If the param SDRC_RFR_CTRL_1 is 0, the parameters
> > + *  are not programmed into the SDRC CS1 registers
> >   */
> >  ENTRY(omap3_sram_configure_core_dpll)
> >  	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
> > -	ldr	r4, [sp, #52]		@ pull extra args off the stack
> > -	ldr	r5, [sp, #56]		@ load extra args from the stack
> > -	ldr	r6, [sp, #60]		@ load extra args from the stack
> > -	ldr	r7, [sp, #64]		@ load extra args from the stack
> > +
> > +					@ pull the extra args off the stack
> > +					@  and store them in SRAM
> > +	ldr	r4, [sp, #52]
> > +	str     r4, omap_sdrc_rfr_ctrl_0_val
> > +	ldr	r4, [sp, #56]
> > +	str     r4, omap_sdrc_actim_ctrl_a_0_val
> > +	ldr	r4, [sp, #60]
> > +	str     r4, omap_sdrc_actim_ctrl_b_0_val
> > +	ldr	r4, [sp, #64]
> > +	str     r4, omap_sdrc_mr_0_val
> > +	ldr	r4, [sp, #68]
> > +	str     r4, omap_sdrc_rfr_ctrl_1_val
> > +	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
> > +	beq	skip_cs1_params		@  do not use cs1 params
> > +	ldr	r4, [sp, #72]
> > +	str     r4, omap_sdrc_actim_ctrl_a_1_val
> > +	ldr	r4, [sp, #76]
> > +	str     r4, omap_sdrc_actim_ctrl_b_1_val
> > +	ldr	r4, [sp, #80]
> > +	str     r4, omap_sdrc_mr_1_val
> > +skip_cs1_params:
> >  	dsb				@ flush buffered writes to interconnect
> > -	cmp	r7, #1			@ if increasing SDRC clk rate,
> > +
> > +	cmp	r3, #1			@ if increasing SDRC clk rate,
> >  	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
> > -	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
> > +	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
> >  	bleq	unlock_dll
> >  	blne	lock_dll
> >  	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
> >  	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
> >  	bl	enable_sdrc		@ take SDRC out of idle
> > -	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
> > +	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
> >  	bleq	wait_dll_unlock
> >  	blne	wait_dll_lock
> > -	cmp	r7, #1			@ if increasing SDRC clk rate,
> > +	cmp	r3, #1			@ if increasing SDRC clk rate,
> >  	beq	return_to_sdram		@ return to SDRAM code, otherwise,
> >  	bl	configure_sdrc		@ reprogram SDRC regs now
> > -	mov	r12, r5
> > +	mov	r12, r2
> >  	bl	wait_clk_stable		@ wait for SDRC to stabilize
> >  return_to_sdram:
> >  	isb				@ prevent speculative exec past here
> > @@ -149,7 +180,7 @@ configure_core_dpll:
> >  	ldr	r12, [r11]
> >  	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
> >  	and	r12, r12, r10
> > -	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
> > +	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
> >  	str	r12, [r11]
> >  	ldr	r12, [r11]		@ posted-write barrier for CM
> >  	bx	lr
> > @@ -187,15 +218,34 @@ wait_dll_unlock:
> >  	bne	wait_dll_unlock
> >  	bx	lr
> >  configure_sdrc:
> > -	ldr	r11, omap3_sdrc_rfr_ctrl
> > -	str	r0, [r11]
> > -	ldr	r11, omap3_sdrc_actim_ctrla
> > -	str	r1, [r11]
> > -	ldr	r11, omap3_sdrc_actim_ctrlb
> > -	str	r2, [r11]
> > +	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
> > +	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
> > +	str	r12, [r11]			@ store
> > +	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
> > +	ldr	r11, omap3_sdrc_actim_ctrl_a_0
> > +	str	r12, [r11]
> > +	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
> > +	ldr	r11, omap3_sdrc_actim_ctrl_b_0
> > +	str	r12, [r11]
> > +	ldr	r12, omap_sdrc_mr_0_val
> >  	ldr	r11, omap3_sdrc_mr_0
> > -	str	r6, [r11]
> > -	ldr	r6, [r11]		@ posted-write barrier for SDRC
> > +	str	r12, [r11]
> > +	ldr	r12, omap_sdrc_rfr_ctrl_1_val
> > +	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
> > +	beq	skip_cs1_prog		@  do not program cs1 params
> > +	ldr	r11, omap3_sdrc_rfr_ctrl_1
> > +	str	r12, [r11]
> > +	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
> > +	ldr	r11, omap3_sdrc_actim_ctrl_a_1
> > +	str	r12, [r11]
> > +	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
> > +	ldr	r11, omap3_sdrc_actim_ctrl_b_1
> > +	str	r12, [r11]
> > +	ldr	r12, omap_sdrc_mr_1_val
> > +	ldr	r11, omap3_sdrc_mr_1
> > +	str	r12, [r11]
> > +skip_cs1_prog:
> > +	ldr	r12, [r11]		@ posted-write barrier for SDRC
> >  	bx	lr
> >
> >  omap3_sdrc_power:
> > @@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
> >  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
> >  omap3_cm_iclken1_core:
> >  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
> > -omap3_sdrc_rfr_ctrl:
> > +
> > +omap3_sdrc_rfr_ctrl_0:
> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
> > -omap3_sdrc_actim_ctrla:
> > +omap3_sdrc_rfr_ctrl_1:
> > +	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
> > +omap3_sdrc_actim_ctrl_a_0:
> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
> > -omap3_sdrc_actim_ctrlb:
> > +omap3_sdrc_actim_ctrl_a_1:
> > +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
> > +omap3_sdrc_actim_ctrl_b_0:
> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
> > +omap3_sdrc_actim_ctrl_b_1:
> > +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
> >  omap3_sdrc_mr_0:
> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
> > +omap3_sdrc_mr_1:
> > +	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
> > +omap_sdrc_rfr_ctrl_0_val:
> > +	.word 0xDEADBEEF
> > +omap_sdrc_rfr_ctrl_1_val:
> > +	.word 0xDEADBEEF
> > +omap_sdrc_actim_ctrl_a_0_val:
> > +	.word 0xDEADBEEF
> > +omap_sdrc_actim_ctrl_a_1_val:
> > +	.word 0xDEADBEEF
> > +omap_sdrc_actim_ctrl_b_0_val:
> > +	.word 0xDEADBEEF
> > +omap_sdrc_actim_ctrl_b_1_val:
> > +	.word 0xDEADBEEF
> > +omap_sdrc_mr_0_val:
> > +	.word 0xDEADBEEF
> > +omap_sdrc_mr_1_val:
> > +	.word 0xDEADBEEF
> > +
> >  omap3_sdrc_dlla_status:
> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
> >  omap3_sdrc_dlla_ctrl:
> > @@ -223,3 +299,4 @@ core_m2_mask_val:
> >
> >  ENTRY(omap3_sram_configure_core_dpll_sz)
> >  	.word	. - omap3_sram_configure_core_dpll
> > +
> > diff --git a/arch/arm/plat-omap/include/mach/io.h
> > b/arch/arm/plat-omap/include/mach/io.h
> > index 54c159b..d4c78b4 100644
> > --- a/arch/arm/plat-omap/include/mach/io.h
> > +++ b/arch/arm/plat-omap/include/mach/io.h
> > @@ -192,7 +192,8 @@ extern void omap1_map_common_io(void);
> >  extern void omap1_init_common_hw(void);
> >
> >  extern void omap2_map_common_io(void);
> > -extern void omap2_init_common_hw(struct omap_sdrc_params *sp,
> > +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
> > +				 struct omap_sdrc_params *sdrc_cs1,
> >  				 struct omap_opp *mpu_opps,
> >  				 struct omap_opp *dsp_opps,
> >  				 struct omap_opp *l3_opps);
> > diff --git a/arch/arm/plat-omap/include/mach/mux.h
> > b/arch/arm/plat-omap/include/mach/mux.h
> > index f7e298a..7368aba 100644
> > --- a/arch/arm/plat-omap/include/mach/mux.h
> > +++ b/arch/arm/plat-omap/include/mach/mux.h
> > @@ -803,6 +803,10 @@ enum omap34xx_index {
> >  	AE5_34XX_GPIO143,
> >  	H19_34XX_GPIO164_OUT,
> >  	J25_34XX_GPIO170,
> > +
> > +	/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
> > +	H16_34XX_SDRC_CKE0,
> > +	H17_34XX_SDRC_CKE1,
> >  };
> >
> >  struct omap_mux_cfg {
> > diff --git a/arch/arm/plat-omap/include/mach/sdrc.h
> > b/arch/arm/plat-omap/include/mach/sdrc.h
> > index a678bc8..7e22143 100644
> > --- a/arch/arm/plat-omap/include/mach/sdrc.h
> > +++ b/arch/arm/plat-omap/include/mach/sdrc.h
> > @@ -114,9 +114,11 @@ struct omap_sdrc_params {
> >
> >  void omap2_sms_save_context(void);
> >  void omap2_sms_restore_context(void);
> > -void __init omap2_sdrc_init(struct omap_sdrc_params *);
> > -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
> > -
> > +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> > +			    struct omap_sdrc_params *sdrc_cs1);
> > +int omap2_sdrc_get_params(unsigned long r,
> > +			  struct omap_sdrc_params **sdrc_cs0,
> > +			  struct omap_sdrc_params **sdrc_cs1);
> >  #ifdef CONFIG_ARCH_OMAP2
> >
> >  struct memory_timings {
> > diff --git a/arch/arm/plat-omap/include/mach/sram.h
> > b/arch/arm/plat-omap/include/mach/sram.h
> > index ad0a600..98906ea 100644
> > --- a/arch/arm/plat-omap/include/mach/sram.h
> > +++ b/arch/arm/plat-omap/include/mach/sram.h
> > @@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level,
> > u32 dll_val,
> >  				      u32 mem_type);
> >  extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int
> > bypass);
> >
> > -extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
> > -				     u32 sdrc_actim_ctrla,
> > -				     u32 sdrc_actim_ctrlb, u32 m2,
> > -				     u32 unlock_dll, u32 f, u32 sdrc_mr,
> > -				     u32 inc);
> > +extern u32 omap3_configure_core_dpll(
> > +			u32 m2, u32 unlock_dll, u32 f, u32 inc,
> > +			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> > +			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> > +			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> > +			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
> > +
> >  extern void omap3_sram_restore_context(void);
> >
> >  /* Do not use these */
> > @@ -61,11 +63,12 @@ extern void omap243x_sram_reprogram_sdrc(u32
> > perf_level, u32 dll_val,
> >  extern unsigned long omap243x_sram_reprogram_sdrc_sz;
> >
> >
> > -extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
> > -					  u32 sdrc_actim_ctrla,
> > -					  u32 sdrc_actim_ctrlb, u32 m2,
> > -					  u32 unlock_dll, u32 f, u32 sdrc_mr,
> > -					  u32 inc);
> > +extern u32 omap3_sram_configure_core_dpll(
> > +			u32 m2, u32 unlock_dll, u32 f, u32 inc,
> > +			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> > +			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> > +			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> > +			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
> >  extern unsigned long omap3_sram_configure_core_dpll_sz;
> >
> >  #ifdef CONFIG_PM
> > diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
> > index a2e60e7..517f45b 100644
> > --- a/arch/arm/plat-omap/sram.c
> > +++ b/arch/arm/plat-omap/sram.c
> > @@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
> >
> >  #ifdef CONFIG_ARCH_OMAP3
> >
> > -static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
> > -					      u32 sdrc_actim_ctrla,
> > -					      u32 sdrc_actim_ctrlb,
> > -					      u32 m2, u32 unlock_dll,
> > -					      u32 f, u32 sdrc_mr, u32 inc);
> > -u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
> > -			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
> > -			      u32 f, u32 sdrc_mr, u32 inc)
> > - {
> > +static u32 (*_omap3_sram_configure_core_dpll)(
> > +				u32 m2, u32 unlock_dll, u32 f, u32 inc,
> > +				u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> > +				u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> > +				u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> > +				u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
> > +
> > +u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
> > +			      u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
> > +			      u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
> > +			      u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
> > +			      u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
> > +{
> >  	if (!_omap3_sram_configure_core_dpll)
> >  		omap_sram_error();
> >
> > -	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
> > -					       sdrc_actim_ctrla,
> > -					       sdrc_actim_ctrlb, m2,
> > -					       unlock_dll, f, sdrc_mr, inc);
> > - }
> > +	return _omap3_sram_configure_core_dpll(
> > +				m2, unlock_dll, f, inc,
> > +				sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
> > +				sdrc_actim_ctrl_b_0, sdrc_mr_0,
> > +				sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
> > +				sdrc_actim_ctrl_b_1, sdrc_mr_1);
> > +}
> >
> >  #ifdef CONFIG_PM
> >  void omap3_sram_restore_context(void)
> > --
> > 1.6.2.5.168.g3823
> >
> > On Friday 05 June 2009 20:10:40 Paul Walmsley wrote:
> >> Hi Jean,
> >>
> >> On Fri, 5 Jun 2009, Jean Pihet wrote:
> >> > Here is the new patch that includes all the remarks and suggestion.
> >> > The description is here below.
> >> >
> >> > Some notes:
> >> > - all calls to omap2_init_common_hw have been adapted in the board
> >> > files. it looks like 2430SDP and Pandora board files are broken since
> >> > they use only one param. Can that be checked on those boards?
> >> > - it is assumed that RX51 only uses 1 CS. Is that correct?
> >> >
> >> > Can you review it and possibly merge?
> >>
> >> Looks great.
> >>
> >> Tero, does RX51 use two SDRC chipselects!
> >>
> >> Acked-by: Paul Walmsley <paul@pwsan.com>
> >>
> >> > Thanks & regards,
> >> > Jean

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects

[Kevin Hilman]

Jean Pihet <jpihet@mvista.com> writes:

> On Monday 08 June 2009 16:59:36 Kevin Hilman wrote:
>> Jean Pihet <jpihet@mvista.com> writes:
>> > Paul,
>> >
>> > Here is the updated patch that fixes the Overo build as well.
>> > Can you check it?
>> >
>> > Kevin, can you push it if it is correct?
>>
>> Can you run it through checkpatch, fix the errors and also merge Tero's
>> RX51 patch if it looks good to you.
> Ok. I will check. The cause might be the mailer.
>
> I think we need the omap_cfg_reg calls in the RX51 board file as
> well, even if the bootloader has the mux setting already right. That
> way a warning will be issued in case of a faulty bootloader. Do you
> agree?

I agree.

Kevin

>>
>> Below are the checkpatch errors I get:  looks lik your mailer is
>> probably wrapping the patch and there is also one error to fix.
>>
>> Kevin
>
> Regards,
> Jean
>>
>> ERROR: patch seems to be corrupt (line wrapped?)
>> #306: FILE: arch/arm/mach-omap2/clock34xx.c:477:
>> unsigned long rate)
>>
>> ERROR: trailing whitespace
>> #494: FILE: arch/arm/mach-omap2/sdrc.c:128:
>> + * @sdrc_cs[01]: pointers to a null-terminated list of struct $
>>
>> total: 2 errors, 0 warnings, 648 lines checked
>>
>> Your patch has style problems, please review.  If any of these errors
>> are false positives report them to the maintainer, see
>> CHECKPATCH in MAINTAINERS.
>>
>> > Regards,
>> > Jean
>> >
>> > From ebe57354b04444de059e1f042e0c488f761853f0 Mon Sep 17 00:00:00 2001
>> > From: Jean Pihet <jpihet@mvista.com>
>> > Date: Fri, 5 Jun 2009 17:19:00 +0200
>> > Subject: OMAP3: add support for 2 SDRAM chip selects
>> >
>> > Some boards (Beagle Cx, Overo) have 2 SDRAM parts
>> > connected to the SDRC.
>> >
>> > This patch adds the following:
>> > - ensure that the CKE signals mux settings are correct
>> > - add a new argument of type omap_sdrc_params struct*
>> > to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
>> > - adapted the OMAP boards files to the new prototype of
>> > omap2_init_common_hw. Only Beagle and Overo are using the 2 CS'es
>> > - adapt the sram sleep code to configure the SDRC for the 2nd CS
>> >
>> > Note: If the 2nd param to omap2_init_common_hw is NULL, then the
>> > parameters are not programmed into the SDRC CS1 registers
>> >
>> > Tested on 3430 SDP and Beagleboard rev C2 and B5, with
>> > suspend/resume and frequency changes (cpufreq).
>> >
>> > Thanks to Paul Walmsley and Kevin Hilman for the suggestions
>> > and code reviews.
>> >
>> > Signed-off-by: Jean Pihet <jpihet@mvista.com>
>> > ---
>> >  arch/arm/mach-omap2/board-2430sdp.c      |    2 +-
>> >  arch/arm/mach-omap2/board-3430sdp.c      |    6 +-
>> >  arch/arm/mach-omap2/board-apollon.c      |    2 +-
>> >  arch/arm/mach-omap2/board-generic.c      |    2 +-
>> >  arch/arm/mach-omap2/board-h4.c           |    2 +-
>> >  arch/arm/mach-omap2/board-ldp.c          |    2 +-
>> >  arch/arm/mach-omap2/board-n800.c         |    2 +-
>> >  arch/arm/mach-omap2/board-omap2evm.c     |    2 +-
>> >  arch/arm/mach-omap2/board-omap3beagle.c  |   11 ++-
>> >  arch/arm/mach-omap2/board-omap3evm.c     |    6 +-
>> >  arch/arm/mach-omap2/board-omap3pandora.c |    3 +-
>> >  arch/arm/mach-omap2/board-overo.c        |    9 ++-
>> >  arch/arm/mach-omap2/board-rx51.c         |    6 +-
>> >  arch/arm/mach-omap2/clock34xx.c          |   37 ++++++--
>> >  arch/arm/mach-omap2/io.c                 |    5 +-
>> >  arch/arm/mach-omap2/mux.c                |    6 ++
>> >  arch/arm/mach-omap2/sdrc.c               |   63 +++++++++-----
>> >  arch/arm/mach-omap2/sram34xx.S           |  137
>> > +++++++++++++++++++++++-------
>> >  arch/arm/plat-omap/include/mach/io.h     |    3 +-
>> >  arch/arm/plat-omap/include/mach/mux.h    |    4 +
>> >  arch/arm/plat-omap/include/mach/sdrc.h   |    8 +-
>> >  arch/arm/plat-omap/include/mach/sram.h   |   23 +++--
>> >  arch/arm/plat-omap/sram.c                |   34 +++++---
>> >  23 files changed, 267 insertions(+), 108 deletions(-)
>> >
>> > diff --git a/arch/arm/mach-omap2/board-2430sdp.c
>> > b/arch/arm/mach-omap2/board-2430sdp.c
>> > index aa5df72..4cb7bc5 100644
>> > --- a/arch/arm/mach-omap2/board-2430sdp.c
>> > +++ b/arch/arm/mach-omap2/board-2430sdp.c
>> > @@ -322,7 +322,7 @@ out:
>> >
>> >  static void __init omap_2430sdp_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(NULL);
>> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  	sdp2430_init_smc91x();
>> > diff --git a/arch/arm/mach-omap2/board-3430sdp.c
>> > b/arch/arm/mach-omap2/board-3430sdp.c
>> > index 195b749..24e2728 100644
>> > --- a/arch/arm/mach-omap2/board-3430sdp.c
>> > +++ b/arch/arm/mach-omap2/board-3430sdp.c
>> > @@ -302,8 +302,10 @@ static inline void __init sdp3430_init_smc91x(void)
>> >
>> >  static void __init omap_3430sdp_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(hyb18m512160af6_sdrc_params, omap3_mpu_rate_table,
>> > -			     omap3_dsp_rate_table, omap3_l3_rate_table);
>> > +	omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL,
>> > +			     omap3_mpu_rate_table,
>> > +			     omap3_dsp_rate_table,
>> > +			     omap3_l3_rate_table);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  	sdp3430_init_smc91x();
>> > diff --git a/arch/arm/mach-omap2/board-apollon.c
>> > b/arch/arm/mach-omap2/board-apollon.c
>> > index 2e24812..2dd1350 100644
>> > --- a/arch/arm/mach-omap2/board-apollon.c
>> > +++ b/arch/arm/mach-omap2/board-apollon.c
>> > @@ -323,7 +323,7 @@ out:
>> >
>> >  static void __init omap_apollon_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  	apollon_init_smc91x();
>> > diff --git a/arch/arm/mach-omap2/board-generic.c
>> > b/arch/arm/mach-omap2/board-generic.c
>> > index be763a9..763329b 100644
>> > --- a/arch/arm/mach-omap2/board-generic.c
>> > +++ b/arch/arm/mach-omap2/board-generic.c
>> > @@ -33,7 +33,7 @@
>> >
>> >  static void __init omap_generic_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  }
>> >
>> > diff --git a/arch/arm/mach-omap2/board-h4.c
>> > b/arch/arm/mach-omap2/board-h4.c index 8f54939..17c3599 100644
>> > --- a/arch/arm/mach-omap2/board-h4.c
>> > +++ b/arch/arm/mach-omap2/board-h4.c
>> > @@ -348,7 +348,7 @@ static void __init h4_init_flash(void)
>> >
>> >  static void __init omap_h4_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  	h4_init_flash();
>> > diff --git a/arch/arm/mach-omap2/board-ldp.c
>> > b/arch/arm/mach-omap2/board-ldp.c index 9f41dc9..b012806 100644
>> > --- a/arch/arm/mach-omap2/board-ldp.c
>> > +++ b/arch/arm/mach-omap2/board-ldp.c
>> > @@ -344,7 +344,7 @@ static inline void __init ldp_init_smc911x(void)
>> >
>> >  static void __init omap_ldp_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  	ldp_init_smc911x();
>> > diff --git a/arch/arm/mach-omap2/board-n800.c
>> > b/arch/arm/mach-omap2/board-n800.c
>> > index ac7cf3f..ad53f4a 100644
>> > --- a/arch/arm/mach-omap2/board-n800.c
>> > +++ b/arch/arm/mach-omap2/board-n800.c
>> > @@ -127,7 +127,7 @@ static struct lm8323_platform_data lm8323_pdata = {
>> >
>> >  void __init nokia_n800_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >
>> > diff --git a/arch/arm/mach-omap2/board-omap2evm.c
>> > b/arch/arm/mach-omap2/board-omap2evm.c
>> > index 4fac1be..56a26d4 100644
>> > --- a/arch/arm/mach-omap2/board-omap2evm.c
>> > +++ b/arch/arm/mach-omap2/board-omap2evm.c
>> > @@ -276,7 +276,7 @@ static struct twl4030_keypad_data omap2evm_kp_data =
>> > {
>> >
>> >  static void __init omap2_evm_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(NULL, NULL, NULL, NULL);
>> > +	omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  	omap2evm_init_smc911x();
>> > diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
>> > b/arch/arm/mach-omap2/board-omap3beagle.c
>> > index 7294dbf..872beb6 100644
>> > --- a/arch/arm/mach-omap2/board-omap3beagle.c
>> > +++ b/arch/arm/mach-omap2/board-omap3beagle.c
>> > @@ -312,8 +312,11 @@ static int __init omap3_beagle_i2c_init(void)
>> >
>> >  static void __init omap3_beagle_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
>> > -			     omap3_dsp_rate_table, omap3_l3_rate_table);
>> > +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>> > +			     mt46h32m32lf6_sdrc_params,
>> > +			     omap3_mpu_rate_table,
>> > +			     omap3_dsp_rate_table,
>> > +			     omap3_l3_rate_table);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  }
>> > @@ -441,6 +444,10 @@ static void __init omap3_beagle_init(void)
>> >  	usb_musb_init();
>> >  	usb_ehci_init();
>> >  	omap3beagle_flash_init();
>> > +
>> > +	/* Ensure SDRC pins are mux'd for self-refresh */
>> > +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
>> > +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
>> >  }
>> >
>> >  static void __init omap3_beagle_map_io(void)
>> > diff --git a/arch/arm/mach-omap2/board-omap3evm.c
>> > b/arch/arm/mach-omap2/board-omap3evm.c
>> > index f017f0d..3b9c96a 100644
>> > --- a/arch/arm/mach-omap2/board-omap3evm.c
>> > +++ b/arch/arm/mach-omap2/board-omap3evm.c
>> > @@ -276,8 +276,10 @@ struct spi_board_info omap3evm_spi_board_info[] = {
>> >
>> >  static void __init omap3_evm_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table,
>> > -	                     omap3_dsp_rate_table, omap3_l3_rate_table);
>> > +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>> > +			     omap3_mpu_rate_table,
>> > +			     omap3_dsp_rate_table,
>> > +			     omap3_l3_rate_table);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  	omap3evm_init_smc911x();
>> > diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
>> > b/arch/arm/mach-omap2/board-omap3pandora.c
>> > index c67f62f..05ab99e 100644
>> > --- a/arch/arm/mach-omap2/board-omap3pandora.c
>> > +++ b/arch/arm/mach-omap2/board-omap3pandora.c
>> > @@ -220,7 +220,8 @@ static int __init omap3pandora_i2c_init(void)
>> >
>> >  static void __init omap3pandora_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
>> > +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>> > +			     NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  }
>> > diff --git a/arch/arm/mach-omap2/board-overo.c
>> > b/arch/arm/mach-omap2/board-overo.c
>> > index 9eae608..50902d4 100644
>> > --- a/arch/arm/mach-omap2/board-overo.c
>> > +++ b/arch/arm/mach-omap2/board-overo.c
>> > @@ -45,6 +45,7 @@
>> >  #include <mach/gpmc.h>
>> >  #include <mach/hardware.h>
>> >  #include <mach/nand.h>
>> > +#include <mach/mux.h>
>> >  #include <mach/usb.h>
>> >
>> >  #include "sdram-micron-mt46h32m32lf-6.h"
>> > @@ -355,7 +356,9 @@ static int __init overo_i2c_init(void)
>> >
>> >  static void __init overo_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL, NULL, NULL);
>> > +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>> > +			     mt46h32m32lf6_sdrc_params,
>> > +			     NULL, NULL, NULL);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  }
>> > @@ -391,6 +394,10 @@ static void __init overo_init(void)
>> >  	overo_init_smsc911x();
>> >  	overo_ads7846_init();
>> >
>> > +	/* Ensure SDRC pins are mux'd for self-refresh */
>> > +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
>> > +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
>> > +
>> >  	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
>> >  			  "OVERO_GPIO_W2W_NRESET") == 0) &&
>> >  	    (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
>> > diff --git a/arch/arm/mach-omap2/board-rx51.c
>> > b/arch/arm/mach-omap2/board-rx51.c
>> > index 09035b0..d48459f 100644
>> > --- a/arch/arm/mach-omap2/board-rx51.c
>> > +++ b/arch/arm/mach-omap2/board-rx51.c
>> > @@ -64,8 +64,10 @@ static struct omap_board_config_kernel rx51_config[] =
>> > {
>> >
>> >  static void __init rx51_init_irq(void)
>> >  {
>> > -	omap2_init_common_hw(rx51_get_sdram_timings(), omap3_mpu_rate_table,
>> > -			     omap3_dsp_rate_table, omap3_l3_rate_table);
>> > +	omap2_init_common_hw(rx51_get_sdram_timings(), NULL,
>> > +			     omap3_mpu_rate_table,
>> > +			     omap3_dsp_rate_table,
>> > +			     omap3_l3_rate_table);
>> >  	omap_init_irq();
>> >  	omap_gpio_init();
>> >  }
>> > diff --git a/arch/arm/mach-omap2/clock34xx.c
>> > b/arch/arm/mach-omap2/clock34xx.c index 3cee6b4..f262787 100644
>> > --- a/arch/arm/mach-omap2/clock34xx.c
>> > +++ b/arch/arm/mach-omap2/clock34xx.c
>> > @@ -478,7 +478,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk
>> > *clk, unsigned long rate)
>> >  	u32 unlock_dll = 0;
>> >  	u32 c;
>> >  	unsigned long validrate, sdrcrate, mpurate;
>> > -	struct omap_sdrc_params *sp;
>> > +	struct omap_sdrc_params *sdrc_cs0;
>> > +	struct omap_sdrc_params *sdrc_cs1;
>> > +	int ret;
>> >
>> >  	if (!clk || !rate)
>> >  		return -EINVAL;
>> > @@ -496,8 +498,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk
>> > *clk, unsigned long rate)
>> >  	else
>> >  		sdrcrate >>= ((clk->rate / rate) >> 1);
>> >
>> > -	sp = omap2_sdrc_get_params(sdrcrate);
>> > -	if (!sp)
>> > +	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
>> > +	if (ret)
>> >  		return -EINVAL;
>> >
>> >  	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
>> > @@ -518,12 +520,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk
>> > *clk, unsigned long rate)
>> >
>> >  	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
>> >  		 validrate);
>> > -	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
>> > -		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
>> > -
>> > -	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
>> > -				  sp->actim_ctrlb, new_div, unlock_dll, c,
>> > -				  sp->mr, rate > clk->rate);
>> > +	pr_debug("clock: SDRC CS0 timing params used:"
>> > +		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
>> > +		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
>> > +		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
>> > +	if (sdrc_cs1)
>> > +		pr_debug("clock: SDRC CS1 timing params used: "
>> > +		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
>> > +		 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
>> > +		 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
>> > +
>> > +	if (sdrc_cs1)
>> > +		omap3_configure_core_dpll(
>> > +				  new_div, unlock_dll, c, rate > clk->rate,
>> > +				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
>> > +				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
>> > +				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
>> > +				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
>> > +	else
>> > +		omap3_configure_core_dpll(
>> > +				  new_div, unlock_dll, c, rate > clk->rate,
>> > +				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
>> > +				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
>> > +				  0, 0, 0, 0);
>> >
>> >  	return 0;
>> >  }
>> > diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
>> > index 6fb6c29..aa000b4 100644
>> > --- a/arch/arm/mach-omap2/io.c
>> > +++ b/arch/arm/mach-omap2/io.c
>> > @@ -231,7 +231,8 @@ static int __init _omap2_init_reprogram_sdrc(void)
>> >  	return v;
>> >  }
>> >
>> > -void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
>> > +void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
>> > +				 struct omap_sdrc_params *sdrc_cs1,
>> >  				 struct omap_opp *mpu_opps,
>> >  				 struct omap_opp *dsp_opps,
>> >  				 struct omap_opp *l3_opps)
>> > @@ -244,7 +245,7 @@ void __init omap2_init_common_hw(struct
>> > omap_sdrc_params *sp,
>> >  	omapdev_init(omapdevs);
>> >  	omap2_clk_init();
>> >  	omap_pm_if_init();
>> > -	omap2_sdrc_init(sp);
>> > +	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
>> >
>> >  	_omap2_init_reprogram_sdrc();
>> >
>> > diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
>> > index 026c4fc..43d6b92 100644
>> > --- a/arch/arm/mach-omap2/mux.c
>> > +++ b/arch/arm/mach-omap2/mux.c
>> > @@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
>> >  		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
>> >  MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
>> >  		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
>> > +
>> > +/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
>> > +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
>> > +		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
>> > +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
>> > +		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
>> >  };
>> >
>> >  #define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)
>> > diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
>> > index c832d83..b42f5ae 100644
>> > --- a/arch/arm/mach-omap2/sdrc.c
>> > +++ b/arch/arm/mach-omap2/sdrc.c
>> > @@ -32,7 +32,7 @@
>> >  #include <mach/sdrc.h>
>> >  #include "sdrc.h"
>> >
>> > -static struct omap_sdrc_params *sdrc_init_params;
>> > +static struct omap_sdrc_params *sdrc_init_params_cs0,
>> > *sdrc_init_params_cs1;
>> >
>> >  void __iomem *omap2_sdrc_base;
>> >  void __iomem *omap2_sms_base;
>> > @@ -71,33 +71,49 @@ void omap2_sms_restore_context(void)
>> >  /**
>> >   * omap2_sdrc_get_params - return SDRC register values for a given clock
>> > rate * @r: SDRC clock rate (in Hz)
>> > + * @sdrc_cs0: chip select 0 ram timings **
>> > + * @sdrc_cs1: chip select 1 ram timings **
>> >   *
>> >   * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
>> > - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
>> > - * SDRC clock rate 'r'.  These parameters control various timing
>> > - * delays in the SDRAM controller that are expressed in terms of the
>> > - * number of SDRC clock cycles to wait; hence the clock rate
>> > - * dependency. Note that sdrc_init_params must be sorted rate
>> > - * descending.  Also assumes that both chip-selects use the same
>> > - * timing parameters.  Returns a struct omap_sdrc_params * upon
>> > - * success, or NULL upon failure.
>> > + *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
>> > + *  structs,for a given SDRC clock rate 'r'.
>> > + * These parameters control various timing delays in the SDRAM
>> > controller + *  that are expressed in terms of the number of SDRC clock
>> > cycles to + *  wait; hence the clock rate dependency.
>> > + *
>> > + * Supports 2 different timing parameters for both chip selects.
>> > + *
>> > + * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
>> > + * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
>> > + *  as sdrc_init_params_cs_0.
>> > + *
>> > + * Fills in the struct omap_sdrc_params * for each chip select.
>> > + * Returns 0 upon success or -1 upon failure.
>> >   */
>> > -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
>> > +int omap2_sdrc_get_params(unsigned long r,
>> > +			  struct omap_sdrc_params **sdrc_cs0,
>> > +			  struct omap_sdrc_params **sdrc_cs1)
>> >  {
>> > -	struct omap_sdrc_params *sp;
>> > +	struct omap_sdrc_params *sp0, *sp1;
>> >
>> > -	if (!sdrc_init_params)
>> > -		return NULL;
>> > +	if (!sdrc_init_params_cs0)
>> > +		return -1;
>> >
>> > -	sp = sdrc_init_params;
>> > +	sp0 = sdrc_init_params_cs0;
>> > +	sp1 = sdrc_init_params_cs1;
>> >
>> > -	while (sp->rate && sp->rate != r)
>> > -		sp++;
>> > +	while (sp0->rate && sp0->rate != r) {
>> > +		sp0++;
>> > +		if (sdrc_init_params_cs1)
>> > +			sp1++;
>> > +	}
>> >
>> > -	if (!sp->rate)
>> > -		return NULL;
>> > +	if (!sp0->rate)
>> > +		return -1;
>> >
>> > -	return sp;
>> > +	*sdrc_cs0 = sp0;
>> > +	*sdrc_cs1 = sp1;
>> > +	return 0;
>> >  }
>> >
>> >
>> > @@ -109,13 +125,15 @@ void __init omap2_set_globals_sdrc(struct
>> > omap_globals *omap2_globals)
>> >
>> >  /**
>> >   * omap2_sdrc_init - initialize SMS, SDRC devices on boot
>> > - * @sp: pointer to a null-terminated list of struct omap_sdrc_params
>> > + * @sdrc_cs[01]: pointers to a null-terminated list of struct
>> > omap_sdrc_params
>> > + *  Support for 2 chip selects timings
>> >   *
>> >   * Turn on smart idle modes for SDRAM scheduler and controller.
>> >   * Program a known-good configuration for the SDRC to deal with buggy
>> >   * bootloaders.
>> >   */
>> > -void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
>> > +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>> > +			    struct omap_sdrc_params *sdrc_cs1)
>> >  {
>> >  	u32 l;
>> >
>> > @@ -129,7 +147,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params
>> > *sp) l |= (0x2 << 3);
>> >  	sdrc_write_reg(l, SDRC_SYSCONFIG);
>> >
>> > -	sdrc_init_params = sp;
>> > +	sdrc_init_params_cs0 = sdrc_cs0;
>> > +	sdrc_init_params_cs1 = sdrc_cs1;
>> >
>> >  	/* XXX Enable SRFRONIDLEREQ here also? */
>> >  	l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
>> > diff --git a/arch/arm/mach-omap2/sram34xx.S
>> > b/arch/arm/mach-omap2/sram34xx.S index f41f8d9..3aef744 100644
>> > --- a/arch/arm/mach-omap2/sram34xx.S
>> > +++ b/arch/arm/mach-omap2/sram34xx.S
>> > @@ -36,7 +36,7 @@
>> >
>> >  	.text
>> >
>> > -/* r4 parameters */
>> > +/* r1 parameters */
>> >  #define SDRC_NO_UNLOCK_DLL		0x0
>> >  #define SDRC_UNLOCK_DLL			0x1
>> >
>> > @@ -71,40 +71,71 @@
>> >
>> >  /*
>> >   * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
>> > - * r0 = new SDRC_RFR_CTRL register contents
>> > - * r1 = new SDRC_ACTIM_CTRLA register contents
>> > - * r2 = new SDRC_ACTIM_CTRLB register contents
>> > - * r3 = new M2 divider setting (only 1 and 2 supported right now)
>> > - * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
>> > + *
>> > + * Params passed in registers:
>> > + *  r0 = new M2 divider setting (only 1 and 2 supported right now)
>> > + *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
>> >   *      SDRC rates < 83MHz
>> > - * r5 = number of MPU cycles to wait for SDRC to stabilize after
>> > + *  r2 = number of MPU cycles to wait for SDRC to stabilize after
>> >   *      reprogramming the SDRC when switching to a slower MPU speed
>> > - * r6 = new SDRC_MR_0 register value
>> > - * r7 = increasing SDRC rate? (1 = yes, 0 = no)
>> > + *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
>> > + *
>> > + * Params passed via the stack. The needed params will be copied in SRAM
>> > + *  before use by the code in SRAM (SDRAM is not accessible during SDRC
>> > + *  reconfiguration):
>> > + *  new SDRC_RFR_CTRL_0 register contents
>> > + *  new SDRC_ACTIM_CTRL_A_0 register contents
>> > + *  new SDRC_ACTIM_CTRL_B_0 register contents
>> > + *  new SDRC_MR_0 register value
>> > + *  new SDRC_RFR_CTRL_1 register contents
>> > + *  new SDRC_ACTIM_CTRL_A_1 register contents
>> > + *  new SDRC_ACTIM_CTRL_B_1 register contents
>> > + *  new SDRC_MR_1 register value
>> >   *
>> > + * If the param SDRC_RFR_CTRL_1 is 0, the parameters
>> > + *  are not programmed into the SDRC CS1 registers
>> >   */
>> >  ENTRY(omap3_sram_configure_core_dpll)
>> >  	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
>> > -	ldr	r4, [sp, #52]		@ pull extra args off the stack
>> > -	ldr	r5, [sp, #56]		@ load extra args from the stack
>> > -	ldr	r6, [sp, #60]		@ load extra args from the stack
>> > -	ldr	r7, [sp, #64]		@ load extra args from the stack
>> > +
>> > +					@ pull the extra args off the stack
>> > +					@  and store them in SRAM
>> > +	ldr	r4, [sp, #52]
>> > +	str     r4, omap_sdrc_rfr_ctrl_0_val
>> > +	ldr	r4, [sp, #56]
>> > +	str     r4, omap_sdrc_actim_ctrl_a_0_val
>> > +	ldr	r4, [sp, #60]
>> > +	str     r4, omap_sdrc_actim_ctrl_b_0_val
>> > +	ldr	r4, [sp, #64]
>> > +	str     r4, omap_sdrc_mr_0_val
>> > +	ldr	r4, [sp, #68]
>> > +	str     r4, omap_sdrc_rfr_ctrl_1_val
>> > +	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
>> > +	beq	skip_cs1_params		@  do not use cs1 params
>> > +	ldr	r4, [sp, #72]
>> > +	str     r4, omap_sdrc_actim_ctrl_a_1_val
>> > +	ldr	r4, [sp, #76]
>> > +	str     r4, omap_sdrc_actim_ctrl_b_1_val
>> > +	ldr	r4, [sp, #80]
>> > +	str     r4, omap_sdrc_mr_1_val
>> > +skip_cs1_params:
>> >  	dsb				@ flush buffered writes to interconnect
>> > -	cmp	r7, #1			@ if increasing SDRC clk rate,
>> > +
>> > +	cmp	r3, #1			@ if increasing SDRC clk rate,
>> >  	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
>> > -	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
>> > +	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
>> >  	bleq	unlock_dll
>> >  	blne	lock_dll
>> >  	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
>> >  	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
>> >  	bl	enable_sdrc		@ take SDRC out of idle
>> > -	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
>> > +	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
>> >  	bleq	wait_dll_unlock
>> >  	blne	wait_dll_lock
>> > -	cmp	r7, #1			@ if increasing SDRC clk rate,
>> > +	cmp	r3, #1			@ if increasing SDRC clk rate,
>> >  	beq	return_to_sdram		@ return to SDRAM code, otherwise,
>> >  	bl	configure_sdrc		@ reprogram SDRC regs now
>> > -	mov	r12, r5
>> > +	mov	r12, r2
>> >  	bl	wait_clk_stable		@ wait for SDRC to stabilize
>> >  return_to_sdram:
>> >  	isb				@ prevent speculative exec past here
>> > @@ -149,7 +180,7 @@ configure_core_dpll:
>> >  	ldr	r12, [r11]
>> >  	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
>> >  	and	r12, r12, r10
>> > -	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
>> > +	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
>> >  	str	r12, [r11]
>> >  	ldr	r12, [r11]		@ posted-write barrier for CM
>> >  	bx	lr
>> > @@ -187,15 +218,34 @@ wait_dll_unlock:
>> >  	bne	wait_dll_unlock
>> >  	bx	lr
>> >  configure_sdrc:
>> > -	ldr	r11, omap3_sdrc_rfr_ctrl
>> > -	str	r0, [r11]
>> > -	ldr	r11, omap3_sdrc_actim_ctrla
>> > -	str	r1, [r11]
>> > -	ldr	r11, omap3_sdrc_actim_ctrlb
>> > -	str	r2, [r11]
>> > +	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
>> > +	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
>> > +	str	r12, [r11]			@ store
>> > +	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
>> > +	ldr	r11, omap3_sdrc_actim_ctrl_a_0
>> > +	str	r12, [r11]
>> > +	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
>> > +	ldr	r11, omap3_sdrc_actim_ctrl_b_0
>> > +	str	r12, [r11]
>> > +	ldr	r12, omap_sdrc_mr_0_val
>> >  	ldr	r11, omap3_sdrc_mr_0
>> > -	str	r6, [r11]
>> > -	ldr	r6, [r11]		@ posted-write barrier for SDRC
>> > +	str	r12, [r11]
>> > +	ldr	r12, omap_sdrc_rfr_ctrl_1_val
>> > +	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
>> > +	beq	skip_cs1_prog		@  do not program cs1 params
>> > +	ldr	r11, omap3_sdrc_rfr_ctrl_1
>> > +	str	r12, [r11]
>> > +	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
>> > +	ldr	r11, omap3_sdrc_actim_ctrl_a_1
>> > +	str	r12, [r11]
>> > +	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
>> > +	ldr	r11, omap3_sdrc_actim_ctrl_b_1
>> > +	str	r12, [r11]
>> > +	ldr	r12, omap_sdrc_mr_1_val
>> > +	ldr	r11, omap3_sdrc_mr_1
>> > +	str	r12, [r11]
>> > +skip_cs1_prog:
>> > +	ldr	r12, [r11]		@ posted-write barrier for SDRC
>> >  	bx	lr
>> >
>> >  omap3_sdrc_power:
>> > @@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
>> >  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
>> >  omap3_cm_iclken1_core:
>> >  	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
>> > -omap3_sdrc_rfr_ctrl:
>> > +
>> > +omap3_sdrc_rfr_ctrl_0:
>> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
>> > -omap3_sdrc_actim_ctrla:
>> > +omap3_sdrc_rfr_ctrl_1:
>> > +	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
>> > +omap3_sdrc_actim_ctrl_a_0:
>> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
>> > -omap3_sdrc_actim_ctrlb:
>> > +omap3_sdrc_actim_ctrl_a_1:
>> > +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
>> > +omap3_sdrc_actim_ctrl_b_0:
>> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
>> > +omap3_sdrc_actim_ctrl_b_1:
>> > +	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
>> >  omap3_sdrc_mr_0:
>> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
>> > +omap3_sdrc_mr_1:
>> > +	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
>> > +omap_sdrc_rfr_ctrl_0_val:
>> > +	.word 0xDEADBEEF
>> > +omap_sdrc_rfr_ctrl_1_val:
>> > +	.word 0xDEADBEEF
>> > +omap_sdrc_actim_ctrl_a_0_val:
>> > +	.word 0xDEADBEEF
>> > +omap_sdrc_actim_ctrl_a_1_val:
>> > +	.word 0xDEADBEEF
>> > +omap_sdrc_actim_ctrl_b_0_val:
>> > +	.word 0xDEADBEEF
>> > +omap_sdrc_actim_ctrl_b_1_val:
>> > +	.word 0xDEADBEEF
>> > +omap_sdrc_mr_0_val:
>> > +	.word 0xDEADBEEF
>> > +omap_sdrc_mr_1_val:
>> > +	.word 0xDEADBEEF
>> > +
>> >  omap3_sdrc_dlla_status:
>> >  	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>> >  omap3_sdrc_dlla_ctrl:
>> > @@ -223,3 +299,4 @@ core_m2_mask_val:
>> >
>> >  ENTRY(omap3_sram_configure_core_dpll_sz)
>> >  	.word	. - omap3_sram_configure_core_dpll
>> > +
>> > diff --git a/arch/arm/plat-omap/include/mach/io.h
>> > b/arch/arm/plat-omap/include/mach/io.h
>> > index 54c159b..d4c78b4 100644
>> > --- a/arch/arm/plat-omap/include/mach/io.h
>> > +++ b/arch/arm/plat-omap/include/mach/io.h
>> > @@ -192,7 +192,8 @@ extern void omap1_map_common_io(void);
>> >  extern void omap1_init_common_hw(void);
>> >
>> >  extern void omap2_map_common_io(void);
>> > -extern void omap2_init_common_hw(struct omap_sdrc_params *sp,
>> > +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
>> > +				 struct omap_sdrc_params *sdrc_cs1,
>> >  				 struct omap_opp *mpu_opps,
>> >  				 struct omap_opp *dsp_opps,
>> >  				 struct omap_opp *l3_opps);
>> > diff --git a/arch/arm/plat-omap/include/mach/mux.h
>> > b/arch/arm/plat-omap/include/mach/mux.h
>> > index f7e298a..7368aba 100644
>> > --- a/arch/arm/plat-omap/include/mach/mux.h
>> > +++ b/arch/arm/plat-omap/include/mach/mux.h
>> > @@ -803,6 +803,10 @@ enum omap34xx_index {
>> >  	AE5_34XX_GPIO143,
>> >  	H19_34XX_GPIO164_OUT,
>> >  	J25_34XX_GPIO170,
>> > +
>> > +	/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
>> > +	H16_34XX_SDRC_CKE0,
>> > +	H17_34XX_SDRC_CKE1,
>> >  };
>> >
>> >  struct omap_mux_cfg {
>> > diff --git a/arch/arm/plat-omap/include/mach/sdrc.h
>> > b/arch/arm/plat-omap/include/mach/sdrc.h
>> > index a678bc8..7e22143 100644
>> > --- a/arch/arm/plat-omap/include/mach/sdrc.h
>> > +++ b/arch/arm/plat-omap/include/mach/sdrc.h
>> > @@ -114,9 +114,11 @@ struct omap_sdrc_params {
>> >
>> >  void omap2_sms_save_context(void);
>> >  void omap2_sms_restore_context(void);
>> > -void __init omap2_sdrc_init(struct omap_sdrc_params *);
>> > -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
>> > -
>> > +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>> > +			    struct omap_sdrc_params *sdrc_cs1);
>> > +int omap2_sdrc_get_params(unsigned long r,
>> > +			  struct omap_sdrc_params **sdrc_cs0,
>> > +			  struct omap_sdrc_params **sdrc_cs1);
>> >  #ifdef CONFIG_ARCH_OMAP2
>> >
>> >  struct memory_timings {
>> > diff --git a/arch/arm/plat-omap/include/mach/sram.h
>> > b/arch/arm/plat-omap/include/mach/sram.h
>> > index ad0a600..98906ea 100644
>> > --- a/arch/arm/plat-omap/include/mach/sram.h
>> > +++ b/arch/arm/plat-omap/include/mach/sram.h
>> > @@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level,
>> > u32 dll_val,
>> >  				      u32 mem_type);
>> >  extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int
>> > bypass);
>> >
>> > -extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
>> > -				     u32 sdrc_actim_ctrla,
>> > -				     u32 sdrc_actim_ctrlb, u32 m2,
>> > -				     u32 unlock_dll, u32 f, u32 sdrc_mr,
>> > -				     u32 inc);
>> > +extern u32 omap3_configure_core_dpll(
>> > +			u32 m2, u32 unlock_dll, u32 f, u32 inc,
>> > +			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
>> > +			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>> > +			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
>> > +			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>> > +
>> >  extern void omap3_sram_restore_context(void);
>> >
>> >  /* Do not use these */
>> > @@ -61,11 +63,12 @@ extern void omap243x_sram_reprogram_sdrc(u32
>> > perf_level, u32 dll_val,
>> >  extern unsigned long omap243x_sram_reprogram_sdrc_sz;
>> >
>> >
>> > -extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
>> > -					  u32 sdrc_actim_ctrla,
>> > -					  u32 sdrc_actim_ctrlb, u32 m2,
>> > -					  u32 unlock_dll, u32 f, u32 sdrc_mr,
>> > -					  u32 inc);
>> > +extern u32 omap3_sram_configure_core_dpll(
>> > +			u32 m2, u32 unlock_dll, u32 f, u32 inc,
>> > +			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
>> > +			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>> > +			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
>> > +			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>> >  extern unsigned long omap3_sram_configure_core_dpll_sz;
>> >
>> >  #ifdef CONFIG_PM
>> > diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
>> > index a2e60e7..517f45b 100644
>> > --- a/arch/arm/plat-omap/sram.c
>> > +++ b/arch/arm/plat-omap/sram.c
>> > @@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
>> >
>> >  #ifdef CONFIG_ARCH_OMAP3
>> >
>> > -static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
>> > -					      u32 sdrc_actim_ctrla,
>> > -					      u32 sdrc_actim_ctrlb,
>> > -					      u32 m2, u32 unlock_dll,
>> > -					      u32 f, u32 sdrc_mr, u32 inc);
>> > -u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
>> > -			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
>> > -			      u32 f, u32 sdrc_mr, u32 inc)
>> > - {
>> > +static u32 (*_omap3_sram_configure_core_dpll)(
>> > +				u32 m2, u32 unlock_dll, u32 f, u32 inc,
>> > +				u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
>> > +				u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>> > +				u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
>> > +				u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>> > +
>> > +u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
>> > +			      u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
>> > +			      u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>> > +			      u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
>> > +			      u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
>> > +{
>> >  	if (!_omap3_sram_configure_core_dpll)
>> >  		omap_sram_error();
>> >
>> > -	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
>> > -					       sdrc_actim_ctrla,
>> > -					       sdrc_actim_ctrlb, m2,
>> > -					       unlock_dll, f, sdrc_mr, inc);
>> > - }
>> > +	return _omap3_sram_configure_core_dpll(
>> > +				m2, unlock_dll, f, inc,
>> > +				sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
>> > +				sdrc_actim_ctrl_b_0, sdrc_mr_0,
>> > +				sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
>> > +				sdrc_actim_ctrl_b_1, sdrc_mr_1);
>> > +}
>> >
>> >  #ifdef CONFIG_PM
>> >  void omap3_sram_restore_context(void)
>> > --
>> > 1.6.2.5.168.g3823
>> >
>> > On Friday 05 June 2009 20:10:40 Paul Walmsley wrote:
>> >> Hi Jean,
>> >>
>> >> On Fri, 5 Jun 2009, Jean Pihet wrote:
>> >> > Here is the new patch that includes all the remarks and suggestion.
>> >> > The description is here below.
>> >> >
>> >> > Some notes:
>> >> > - all calls to omap2_init_common_hw have been adapted in the board
>> >> > files. it looks like 2430SDP and Pandora board files are broken since
>> >> > they use only one param. Can that be checked on those boards?
>> >> > - it is assumed that RX51 only uses 1 CS. Is that correct?
>> >> >
>> >> > Can you review it and possibly merge?
>> >>
>> >> Looks great.
>> >>
>> >> Tero, does RX51 use two SDRC chipselects!
>> >>
>> >> Acked-by: Paul Walmsley <paul@pwsan.com>
>> >>
>> >> > Thanks & regards,
>> >> > Jean

RE: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects

[Tero.Kristo]

>-----Original Message-----
>From: ext Kevin Hilman [mailto:khilman@deeprootsystems.com]
>Sent: 08 June, 2009 20:24
>To: Jean Pihet
>Cc: Paul Walmsley; Kristo Tero (Nokia-D/Tampere); linux-omap
>Subject: Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects
>
>Jean Pihet <jpihet@mvista.com> writes:
>
>> On Monday 08 June 2009 16:59:36 Kevin Hilman wrote:
>>> Jean Pihet <jpihet@mvista.com> writes:
>>> > Paul,
>>> >
>>> > Here is the updated patch that fixes the Overo build as well.
>>> > Can you check it?
>>> >
>>> > Kevin, can you push it if it is correct?
>>>
>>> Can you run it through checkpatch, fix the errors and also merge
>>> Tero's
>>> RX51 patch if it looks good to you.
>> Ok. I will check. The cause might be the mailer.
>>
>> I think we need the omap_cfg_reg calls in the RX51 board
>file as well,
>> even if the bootloader has the mux setting already right. That way a
>> warning will be issued in case of a faulty bootloader. Do you agree?
>
>I agree.

Well, this is ok for me too as it does not really change anything. I will voice my opinion here though. :)

I find it somewhat weird that we take care of two pads in this fashion out of ~350 or so, where in most cases we just assume that the pads are configured properly by the boot loader. Should we do the same for every pad? Does the kernel even boot if the CKE signals are configured incorrectly? I would guess the boot loader will fail to load the kernel image into SDRAM in that case.

-Tero

>
>Kevin
>
>>>
>>> Below are the checkpatch errors I get:  looks lik your mailer is
>>> probably wrapping the patch and there is also one error to fix.
>>>
>>> Kevin
>>
>> Regards,
>> Jean
>>>
>>> ERROR: patch seems to be corrupt (line wrapped?)
>>> #306: FILE: arch/arm/mach-omap2/clock34xx.c:477:
>>> unsigned long rate)
>>>
>>> ERROR: trailing whitespace
>>> #494: FILE: arch/arm/mach-omap2/sdrc.c:128:
>>> + * @sdrc_cs[01]: pointers to a null-terminated list of struct $
>>>
>>> total: 2 errors, 0 warnings, 648 lines checked
>>>
>>> Your patch has style problems, please review.  If any of
>these errors
>>> are false positives report them to the maintainer, see
>CHECKPATCH in
>>> MAINTAINERS.
>>>
>>> > Regards,
>>> > Jean
>>> >
>>> > From ebe57354b04444de059e1f042e0c488f761853f0 Mon Sep 17 00:00:00
>>> > 2001
>>> > From: Jean Pihet <jpihet@mvista.com>
>>> > Date: Fri, 5 Jun 2009 17:19:00 +0200
>>> > Subject: OMAP3: add support for 2 SDRAM chip selects
>>> >
>>> > Some boards (Beagle Cx, Overo) have 2 SDRAM parts
>connected to the
>>> > SDRC.
>>> >
>>> > This patch adds the following:
>>> > - ensure that the CKE signals mux settings are correct
>>> > - add a new argument of type omap_sdrc_params struct* to
>>> > omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
>>> > - adapted the OMAP boards files to the new prototype of
>>> > omap2_init_common_hw. Only Beagle and Overo are using the 2 CS'es
>>> > - adapt the sram sleep code to configure the SDRC for the 2nd CS
>>> >
>>> > Note: If the 2nd param to omap2_init_common_hw is NULL, then the
>>> > parameters are not programmed into the SDRC CS1 registers
>>> >
>>> > Tested on 3430 SDP and Beagleboard rev C2 and B5, with
>>> > suspend/resume and frequency changes (cpufreq).
>>> >
>>> > Thanks to Paul Walmsley and Kevin Hilman for the suggestions and
>>> > code reviews.
>>> >
>>> > Signed-off-by: Jean Pihet <jpihet@mvista.com>
>>> > ---
>>> >  arch/arm/mach-omap2/board-2430sdp.c      |    2 +-
>>> >  arch/arm/mach-omap2/board-3430sdp.c      |    6 +-
>>> >  arch/arm/mach-omap2/board-apollon.c      |    2 +-
>>> >  arch/arm/mach-omap2/board-generic.c      |    2 +-
>>> >  arch/arm/mach-omap2/board-h4.c           |    2 +-
>>> >  arch/arm/mach-omap2/board-ldp.c          |    2 +-
>>> >  arch/arm/mach-omap2/board-n800.c         |    2 +-
>>> >  arch/arm/mach-omap2/board-omap2evm.c     |    2 +-
>>> >  arch/arm/mach-omap2/board-omap3beagle.c  |   11 ++-
>>> >  arch/arm/mach-omap2/board-omap3evm.c     |    6 +-
>>> >  arch/arm/mach-omap2/board-omap3pandora.c |    3 +-
>>> >  arch/arm/mach-omap2/board-overo.c        |    9 ++-
>>> >  arch/arm/mach-omap2/board-rx51.c         |    6 +-
>>> >  arch/arm/mach-omap2/clock34xx.c          |   37 ++++++--
>>> >  arch/arm/mach-omap2/io.c                 |    5 +-
>>> >  arch/arm/mach-omap2/mux.c                |    6 ++
>>> >  arch/arm/mach-omap2/sdrc.c               |   63 +++++++++-----
>>> >  arch/arm/mach-omap2/sram34xx.S           |  137
>>> > +++++++++++++++++++++++-------
>>> >  arch/arm/plat-omap/include/mach/io.h     |    3 +-
>>> >  arch/arm/plat-omap/include/mach/mux.h    |    4 +
>>> >  arch/arm/plat-omap/include/mach/sdrc.h   |    8 +-
>>> >  arch/arm/plat-omap/include/mach/sram.h   |   23 +++--
>>> >  arch/arm/plat-omap/sram.c                |   34 +++++---
>>> >  23 files changed, 267 insertions(+), 108 deletions(-)
>>> >
>>> > diff --git a/arch/arm/mach-omap2/board-2430sdp.c
>>> > b/arch/arm/mach-omap2/board-2430sdp.c
>>> > index aa5df72..4cb7bc5 100644
>>> > --- a/arch/arm/mach-omap2/board-2430sdp.c
>>> > +++ b/arch/arm/mach-omap2/board-2430sdp.c
>>> > @@ -322,7 +322,7 @@ out:
>>> >
>>> >  static void __init omap_2430sdp_init_irq(void)  {
>>> > - omap2_init_common_hw(NULL);
>>> > + omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >   sdp2430_init_smc91x();
>>> > diff --git a/arch/arm/mach-omap2/board-3430sdp.c
>>> > b/arch/arm/mach-omap2/board-3430sdp.c
>>> > index 195b749..24e2728 100644
>>> > --- a/arch/arm/mach-omap2/board-3430sdp.c
>>> > +++ b/arch/arm/mach-omap2/board-3430sdp.c
>>> > @@ -302,8 +302,10 @@ static inline void __init
>>> > sdp3430_init_smc91x(void)
>>> >
>>> >  static void __init omap_3430sdp_init_irq(void)  {
>>> > - omap2_init_common_hw(hyb18m512160af6_sdrc_params,
>omap3_mpu_rate_table,
>>> > -                      omap3_dsp_rate_table, omap3_l3_rate_table);
>>> > + omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL,
>>> > +                      omap3_mpu_rate_table,
>>> > +                      omap3_dsp_rate_table,
>>> > +                      omap3_l3_rate_table);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >   sdp3430_init_smc91x();
>>> > diff --git a/arch/arm/mach-omap2/board-apollon.c
>>> > b/arch/arm/mach-omap2/board-apollon.c
>>> > index 2e24812..2dd1350 100644
>>> > --- a/arch/arm/mach-omap2/board-apollon.c
>>> > +++ b/arch/arm/mach-omap2/board-apollon.c
>>> > @@ -323,7 +323,7 @@ out:
>>> >
>>> >  static void __init omap_apollon_init_irq(void)  {
>>> > - omap2_init_common_hw(NULL, NULL, NULL, NULL);
>>> > + omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >   apollon_init_smc91x();
>>> > diff --git a/arch/arm/mach-omap2/board-generic.c
>>> > b/arch/arm/mach-omap2/board-generic.c
>>> > index be763a9..763329b 100644
>>> > --- a/arch/arm/mach-omap2/board-generic.c
>>> > +++ b/arch/arm/mach-omap2/board-generic.c
>>> > @@ -33,7 +33,7 @@
>>> >
>>> >  static void __init omap_generic_init_irq(void)  {
>>> > - omap2_init_common_hw(NULL, NULL, NULL, NULL);
>>> > + omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >  }
>>> >
>>> > diff --git a/arch/arm/mach-omap2/board-h4.c
>>> > b/arch/arm/mach-omap2/board-h4.c index 8f54939..17c3599 100644
>>> > --- a/arch/arm/mach-omap2/board-h4.c
>>> > +++ b/arch/arm/mach-omap2/board-h4.c
>>> > @@ -348,7 +348,7 @@ static void __init h4_init_flash(void)
>>> >
>>> >  static void __init omap_h4_init_irq(void)  {
>>> > - omap2_init_common_hw(NULL, NULL, NULL, NULL);
>>> > + omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >   h4_init_flash();
>>> > diff --git a/arch/arm/mach-omap2/board-ldp.c
>>> > b/arch/arm/mach-omap2/board-ldp.c index 9f41dc9..b012806 100644
>>> > --- a/arch/arm/mach-omap2/board-ldp.c
>>> > +++ b/arch/arm/mach-omap2/board-ldp.c
>>> > @@ -344,7 +344,7 @@ static inline void __init
>>> > ldp_init_smc911x(void)
>>> >
>>> >  static void __init omap_ldp_init_irq(void)  {
>>> > - omap2_init_common_hw(NULL, NULL, NULL, NULL);
>>> > + omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >   ldp_init_smc911x();
>>> > diff --git a/arch/arm/mach-omap2/board-n800.c
>>> > b/arch/arm/mach-omap2/board-n800.c
>>> > index ac7cf3f..ad53f4a 100644
>>> > --- a/arch/arm/mach-omap2/board-n800.c
>>> > +++ b/arch/arm/mach-omap2/board-n800.c
>>> > @@ -127,7 +127,7 @@ static struct lm8323_platform_data
>lm8323_pdata
>>> > = {
>>> >
>>> >  void __init nokia_n800_init_irq(void)  {
>>> > - omap2_init_common_hw(NULL, NULL, NULL, NULL);
>>> > + omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >
>>> > diff --git a/arch/arm/mach-omap2/board-omap2evm.c
>>> > b/arch/arm/mach-omap2/board-omap2evm.c
>>> > index 4fac1be..56a26d4 100644
>>> > --- a/arch/arm/mach-omap2/board-omap2evm.c
>>> > +++ b/arch/arm/mach-omap2/board-omap2evm.c
>>> > @@ -276,7 +276,7 @@ static struct twl4030_keypad_data
>>> > omap2evm_kp_data = {
>>> >
>>> >  static void __init omap2_evm_init_irq(void)  {
>>> > - omap2_init_common_hw(NULL, NULL, NULL, NULL);
>>> > + omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >   omap2evm_init_smc911x();
>>> > diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
>>> > b/arch/arm/mach-omap2/board-omap3beagle.c
>>> > index 7294dbf..872beb6 100644
>>> > --- a/arch/arm/mach-omap2/board-omap3beagle.c
>>> > +++ b/arch/arm/mach-omap2/board-omap3beagle.c
>>> > @@ -312,8 +312,11 @@ static int __init omap3_beagle_i2c_init(void)
>>> >
>>> >  static void __init omap3_beagle_init_irq(void)  {
>>> > - omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>omap3_mpu_rate_table,
>>> > -                      omap3_dsp_rate_table, omap3_l3_rate_table);
>>> > + omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>>> > +                      mt46h32m32lf6_sdrc_params,
>>> > +                      omap3_mpu_rate_table,
>>> > +                      omap3_dsp_rate_table,
>>> > +                      omap3_l3_rate_table);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >  }
>>> > @@ -441,6 +444,10 @@ static void __init omap3_beagle_init(void)
>>> >   usb_musb_init();
>>> >   usb_ehci_init();
>>> >   omap3beagle_flash_init();
>>> > +
>>> > + /* Ensure SDRC pins are mux'd for self-refresh */
>>> > + omap_cfg_reg(H16_34XX_SDRC_CKE0);
>>> > + omap_cfg_reg(H17_34XX_SDRC_CKE1);
>>> >  }
>>> >
>>> >  static void __init omap3_beagle_map_io(void) diff --git
>>> > a/arch/arm/mach-omap2/board-omap3evm.c
>>> > b/arch/arm/mach-omap2/board-omap3evm.c
>>> > index f017f0d..3b9c96a 100644
>>> > --- a/arch/arm/mach-omap2/board-omap3evm.c
>>> > +++ b/arch/arm/mach-omap2/board-omap3evm.c
>>> > @@ -276,8 +276,10 @@ struct spi_board_info
>>> > omap3evm_spi_board_info[] = {
>>> >
>>> >  static void __init omap3_evm_init_irq(void)  {
>>> > - omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>omap3_mpu_rate_table,
>>> > -                      omap3_dsp_rate_table, omap3_l3_rate_table);
>>> > + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>>> > +                      omap3_mpu_rate_table,
>>> > +                      omap3_dsp_rate_table,
>>> > +                      omap3_l3_rate_table);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >   omap3evm_init_smc911x();
>>> > diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
>>> > b/arch/arm/mach-omap2/board-omap3pandora.c
>>> > index c67f62f..05ab99e 100644
>>> > --- a/arch/arm/mach-omap2/board-omap3pandora.c
>>> > +++ b/arch/arm/mach-omap2/board-omap3pandora.c
>>> > @@ -220,7 +220,8 @@ static int __init omap3pandora_i2c_init(void)
>>> >
>>> >  static void __init omap3pandora_init_irq(void)  {
>>> > - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
>>> > + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>>> > +                      NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >  }
>>> > diff --git a/arch/arm/mach-omap2/board-overo.c
>>> > b/arch/arm/mach-omap2/board-overo.c
>>> > index 9eae608..50902d4 100644
>>> > --- a/arch/arm/mach-omap2/board-overo.c
>>> > +++ b/arch/arm/mach-omap2/board-overo.c
>>> > @@ -45,6 +45,7 @@
>>> >  #include <mach/gpmc.h>
>>> >  #include <mach/hardware.h>
>>> >  #include <mach/nand.h>
>>> > +#include <mach/mux.h>
>>> >  #include <mach/usb.h>
>>> >
>>> >  #include "sdram-micron-mt46h32m32lf-6.h"
>>> > @@ -355,7 +356,9 @@ static int __init overo_i2c_init(void)
>>> >
>>> >  static void __init overo_init_irq(void)  {
>>> > - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>NULL, NULL);
>>> > + omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>>> > +                      mt46h32m32lf6_sdrc_params,
>>> > +                      NULL, NULL, NULL);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >  }
>>> > @@ -391,6 +394,10 @@ static void __init overo_init(void)
>>> >   overo_init_smsc911x();
>>> >   overo_ads7846_init();
>>> >
>>> > + /* Ensure SDRC pins are mux'd for self-refresh */
>>> > + omap_cfg_reg(H16_34XX_SDRC_CKE0);
>>> > + omap_cfg_reg(H17_34XX_SDRC_CKE1);
>>> > +
>>> >   if ((gpio_request(OVERO_GPIO_W2W_NRESET,
>>> >                     "OVERO_GPIO_W2W_NRESET") == 0) &&
>>> >       (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
>>> > diff --git a/arch/arm/mach-omap2/board-rx51.c
>>> > b/arch/arm/mach-omap2/board-rx51.c
>>> > index 09035b0..d48459f 100644
>>> > --- a/arch/arm/mach-omap2/board-rx51.c
>>> > +++ b/arch/arm/mach-omap2/board-rx51.c
>>> > @@ -64,8 +64,10 @@ static struct omap_board_config_kernel
>>> > rx51_config[] = {
>>> >
>>> >  static void __init rx51_init_irq(void)  {
>>> > - omap2_init_common_hw(rx51_get_sdram_timings(),
>omap3_mpu_rate_table,
>>> > -                      omap3_dsp_rate_table, omap3_l3_rate_table);
>>> > + omap2_init_common_hw(rx51_get_sdram_timings(), NULL,
>>> > +                      omap3_mpu_rate_table,
>>> > +                      omap3_dsp_rate_table,
>>> > +                      omap3_l3_rate_table);
>>> >   omap_init_irq();
>>> >   omap_gpio_init();
>>> >  }
>>> > diff --git a/arch/arm/mach-omap2/clock34xx.c
>>> > b/arch/arm/mach-omap2/clock34xx.c index 3cee6b4..f262787 100644
>>> > --- a/arch/arm/mach-omap2/clock34xx.c
>>> > +++ b/arch/arm/mach-omap2/clock34xx.c
>>> > @@ -478,7 +478,9 @@ static int omap3_core_dpll_m2_set_rate(struct
>>> > clk *clk, unsigned long rate)
>>> >   u32 unlock_dll = 0;
>>> >   u32 c;
>>> >   unsigned long validrate, sdrcrate, mpurate;
>>> > - struct omap_sdrc_params *sp;
>>> > + struct omap_sdrc_params *sdrc_cs0;
>>> > + struct omap_sdrc_params *sdrc_cs1;
>>> > + int ret;
>>> >
>>> >   if (!clk || !rate)
>>> >           return -EINVAL;
>>> > @@ -496,8 +498,8 @@ static int omap3_core_dpll_m2_set_rate(struct
>>> > clk *clk, unsigned long rate)
>>> >   else
>>> >           sdrcrate >>= ((clk->rate / rate) >> 1);
>>> >
>>> > - sp = omap2_sdrc_get_params(sdrcrate);
>>> > - if (!sp)
>>> > + ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
>>> > + if (ret)
>>> >           return -EINVAL;
>>> >
>>> >   if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { @@ -518,12 +520,29 @@
>>> > static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned
>>> > long rate)
>>> >
>>> >   pr_debug("clock: changing CORE DPLL rate from %lu to
>%lu\n", clk->rate,
>>> >            validrate);
>>> > - pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
>>> > -          sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
>>> > -
>>> > - omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
>>> > -                           sp->actim_ctrlb, new_div,
>unlock_dll, c,
>>> > -                           sp->mr, rate > clk->rate);
>>> > + pr_debug("clock: SDRC CS0 timing params used:"
>>> > +          " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
>>> > +          sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
>>> > +          sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
>>> > + if (sdrc_cs1)
>>> > +         pr_debug("clock: SDRC CS1 timing params used: "
>>> > +          " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
>>> > +          sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
>>> > +          sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
>>> > +
>>> > + if (sdrc_cs1)
>>> > +         omap3_configure_core_dpll(
>>> > +                           new_div, unlock_dll, c, rate
>> clk->rate,
>>> > +                           sdrc_cs0->rfr_ctrl,
>sdrc_cs0->actim_ctrla,
>>> > +                           sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
>>> > +                           sdrc_cs1->rfr_ctrl,
>sdrc_cs1->actim_ctrla,
>>> > +                           sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
>>> > + else
>>> > +         omap3_configure_core_dpll(
>>> > +                           new_div, unlock_dll, c, rate
>> clk->rate,
>>> > +                           sdrc_cs0->rfr_ctrl,
>sdrc_cs0->actim_ctrla,
>>> > +                           sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
>>> > +                           0, 0, 0, 0);
>>> >
>>> >   return 0;
>>> >  }
>>> > diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
>>> > index 6fb6c29..aa000b4 100644
>>> > --- a/arch/arm/mach-omap2/io.c
>>> > +++ b/arch/arm/mach-omap2/io.c
>>> > @@ -231,7 +231,8 @@ static int __init
>_omap2_init_reprogram_sdrc(void)
>>> >   return v;
>>> >  }
>>> >
>>> > -void __init omap2_init_common_hw(struct omap_sdrc_params *sp,
>>> > +void __init omap2_init_common_hw(struct omap_sdrc_params
>*sdrc_cs0,
>>> > +                          struct omap_sdrc_params *sdrc_cs1,
>>> >                            struct omap_opp *mpu_opps,
>>> >                            struct omap_opp *dsp_opps,
>>> >                            struct omap_opp *l3_opps)
>>> > @@ -244,7 +245,7 @@ void __init omap2_init_common_hw(struct
>>> > omap_sdrc_params *sp,
>>> >   omapdev_init(omapdevs);
>>> >   omap2_clk_init();
>>> >   omap_pm_if_init();
>>> > - omap2_sdrc_init(sp);
>>> > + omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
>>> >
>>> >   _omap2_init_reprogram_sdrc();
>>> >
>>> > diff --git a/arch/arm/mach-omap2/mux.c
>b/arch/arm/mach-omap2/mux.c
>>> > index 026c4fc..43d6b92 100644
>>> > --- a/arch/arm/mach-omap2/mux.c
>>> > +++ b/arch/arm/mach-omap2/mux.c
>>> > @@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
>>> >           OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
>>> > MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
>>> >           OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
>>> > +
>>> > +/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
>>> > +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
>>> > +         OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
>>> > +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
>>> > +         OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
>>> >  };
>>> >
>>> >  #define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
>>> > diff --git a/arch/arm/mach-omap2/sdrc.c
>>> > b/arch/arm/mach-omap2/sdrc.c index c832d83..b42f5ae 100644
>>> > --- a/arch/arm/mach-omap2/sdrc.c
>>> > +++ b/arch/arm/mach-omap2/sdrc.c
>>> > @@ -32,7 +32,7 @@
>>> >  #include <mach/sdrc.h>
>>> >  #include "sdrc.h"
>>> >
>>> > -static struct omap_sdrc_params *sdrc_init_params;
>>> > +static struct omap_sdrc_params *sdrc_init_params_cs0,
>>> > *sdrc_init_params_cs1;
>>> >
>>> >  void __iomem *omap2_sdrc_base;
>>> >  void __iomem *omap2_sms_base;
>>> > @@ -71,33 +71,49 @@ void omap2_sms_restore_context(void)
>>> >  /**
>>> >   * omap2_sdrc_get_params - return SDRC register values
>for a given
>>> > clock rate * @r: SDRC clock rate (in Hz)
>>> > + * @sdrc_cs0: chip select 0 ram timings **
>>> > + * @sdrc_cs1: chip select 1 ram timings **
>>> >   *
>>> >   * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
>>> > - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a
>>> > given
>>> > - * SDRC clock rate 'r'.  These parameters control various timing
>>> > - * delays in the SDRAM controller that are expressed in terms of
>>> > the
>>> > - * number of SDRC clock cycles to wait; hence the clock rate
>>> > - * dependency. Note that sdrc_init_params must be sorted rate
>>> > - * descending.  Also assumes that both chip-selects use the same
>>> > - * timing parameters.  Returns a struct omap_sdrc_params * upon
>>> > - * success, or NULL upon failure.
>>> > + *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in
>>> > + sdrc_cs[01]
>>> > + *  structs,for a given SDRC clock rate 'r'.
>>> > + * These parameters control various timing delays in the SDRAM
>>> > controller + *  that are expressed in terms of the number of SDRC
>>> > clock cycles to + *  wait; hence the clock rate dependency.
>>> > + *
>>> > + * Supports 2 different timing parameters for both chip selects.
>>> > + *
>>> > + * Note 1: the sdrc_init_params_cs[01] must be sorted
>rate descending.
>>> > + * Note 2: If sdrc_init_params_cs_1 is not NULL it must
>be of same
>>> > + size
>>> > + *  as sdrc_init_params_cs_0.
>>> > + *
>>> > + * Fills in the struct omap_sdrc_params * for each chip select.
>>> > + * Returns 0 upon success or -1 upon failure.
>>> >   */
>>> > -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
>>> > +int omap2_sdrc_get_params(unsigned long r,
>>> > +                   struct omap_sdrc_params **sdrc_cs0,
>>> > +                   struct omap_sdrc_params **sdrc_cs1)
>>> >  {
>>> > - struct omap_sdrc_params *sp;
>>> > + struct omap_sdrc_params *sp0, *sp1;
>>> >
>>> > - if (!sdrc_init_params)
>>> > -         return NULL;
>>> > + if (!sdrc_init_params_cs0)
>>> > +         return -1;
>>> >
>>> > - sp = sdrc_init_params;
>>> > + sp0 = sdrc_init_params_cs0;
>>> > + sp1 = sdrc_init_params_cs1;
>>> >
>>> > - while (sp->rate && sp->rate != r)
>>> > -         sp++;
>>> > + while (sp0->rate && sp0->rate != r) {
>>> > +         sp0++;
>>> > +         if (sdrc_init_params_cs1)
>>> > +                 sp1++;
>>> > + }
>>> >
>>> > - if (!sp->rate)
>>> > -         return NULL;
>>> > + if (!sp0->rate)
>>> > +         return -1;
>>> >
>>> > - return sp;
>>> > + *sdrc_cs0 = sp0;
>>> > + *sdrc_cs1 = sp1;
>>> > + return 0;
>>> >  }
>>> >
>>> >
>>> > @@ -109,13 +125,15 @@ void __init omap2_set_globals_sdrc(struct
>>> > omap_globals *omap2_globals)
>>> >
>>> >  /**
>>> >   * omap2_sdrc_init - initialize SMS, SDRC devices on boot
>>> > - * @sp: pointer to a null-terminated list of struct
>>> > omap_sdrc_params
>>> > + * @sdrc_cs[01]: pointers to a null-terminated list of struct
>>> > omap_sdrc_params
>>> > + *  Support for 2 chip selects timings
>>> >   *
>>> >   * Turn on smart idle modes for SDRAM scheduler and controller.
>>> >   * Program a known-good configuration for the SDRC to
>deal with buggy
>>> >   * bootloaders.
>>> >   */
>>> > -void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
>>> > +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>>> > +                     struct omap_sdrc_params *sdrc_cs1)
>>> >  {
>>> >   u32 l;
>>> >
>>> > @@ -129,7 +147,8 @@ void __init omap2_sdrc_init(struct
>>> > omap_sdrc_params
>>> > *sp) l |= (0x2 << 3);
>>> >   sdrc_write_reg(l, SDRC_SYSCONFIG);
>>> >
>>> > - sdrc_init_params = sp;
>>> > + sdrc_init_params_cs0 = sdrc_cs0;
>>> > + sdrc_init_params_cs1 = sdrc_cs1;
>>> >
>>> >   /* XXX Enable SRFRONIDLEREQ here also? */
>>> >   l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | diff --git
>>> > a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
>>> > index f41f8d9..3aef744 100644
>>> > --- a/arch/arm/mach-omap2/sram34xx.S
>>> > +++ b/arch/arm/mach-omap2/sram34xx.S
>>> > @@ -36,7 +36,7 @@
>>> >
>>> >   .text
>>> >
>>> > -/* r4 parameters */
>>> > +/* r1 parameters */
>>> >  #define SDRC_NO_UNLOCK_DLL               0x0
>>> >  #define SDRC_UNLOCK_DLL                  0x1
>>> >
>>> > @@ -71,40 +71,71 @@
>>> >
>>> >  /*
>>> >   * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
>>> > - * r0 = new SDRC_RFR_CTRL register contents
>>> > - * r1 = new SDRC_ACTIM_CTRLA register contents
>>> > - * r2 = new SDRC_ACTIM_CTRLB register contents
>>> > - * r3 = new M2 divider setting (only 1 and 2 supported right now)
>>> > - * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
>>> > + *
>>> > + * Params passed in registers:
>>> > + *  r0 = new M2 divider setting (only 1 and 2 supported
>right now)
>>> > + *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
>>> >   *      SDRC rates < 83MHz
>>> > - * r5 = number of MPU cycles to wait for SDRC to stabilize after
>>> > + *  r2 = number of MPU cycles to wait for SDRC to stabilize after
>>> >   *      reprogramming the SDRC when switching to a
>slower MPU speed
>>> > - * r6 = new SDRC_MR_0 register value
>>> > - * r7 = increasing SDRC rate? (1 = yes, 0 = no)
>>> > + *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
>>> > + *
>>> > + * Params passed via the stack. The needed params will be copied
>>> > + in SRAM
>>> > + *  before use by the code in SRAM (SDRAM is not
>accessible during
>>> > + SDRC
>>> > + *  reconfiguration):
>>> > + *  new SDRC_RFR_CTRL_0 register contents
>>> > + *  new SDRC_ACTIM_CTRL_A_0 register contents
>>> > + *  new SDRC_ACTIM_CTRL_B_0 register contents
>>> > + *  new SDRC_MR_0 register value
>>> > + *  new SDRC_RFR_CTRL_1 register contents
>>> > + *  new SDRC_ACTIM_CTRL_A_1 register contents
>>> > + *  new SDRC_ACTIM_CTRL_B_1 register contents
>>> > + *  new SDRC_MR_1 register value
>>> >   *
>>> > + * If the param SDRC_RFR_CTRL_1 is 0, the parameters
>>> > + *  are not programmed into the SDRC CS1 registers
>>> >   */
>>> >  ENTRY(omap3_sram_configure_core_dpll)
>>> >   stmfd   sp!, {r1-r12, lr}       @ store regs to stack
>>> > - ldr     r4, [sp, #52]           @ pull extra args off the stack
>>> > - ldr     r5, [sp, #56]           @ load extra args from the stack
>>> > - ldr     r6, [sp, #60]           @ load extra args from the stack
>>> > - ldr     r7, [sp, #64]           @ load extra args from the stack
>>> > +
>>> > +                                 @ pull the extra args
>off the stack
>>> > +                                 @  and store them in SRAM
>>> > + ldr     r4, [sp, #52]
>>> > + str     r4, omap_sdrc_rfr_ctrl_0_val
>>> > + ldr     r4, [sp, #56]
>>> > + str     r4, omap_sdrc_actim_ctrl_a_0_val
>>> > + ldr     r4, [sp, #60]
>>> > + str     r4, omap_sdrc_actim_ctrl_b_0_val
>>> > + ldr     r4, [sp, #64]
>>> > + str     r4, omap_sdrc_mr_0_val
>>> > + ldr     r4, [sp, #68]
>>> > + str     r4, omap_sdrc_rfr_ctrl_1_val
>>> > + cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
>>> > + beq     skip_cs1_params         @  do not use cs1 params
>>> > + ldr     r4, [sp, #72]
>>> > + str     r4, omap_sdrc_actim_ctrl_a_1_val
>>> > + ldr     r4, [sp, #76]
>>> > + str     r4, omap_sdrc_actim_ctrl_b_1_val
>>> > + ldr     r4, [sp, #80]
>>> > + str     r4, omap_sdrc_mr_1_val
>>> > +skip_cs1_params:
>>> >   dsb                             @ flush buffered writes
>to interconnect
>>> > - cmp     r7, #1                  @ if increasing SDRC clk rate,
>>> > +
>>> > + cmp     r3, #1                  @ if increasing SDRC clk rate,
>>> >   bleq    configure_sdrc          @ program the SDRC regs
>early (for RFR)
>>> > - cmp     r4, #SDRC_UNLOCK_DLL    @ set the intended DLL state
>>> > + cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
>>> >   bleq    unlock_dll
>>> >   blne    lock_dll
>>> >   bl      sdram_in_selfrefresh    @ put SDRAM in self
>refresh, idle SDRC
>>> >   bl      configure_core_dpll     @ change the DPLL3 M2 divider
>>> >   bl      enable_sdrc             @ take SDRC out of idle
>>> > - cmp     r4, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
>>> > + cmp     r1, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
>>> >   bleq    wait_dll_unlock
>>> >   blne    wait_dll_lock
>>> > - cmp     r7, #1                  @ if increasing SDRC clk rate,
>>> > + cmp     r3, #1                  @ if increasing SDRC clk rate,
>>> >   beq     return_to_sdram         @ return to SDRAM code,
>otherwise,
>>> >   bl      configure_sdrc          @ reprogram SDRC regs now
>>> > - mov     r12, r5
>>> > + mov     r12, r2
>>> >   bl      wait_clk_stable         @ wait for SDRC to stabilize
>>> >  return_to_sdram:
>>> >   isb                             @ prevent speculative
>exec past here
>>> > @@ -149,7 +180,7 @@ configure_core_dpll:
>>> >   ldr     r12, [r11]
>>> >   ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
>>> >   and     r12, r12, r10
>>> > - orr     r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
>>> > + orr     r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
>>> >   str     r12, [r11]
>>> >   ldr     r12, [r11]              @ posted-write barrier for CM
>>> >   bx      lr
>>> > @@ -187,15 +218,34 @@ wait_dll_unlock:
>>> >   bne     wait_dll_unlock
>>> >   bx      lr
>>> >  configure_sdrc:
>>> > - ldr     r11, omap3_sdrc_rfr_ctrl
>>> > - str     r0, [r11]
>>> > - ldr     r11, omap3_sdrc_actim_ctrla
>>> > - str     r1, [r11]
>>> > - ldr     r11, omap3_sdrc_actim_ctrlb
>>> > - str     r2, [r11]
>>> > + ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
>>> > + ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
>>> > + str     r12, [r11]                      @ store
>>> > + ldr     r12, omap_sdrc_actim_ctrl_a_0_val
>>> > + ldr     r11, omap3_sdrc_actim_ctrl_a_0
>>> > + str     r12, [r11]
>>> > + ldr     r12, omap_sdrc_actim_ctrl_b_0_val
>>> > + ldr     r11, omap3_sdrc_actim_ctrl_b_0
>>> > + str     r12, [r11]
>>> > + ldr     r12, omap_sdrc_mr_0_val
>>> >   ldr     r11, omap3_sdrc_mr_0
>>> > - str     r6, [r11]
>>> > - ldr     r6, [r11]               @ posted-write barrier for SDRC
>>> > + str     r12, [r11]
>>> > + ldr     r12, omap_sdrc_rfr_ctrl_1_val
>>> > + cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
>>> > + beq     skip_cs1_prog           @  do not program cs1 params
>>> > + ldr     r11, omap3_sdrc_rfr_ctrl_1
>>> > + str     r12, [r11]
>>> > + ldr     r12, omap_sdrc_actim_ctrl_a_1_val
>>> > + ldr     r11, omap3_sdrc_actim_ctrl_a_1
>>> > + str     r12, [r11]
>>> > + ldr     r12, omap_sdrc_actim_ctrl_b_1_val
>>> > + ldr     r11, omap3_sdrc_actim_ctrl_b_1
>>> > + str     r12, [r11]
>>> > + ldr     r12, omap_sdrc_mr_1_val
>>> > + ldr     r11, omap3_sdrc_mr_1
>>> > + str     r12, [r11]
>>> > +skip_cs1_prog:
>>> > + ldr     r12, [r11]              @ posted-write barrier for SDRC
>>> >   bx      lr
>>> >
>>> >  omap3_sdrc_power:
>>> > @@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
>>> >   .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
>>> >  omap3_cm_iclken1_core:
>>> >   .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
>>> > -omap3_sdrc_rfr_ctrl:
>>> > +
>>> > +omap3_sdrc_rfr_ctrl_0:
>>> >   .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
>>> > -omap3_sdrc_actim_ctrla:
>>> > +omap3_sdrc_rfr_ctrl_1:
>>> > + .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
>>> > +omap3_sdrc_actim_ctrl_a_0:
>>> >   .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
>>> > -omap3_sdrc_actim_ctrlb:
>>> > +omap3_sdrc_actim_ctrl_a_1:
>>> > + .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
>>> > +omap3_sdrc_actim_ctrl_b_0:
>>> >   .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
>>> > +omap3_sdrc_actim_ctrl_b_1:
>>> > + .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
>>> >  omap3_sdrc_mr_0:
>>> >   .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
>>> > +omap3_sdrc_mr_1:
>>> > + .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
>>> > +omap_sdrc_rfr_ctrl_0_val:
>>> > + .word 0xDEADBEEF
>>> > +omap_sdrc_rfr_ctrl_1_val:
>>> > + .word 0xDEADBEEF
>>> > +omap_sdrc_actim_ctrl_a_0_val:
>>> > + .word 0xDEADBEEF
>>> > +omap_sdrc_actim_ctrl_a_1_val:
>>> > + .word 0xDEADBEEF
>>> > +omap_sdrc_actim_ctrl_b_0_val:
>>> > + .word 0xDEADBEEF
>>> > +omap_sdrc_actim_ctrl_b_1_val:
>>> > + .word 0xDEADBEEF
>>> > +omap_sdrc_mr_0_val:
>>> > + .word 0xDEADBEEF
>>> > +omap_sdrc_mr_1_val:
>>> > + .word 0xDEADBEEF
>>> > +
>>> >  omap3_sdrc_dlla_status:
>>> >   .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>>> >  omap3_sdrc_dlla_ctrl:
>>> > @@ -223,3 +299,4 @@ core_m2_mask_val:
>>> >
>>> >  ENTRY(omap3_sram_configure_core_dpll_sz)
>>> >   .word   . - omap3_sram_configure_core_dpll
>>> > +
>>> > diff --git a/arch/arm/plat-omap/include/mach/io.h
>>> > b/arch/arm/plat-omap/include/mach/io.h
>>> > index 54c159b..d4c78b4 100644
>>> > --- a/arch/arm/plat-omap/include/mach/io.h
>>> > +++ b/arch/arm/plat-omap/include/mach/io.h
>>> > @@ -192,7 +192,8 @@ extern void
>omap1_map_common_io(void);  extern
>>> > void omap1_init_common_hw(void);
>>> >
>>> >  extern void omap2_map_common_io(void); -extern void
>>> > omap2_init_common_hw(struct omap_sdrc_params *sp,
>>> > +extern void omap2_init_common_hw(struct omap_sdrc_params
>*sdrc_cs0,
>>> > +                          struct omap_sdrc_params *sdrc_cs1,
>>> >                            struct omap_opp *mpu_opps,
>>> >                            struct omap_opp *dsp_opps,
>>> >                            struct omap_opp *l3_opps);
>>> > diff --git a/arch/arm/plat-omap/include/mach/mux.h
>>> > b/arch/arm/plat-omap/include/mach/mux.h
>>> > index f7e298a..7368aba 100644
>>> > --- a/arch/arm/plat-omap/include/mach/mux.h
>>> > +++ b/arch/arm/plat-omap/include/mach/mux.h
>>> > @@ -803,6 +803,10 @@ enum omap34xx_index {
>>> >   AE5_34XX_GPIO143,
>>> >   H19_34XX_GPIO164_OUT,
>>> >   J25_34XX_GPIO170,
>>> > +
>>> > + /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
>>> > + H16_34XX_SDRC_CKE0,
>>> > + H17_34XX_SDRC_CKE1,
>>> >  };
>>> >
>>> >  struct omap_mux_cfg {
>>> > diff --git a/arch/arm/plat-omap/include/mach/sdrc.h
>>> > b/arch/arm/plat-omap/include/mach/sdrc.h
>>> > index a678bc8..7e22143 100644
>>> > --- a/arch/arm/plat-omap/include/mach/sdrc.h
>>> > +++ b/arch/arm/plat-omap/include/mach/sdrc.h
>>> > @@ -114,9 +114,11 @@ struct omap_sdrc_params {
>>> >
>>> >  void omap2_sms_save_context(void);  void
>>> > omap2_sms_restore_context(void); -void __init
>>> > omap2_sdrc_init(struct omap_sdrc_params *); -struct
>>> > omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
>>> > -
>>> > +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>>> > +                     struct omap_sdrc_params *sdrc_cs1); int
>>> > +omap2_sdrc_get_params(unsigned long r,
>>> > +                   struct omap_sdrc_params **sdrc_cs0,
>>> > +                   struct omap_sdrc_params **sdrc_cs1);
>>> >  #ifdef CONFIG_ARCH_OMAP2
>>> >
>>> >  struct memory_timings {
>>> > diff --git a/arch/arm/plat-omap/include/mach/sram.h
>>> > b/arch/arm/plat-omap/include/mach/sram.h
>>> > index ad0a600..98906ea 100644
>>> > --- a/arch/arm/plat-omap/include/mach/sram.h
>>> > +++ b/arch/arm/plat-omap/include/mach/sram.h
>>> > @@ -21,11 +21,13 @@ extern void omap2_sram_reprogram_sdrc(u32
>>> > perf_level,
>>> > u32 dll_val,
>>> >                                 u32 mem_type);
>>> >  extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32
>sdrc_rfr_val, int
>>> > bypass);
>>> >
>>> > -extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
>>> > -                              u32 sdrc_actim_ctrla,
>>> > -                              u32 sdrc_actim_ctrlb, u32 m2,
>>> > -                              u32 unlock_dll, u32 f, u32 sdrc_mr,
>>> > -                              u32 inc);
>>> > +extern u32 omap3_configure_core_dpll(
>>> > +                 u32 m2, u32 unlock_dll, u32 f, u32 inc,
>>> > +                 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
>>> > +                 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>>> > +                 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
>>> > +                 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>>> > +
>>> >  extern void omap3_sram_restore_context(void);
>>> >
>>> >  /* Do not use these */
>>> > @@ -61,11 +63,12 @@ extern void omap243x_sram_reprogram_sdrc(u32
>>> > perf_level, u32 dll_val,  extern unsigned long
>>> > omap243x_sram_reprogram_sdrc_sz;
>>> >
>>> >
>>> > -extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
>>> > -                                   u32 sdrc_actim_ctrla,
>>> > -                                   u32 sdrc_actim_ctrlb, u32 m2,
>>> > -                                   u32 unlock_dll, u32
>f, u32 sdrc_mr,
>>> > -                                   u32 inc);
>>> > +extern u32 omap3_sram_configure_core_dpll(
>>> > +                 u32 m2, u32 unlock_dll, u32 f, u32 inc,
>>> > +                 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
>>> > +                 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>>> > +                 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
>>> > +                 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>>> >  extern unsigned long omap3_sram_configure_core_dpll_sz;
>>> >
>>> >  #ifdef CONFIG_PM
>>> > diff --git a/arch/arm/plat-omap/sram.c
>b/arch/arm/plat-omap/sram.c
>>> > index a2e60e7..517f45b 100644
>>> > --- a/arch/arm/plat-omap/sram.c
>>> > +++ b/arch/arm/plat-omap/sram.c
>>> > @@ -368,23 +368,29 @@ static inline int omap243x_sram_init(void)
>>> >
>>> >  #ifdef CONFIG_ARCH_OMAP3
>>> >
>>> > -static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
>>> > -                                       u32 sdrc_actim_ctrla,
>>> > -                                       u32 sdrc_actim_ctrlb,
>>> > -                                       u32 m2, u32 unlock_dll,
>>> > -                                       u32 f, u32
>sdrc_mr, u32 inc);
>>> > -u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32
>sdrc_actim_ctrla,
>>> > -                       u32 sdrc_actim_ctrlb, u32 m2, u32
>unlock_dll,
>>> > -                       u32 f, u32 sdrc_mr, u32 inc)
>>> > - {
>>> > +static u32 (*_omap3_sram_configure_core_dpll)(
>>> > +                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
>>> > +                         u32 sdrc_rfr_ctrl_0, u32
>sdrc_actim_ctrl_a_0,
>>> > +                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>>> > +                         u32 sdrc_rfr_ctrl_1, u32
>sdrc_actim_ctrl_a_1,
>>> > +                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
>>> > +
>>> > +u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll,
>u32 f, u32 inc,
>>> > +                       u32 sdrc_rfr_ctrl_0, u32
>sdrc_actim_ctrl_a_0,
>>> > +                       u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
>>> > +                       u32 sdrc_rfr_ctrl_1, u32
>sdrc_actim_ctrl_a_1,
>>> > +                       u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1) {
>>> >   if (!_omap3_sram_configure_core_dpll)
>>> >           omap_sram_error();
>>> >
>>> > - return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
>>> > -                                        sdrc_actim_ctrla,
>>> > -                                        sdrc_actim_ctrlb, m2,
>>> > -                                        unlock_dll, f,
>sdrc_mr, inc);
>>> > - }
>>> > + return _omap3_sram_configure_core_dpll(
>>> > +                         m2, unlock_dll, f, inc,
>>> > +                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
>>> > +                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
>>> > +                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
>>> > +                         sdrc_actim_ctrl_b_1, sdrc_mr_1); }
>>> >
>>> >  #ifdef CONFIG_PM
>>> >  void omap3_sram_restore_context(void)
>>> > --
>>> > 1.6.2.5.168.g3823
>>> >
>>> > On Friday 05 June 2009 20:10:40 Paul Walmsley wrote:
>>> >> Hi Jean,
>>> >>
>>> >> On Fri, 5 Jun 2009, Jean Pihet wrote:
>>> >> > Here is the new patch that includes all the remarks
>and suggestion.
>>> >> > The description is here below.
>>> >> >
>>> >> > Some notes:
>>> >> > - all calls to omap2_init_common_hw have been adapted in the
>>> >> > board files. it looks like 2430SDP and Pandora board files are
>>> >> > broken since they use only one param. Can that be
>checked on those boards?
>>> >> > - it is assumed that RX51 only uses 1 CS. Is that correct?
>>> >> >
>>> >> > Can you review it and possibly merge?
>>> >>
>>> >> Looks great.
>>> >>
>>> >> Tero, does RX51 use two SDRC chipselects!
>>> >>
>>> >> Acked-by: Paul Walmsley <paul@pwsan.com>
>>> >>
>>> >> > Thanks & regards,
>>> >> > Jean
>

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects

[Jean Pihet]

On Tuesday 09 June 2009 10:14:58 Tero.Kristo@nokia.com wrote:
> >-----Original Message-----
> >From: ext Kevin Hilman [mailto:khilman@deeprootsystems.com]
> >Sent: 08 June, 2009 20:24
> >To: Jean Pihet
> >Cc: Paul Walmsley; Kristo Tero (Nokia-D/Tampere); linux-omap
> >Subject: Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects
> >
> >Jean Pihet <jpihet@mvista.com> writes:
> >> On Monday 08 June 2009 16:59:36 Kevin Hilman wrote:
> >>> Jean Pihet <jpihet@mvista.com> writes:
> >>> > Paul,
> >>> >
> >>> > Here is the updated patch that fixes the Overo build as well.
> >>> > Can you check it?
> >>> >
> >>> > Kevin, can you push it if it is correct?
> >>>
> >>> Can you run it through checkpatch, fix the errors and also merge
> >>> Tero's
> >>> RX51 patch if it looks good to you.
> >>
> >> Ok. I will check. The cause might be the mailer.
> >>
> >> I think we need the omap_cfg_reg calls in the RX51 board
> >
> >file as well,
> >
> >> even if the bootloader has the mux setting already right. That way a
> >> warning will be issued in case of a faulty bootloader. Do you agree?
> >
> >I agree.
>
> Well, this is ok for me too as it does not really change anything. I will
> voice my opinion here though. :)
>
> I find it somewhat weird that we take care of two pads in this fashion out
> of ~350 or so, where in most cases we just assume that the pads are
> configured properly by the boot loader. Should we do the same for every
> pad?
Got your point. This omap_cfg_reg throws a warning if the pad is incorrectly 
configured. The goal is to better track the problem in case of a wrong/older 
bootloader. In the ideal world the bootloader and kernel should match and do 
it all right!

> Does the kernel even boot if the CKE signals are configured 
> incorrectly? I would guess the boot loader will fail to load the kernel
> image into SDRAM in that case.
The kernel boots fine in that case, only the SDRAM contents are not preserved 
when going to low power mode.
>
> -Tero

RE: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects

[Tero.Kristo]

 

>-----Original Message-----
>From: ext Jean Pihet [mailto:jpihet@mvista.com] 
>Sent: 09 June, 2009 11:24
>To: Kristo Tero (Nokia-D/Tampere)
>Cc: khilman@deeprootsystems.com; paul@pwsan.com; 
>linux-omap@vger.kernel.org
>Subject: Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects
>
>On Tuesday 09 June 2009 10:14:58 Tero.Kristo@nokia.com wrote:
>> >-----Original Message-----
>> >From: ext Kevin Hilman [mailto:khilman@deeprootsystems.com]
>> >Sent: 08 June, 2009 20:24
>> >To: Jean Pihet
>> >Cc: Paul Walmsley; Kristo Tero (Nokia-D/Tampere); linux-omap
>> >Subject: Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM 
>chip selects
>> >
>> >Jean Pihet <jpihet@mvista.com> writes:
>> >> On Monday 08 June 2009 16:59:36 Kevin Hilman wrote:
>> >>> Jean Pihet <jpihet@mvista.com> writes:
>> >>> > Paul,
>> >>> >
>> >>> > Here is the updated patch that fixes the Overo build as well.
>> >>> > Can you check it?
>> >>> >
>> >>> > Kevin, can you push it if it is correct?
>> >>>
>> >>> Can you run it through checkpatch, fix the errors and also merge 
>> >>> Tero's
>> >>> RX51 patch if it looks good to you.
>> >>
>> >> Ok. I will check. The cause might be the mailer.
>> >>
>> >> I think we need the omap_cfg_reg calls in the RX51 board
>> >
>> >file as well,
>> >
>> >> even if the bootloader has the mux setting already right. 
>That way 
>> >> a warning will be issued in case of a faulty bootloader. 
>Do you agree?
>> >
>> >I agree.
>>
>> Well, this is ok for me too as it does not really change anything. I 
>> will voice my opinion here though. :)
>>
>> I find it somewhat weird that we take care of two pads in 
>this fashion 
>> out of ~350 or so, where in most cases we just assume that the pads 
>> are configured properly by the boot loader. Should we do the 
>same for 
>> every pad?
>Got your point. This omap_cfg_reg throws a warning if the pad 
>is incorrectly configured. The goal is to better track the 
>problem in case of a wrong/older bootloader. In the ideal 
>world the bootloader and kernel should match and do it all right!
>
>> Does the kernel even boot if the CKE signals are configured 
>> incorrectly? I would guess the boot loader will fail to load the 
>> kernel image into SDRAM in that case.
>The kernel boots fine in that case, only the SDRAM contents 
>are not preserved when going to low power mode.

Ok, in this case it sounds ok to me also as it might generate hard to track bugs.

-Tero

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Paul Walmsley]

Hi Jean,

On Mon, 8 Jun 2009, Jean Pihet wrote:

> Here is the updated patch that fixes the Overo build as well.
> Can you check it?

> diff --git a/arch/arm/mach-omap2/board-overo.c 
> b/arch/arm/mach-omap2/board-overo.c
> index 9eae608..50902d4 100644
> --- a/arch/arm/mach-omap2/board-overo.c
> +++ b/arch/arm/mach-omap2/board-overo.c
> @@ -45,6 +45,7 @@
>  #include <mach/gpmc.h>
>  #include <mach/hardware.h>
>  #include <mach/nand.h>
> +#include <mach/mux.h>
>  #include <mach/usb.h>
>  
>  #include "sdram-micron-mt46h32m32lf-6.h"
> @@ -355,7 +356,9 @@ static int __init overo_i2c_init(void)
>  
>  static void __init overo_init_irq(void)
>  {
> -	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL, NULL, NULL);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> +			     mt46h32m32lf6_sdrc_params,
> +			     NULL, NULL, NULL);
>  	omap_init_irq();
>  	omap_gpio_init();
>  }
> @@ -391,6 +394,10 @@ static void __init overo_init(void)
>  	overo_init_smsc911x();
>  	overo_ads7846_init();
>  
> +	/* Ensure SDRC pins are mux'd for self-refresh */
> +	omap_cfg_reg(H16_34XX_SDRC_CKE0);
> +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
> +
>  	if ((gpio_request(OVERO_GPIO_W2W_NRESET,
>  			  "OVERO_GPIO_W2W_NRESET") == 0) &&
>  	    (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {

These changes look fine to me based on a quick look.  Haven't tried 
building it.


- Paul

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 468 bytes --]

Hi Jean,

On Fri, 5 Jun 2009, Jean Pihet wrote:

> Some notes:
> - all calls to omap2_init_common_hw have been adapted in the board files. it 
> looks like 2430SDP and Pandora board files are broken since they use only one 
> param. Can that be checked on those boards?

Yep, builds with those two boards are broken on the PM branch, and it 
looks like your patch fixes both.  

Gražyvdas, looks like Pandora might use 2 SDRAM chipselects also?


- Paul

Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Grazvydas Ignotas]

On Fri, Jun 5, 2009 at 10:14 PM, Paul Walmsley<paul@pwsan.com> wrote:
> Hi Jean,
>
> On Fri, 5 Jun 2009, Jean Pihet wrote:
>
>> Some notes:
>> - all calls to omap2_init_common_hw have been adapted in the board files. it
>> looks like 2430SDP and Pandora board files are broken since they use only one
>> param. Can that be checked on those boards?
>
> Yep, builds with those two boards are broken on the PM branch, and it
> looks like your patch fixes both.
>
> Gražyvdas, looks like Pandora might use 2 SDRAM chipselects also?

Yes it does, it uses different part than Beagle rev C (256/512
RAM/NAND instead of 256/256), but RAM portion should be identical I
guess.


Gražvydas
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Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Jean Pihet]

Paul, Gražvydas,

Ok, thanks!

Here is a patch that addresses the Pandora's use of 2 SDRAM chip selects.
It applies on top of 'OMAP3: add support for 2 SDRAM chip selects'.

Is that OK? It has been build tested only.

Regards,
Jean

From 297a0b09267fc1a0ae4428771ff54b73b27d5bbe Mon Sep 17 00:00:00 2001
From: Jean Pihet <jpihet@mvista.com>
Date: Mon, 8 Jun 2009 10:49:53 +0200
Subject: OMAP3 Pandora: add support for 2 SDRAM chip selects

This allows the self refresh to work correctly on
Pandora.

Signed-off-by: Jean Pihet <jpihet@mvista.com>
---
 arch/arm/mach-omap2/board-omap3pandora.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap3pandora.c 
b/arch/arm/mach-omap2/board-omap3pandora.c
index 05ab99e..ba015b4 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -44,6 +44,7 @@
 #include <mach/gpmc.h>
 #include <mach/hardware.h>
 #include <mach/nand.h>
+#include <mach/mux.h>
 #include <mach/usb.h>
 #include <mach/mcspi.h>
 
@@ -220,7 +221,8 @@ static int __init omap3pandora_i2c_init(void)
 
 static void __init omap3pandora_init_irq(void)
 {
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+			     mt46h32m32lf6_sdrc_params,
 			     NULL, NULL, NULL);
 	omap_init_irq();
 	omap_gpio_init();
@@ -307,6 +309,10 @@ static void __init omap3pandora_init(void)
 	usb_ehci_init();
 	omap3pandora_flash_init();
 	omap3pandora_ads7846_init();
+
+	/* Ensure SDRC pins are mux'd for self-refresh */
+	omap_cfg_reg(H16_34XX_SDRC_CKE0);
+	omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3pandora_map_io(void)
-- 
1.6.2.5.168.g3823


On Saturday 06 June 2009 12:50:42 Grazvydas Ignotas wrote:
> On Fri, Jun 5, 2009 at 10:14 PM, Paul Walmsley<paul@pwsan.com> wrote:
> > Hi Jean,
> >
> > On Fri, 5 Jun 2009, Jean Pihet wrote:
> >> Some notes:
> >> - all calls to omap2_init_common_hw have been adapted in the board
> >> files. it looks like 2430SDP and Pandora board files are broken since
> >> they use only one param. Can that be checked on those boards?
> >
> > Yep, builds with those two boards are broken on the PM branch, and it
> > looks like your patch fixes both.
> >
> > Gražyvdas, looks like Pandora might use 2 SDRAM chipselects also?
>
> Yes it does, it uses different part than Beagle rev C (256/512
> RAM/NAND instead of 256/256), but RAM portion should be identical I
> guess.
>
>
> Gražvydas


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Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Grazvydas Ignotas]

On Mon, Jun 8, 2009 at 12:02 PM, Jean Pihet<jpihet@mvista.com> wrote:
> Paul, Gražvydas,
>
> Ok, thanks!
>
> Here is a patch that addresses the Pandora's use of 2 SDRAM chip selects.
> It applies on top of 'OMAP3: add support for 2 SDRAM chip selects'.
>
> Is that OK? It has been build tested only.

thanks!

>
> Regards,
> Jean
>
> From 297a0b09267fc1a0ae4428771ff54b73b27d5bbe Mon Sep 17 00:00:00 2001
> From: Jean Pihet <jpihet@mvista.com>
> Date: Mon, 8 Jun 2009 10:49:53 +0200
> Subject: OMAP3 Pandora: add support for 2 SDRAM chip selects
>
> This allows the self refresh to work correctly on
> Pandora.
>
> Signed-off-by: Jean Pihet <jpihet@mvista.com>
> ---
>  arch/arm/mach-omap2/board-omap3pandora.c |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
> b/arch/arm/mach-omap2/board-omap3pandora.c
> index 05ab99e..ba015b4 100644
> --- a/arch/arm/mach-omap2/board-omap3pandora.c
> +++ b/arch/arm/mach-omap2/board-omap3pandora.c
> @@ -44,6 +44,7 @@
>  #include <mach/gpmc.h>
>  #include <mach/hardware.h>
>  #include <mach/nand.h>
> +#include <mach/mux.h>
>  #include <mach/usb.h>
>  #include <mach/mcspi.h>
>
> @@ -220,7 +221,8 @@ static int __init omap3pandora_i2c_init(void)
>
>  static void __init omap3pandora_init_irq(void)
>  {
> -       omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
> +       omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> +                            mt46h32m32lf6_sdrc_params,
>                             NULL, NULL, NULL);

Hm, since pandora uses OMAP3530, maybe it should also have
omap3_*_rate_table args passed? Could also be true for Overo, at least
for omap3_mpu_rate_table and omap3_l3_rate_table, as some models use
OMAP3503 without the DSP.

>        omap_init_irq();
>        omap_gpio_init();
> @@ -307,6 +309,10 @@ static void __init omap3pandora_init(void)
>        usb_ehci_init();
>        omap3pandora_flash_init();
>        omap3pandora_ads7846_init();
> +
> +       /* Ensure SDRC pins are mux'd for self-refresh */
> +       omap_cfg_reg(H16_34XX_SDRC_CKE0);
> +       omap_cfg_reg(H17_34XX_SDRC_CKE1);
>  }
>
>  static void __init omap3pandora_map_io(void)
> --
> 1.6.2.5.168.g3823
>
>
> On Saturday 06 June 2009 12:50:42 Grazvydas Ignotas wrote:
>> On Fri, Jun 5, 2009 at 10:14 PM, Paul Walmsley<paul@pwsan.com> wrote:
>> > Hi Jean,
>> >
>> > On Fri, 5 Jun 2009, Jean Pihet wrote:
>> >> Some notes:
>> >> - all calls to omap2_init_common_hw have been adapted in the board
>> >> files. it looks like 2430SDP and Pandora board files are broken since
>> >> they use only one param. Can that be checked on those boards?
>> >
>> > Yep, builds with those two boards are broken on the PM branch, and it
>> > looks like your patch fixes both.
>> >
>> > Gražyvdas, looks like Pandora might use 2 SDRAM chipselects also?
>>
>> Yes it does, it uses different part than Beagle rev C (256/512
>> RAM/NAND instead of 256/256), but RAM portion should be identical I
>> guess.
>>
>>
>> Gražvydas
>
>
>
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Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects (was: Re: Beagleboard rev C memory timings & suspend/resume)

[Jean Pihet]

Hi Kevin,

On Monday 08 June 2009 13:01:18 Grazvydas Ignotas wrote:
> >  static void __init omap3pandora_init_irq(void)
> >  {
> > -       omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
> > +       omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> > +                            mt46h32m32lf6_sdrc_params,
> >                             NULL, NULL, NULL);
>
> Hm, since pandora uses OMAP3530, maybe it should also have
> omap3_*_rate_table args passed? Could also be true for Overo, at least
> for omap3_mpu_rate_table and omap3_l3_rate_table, as some models use
> OMAP3503 without the DSP.
Which table rates shall we pass for Overo and Pandora?
I will update the patch set with the needed ones.

Regards,
Jean
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Re: [RFC][PATCH] OMAP3: add support for 2 SDRAM chip selects

[Kevin Hilman]

Jean Pihet <jpihet@mvista.com> writes:

> Hi Kevin,
>
> On Monday 08 June 2009 13:01:18 Grazvydas Ignotas wrote:
>> >  static void __init omap3pandora_init_irq(void)
>> >  {
>> > -       omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL,
>> > +       omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
>> > +                            mt46h32m32lf6_sdrc_params,
>> >                             NULL, NULL, NULL);
>>
>> Hm, since pandora uses OMAP3530, maybe it should also have
>> omap3_*_rate_table args passed? Could also be true for Overo, at least
>> for omap3_mpu_rate_table and omap3_l3_rate_table, as some models use
>> OMAP3503 without the DSP.
>
> Which table rates shall we pass for Overo and Pandora?
> I will update the patch set with the needed ones.
>

Let's leave any rate table changes out of this series.  That is an
unrelated change.

The Pandora/Overo folks should do some testing with the current rate
tables and DVFS/CPUfreq to see if they work for them.

Kevin
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Re: Beagleboard rev C memory timings & suspend/resume

[Paul Walmsley]

Hello Jean,

one other suggestion.  You mentioned that you had self-refresh working on 
another OMAP3430 board with two SDRAM chip-selects.  You might consider 
dumping the SDRC registers from that board, and dumping the SDRC registers 
on Beagle rev C, and comparing.  It could be that the bootloader on your 
other board is setting some important bit.


- Paul

Re: Beagleboard rev C memory timings & suspend/resume

[Jean Pihet]

On Thursday 07 May 2009 21:18:41 Paul Walmsley wrote:
> Hello Jean,
>
> one other suggestion.  You mentioned that you had self-refresh working on
> another OMAP3430 board with two SDRAM chip-selects.  You might consider
> dumping the SDRC registers from that board, and dumping the SDRC registers
> on Beagle rev C, and comparing.  It could be that the bootloader on your
> other board is setting some important bit.
The comparison gives the following:
- the timings are slightly different but given that the parts are not the same 
I do not think it is a problem
- the fields FIXEDDELAY and MODEFIXEDDELAYINITLAT are set in SDRC_DLLA_CTRL, 
the register value is 0x2600000A. Does that affect the 166MHz operation?
- the field DEEPPD of SDRC_MCFG_p is set to 0. That setting could affect the 
suspend/resume
- the MUX scheme is different: ADDRMUXLEGACY is set to 0
- the field BANKALLOCATION of SDRC_MCFG_p is set to 0 instead of 2

I tried to change those fields on the Beagleboard but still suspending for 
more than 10sec corrupts the memory.

> - Paul

Regards,
Jean

Re: Beagleboard rev C memory timings & suspend/resume

[Paul Walmsley]

On Fri, 8 May 2009, Jean Pihet wrote:

> On Thursday 07 May 2009 21:18:41 Paul Walmsley wrote:
> > Hello Jean,
> >
> > one other suggestion.  You mentioned that you had self-refresh working on
> > another OMAP3430 board with two SDRAM chip-selects.  You might consider
> > dumping the SDRC registers from that board, and dumping the SDRC registers
> > on Beagle rev C, and comparing.  It could be that the bootloader on your
> > other board is setting some important bit.
> The comparison gives the following:
> - the timings are slightly different but given that the parts are not the same 
> I do not think it is a problem
> - the fields FIXEDDELAY and MODEFIXEDDELAYINITLAT are set in SDRC_DLLA_CTRL, 
> the register value is 0x2600000A. Does that affect the 166MHz operation?

It shouldn't.

> - the field DEEPPD of SDRC_MCFG_p is set to 0. That setting could affect the 
> suspend/resume

I don't think this should matter, since we never power off the SDRAM.

> - the MUX scheme is different: ADDRMUXLEGACY is set to 0
> - the field BANKALLOCATION of SDRC_MCFG_p is set to 0 instead of 2

- Paul