From: Paul Walmsley <paul@pwsan.com>
To: linux-arm-kernel@lists.arm.linux.org.uk
Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
Paul Walmsley <paul@pwsan.com>
Subject: [PATCH 04/10] OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change
Date: Tue, 12 May 2009 18:05:18 -0600 [thread overview]
Message-ID: <20090513000517.10349.22865.stgit@localhost.localdomain> (raw)
In-Reply-To: <20090512235713.10349.49339.stgit@localhost.localdomain>
Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh
mode. This prevents the SDRC from attempting to power off the SDRAM,
which can cause the system to hang.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/sram34xx.S | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 8d524f3..9a45415 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -77,7 +77,9 @@ lock_dll:
sdram_in_selfrefresh:
ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
ldr r5, [r4] @ read the contents of SDRC_POWER
+ mov r9, r5 @ keep a copy of SDRC_POWER bits
orr r5, r5, #0x40 @ enable self refresh on idle req
+ bic r5, r5, #0x4 @ clear PWDENA
str r5, [r4] @ write back to SDRC_POWER register
ldr r5, [r4] @ posted-write barrier for SDRC
ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
@@ -128,10 +130,9 @@ wait_sdrc_idle1:
and r5, r5, #0x2
cmp r5, #0
bne wait_sdrc_idle1
+restore_sdrc_power_val:
ldr r4, omap3_sdrc_power
- ldr r5, [r4]
- bic r5, r5, #0x40
- str r5, [r4]
+ str r9, [r4] @ restore SDRC_POWER, no barrier needed
bx lr
wait_dll_lock:
ldr r4, omap3_sdrc_dlla_status
next prev parent reply other threads:[~2009-05-13 0:07 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-13 0:05 [PATCH 00/10] OMAP clock/SDRC patches on v2.6.30-rc5 Paul Walmsley
2009-05-13 0:05 ` [PATCH 01/10] OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory Paul Walmsley
2009-05-13 0:05 ` [PATCH 02/10] OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll Paul Walmsley
2009-05-13 0:05 ` [PATCH 03/10] OMAP3 clock: add interconnect barriers to CORE DPLL M2 change Paul Walmsley
2009-05-13 0:05 ` Paul Walmsley [this message]
2009-05-13 0:05 ` [PATCH 05/10] OMAP3 SDRC: initialize SDRC_POWER at boot Paul Walmsley
2009-05-13 0:05 ` [PATCH 06/10] OMAP3 SRAM: renumber registers to make space for argument passing Paul Walmsley
2009-05-13 0:05 ` [PATCH 07/10] OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz Paul Walmsley
2009-05-13 0:05 ` [PATCH 08/10] OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code Paul Walmsley
2009-05-13 0:05 ` [PATCH 09/10] OMAP3 clock: lessen amount of noisy messages Paul Walmsley
2009-05-13 0:05 ` [PATCH 10/10] OMAP2xxx clock: rename clk_init_one() to clk_preinit() Paul Walmsley
2009-05-26 16:29 ` [PATCH 00/10] OMAP clock/SDRC patches on v2.6.30-rc5 Paul Walmsley
2009-05-26 16:37 ` Russell King - ARM Linux
2009-05-26 16:51 ` Paul Walmsley
2009-05-26 22:04 ` Tony Lindgren
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