[PATCH 0/2] PM: OMAP3 SDRC: fix some SDRAM settings for Qimonda parts

[PATCH 0/2] PM: OMAP3 SDRC: fix some SDRAM settings for Qimonda parts

[Paul Walmsley]

Hi,

This series updates some SDRAM parameter settings for the Qimonda parts
used on some 3430SDP boards.

Finally some 3430SDP boards are using bootloaders with rounded DPLL3 rates
(e.g., 166000000 Hz rather than 165941176 Hz); update the Qimonda SDRAM
parameters.

Also when reviewing the timing calculations, it appears that the lowest speed
setting had an error in its autorefresh counter value.  I don't know if
anything out there still uses this low-speed setting - my recollection is
that it was added for some early Labrador boards that had speed restrictions -
any comments from TI on whether these 133.3MHz/66.6MHz rates should be dropped
is most welcome.

These patches will be queued up into the omap-clock-testing branch at the
next possible opportunity.


- Paul

---

size:
  text    data     bss     dec     hex filename
3667957  196224  113216 3977397  3cb0b5 vmlinux.3430sdp.orig
3667957  196256  113216 3977429  3cb0d5 vmlinux.3430sdp


Paul Walmsley (2):
      OMAP3 SDRC: Add rounded rates for devices using the Qimonda SDRAM
      OMAP3 SDRC: Fix autorefresh counter for Qimonda SDRAM 66.6MHz rate


 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |   28 +++++++++++++++-----
 1 files changed, 21 insertions(+), 7 deletions(-)

[PATCH 1/2] OMAP3 SDRC: Fix autorefresh counter for Qimonda SDRAM 66.6MHz rate

[Paul Walmsley]

The autorefresh counter value for the 66.6MHz rate for the Qimonda SDRAM
part is wrong; fix it.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
index 74a92c8..304336b 100644
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -1,8 +1,8 @@
 /*
  * SDRC register values for the Qimonda HYB18M512160AF-6
  *
- * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Nokia Corporation
  *
  * Paul Walmsley
  *
@@ -44,7 +44,7 @@ static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
 		.rate	     = 66666666,
 		.actim_ctrla = 0x290d2243,
 		.actim_ctrlb = 0x00012208,
-		.rfr_ctrl    = 0x0001d601,
+		.rfr_ctrl    = 0x0001d501,
 		.mr	     = 0x00000022,
 	},
 	[4] = {

[PATCH 2/2] OMAP3 SDRC: Add rounded rates for devices using the Qimonda SDRAM

[Paul Walmsley]

The 3430SDPs, many of which use Qimonda SDRAM, are finally using
bootloaders that program rounded rates for DPLL3.  Since no SDRAM
memory timings are defined for the rounded rates, the initial SDRC
reprogram during init fails.  Add in the correct timings here.

Problem reported by Kevin Hilman <khilman@deeprootsystems.com>.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |   22 ++++++++++++++++----
 1 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
index 304336b..b190b45 100644
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -20,34 +20,48 @@
 /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
 static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
 	[0] = {
-		.rate	     = 165941176,
+		.rate	     = 166000000,
 		.actim_ctrla = 0x629db4c6,
 		.actim_ctrlb = 0x00012214,
 		.rfr_ctrl    = 0x0004dc01,
 		.mr	     = 0x00000032,
 	},
 	[1] = {
+		.rate	     = 165941176,
+		.actim_ctrla = 0x629db4c6,
+		.actim_ctrlb = 0x00012214,
+		.rfr_ctrl    = 0x0004dc01,
+		.mr	     = 0x00000032,
+	},
+	[2] = {
 		.rate	     = 133333333,
 		.actim_ctrla = 0x5219b485,
 		.actim_ctrlb = 0x00012210,
 		.rfr_ctrl    = 0x0003de01,
 		.mr	     = 0x00000032,
 	},
-	[2] = {
+	[3] = {
+		.rate	     = 83000000,
+		.actim_ctrla = 0x31512283,
+		.actim_ctrlb = 0x0001220a,
+		.rfr_ctrl    = 0x00025501,
+		.mr	     = 0x00000022,
+	},
+	[4] = {
 		.rate	     = 82970588,
 		.actim_ctrla = 0x31512283,
 		.actim_ctrlb = 0x0001220a,
 		.rfr_ctrl    = 0x00025501,
 		.mr	     = 0x00000022,
 	},
-	[3] = {
+	[5] = {
 		.rate	     = 66666666,
 		.actim_ctrla = 0x290d2243,
 		.actim_ctrlb = 0x00012208,
 		.rfr_ctrl    = 0x0001d501,
 		.mr	     = 0x00000022,
 	},
-	[4] = {
+	[6] = {
 		.rate	     = 0
 	},
 };

RE: [PATCH 0/2] PM: OMAP3 SDRC: fix some SDRAM settings for Qimonda parts

[Woodruff, Richard]

> Also when reviewing the timing calculations, it appears that the lowest speed
> setting had an error in its autorefresh counter value.  I don't know if
> anything out there still uses this low-speed setting - my recollection is
> that it was added for some early Labrador boards that had speed restrictions -
> any comments from TI on whether these 133.3MHz/66.6MHz rates should be dropped
> is most welcome.

Alpha LDP board had only 133MHz rated memory on them.  These were quickly replaced with beta then production boards with 166MHz rated memory.

Probably only a few dumpsters at TI have 133MHz restricted alpha boards (and maybe at logicpd).  I don’t' think you will even find an alpha in plastics.

Nothing stops a person from running at 133 on the 166 rated parts.  But most won't choose to on a 3430.

Regards,
Richard W.

RE: [PATCH 0/2] PM: OMAP3 SDRC: fix some SDRAM settings for Qimonda parts

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 975 bytes --]

On Thu, 14 May 2009, Woodruff, Richard wrote:

> > Also when reviewing the timing calculations, it appears that the lowest speed
> > setting had an error in its autorefresh counter value.  I don't know if
> > anything out there still uses this low-speed setting - my recollection is
> > that it was added for some early Labrador boards that had speed restrictions -
> > any comments from TI on whether these 133.3MHz/66.6MHz rates should be dropped
> > is most welcome.
> 
> Alpha LDP board had only 133MHz rated memory on them.  These were quickly replaced with beta then production boards with 166MHz rated memory.
> 
> Probably only a few dumpsters at TI have 133MHz restricted alpha boards (and maybe at logicpd).  I don’t' think you will even find an alpha in plastics.
> 
> Nothing stops a person from running at 133 on the 166 rated parts.  But most won't choose to on a 3430.

Great, thanks Richard.  Will add a patch to drop those rates...

- Paul