* [PATCH] ehci: fix ehci pin mux init
@ 2009-07-03 10:39 Ajay Kumar Gupta
2009-07-03 10:47 ` Felipe Balbi
0 siblings, 1 reply; 3+ messages in thread
From: Ajay Kumar Gupta @ 2009-07-03 10:39 UTC (permalink / raw)
To: linux-omap; +Cc: tony, felipe.balbi, Ajay Kumar Gupta
EHCI pin mux init fucntion is still using old #ifdef
which are not defined anymore.This causes pin mux init to
always set TLL settings and thus EHCI PHY mode doesn't work.
Fixing this issue by using phy_mode parameter to initialize
mux settings.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
---
arch/arm/mach-omap2/usb-ehci.c | 167 ++++++++++++++++++++--------------------
1 files changed, 83 insertions(+), 84 deletions(-)
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
index 0fe26f2..53e6e85 100644
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ b/arch/arm/mach-omap2/usb-ehci.c
@@ -68,90 +68,89 @@ static struct platform_device ehci_device = {
/*
* setup_ehci_io_mux - initialize IO pad mux for USBHOST
*/
-static void setup_ehci_io_mux(void)
+static void setup_ehci_io_mux(enum ehci_hcd_omap_mode phy_mode)
{
-#ifdef CONFIG_OMAP_EHCI_PHY_MODE
- /* PHY mode of operation for board: 750-2083-001
- * ISP1504 connected to Port1 and Port2
- * Do Func Mux setting for 12-pin ULPI PHY mode
- */
-
- /* Port1 */
- omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
- omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
- omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
- omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
- omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
- omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
- omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
- omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
- omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
- omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
- omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
- omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
-
- /* Port2 */
- omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
- omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
- omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
- omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
- omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
- omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
- omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
- omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
- omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
- omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
- omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
- omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
-
-#else
- /* Set Func mux for :
- * TLL mode of operation
- * 12-pin ULPI SDR TLL mode for Port1/2/3
- */
-
- /* Port1 */
- omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
- omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
- omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
- omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
- omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
- omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
- omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
- omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
- omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
- omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
- omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
- omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
-
- /* Port2 */
- omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
- omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
- omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
- omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
- omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
- omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
- omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
- omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
- omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
- omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
- omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
- omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
-
- /* Port3 */
- omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
- omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
- omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
- omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
- omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
- omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
- omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
- omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
- omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
- omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
- omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
- omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
-#endif /* CONFIG_OMAP_EHCI_PHY_MODE */
+ if (phy_mode == EHCI_HCD_OMAP_MODE_PHY) {
+ /* PHY mode of operation for board: 750-2083-001
+ * ISP1504 connected to Port1 and Port2
+ * Do Func Mux setting for 12-pin ULPI PHY mode
+ */
+ /* Port1 */
+ omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
+ omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
+ omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
+ omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
+ omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
+ omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
+ omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
+ omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
+ omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
+ omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
+ omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
+ omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
+
+ /* Port2 */
+ omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
+ omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
+ omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
+ omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
+ omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
+ omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
+ omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
+ omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
+ omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
+ omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
+ omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
+ omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
+
+ } else {
+ /* Set Func mux for :
+ * TLL mode of operation
+ * 12-pin ULPI SDR TLL mode for Port1/2/3
+ */
+
+ /* Port1 */
+ omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
+ omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
+ omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
+ omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
+ omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
+ omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
+ omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
+ omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
+ omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
+ omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
+ omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
+ omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
+
+ /* Port2 */
+ omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
+ omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
+ omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
+ omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
+ omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
+ omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
+ omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
+ omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
+ omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
+ omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
+ omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
+ omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
+
+ /* Port3 */
+ omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
+ omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
+ omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
+ omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
+ omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
+ omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
+ omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
+ omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
+ omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
+ omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
+ omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
+ omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
+ }
return;
}
@@ -172,7 +171,7 @@ void __init usb_ehci_init(enum ehci_hcd_omap_mode phy_mode,
/* Setup Pin IO MUX for EHCI */
if (cpu_is_omap34xx())
- setup_ehci_io_mux();
+ setup_ehci_io_mux(phy_mode);
if (platform_device_register(&ehci_device) < 0) {
printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
--
1.6.2.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] ehci: fix ehci pin mux init
2009-07-03 10:39 [PATCH] ehci: fix ehci pin mux init Ajay Kumar Gupta
@ 2009-07-03 10:47 ` Felipe Balbi
2009-09-22 0:47 ` Tony Lindgren
0 siblings, 1 reply; 3+ messages in thread
From: Felipe Balbi @ 2009-07-03 10:47 UTC (permalink / raw)
To: ext Ajay Kumar Gupta
Cc: linux-omap@vger.kernel.org, tony@atomide.com,
Balbi Felipe (Nokia-D/Helsinki)
On Fri, Jul 03, 2009 at 12:39:21PM +0200, ext Ajay Kumar Gupta wrote:
> EHCI pin mux init fucntion is still using old #ifdef
> which are not defined anymore.This causes pin mux init to
> always set TLL settings and thus EHCI PHY mode doesn't work.
>
> Fixing this issue by using phy_mode parameter to initialize
> mux settings.
>
> Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Acked-by: Felipe Balbi <felipe.balbi@nokia.com>
--
balbi
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] ehci: fix ehci pin mux init
2009-07-03 10:47 ` Felipe Balbi
@ 2009-09-22 0:47 ` Tony Lindgren
0 siblings, 0 replies; 3+ messages in thread
From: Tony Lindgren @ 2009-09-22 0:47 UTC (permalink / raw)
To: Felipe Balbi; +Cc: ext Ajay Kumar Gupta, linux-omap@vger.kernel.org
* Felipe Balbi <felipe.balbi@nokia.com> [090703 03:47]:
> On Fri, Jul 03, 2009 at 12:39:21PM +0200, ext Ajay Kumar Gupta wrote:
> > EHCI pin mux init fucntion is still using old #ifdef
> > which are not defined anymore.This causes pin mux init to
> > always set TLL settings and thus EHCI PHY mode doesn't work.
> >
> > Fixing this issue by using phy_mode parameter to initialize
> > mux settings.
> >
> > Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
>
> Acked-by: Felipe Balbi <felipe.balbi@nokia.com>
Adding this to ehci branch.
Tony
^ permalink raw reply [flat|nested] 3+ messages in thread
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2009-07-03 10:47 ` Felipe Balbi
2009-09-22 0:47 ` Tony Lindgren
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