[PATCH] save and restore etm state across core OFF modes

[PATCH] save and restore etm state across core OFF modes

[Alexander Shishkin]

This prevents ETM stalls whenever core enters OFF mode. Original patch
author is Richard Woodruff <r-woodruff2@ti.com>.

This patch applies on top of pm branch.

Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
CC: Richard Woodruff <r-woodruff2@ti.com>
---
 arch/arm/mach-omap2/Kconfig               |    9 ++
 arch/arm/mach-omap2/control.c             |    2 +-
 arch/arm/mach-omap2/sleep34xx.S           |  133 +++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/control.h |    2 +-
 4 files changed, 144 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 606bf04..02ea136 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -153,6 +153,15 @@ config MACH_OMAP_4430SDP
 	bool "OMAP 4430 SDP board"
 	depends on ARCH_OMAP4
 
+config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	bool "Enable hardware emulation context save and restore"
+	depends on ARCH_OMAP3
+	default y
+	help
+	  This option enables JTAG & ETM debugging across power states.
+	  With out this option emulation features are reset across OFF
+	  mode state changes.
+
 config OMAP3_EMU
 	bool "OMAP3 debugging peripherals"
 	depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index cdd1f35..78f4634 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
  * The address is stored in scratchpad, so that it can be used
  * during the restore path.
  */
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
 
 struct omap3_control_regs {
 	u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 69521be..0a5ec86 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -59,6 +59,13 @@
 #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
+#define CORTEX_CORSIGHT_OFF     (0x00011000)
+#define CORTEX_EMU_DEBUG_V      (L4_EMU_34XX_VIRT + CORTEX_CORSIGHT_OFF)
+#define CORTEX_EMU_DEBUG_P      (L4_EMU_34XX_PHYS + CORTEX_CORSIGHT_OFF)
+#define ETM_CORSIGHT_OFF        (0x00010000)
+#define CORTEX_EMU_ETM_V        (L4_EMU_34XX_VIRT + ETM_CORSIGHT_OFF)
+#define CORTEX_EMU_ETM_P        (L4_EMU_34XX_PHYS + ETM_CORSIGHT_OFF)
+
         .text
 /* Function to aquire the semaphore in scratchpad */
 ENTRY(lock_scratchpad_sem)
@@ -226,6 +233,18 @@ loop:
 	nop
 	bl wait_sdrc_ok
 
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	/*
+	 * Restore Coresight debug registers
+	 */
+	ldr     r6, debug_vbase      /* base Vaddr of CortexA8-Debug */
+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
+	bl      unlock_debug         /* remove global lock if set */
+	ldr     r6, etm_vbase        /* base Vaddr of ETM */
+	bl      unlock_debug         /* remove global lock if set */
+	str     r6, [r6, #0x300]     /* clear OSLAR lock using non-key */
+#endif
+
 	ldmfd	sp!, {r0-r12, pc}		@ restore regs and return
 restore_es3:
 	/*b restore_es3*/		@ Enable to debug restore code
@@ -385,6 +404,50 @@ logic_l1_restore:
 	/*normal memory remap register */
 	MCR p15, 0, r5, c10, c2, 1
 
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	/*
+	 * Restore Coresight debug registers
+	 */
+	ldr     r6, debug_pbase      /* base paddr of CortexA8-Debug */
+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
+	bl      unlock_debug         /* remove global lock if set */
+	str     r4, [r6, #0x300]     /* reset-pointer (already locked) */
+	ldr     r4, [r6, #0x308]     /* dummy read */
+	ldr     r4, [r3], #4         /* load save size */
+	cmp     r4, #0               /* check for zero */
+debug_restore:
+	ittt    ne                   /* t2/compat if-then block */
+	ldrne   r5, [r3], #4         /* get save value */
+	strne   r5, [r6,#0x308]      /* restore cp14 value */
+	subnes  r4, r4, #1           /* decrement loop */
+	bne     debug_restore        /* loop till done */
+	str     r5, [r6, #0x300]     /* clear lock */
+	/*
+	 * Restore CoreSight ETM registers
+	 */
+	ldr     r6, etm_pbase        /* base paddr of ETM */
+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
+	bl      unlock_debug         /* remove global lock if set */
+	ldr     r4, [r3], #4         /* load save size */
+	cmp     r4, #0               /* check for zero */
+	beq     etm_skip
+	sub     r4, #1
+	ldr     r7, [r3], #4         /* get/store first value to r7 */
+	mov     r5, #0x3             /* enable programming in ETMCR*/
+	lsl     r5, r5, #10
+	orr     r5, r7
+	str     r5,[r6], #4
+	cmp     r4, #0               /* check for zero */
+etm_restore:
+	ldrne   r5, [r3], #4         /* get save value */
+	strne   r5, [r6], #4         /* restore cp14 value */
+	subnes  r4, r4, #1           /* decrement loop */
+	bne     etm_restore          /* loop till done */
+	ldr     r6, etm_pbase        /* base paddr of ETM */
+	str     r7,[r6]              /* dis-able programming in ETMCR */
+etm_skip:
+#endif
+
 	/* Restore cpsr */
 	ldmia	r3!,{r4}	/*load CPSR from SDRAM*/
 	msr	cpsr, r4	/*store cpsr */
@@ -506,6 +569,39 @@ l1_logic_lost:
 	mrc	p15, 0, r5, c10, c2, 1
 	stmia	r8!,{r4-r5}
 
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	/*
+	 * Save Coresight debug registers
+	 */
+	ldr     r6, debug_vbase      /* base vaddr of CortexA8-Debug */
+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
+	bl      unlock_debug         /* force global unlock */
+	str     r4, [r6, #0x300]     /* lock debug access */
+	ldr     r4, [r6, #0x308]     /* OSSRR returns size on first read */
+	str     r4, [r8], #4         /* push item to save area */
+	cmp     r4, #0               /* zero check */
+debug_save:
+	ittt    ne                   /* thumb 2 compat if-then block */
+	ldrne   r5, [r6, #0x308]     /* get reg value */
+	strne   r5, [r8], #4         /* push item to save area */
+	subnes  r4, r4, #1           /* decrement size */
+	bne     debug_save           /* loop till done */
+	/*
+	 * Save etm registers
+	 */
+	ldr     r6, etm_vbase        /* base vaddr of CortexA8-Debug */
+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
+	bl      unlock_debug         /* force global unlock */
+	mov     r4, #128             /* OSSRR returns size on first read */
+	str     r4, [r8], #4         /* push item to save area */
+	cmp     r4, #0               /* zero check */
+etm_save:
+	ldrne   r5, [r6], #4         /* get reg value */
+	strne   r5, [r8], #4         /* push item to save area */
+	subnes  r4, r4, #1           /* decrement size */
+	bne     etm_save             /* loop till done */
+#endif
+
 	/* Store current cpsr*/
 	mrs	r2, cpsr
 	stmia	r8!, {r2}
@@ -520,6 +616,7 @@ clean_caches:
 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
 	bne	skip_l2_inval
 clean_l2:
+#if 0
 	/* read clidr */
 	mrc     p15, 1, r0, c0, c0, 1
 	/* extract loc from clidr */
@@ -586,6 +683,12 @@ finished:
 	/* select current cache level in cssr */
 	mcr     p15, 2, r10, c0, c0, 0
 	isb
+#else
+	ldr r1, kernel_flush     /* get 32 bit addr of flush */
+	mov lr, pc               /* prepare for return */
+	bx  r1                   /* do it */
+#endif
+
 skip_l2_inval:
 	/* Data memory barrier and Data sync barrier */
 	mov     r1, #0
@@ -632,6 +735,36 @@ wait_dll_lock:
         bne     wait_dll_lock
         bx      lr
 
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	/*
+	 * unlock debug:
+	 *  Input:
+	 *      r6 has base address of emulation
+	 *      r4 has unlock key
+	 *  Output
+	 *      r5 has PDS value (1=accessable)
+	 */
+unlock_debug:
+	ldr     r5, [r6, #0xfb4]     /* get LSR */
+	cmp     r5, #0x3             /* need unlocking? */
+	streq   r4, [r6, #0xfb0]     /* unlock if so */
+	ldr     r5, [r6, #0x314]     /* clear power status */
+	bx      lr                   /* back to caller */
+
+debug_vbase:
+	.word CORTEX_EMU_DEBUG_V
+debug_pbase:
+	.word CORTEX_EMU_DEBUG_P
+etm_vbase:
+	.word CORTEX_EMU_ETM_V
+etm_pbase:
+	.word CORTEX_EMU_ETM_P
+debug_xlar_key:
+	.word 0xC5ACCE55
+#endif
+
+kernel_flush:
+	.word v7_flush_dcache_all
 cm_idlest1_core:
 	.word	CM_IDLEST1_CORE_V
 sdrc_dlla_status:
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 69428ff..22c492c 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -324,7 +324,7 @@ extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
 extern u32 *get_restore_pointer(void);
 extern u32 *get_es3_restore_pointer(void);
-extern u32 omap3_arm_context[128];
+extern u32 omap3_arm_context[256];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);
 
-- 
1.6.3.3

Re: [PATCH] save and restore etm state across core OFF modes

[Nishanth Menon]

Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
> This prevents ETM stalls whenever core enters OFF mode. Original patch
> author is Richard Woodruff <r-woodruff2@ti.com>.
> 
> This patch applies on top of pm branch.
> 
> Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
> CC: Richard Woodruff <r-woodruff2@ti.com>

thanks..

> ---
>  arch/arm/mach-omap2/Kconfig               |    9 ++
>  arch/arm/mach-omap2/control.c             |    2 +-
>  arch/arm/mach-omap2/sleep34xx.S           |  133 +++++++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/control.h |    2 +-
>  4 files changed, 144 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 606bf04..02ea136 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -153,6 +153,15 @@ config MACH_OMAP_4430SDP
>  	bool "OMAP 4430 SDP board"
>  	depends on ARCH_OMAP4
>  
> +config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	bool "Enable hardware emulation context save and restore"
> +	depends on ARCH_OMAP3
> +	default y
> +	help
> +	  This option enables JTAG & ETM debugging across power states.
> +	  With out this option emulation features are reset across OFF
> +	  mode state changes.
> +
>  config OMAP3_EMU
>  	bool "OMAP3 debugging peripherals"
>  	depends on ARCH_OMAP3
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index cdd1f35..78f4634 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
>   * The address is stored in scratchpad, so that it can be used
>   * during the restore path.
>   */
> -u32 omap3_arm_context[128];
> +u32 omap3_arm_context[256];
>  
>  struct omap3_control_regs {
>  	u32 sysconfig;
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 69521be..0a5ec86 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -59,6 +59,13 @@
>  #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
>  
> +#define CORTEX_CORSIGHT_OFF     (0x00011000)
> +#define CORTEX_EMU_DEBUG_V      (L4_EMU_34XX_VIRT + CORTEX_CORSIGHT_OFF)
> +#define CORTEX_EMU_DEBUG_P      (L4_EMU_34XX_PHYS + CORTEX_CORSIGHT_OFF)
> +#define ETM_CORSIGHT_OFF        (0x00010000)
> +#define CORTEX_EMU_ETM_V        (L4_EMU_34XX_VIRT + ETM_CORSIGHT_OFF)
> +#define CORTEX_EMU_ETM_P        (L4_EMU_34XX_PHYS + ETM_CORSIGHT_OFF)
> +
>          .text
>  /* Function to aquire the semaphore in scratchpad */
>  ENTRY(lock_scratchpad_sem)
> @@ -226,6 +233,18 @@ loop:
>  	nop
>  	bl wait_sdrc_ok
>  
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	/*
> +	 * Restore Coresight debug registers
> +	 */
> +	ldr     r6, debug_vbase      /* base Vaddr of CortexA8-Debug */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* remove global lock if set */
> +	ldr     r6, etm_vbase        /* base Vaddr of ETM */
> +	bl      unlock_debug         /* remove global lock if set */
> +	str     r6, [r6, #0x300]     /* clear OSLAR lock using non-key */
> +#endif
> +
>  	ldmfd	sp!, {r0-r12, pc}		@ restore regs and return
>  restore_es3:
>  	/*b restore_es3*/		@ Enable to debug restore code
> @@ -385,6 +404,50 @@ logic_l1_restore:
>  	/*normal memory remap register */
>  	MCR p15, 0, r5, c10, c2, 1
>  
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	/*
> +	 * Restore Coresight debug registers
> +	 */
> +	ldr     r6, debug_pbase      /* base paddr of CortexA8-Debug */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* remove global lock if set */
> +	str     r4, [r6, #0x300]     /* reset-pointer (already locked) */
> +	ldr     r4, [r6, #0x308]     /* dummy read */
> +	ldr     r4, [r3], #4         /* load save size */
> +	cmp     r4, #0               /* check for zero */
> +debug_restore:
> +	ittt    ne                   /* t2/compat if-then block */
> +	ldrne   r5, [r3], #4         /* get save value */
> +	strne   r5, [r6,#0x308]      /* restore cp14 value */
> +	subnes  r4, r4, #1           /* decrement loop */
> +	bne     debug_restore        /* loop till done */
> +	str     r5, [r6, #0x300]     /* clear lock */
> +	/*
> +	 * Restore CoreSight ETM registers
> +	 */
> +	ldr     r6, etm_pbase        /* base paddr of ETM */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* remove global lock if set */
> +	ldr     r4, [r3], #4         /* load save size */
> +	cmp     r4, #0               /* check for zero */
> +	beq     etm_skip
> +	sub     r4, #1
> +	ldr     r7, [r3], #4         /* get/store first value to r7 */
> +	mov     r5, #0x3             /* enable programming in ETMCR*/
> +	lsl     r5, r5, #10
> +	orr     r5, r7
> +	str     r5,[r6], #4
> +	cmp     r4, #0               /* check for zero */
> +etm_restore:
> +	ldrne   r5, [r3], #4         /* get save value */
> +	strne   r5, [r6], #4         /* restore cp14 value */
> +	subnes  r4, r4, #1           /* decrement loop */
> +	bne     etm_restore          /* loop till done */
> +	ldr     r6, etm_pbase        /* base paddr of ETM */
> +	str     r7,[r6]              /* dis-able programming in ETMCR */
> +etm_skip:
> +#endif
> +
>  	/* Restore cpsr */
>  	ldmia	r3!,{r4}	/*load CPSR from SDRAM*/
>  	msr	cpsr, r4	/*store cpsr */
> @@ -506,6 +569,39 @@ l1_logic_lost:
>  	mrc	p15, 0, r5, c10, c2, 1
>  	stmia	r8!,{r4-r5}
>  
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	/*
> +	 * Save Coresight debug registers
> +	 */
> +	ldr     r6, debug_vbase      /* base vaddr of CortexA8-Debug */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* force global unlock */
> +	str     r4, [r6, #0x300]     /* lock debug access */
> +	ldr     r4, [r6, #0x308]     /* OSSRR returns size on first read */
> +	str     r4, [r8], #4         /* push item to save area */
> +	cmp     r4, #0               /* zero check */
> +debug_save:
> +	ittt    ne                   /* thumb 2 compat if-then block */
> +	ldrne   r5, [r6, #0x308]     /* get reg value */
> +	strne   r5, [r8], #4         /* push item to save area */
> +	subnes  r4, r4, #1           /* decrement size */
> +	bne     debug_save           /* loop till done */
> +	/*
> +	 * Save etm registers
> +	 */
> +	ldr     r6, etm_vbase        /* base vaddr of CortexA8-Debug */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* force global unlock */
> +	mov     r4, #128             /* OSSRR returns size on first read */
> +	str     r4, [r8], #4         /* push item to save area */
> +	cmp     r4, #0               /* zero check */
> +etm_save:
> +	ldrne   r5, [r6], #4         /* get reg value */
> +	strne   r5, [r8], #4         /* push item to save area */
> +	subnes  r4, r4, #1           /* decrement size */
> +	bne     etm_save             /* loop till done */
> +#endif
> +
>  	/* Store current cpsr*/
>  	mrs	r2, cpsr
>  	stmia	r8!, {r2}
> @@ -520,6 +616,7 @@ clean_caches:
>  	cmp	r9, #1 /* Check whether L2 inval is required or not*/
>  	bne	skip_l2_inval
>  clean_l2:
> +#if 0

my aversion to #if 0 kicks in here :(.. do we have an alternative like 
using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something else?

>  	/* read clidr */
>  	mrc     p15, 1, r0, c0, c0, 1
>  	/* extract loc from clidr */
> @@ -586,6 +683,12 @@ finished:
>  	/* select current cache level in cssr */
>  	mcr     p15, 2, r10, c0, c0, 0
>  	isb
> +#else
> +	ldr r1, kernel_flush     /* get 32 bit addr of flush */
> +	mov lr, pc               /* prepare for return */
> +	bx  r1                   /* do it */
> +#endif
> +
>  skip_l2_inval:
>  	/* Data memory barrier and Data sync barrier */
>  	mov     r1, #0
> @@ -632,6 +735,36 @@ wait_dll_lock:
>          bne     wait_dll_lock
>          bx      lr
>  
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	/*
> +	 * unlock debug:
> +	 *  Input:
> +	 *      r6 has base address of emulation
> +	 *      r4 has unlock key
> +	 *  Output
> +	 *      r5 has PDS value (1=accessable)
> +	 */
> +unlock_debug:
> +	ldr     r5, [r6, #0xfb4]     /* get LSR */
> +	cmp     r5, #0x3             /* need unlocking? */
> +	streq   r4, [r6, #0xfb0]     /* unlock if so */
> +	ldr     r5, [r6, #0x314]     /* clear power status */
> +	bx      lr                   /* back to caller */
> +
> +debug_vbase:
> +	.word CORTEX_EMU_DEBUG_V
> +debug_pbase:
> +	.word CORTEX_EMU_DEBUG_P
> +etm_vbase:
> +	.word CORTEX_EMU_ETM_V
> +etm_pbase:
> +	.word CORTEX_EMU_ETM_P
> +debug_xlar_key:
> +	.word 0xC5ACCE55
> +#endif
> +
> +kernel_flush:
> +	.word v7_flush_dcache_all
>  cm_idlest1_core:
>  	.word	CM_IDLEST1_CORE_V
>  sdrc_dlla_status:
> diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
> index 69428ff..22c492c 100644
> --- a/arch/arm/plat-omap/include/plat/control.h
> +++ b/arch/arm/plat-omap/include/plat/control.h
> @@ -324,7 +324,7 @@ extern void omap3_save_scratchpad_contents(void);
>  extern void omap3_clear_scratchpad_contents(void);
>  extern u32 *get_restore_pointer(void);
>  extern u32 *get_es3_restore_pointer(void);
> -extern u32 omap3_arm_context[128];
> +extern u32 omap3_arm_context[256];
>  extern void omap3_control_save_context(void);
>  extern void omap3_control_restore_context(void);
>  


-- 
Regards,
Nishanth Menon

Re: [PATCH] save and restore etm state across core OFF modes

[Alexander Shishkin]

On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
> Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
> >This prevents ETM stalls whenever core enters OFF mode. Original patch
> >author is Richard Woodruff <r-woodruff2@ti.com>.
> >
> >This patch applies on top of pm branch.
> >
> >Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
> >CC: Richard Woodruff <r-woodruff2@ti.com>
> 
> thanks..
> 
> >---
> > arch/arm/mach-omap2/Kconfig               |    9 ++
> > arch/arm/mach-omap2/control.c             |    2 +-
> > arch/arm/mach-omap2/sleep34xx.S           |  133 +++++++++++++++++++++++++++++
> > arch/arm/plat-omap/include/plat/control.h |    2 +-
> > 4 files changed, 144 insertions(+), 2 deletions(-)
> >
> >diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> >index 606bf04..02ea136 100644
> >--- a/arch/arm/mach-omap2/Kconfig
> >+++ b/arch/arm/mach-omap2/Kconfig
> >@@ -153,6 +153,15 @@ config MACH_OMAP_4430SDP
> > 	bool "OMAP 4430 SDP board"
> > 	depends on ARCH_OMAP4
> >+config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> >+	bool "Enable hardware emulation context save and restore"
> >+	depends on ARCH_OMAP3
> >+	default y
> >+	help
> >+	  This option enables JTAG & ETM debugging across power states.
> >+	  With out this option emulation features are reset across OFF
> >+	  mode state changes.
> >+
> > config OMAP3_EMU
> > 	bool "OMAP3 debugging peripherals"
> > 	depends on ARCH_OMAP3
> >diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> >index cdd1f35..78f4634 100644
> >--- a/arch/arm/mach-omap2/control.c
> >+++ b/arch/arm/mach-omap2/control.c
> >@@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
> >  * The address is stored in scratchpad, so that it can be used
> >  * during the restore path.
> >  */
> >-u32 omap3_arm_context[128];
> >+u32 omap3_arm_context[256];
> > struct omap3_control_regs {
> > 	u32 sysconfig;
> >diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> >index 69521be..0a5ec86 100644
> >--- a/arch/arm/mach-omap2/sleep34xx.S
> >+++ b/arch/arm/mach-omap2/sleep34xx.S
> >@@ -59,6 +59,13 @@
> > #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
> > #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
> >+#define CORTEX_CORSIGHT_OFF     (0x00011000)
> >+#define CORTEX_EMU_DEBUG_V      (L4_EMU_34XX_VIRT + CORTEX_CORSIGHT_OFF)
> >+#define CORTEX_EMU_DEBUG_P      (L4_EMU_34XX_PHYS + CORTEX_CORSIGHT_OFF)
> >+#define ETM_CORSIGHT_OFF        (0x00010000)
> >+#define CORTEX_EMU_ETM_V        (L4_EMU_34XX_VIRT + ETM_CORSIGHT_OFF)
> >+#define CORTEX_EMU_ETM_P        (L4_EMU_34XX_PHYS + ETM_CORSIGHT_OFF)
> >+
> >         .text
> > /* Function to aquire the semaphore in scratchpad */
> > ENTRY(lock_scratchpad_sem)
> >@@ -226,6 +233,18 @@ loop:
> > 	nop
> > 	bl wait_sdrc_ok
> >+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> >+	/*
> >+	 * Restore Coresight debug registers
> >+	 */
> >+	ldr     r6, debug_vbase      /* base Vaddr of CortexA8-Debug */
> >+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> >+	bl      unlock_debug         /* remove global lock if set */
> >+	ldr     r6, etm_vbase        /* base Vaddr of ETM */
> >+	bl      unlock_debug         /* remove global lock if set */
> >+	str     r6, [r6, #0x300]     /* clear OSLAR lock using non-key */
> >+#endif
> >+
> > 	ldmfd	sp!, {r0-r12, pc}		@ restore regs and return
> > restore_es3:
> > 	/*b restore_es3*/		@ Enable to debug restore code
> >@@ -385,6 +404,50 @@ logic_l1_restore:
> > 	/*normal memory remap register */
> > 	MCR p15, 0, r5, c10, c2, 1
> >+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> >+	/*
> >+	 * Restore Coresight debug registers
> >+	 */
> >+	ldr     r6, debug_pbase      /* base paddr of CortexA8-Debug */
> >+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> >+	bl      unlock_debug         /* remove global lock if set */
> >+	str     r4, [r6, #0x300]     /* reset-pointer (already locked) */
> >+	ldr     r4, [r6, #0x308]     /* dummy read */
> >+	ldr     r4, [r3], #4         /* load save size */
> >+	cmp     r4, #0               /* check for zero */
> >+debug_restore:
> >+	ittt    ne                   /* t2/compat if-then block */
> >+	ldrne   r5, [r3], #4         /* get save value */
> >+	strne   r5, [r6,#0x308]      /* restore cp14 value */
> >+	subnes  r4, r4, #1           /* decrement loop */
> >+	bne     debug_restore        /* loop till done */
> >+	str     r5, [r6, #0x300]     /* clear lock */
> >+	/*
> >+	 * Restore CoreSight ETM registers
> >+	 */
> >+	ldr     r6, etm_pbase        /* base paddr of ETM */
> >+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> >+	bl      unlock_debug         /* remove global lock if set */
> >+	ldr     r4, [r3], #4         /* load save size */
> >+	cmp     r4, #0               /* check for zero */
> >+	beq     etm_skip
> >+	sub     r4, #1
> >+	ldr     r7, [r3], #4         /* get/store first value to r7 */
> >+	mov     r5, #0x3             /* enable programming in ETMCR*/
> >+	lsl     r5, r5, #10
> >+	orr     r5, r7
> >+	str     r5,[r6], #4
> >+	cmp     r4, #0               /* check for zero */
> >+etm_restore:
> >+	ldrne   r5, [r3], #4         /* get save value */
> >+	strne   r5, [r6], #4         /* restore cp14 value */
> >+	subnes  r4, r4, #1           /* decrement loop */
> >+	bne     etm_restore          /* loop till done */
> >+	ldr     r6, etm_pbase        /* base paddr of ETM */
> >+	str     r7,[r6]              /* dis-able programming in ETMCR */
> >+etm_skip:
> >+#endif
> >+
> > 	/* Restore cpsr */
> > 	ldmia	r3!,{r4}	/*load CPSR from SDRAM*/
> > 	msr	cpsr, r4	/*store cpsr */
> >@@ -506,6 +569,39 @@ l1_logic_lost:
> > 	mrc	p15, 0, r5, c10, c2, 1
> > 	stmia	r8!,{r4-r5}
> >+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> >+	/*
> >+	 * Save Coresight debug registers
> >+	 */
> >+	ldr     r6, debug_vbase      /* base vaddr of CortexA8-Debug */
> >+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> >+	bl      unlock_debug         /* force global unlock */
> >+	str     r4, [r6, #0x300]     /* lock debug access */
> >+	ldr     r4, [r6, #0x308]     /* OSSRR returns size on first read */
> >+	str     r4, [r8], #4         /* push item to save area */
> >+	cmp     r4, #0               /* zero check */
> >+debug_save:
> >+	ittt    ne                   /* thumb 2 compat if-then block */
> >+	ldrne   r5, [r6, #0x308]     /* get reg value */
> >+	strne   r5, [r8], #4         /* push item to save area */
> >+	subnes  r4, r4, #1           /* decrement size */
> >+	bne     debug_save           /* loop till done */
> >+	/*
> >+	 * Save etm registers
> >+	 */
> >+	ldr     r6, etm_vbase        /* base vaddr of CortexA8-Debug */
> >+	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> >+	bl      unlock_debug         /* force global unlock */
> >+	mov     r4, #128             /* OSSRR returns size on first read */
> >+	str     r4, [r8], #4         /* push item to save area */
> >+	cmp     r4, #0               /* zero check */
> >+etm_save:
> >+	ldrne   r5, [r6], #4         /* get reg value */
> >+	strne   r5, [r8], #4         /* push item to save area */
> >+	subnes  r4, r4, #1           /* decrement size */
> >+	bne     etm_save             /* loop till done */
> >+#endif
> >+
> > 	/* Store current cpsr*/
> > 	mrs	r2, cpsr
> > 	stmia	r8!, {r2}
> >@@ -520,6 +616,7 @@ clean_caches:
> > 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
> > 	bne	skip_l2_inval
> > clean_l2:
> >+#if 0
> 
> my aversion to #if 0 kicks in here :(.. do we have an alternative
> like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
> else?

Fair enough. I could replace it with "#if !defined(...)" as the first
thing that comes to mind. This way it will only take disabling the
config option to catch any possible regressions in between. Does this
sound reasonable?

Regards,
--
Alex

Re: [PATCH] save and restore etm state across core OFF modes

[Nishanth Menon]

Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
> On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
>> Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:

>>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>>> index 69521be..0a5ec86 100644
>>> --- a/arch/arm/mach-omap2/sleep34xx.S
>>> +++ b/arch/arm/mach-omap2/sleep34xx.S
[...]
>>> 	/* Store current cpsr*/
>>> 	mrs	r2, cpsr
>>> 	stmia	r8!, {r2}
>>> @@ -520,6 +616,7 @@ clean_caches:
>>> 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
>>> 	bne	skip_l2_inval
>>> clean_l2:
>>> +#if 0
>> my aversion to #if 0 kicks in here :(.. do we have an alternative
>> like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
>> else?
> 
> Fair enough. I could replace it with "#if !defined(...)" as the first
> thing that comes to mind. This way it will only take disabling the
> config option to catch any possible regressions in between. Does this
> sound reasonable?
sounds ok to me.. unless folks have ideas coz of clean_l2 label.. more 
comments might be useful before a rev2 of the patch..

-- 
Regards,
Nishanth Menon

Re: [PATCH] save and restore etm state across core OFF modes

[Tony Lindgren]

* Nishanth Menon <nm@ti.com> [100112 09:31]:
> Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
> >On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
> >>Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
> 
> >>>diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> >>>index 69521be..0a5ec86 100644
> >>>--- a/arch/arm/mach-omap2/sleep34xx.S
> >>>+++ b/arch/arm/mach-omap2/sleep34xx.S
> [...]
> >>>	/* Store current cpsr*/
> >>>	mrs	r2, cpsr
> >>>	stmia	r8!, {r2}
> >>>@@ -520,6 +616,7 @@ clean_caches:
> >>>	cmp	r9, #1 /* Check whether L2 inval is required or not*/
> >>>	bne	skip_l2_inval
> >>>clean_l2:
> >>>+#if 0
> >>my aversion to #if 0 kicks in here :(.. do we have an alternative
> >>like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
> >>else?
> >
> >Fair enough. I could replace it with "#if !defined(...)" as the first
> >thing that comes to mind. This way it will only take disabling the
> >config option to catch any possible regressions in between. Does this
> >sound reasonable?
> sounds ok to me.. unless folks have ideas coz of clean_l2 label..
> more comments might be useful before a rev2 of the patch..

The best solution would be to be able to toggle this via sysfs or
debugfs by swapping the sram code for idle loop when JTAG support
is needed.

Regards,

Tony

Re: [PATCH] save and restore etm state across core OFF modes

[Alexander Shishkin]

On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
> * Nishanth Menon <nm@ti.com> [100112 09:31]:
> > Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
> > >On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
> > >>Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
> > 
> > >>>diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> > >>>index 69521be..0a5ec86 100644
> > >>>--- a/arch/arm/mach-omap2/sleep34xx.S
> > >>>+++ b/arch/arm/mach-omap2/sleep34xx.S
> > [...]
> > >>>	/* Store current cpsr*/
> > >>>	mrs	r2, cpsr
> > >>>	stmia	r8!, {r2}
> > >>>@@ -520,6 +616,7 @@ clean_caches:
> > >>>	cmp	r9, #1 /* Check whether L2 inval is required or not*/
> > >>>	bne	skip_l2_inval
> > >>>clean_l2:
> > >>>+#if 0
> > >>my aversion to #if 0 kicks in here :(.. do we have an alternative
> > >>like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
> > >>else?
> > >
> > >Fair enough. I could replace it with "#if !defined(...)" as the first
> > >thing that comes to mind. This way it will only take disabling the
> > >config option to catch any possible regressions in between. Does this
> > >sound reasonable?
> > sounds ok to me.. unless folks have ideas coz of clean_l2 label..
> > more comments might be useful before a rev2 of the patch..
> 
> The best solution would be to be able to toggle this via sysfs or
> debugfs by swapping the sram code for idle loop when JTAG support
> is needed.

Well, if you say, compile the ETM driver in, this will be needed most of
the time.

Regards,
--
Alex

Re: [PATCH] save and restore etm state across core OFF modes

[Nishanth Menon]

Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
> On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
>> * Nishanth Menon <nm@ti.com> [100112 09:31]:
>>> Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
>>>> On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
>>>>> Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
>>>>>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>>>>>> index 69521be..0a5ec86 100644
>>>>>> --- a/arch/arm/mach-omap2/sleep34xx.S
>>>>>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>>> [...]
>>>>>> 	/* Store current cpsr*/
>>>>>> 	mrs	r2, cpsr
>>>>>> 	stmia	r8!, {r2}
>>>>>> @@ -520,6 +616,7 @@ clean_caches:
>>>>>> 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
>>>>>> 	bne	skip_l2_inval
>>>>>> clean_l2:
>>>>>> +#if 0
>>>>> my aversion to #if 0 kicks in here :(.. do we have an alternative
>>>>> like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
>>>>> else?
>>>> Fair enough. I could replace it with "#if !defined(...)" as the first
>>>> thing that comes to mind. This way it will only take disabling the
>>>> config option to catch any possible regressions in between. Does this
>>>> sound reasonable?
>>> sounds ok to me.. unless folks have ideas coz of clean_l2 label..
>>> more comments might be useful before a rev2 of the patch..
>> The best solution would be to be able to toggle this via sysfs or
>> debugfs by swapping the sram code for idle loop when JTAG support
>> is needed.
> 
> Well, if you say, compile the ETM driver in, this will be needed most of
> the time.
> 
I can think of reasons for an against a sysfs entry (as part of 
discussion -warning lot of self contradictions below- but I think might 
save a bit of back and froth ;)):

for sysfs entry:
a) save and restore will have additional latency when you save a chunk 
such as EMU domain regs - this will not be needed in production phones, 
disabling it might pop up surprises
	counter: having a disabled defconfig allows relevant folks to
	enable on a need basis
		counter to counter: what do you do when a user reports
		an issue in a release and you'd want to debug it with 		
		ETM on his platform other than doing a rebuild?
b) mostly a debug support -> only for blokes using ETM/JTAG interfaces - 
not everyone can afford these (no offense to openOCD guys - but they are 
still a bit away from being able to debug kernel yet on OMAP)..
	counter and counter to counter - just like previous point
c) easy mechanism to enable/disable the path runtime
	counter: defconfig rebuild is not *that difficult*
		counter to counter: sysfs is easier and faster, saves
		developer time == money

for defconfig:
a) defconfig restricts un-informed users to not mess with something they 
should'nt use in the first place
	counter: -EINVAL
b) defconfig removes the entire code structure out - saving on space of 
save and restore memory + code path
	counter: sysfs option could be wrapped within a defconfig to do exactly 
the same.
c) what do you do if you need to use ETM during initial boottime (Vs 
echo 1>/sys/.../etm_saverestore
	counter: use save-restore sysfs entry enabled at init - a defconfig 
might be helpful


-- 
Regards,
Nishanth Menon

Re: [PATCH] save and restore etm state across core OFF modes

[Tony Lindgren]

* Nishanth Menon <nm@ti.com> [100112 14:06]:
> Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
> >On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
> >>* Nishanth Menon <nm@ti.com> [100112 09:31]:
> >>>Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
> >>>>On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
> >>>>>Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
> >>>>>>diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> >>>>>>index 69521be..0a5ec86 100644
> >>>>>>--- a/arch/arm/mach-omap2/sleep34xx.S
> >>>>>>+++ b/arch/arm/mach-omap2/sleep34xx.S
> >>>[...]
> >>>>>>	/* Store current cpsr*/
> >>>>>>	mrs	r2, cpsr
> >>>>>>	stmia	r8!, {r2}
> >>>>>>@@ -520,6 +616,7 @@ clean_caches:
> >>>>>>	cmp	r9, #1 /* Check whether L2 inval is required or not*/
> >>>>>>	bne	skip_l2_inval
> >>>>>>clean_l2:
> >>>>>>+#if 0
> >>>>>my aversion to #if 0 kicks in here :(.. do we have an alternative
> >>>>>like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
> >>>>>else?
> >>>>Fair enough. I could replace it with "#if !defined(...)" as the first
> >>>>thing that comes to mind. This way it will only take disabling the
> >>>>config option to catch any possible regressions in between. Does this
> >>>>sound reasonable?
> >>>sounds ok to me.. unless folks have ideas coz of clean_l2 label..
> >>>more comments might be useful before a rev2 of the patch..
> >>The best solution would be to be able to toggle this via sysfs or
> >>debugfs by swapping the sram code for idle loop when JTAG support
> >>is needed.
> >
> >Well, if you say, compile the ETM driver in, this will be needed most of
> >the time.
> >
> I can think of reasons for an against a sysfs entry (as part of
> discussion -warning lot of self contradictions below- but I think
> might save a bit of back and froth ;)):
> 
> for sysfs entry:
> a) save and restore will have additional latency when you save a
> chunk such as EMU domain regs - this will not be needed in
> production phones, disabling it might pop up surprises

There's no overhead if you're just replacing the function
loaded to SRAM as needed. But for sure it's a debug tool only.

Regards,

Tony

Re: [PATCH] save and restore etm state across core OFF modes

[Nishanth Menon]

Tony Lindgren had written, on 01/12/2010 04:15 PM, the following:
> * Nishanth Menon <nm@ti.com> [100112 14:06]:
>> Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
>>> On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
>>>> * Nishanth Menon <nm@ti.com> [100112 09:31]:
>>>>> Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
>>>>>> On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
>>>>>>> Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
>>>>>>>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>>>>>>>> index 69521be..0a5ec86 100644
>>>>>>>> --- a/arch/arm/mach-omap2/sleep34xx.S
>>>>>>>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>>>>> [...]
>>>>>>>> 	/* Store current cpsr*/
>>>>>>>> 	mrs	r2, cpsr
>>>>>>>> 	stmia	r8!, {r2}
>>>>>>>> @@ -520,6 +616,7 @@ clean_caches:
>>>>>>>> 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
>>>>>>>> 	bne	skip_l2_inval
>>>>>>>> clean_l2:
>>>>>>>> +#if 0
>>>>>>> my aversion to #if 0 kicks in here :(.. do we have an alternative
>>>>>>> like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
>>>>>>> else?
>>>>>> Fair enough. I could replace it with "#if !defined(...)" as the first
>>>>>> thing that comes to mind. This way it will only take disabling the
>>>>>> config option to catch any possible regressions in between. Does this
>>>>>> sound reasonable?
>>>>> sounds ok to me.. unless folks have ideas coz of clean_l2 label..
>>>>> more comments might be useful before a rev2 of the patch..
>>>> The best solution would be to be able to toggle this via sysfs or
>>>> debugfs by swapping the sram code for idle loop when JTAG support
>>>> is needed.
>>> Well, if you say, compile the ETM driver in, this will be needed most of
>>> the time.
>>>
>> I can think of reasons for an against a sysfs entry (as part of
>> discussion -warning lot of self contradictions below- but I think
>> might save a bit of back and froth ;)):
>>
>> for sysfs entry:
>> a) save and restore will have additional latency when you save a
>> chunk such as EMU domain regs - this will not be needed in
>> production phones, disabling it might pop up surprises
> 
> There's no overhead if you're just replacing the function
> loaded to SRAM as needed. But for sure it's a debug tool only.

I should probably have been more clear ->I agree function relocation to 
SRAM is not a major factor here, my concern was the additional latency 
incurred during scratchpad save and restore logic as seen by the patch:
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
the arm context has doubled albiet 128bytes only.. it still changes the 
latencies involved on the save and restore paths.. few interesting 
behavior seen with EHCI save and restore comes to mind here - but maybe 
irrelevant to the discussion..

-- 
Regards,
Nishanth Menon

Re: [PATCH] save and restore etm state across core OFF modes

[Alexander Shishkin]

On Tue, Jan 12, 2010 at 04:53:51 -0600, Nishanth Menon wrote:
> Tony Lindgren had written, on 01/12/2010 04:15 PM, the following:
> >* Nishanth Menon <nm@ti.com> [100112 14:06]:
> >>Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
> >>>On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
> >>>>* Nishanth Menon <nm@ti.com> [100112 09:31]:
> >>>>>Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
> >>>>>>On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
> >>>>>>>Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
> >>>>>>>>diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> >>>>>>>>index 69521be..0a5ec86 100644
> >>>>>>>>--- a/arch/arm/mach-omap2/sleep34xx.S
> >>>>>>>>+++ b/arch/arm/mach-omap2/sleep34xx.S
> >>>>>[...]
> >>>>>>>>	/* Store current cpsr*/
> >>>>>>>>	mrs	r2, cpsr
> >>>>>>>>	stmia	r8!, {r2}
> >>>>>>>>@@ -520,6 +616,7 @@ clean_caches:
> >>>>>>>>	cmp	r9, #1 /* Check whether L2 inval is required or not*/
> >>>>>>>>	bne	skip_l2_inval
> >>>>>>>>clean_l2:
> >>>>>>>>+#if 0
> >>>>>>>my aversion to #if 0 kicks in here :(.. do we have an alternative
> >>>>>>>like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
> >>>>>>>else?
> >>>>>>Fair enough. I could replace it with "#if !defined(...)" as the first
> >>>>>>thing that comes to mind. This way it will only take disabling the
> >>>>>>config option to catch any possible regressions in between. Does this
> >>>>>>sound reasonable?
> >>>>>sounds ok to me.. unless folks have ideas coz of clean_l2 label..
> >>>>>more comments might be useful before a rev2 of the patch..
> >>>>The best solution would be to be able to toggle this via sysfs or
> >>>>debugfs by swapping the sram code for idle loop when JTAG support
> >>>>is needed.
> >>>Well, if you say, compile the ETM driver in, this will be needed most of
> >>>the time.
> >>>
> >>I can think of reasons for an against a sysfs entry (as part of
> >>discussion -warning lot of self contradictions below- but I think
> >>might save a bit of back and froth ;)):
> >>
> >>for sysfs entry:
> >>a) save and restore will have additional latency when you save a
> >>chunk such as EMU domain regs - this will not be needed in
> >>production phones, disabling it might pop up surprises
> >
> >There's no overhead if you're just replacing the function
> >loaded to SRAM as needed. But for sure it's a debug tool only.
> 
> I should probably have been more clear ->I agree function relocation
> to SRAM is not a major factor here, my concern was the additional
> latency incurred during scratchpad save and restore logic as seen by
> the patch:
> -u32 omap3_arm_context[128];
> +u32 omap3_arm_context[256];
> the arm context has doubled albiet 128bytes only.. it still changes

I've tried to address this and other concerns expressed in this thread
and I'll post a new patchset in a few minutes.

> the latencies involved on the save and restore paths.. few
> interesting behavior seen with EHCI save and restore comes to mind
> here - but maybe irrelevant to the discussion..

Regards,
--
Alex

Re: [PATCH] save and restore etm state across core OFF modes

[Alexander Shishkin]

On Tue, Jan 12, 2010 at 04:08:23 -0600, Nishanth Menon wrote:
> Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
> >On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
> >>* Nishanth Menon <nm@ti.com> [100112 09:31]:
> >>>Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
> >>>>On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
> >>>>>Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
> >>>>>>diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> >>>>>>index 69521be..0a5ec86 100644
> >>>>>>--- a/arch/arm/mach-omap2/sleep34xx.S
> >>>>>>+++ b/arch/arm/mach-omap2/sleep34xx.S
> >>>[...]
> >>>>>>	/* Store current cpsr*/
> >>>>>>	mrs	r2, cpsr
> >>>>>>	stmia	r8!, {r2}
> >>>>>>@@ -520,6 +616,7 @@ clean_caches:
> >>>>>>	cmp	r9, #1 /* Check whether L2 inval is required or not*/
> >>>>>>	bne	skip_l2_inval
> >>>>>>clean_l2:
> >>>>>>+#if 0
> >>>>>my aversion to #if 0 kicks in here :(.. do we have an alternative
> >>>>>like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
> >>>>>else?
> >>>>Fair enough. I could replace it with "#if !defined(...)" as the first
> >>>>thing that comes to mind. This way it will only take disabling the
> >>>>config option to catch any possible regressions in between. Does this
> >>>>sound reasonable?
> >>>sounds ok to me.. unless folks have ideas coz of clean_l2 label..
> >>>more comments might be useful before a rev2 of the patch..
> >>The best solution would be to be able to toggle this via sysfs or
> >>debugfs by swapping the sram code for idle loop when JTAG support
> >>is needed.
> >
> >Well, if you say, compile the ETM driver in, this will be needed most of
> >the time.
> >
> I can think of reasons for an against a sysfs entry (as part of
> discussion -warning lot of self contradictions below- but I think
> might save a bit of back and froth ;)):
> 
> for sysfs entry:
> a) save and restore will have additional latency when you save a
> chunk such as EMU domain regs - this will not be needed in
> production phones, disabling it might pop up surprises
> 	counter: having a disabled defconfig allows relevant folks to
> 	enable on a need basis
> 		counter to counter: what do you do when a user reports
> 		an issue in a release and you'd want to debug it with 		
> 		ETM on his platform other than doing a rebuild?

Well, my intention is to have it enabled for most of the cases only having
it disabled for testing purposes.

> b) mostly a debug support -> only for blokes using ETM/JTAG
> interfaces - not everyone can afford these (no offense to openOCD
> guys - but they are still a bit away from being able to debug kernel
> yet on OMAP)..

Not really, you can still make use of ETM without any additional hardware
attached.

Regards,
--
Alex

Re: [PATCH] save and restore etm state across core OFF modes

[Nishanth Menon]

Alexander Shishkin said the following on 01/13/2010 05:36 AM:
> On Tue, Jan 12, 2010 at 04:08:23 -0600, Nishanth Menon wrote:
>   
>> Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
>>     
>>> On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
>>>       
>>>> * Nishanth Menon <nm@ti.com> [100112 09:31]:
>>>>         
>>>>> Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
>>>>>           
>>>>>> On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
>>>>>>             
>>>>>>> Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
>>>>>>>               
>>>>>>>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>>>>>>>> index 69521be..0a5ec86 100644
>>>>>>>> --- a/arch/arm/mach-omap2/sleep34xx.S
>>>>>>>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>>>>>>>>                 
>>>>> [...]
>>>>>           
>>>>>>>> 	/* Store current cpsr*/
>>>>>>>> 	mrs	r2, cpsr
>>>>>>>> 	stmia	r8!, {r2}
>>>>>>>> @@ -520,6 +616,7 @@ clean_caches:
>>>>>>>> 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
>>>>>>>> 	bne	skip_l2_inval
>>>>>>>> clean_l2:
>>>>>>>> +#if 0
>>>>>>>>                 
>>>>>>> my aversion to #if 0 kicks in here :(.. do we have an alternative
>>>>>>> like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
>>>>>>> else?
>>>>>>>               
>>>>>> Fair enough. I could replace it with "#if !defined(...)" as the first
>>>>>> thing that comes to mind. This way it will only take disabling the
>>>>>> config option to catch any possible regressions in between. Does this
>>>>>> sound reasonable?
>>>>>>             
>>>>> sounds ok to me.. unless folks have ideas coz of clean_l2 label..
>>>>> more comments might be useful before a rev2 of the patch..
>>>>>           
>>>> The best solution would be to be able to toggle this via sysfs or
>>>> debugfs by swapping the sram code for idle loop when JTAG support
>>>> is needed.
>>>>         
>>> Well, if you say, compile the ETM driver in, this will be needed most of
>>> the time.
>>>
>>>       
>> I can think of reasons for an against a sysfs entry (as part of
>> discussion -warning lot of self contradictions below- but I think
>> might save a bit of back and froth ;)):
>>
>> for sysfs entry:
>> a) save and restore will have additional latency when you save a
>> chunk such as EMU domain regs - this will not be needed in
>> production phones, disabling it might pop up surprises
>> 	counter: having a disabled defconfig allows relevant folks to
>> 	enable on a need basis
>> 		counter to counter: what do you do when a user reports
>> 		an issue in a release and you'd want to debug it with 		
>> 		ETM on his platform other than doing a rebuild?
>>     
>
> Well, my intention is to have it enabled for most of the cases only having
> it disabled for testing purposes.
>   
with a sysfs you can go either way, with proper #ifdeferry, you can get 
the best of all worlds I guess.. I know in one of the products, a 
similar patch was not taken in due to introduction of additional 
scratchpad space and latencies - so there are folks who would like this 
and those who would like to see this not present in the binary they 
flash to thier device.

>   
>> b) mostly a debug support -> only for blokes using ETM/JTAG
>> interfaces - not everyone can afford these (no offense to openOCD
>> guys - but they are still a bit away from being able to debug kernel
>> yet on OMAP)..
>>     
>
> Not really, you can still make use of ETM without any additional hardware
> attached.
For the unitiated (like me) link from Alex's offline email[1].

Regards,
Nishanth Menon

[1]

http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=c5d6c7708c3e58015b2e4e13e6cea02c8567a94e

Re: [PATCH] save and restore etm state across core OFF modes

[Alexander Shishkin]

On Wed, Jan 13, 2010 at 06:58:28 -0600, Nishanth Menon wrote:
> Alexander Shishkin said the following on 01/13/2010 05:36 AM:
> >On Tue, Jan 12, 2010 at 04:08:23 -0600, Nishanth Menon wrote:
> >>Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
> >>>On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
> >>>>* Nishanth Menon <nm@ti.com> [100112 09:31]:
> >>>>>Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
> >>>>>>On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
> >>>>>>>Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
> >>>>>>>>diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> >>>>>>>>index 69521be..0a5ec86 100644
> >>>>>>>>--- a/arch/arm/mach-omap2/sleep34xx.S
> >>>>>>>>+++ b/arch/arm/mach-omap2/sleep34xx.S
> >>>>>[...]
> >>>>>>>>	/* Store current cpsr*/
> >>>>>>>>	mrs	r2, cpsr
> >>>>>>>>	stmia	r8!, {r2}
> >>>>>>>>@@ -520,6 +616,7 @@ clean_caches:
> >>>>>>>>	cmp	r9, #1 /* Check whether L2 inval is required or not*/
> >>>>>>>>	bne	skip_l2_inval
> >>>>>>>>clean_l2:
> >>>>>>>>+#if 0
> >>>>>>>my aversion to #if 0 kicks in here :(.. do we have an alternative
> >>>>>>>like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
> >>>>>>>else?
> >>>>>>Fair enough. I could replace it with "#if !defined(...)" as the first
> >>>>>>thing that comes to mind. This way it will only take disabling the
> >>>>>>config option to catch any possible regressions in between. Does this
> >>>>>>sound reasonable?
> >>>>>sounds ok to me.. unless folks have ideas coz of clean_l2 label..
> >>>>>more comments might be useful before a rev2 of the patch..
> >>>>The best solution would be to be able to toggle this via sysfs or
> >>>>debugfs by swapping the sram code for idle loop when JTAG support
> >>>>is needed.
> >>>Well, if you say, compile the ETM driver in, this will be needed most of
> >>>the time.
> >>>
> >>I can think of reasons for an against a sysfs entry (as part of
> >>discussion -warning lot of self contradictions below- but I think
> >>might save a bit of back and froth ;)):
> >>
> >>for sysfs entry:
> >>a) save and restore will have additional latency when you save a
> >>chunk such as EMU domain regs - this will not be needed in
> >>production phones, disabling it might pop up surprises
> >>	counter: having a disabled defconfig allows relevant folks to
> >>	enable on a need basis
> >>		counter to counter: what do you do when a user reports
> >>		an issue in a release and you'd want to debug it with 		
> >>		ETM on his platform other than doing a rebuild?
> >
> >Well, my intention is to have it enabled for most of the cases only having
> >it disabled for testing purposes.
> with a sysfs you can go either way, with proper #ifdeferry, you can
> get the best of all worlds I guess.. I know in one of the products,
> a similar patch was not taken in due to introduction of additional
> scratchpad space and latencies - so there are folks who would like
> this and those who would like to see this not present in the binary
> they flash to thier device.

What would you suggest for a place in sysfs for such a file? I'm thinking
/sys/power.

Regards,
--
Alex

Re: [PATCH] save and restore etm state across core OFF modes

[Nishanth Menon]

Alexander Shishkin said the following on 01/18/2010 04:46 AM:
> On Wed, Jan 13, 2010 at 06:58:28 -0600, Nishanth Menon wrote:
>> Alexander Shishkin said the following on 01/13/2010 05:36 AM:
>>> On Tue, Jan 12, 2010 at 04:08:23 -0600, Nishanth Menon wrote:
>>>> Alexander Shishkin had written, on 01/12/2010 03:46 PM, the following:
>>>>> On Tue, Jan 12, 2010 at 01:04:04 -0800, Tony Lindgren wrote:
>>>>>> * Nishanth Menon <nm@ti.com> [100112 09:31]:
>>>>>>> Alexander Shishkin had written, on 01/12/2010 11:30 AM, the following:
>>>>>>>> On Tue, Jan 12, 2010 at 11:13:13 -0600, Nishanth Menon wrote:
>>>>>>>>> Alexander Shishkin had written, on 01/12/2010 11:04 AM, the following:
>>>>>>>>>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>>>>>>>>>> index 69521be..0a5ec86 100644
>>>>>>>>>> --- a/arch/arm/mach-omap2/sleep34xx.S
>>>>>>>>>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>>>>>>> [...]
>>>>>>>>>> 	/* Store current cpsr*/
>>>>>>>>>> 	mrs	r2, cpsr
>>>>>>>>>> 	stmia	r8!, {r2}
>>>>>>>>>> @@ -520,6 +616,7 @@ clean_caches:
>>>>>>>>>> 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
>>>>>>>>>> 	bne	skip_l2_inval
>>>>>>>>>> clean_l2:
>>>>>>>>>> +#if 0
>>>>>>>>> my aversion to #if 0 kicks in here :(.. do we have an alternative
>>>>>>>>> like using the CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG or something
>>>>>>>>> else?
>>>>>>>> Fair enough. I could replace it with "#if !defined(...)" as the first
>>>>>>>> thing that comes to mind. This way it will only take disabling the
>>>>>>>> config option to catch any possible regressions in between. Does this
>>>>>>>> sound reasonable?
>>>>>>> sounds ok to me.. unless folks have ideas coz of clean_l2 label..
>>>>>>> more comments might be useful before a rev2 of the patch..
>>>>>> The best solution would be to be able to toggle this via sysfs or
>>>>>> debugfs by swapping the sram code for idle loop when JTAG support
>>>>>> is needed.
>>>>> Well, if you say, compile the ETM driver in, this will be needed most of
>>>>> the time.
>>>>>
>>>> I can think of reasons for an against a sysfs entry (as part of
>>>> discussion -warning lot of self contradictions below- but I think
>>>> might save a bit of back and froth ;)):
>>>>
>>>> for sysfs entry:
>>>> a) save and restore will have additional latency when you save a
>>>> chunk such as EMU domain regs - this will not be needed in
>>>> production phones, disabling it might pop up surprises
>>>> 	counter: having a disabled defconfig allows relevant folks to
>>>> 	enable on a need basis
>>>> 		counter to counter: what do you do when a user reports
>>>> 		an issue in a release and you'd want to debug it with 		
>>>> 		ETM on his platform other than doing a rebuild?
>>> Well, my intention is to have it enabled for most of the cases only having
>>> it disabled for testing purposes.
>> with a sysfs you can go either way, with proper #ifdeferry, you can
>> get the best of all worlds I guess.. I know in one of the products,
>> a similar patch was not taken in due to introduction of additional
>> scratchpad space and latencies - so there are folks who would like
>> this and those who would like to see this not present in the binary
>> they flash to thier device.
> 
> What would you suggest for a place in sysfs for such a file? I'm thinking
> /sys/power.
I would have imagined this is a perfect candidate for debugfs?
Regards,
Nishanth Menon

Re: [PATCH] save and restore etm state across core OFF modes

[Kevin Hilman]

Alexander Shishkin <virtuoso@slind.org> writes:

> This prevents ETM stalls whenever core enters OFF mode. Original patch
> author is Richard Woodruff <r-woodruff2@ti.com>.
>
> This patch applies on top of pm branch.

There doesn't seem to be any dependencies on PM branch here.

Applying to l-o master has a minor conflict with the adding of the
base addresses that could be easily fixed.

Please rebase onto l-o master.

Thanks,

Kevin

> Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
> CC: Richard Woodruff <r-woodruff2@ti.com>
> ---
>  arch/arm/mach-omap2/Kconfig               |    9 ++
>  arch/arm/mach-omap2/control.c             |    2 +-
>  arch/arm/mach-omap2/sleep34xx.S           |  133 +++++++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/control.h |    2 +-
>  4 files changed, 144 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 606bf04..02ea136 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -153,6 +153,15 @@ config MACH_OMAP_4430SDP
>  	bool "OMAP 4430 SDP board"
>  	depends on ARCH_OMAP4
>  
> +config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	bool "Enable hardware emulation context save and restore"
> +	depends on ARCH_OMAP3
> +	default y
> +	help
> +	  This option enables JTAG & ETM debugging across power states.
> +	  With out this option emulation features are reset across OFF
> +	  mode state changes.
> +
>  config OMAP3_EMU
>  	bool "OMAP3 debugging peripherals"
>  	depends on ARCH_OMAP3
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index cdd1f35..78f4634 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
>   * The address is stored in scratchpad, so that it can be used
>   * during the restore path.
>   */
> -u32 omap3_arm_context[128];
> +u32 omap3_arm_context[256];
>  
>  struct omap3_control_regs {
>  	u32 sysconfig;
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 69521be..0a5ec86 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -59,6 +59,13 @@
>  #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
>  
> +#define CORTEX_CORSIGHT_OFF     (0x00011000)
> +#define CORTEX_EMU_DEBUG_V      (L4_EMU_34XX_VIRT + CORTEX_CORSIGHT_OFF)
> +#define CORTEX_EMU_DEBUG_P      (L4_EMU_34XX_PHYS + CORTEX_CORSIGHT_OFF)
> +#define ETM_CORSIGHT_OFF        (0x00010000)
> +#define CORTEX_EMU_ETM_V        (L4_EMU_34XX_VIRT + ETM_CORSIGHT_OFF)
> +#define CORTEX_EMU_ETM_P        (L4_EMU_34XX_PHYS + ETM_CORSIGHT_OFF)
> +
>          .text
>  /* Function to aquire the semaphore in scratchpad */
>  ENTRY(lock_scratchpad_sem)
> @@ -226,6 +233,18 @@ loop:
>  	nop
>  	bl wait_sdrc_ok
>  
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	/*
> +	 * Restore Coresight debug registers
> +	 */
> +	ldr     r6, debug_vbase      /* base Vaddr of CortexA8-Debug */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* remove global lock if set */
> +	ldr     r6, etm_vbase        /* base Vaddr of ETM */
> +	bl      unlock_debug         /* remove global lock if set */
> +	str     r6, [r6, #0x300]     /* clear OSLAR lock using non-key */
> +#endif
> +
>  	ldmfd	sp!, {r0-r12, pc}		@ restore regs and return
>  restore_es3:
>  	/*b restore_es3*/		@ Enable to debug restore code
> @@ -385,6 +404,50 @@ logic_l1_restore:
>  	/*normal memory remap register */
>  	MCR p15, 0, r5, c10, c2, 1
>  
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	/*
> +	 * Restore Coresight debug registers
> +	 */
> +	ldr     r6, debug_pbase      /* base paddr of CortexA8-Debug */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* remove global lock if set */
> +	str     r4, [r6, #0x300]     /* reset-pointer (already locked) */
> +	ldr     r4, [r6, #0x308]     /* dummy read */
> +	ldr     r4, [r3], #4         /* load save size */
> +	cmp     r4, #0               /* check for zero */
> +debug_restore:
> +	ittt    ne                   /* t2/compat if-then block */
> +	ldrne   r5, [r3], #4         /* get save value */
> +	strne   r5, [r6,#0x308]      /* restore cp14 value */
> +	subnes  r4, r4, #1           /* decrement loop */
> +	bne     debug_restore        /* loop till done */
> +	str     r5, [r6, #0x300]     /* clear lock */
> +	/*
> +	 * Restore CoreSight ETM registers
> +	 */
> +	ldr     r6, etm_pbase        /* base paddr of ETM */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* remove global lock if set */
> +	ldr     r4, [r3], #4         /* load save size */
> +	cmp     r4, #0               /* check for zero */
> +	beq     etm_skip
> +	sub     r4, #1
> +	ldr     r7, [r3], #4         /* get/store first value to r7 */
> +	mov     r5, #0x3             /* enable programming in ETMCR*/
> +	lsl     r5, r5, #10
> +	orr     r5, r7
> +	str     r5,[r6], #4
> +	cmp     r4, #0               /* check for zero */
> +etm_restore:
> +	ldrne   r5, [r3], #4         /* get save value */
> +	strne   r5, [r6], #4         /* restore cp14 value */
> +	subnes  r4, r4, #1           /* decrement loop */
> +	bne     etm_restore          /* loop till done */
> +	ldr     r6, etm_pbase        /* base paddr of ETM */
> +	str     r7,[r6]              /* dis-able programming in ETMCR */
> +etm_skip:
> +#endif
> +
>  	/* Restore cpsr */
>  	ldmia	r3!,{r4}	/*load CPSR from SDRAM*/
>  	msr	cpsr, r4	/*store cpsr */
> @@ -506,6 +569,39 @@ l1_logic_lost:
>  	mrc	p15, 0, r5, c10, c2, 1
>  	stmia	r8!,{r4-r5}
>  
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	/*
> +	 * Save Coresight debug registers
> +	 */
> +	ldr     r6, debug_vbase      /* base vaddr of CortexA8-Debug */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* force global unlock */
> +	str     r4, [r6, #0x300]     /* lock debug access */
> +	ldr     r4, [r6, #0x308]     /* OSSRR returns size on first read */
> +	str     r4, [r8], #4         /* push item to save area */
> +	cmp     r4, #0               /* zero check */
> +debug_save:
> +	ittt    ne                   /* thumb 2 compat if-then block */
> +	ldrne   r5, [r6, #0x308]     /* get reg value */
> +	strne   r5, [r8], #4         /* push item to save area */
> +	subnes  r4, r4, #1           /* decrement size */
> +	bne     debug_save           /* loop till done */
> +	/*
> +	 * Save etm registers
> +	 */
> +	ldr     r6, etm_vbase        /* base vaddr of CortexA8-Debug */
> +	ldr     r4, debug_xlar_key   /* get lock key for OSLAR */
> +	bl      unlock_debug         /* force global unlock */
> +	mov     r4, #128             /* OSSRR returns size on first read */
> +	str     r4, [r8], #4         /* push item to save area */
> +	cmp     r4, #0               /* zero check */
> +etm_save:
> +	ldrne   r5, [r6], #4         /* get reg value */
> +	strne   r5, [r8], #4         /* push item to save area */
> +	subnes  r4, r4, #1           /* decrement size */
> +	bne     etm_save             /* loop till done */
> +#endif
> +
>  	/* Store current cpsr*/
>  	mrs	r2, cpsr
>  	stmia	r8!, {r2}
> @@ -520,6 +616,7 @@ clean_caches:
>  	cmp	r9, #1 /* Check whether L2 inval is required or not*/
>  	bne	skip_l2_inval
>  clean_l2:
> +#if 0
>  	/* read clidr */
>  	mrc     p15, 1, r0, c0, c0, 1
>  	/* extract loc from clidr */
> @@ -586,6 +683,12 @@ finished:
>  	/* select current cache level in cssr */
>  	mcr     p15, 2, r10, c0, c0, 0
>  	isb
> +#else
> +	ldr r1, kernel_flush     /* get 32 bit addr of flush */
> +	mov lr, pc               /* prepare for return */
> +	bx  r1                   /* do it */
> +#endif
> +
>  skip_l2_inval:
>  	/* Data memory barrier and Data sync barrier */
>  	mov     r1, #0
> @@ -632,6 +735,36 @@ wait_dll_lock:
>          bne     wait_dll_lock
>          bx      lr
>  
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +	/*
> +	 * unlock debug:
> +	 *  Input:
> +	 *      r6 has base address of emulation
> +	 *      r4 has unlock key
> +	 *  Output
> +	 *      r5 has PDS value (1=accessable)
> +	 */
> +unlock_debug:
> +	ldr     r5, [r6, #0xfb4]     /* get LSR */
> +	cmp     r5, #0x3             /* need unlocking? */
> +	streq   r4, [r6, #0xfb0]     /* unlock if so */
> +	ldr     r5, [r6, #0x314]     /* clear power status */
> +	bx      lr                   /* back to caller */
> +
> +debug_vbase:
> +	.word CORTEX_EMU_DEBUG_V
> +debug_pbase:
> +	.word CORTEX_EMU_DEBUG_P
> +etm_vbase:
> +	.word CORTEX_EMU_ETM_V
> +etm_pbase:
> +	.word CORTEX_EMU_ETM_P
> +debug_xlar_key:
> +	.word 0xC5ACCE55
> +#endif
> +
> +kernel_flush:
> +	.word v7_flush_dcache_all
>  cm_idlest1_core:
>  	.word	CM_IDLEST1_CORE_V
>  sdrc_dlla_status:
> diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
> index 69428ff..22c492c 100644
> --- a/arch/arm/plat-omap/include/plat/control.h
> +++ b/arch/arm/plat-omap/include/plat/control.h
> @@ -324,7 +324,7 @@ extern void omap3_save_scratchpad_contents(void);
>  extern void omap3_clear_scratchpad_contents(void);
>  extern u32 *get_restore_pointer(void);
>  extern u32 *get_es3_restore_pointer(void);
> -extern u32 omap3_arm_context[128];
> +extern u32 omap3_arm_context[256];
>  extern void omap3_control_save_context(void);
>  extern void omap3_control_restore_context(void);
>  
> -- 
> 1.6.3.3

Re: [PATCH 6/7] save and restore etm state across core OFF modes

[Hari Kanigeri]

> +config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> +       bool "Enable hardware emulation context save and restore"
> +       depends on ARCH_OMAP3

-- Shouldn't this be depends on OMAP3_EMU instead ?

> +       default y

-- As this is debug option, can you keep this "n" by default ?

> +       help
> +         This option enables JTAG & ETM debugging across power states.
> +         With out this option emulation features are reset across OFF
> +         mode state changes.
> +

Hari
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[PATCH] save and restore etm state across core OFF modes

[Alexander Shishkin]

This prevents ETM stalls whenever core enters OFF mode. Original patch
author is Richard Woodruff <r-woodruff2@ti.com>.

This version of the patch makes use of the ETM OS save/restore mechanism,
which takes about 55 words in omap3_arm_context[] instead of 128. Also,
saving ETM context can be switched on/off at runtime.

Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/mach-omap2/Kconfig               |   12 +++
 arch/arm/mach-omap2/control.c             |    2 +-
 arch/arm/mach-omap2/sleep34xx.S           |  135 +++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/control.h |    2 +-
 4 files changed, 149 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf..b00d719 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -243,6 +243,18 @@ config MACH_OMAP4_PANDA
 	default y
 	depends on ARCH_OMAP4
 
+config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	bool "Enable hardware emulation context save and restore"
+	depends on ARCH_OMAP3
+	default y
+	help
+	  This option enables the code that controls the capability to
+	  save and restore JTAG & ETM debugging across power states. It
+	  may be required when using the ETM/ETB tracing driver or an
+	  external debugging hardware.
+	  Without this option emulation features' states are reset across
+	  OFF mode state changes.
+
 config OMAP3_EMU
 	bool "OMAP3 debugging peripherals"
 	depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a8d20ee..22dd240 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
  * The address is stored in scratchpad, so that it can be used
  * during the restore path.
  */
-u32 omap3_arm_context[128];
+u32 omap3_arm_context[256];
 
 struct omap3_control_regs {
 	u32 sysconfig;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index d522cd7..cd6a1d4 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -28,6 +28,7 @@
 #include <asm/assembler.h>
 #include <mach/io.h>
 #include <plat/control.h>
+#include <asm/hardware/coresight.h>
 
 #include "cm.h"
 #include "prm.h"
@@ -226,6 +227,18 @@ loop:
 	nop
 	bl wait_sdrc_ok
 
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	/*
+	 * Restore Coresight debug registers
+	 */
+	ldr	r6, debug_vbase		/* base Vaddr of CortexA8-Debug */
+	ldr	r4, debug_xlar_key	/* get lock key for OSLAR */
+	bl	unlock_debug		/* remove global lock if set */
+	ldr	r6, etm_vbase		/* base Vaddr of ETM */
+	bl	unlock_debug		/* remove global lock if set */
+	str	r6, [r6, #ETMMR_OSLAR]	/* clear OSLAR lock using non-key */
+#endif
+
 	ldmfd	sp!, {r0-r12, pc}		@ restore regs and return
 restore_es3:
 	/*b restore_es3*/		@ Enable to debug restore code
@@ -385,6 +398,44 @@ logic_l1_restore:
 	/*normal memory remap register */
 	MCR p15, 0, r5, c10, c2, 1
 
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	/*
+	 * Restore Coresight debug registers
+	 */
+	ldr	r6, debug_pbase		/* base paddr of CortexA8-Debug */
+	ldr	r4, debug_xlar_key	/* get lock key for OSLAR */
+	bl	unlock_debug		/* remove global lock if set */
+	str	r4, [r6, #ETMMR_OSLAR]	/* reset-pointer (already locked) */
+	ldr	r4, [r6, #ETMMR_OSSRR]	/* dummy read */
+	ldr	r4, [r3], #4		/* load save size */
+	cmp	r4, #0			/* check for zero */
+debug_restore:
+	ittt	ne			/* t2/compat if-then block */
+	ldrne	r5, [r3], #4		/* get saved value */
+	strne	r5, [r6,#ETMMR_OSSRR]	/* restore saved value */
+	subnes	r4, r4, #1		/* decrement loop */
+	bne	debug_restore		/* loop till done */
+	str	r5, [r6, #ETMMR_OSSRR]	/* clear lock */
+	/*
+	 * Restore CoreSight ETM registers
+	 */
+	ldr	r6, etm_pbase		/* base paddr of ETM */
+	ldr	r4, debug_xlar_key	/* get lock key for OSLAR */
+	bl	unlock_debug		/* remove global lock if set */
+	str	r4, [r6, #ETMMR_OSLAR]	/* reset-pointer (already locked) */
+	ldr	r4, [r6, #ETMMR_OSSRR]	/* dummy read */
+	ldr	r4, [r3], #4		/* load save size */
+	cmp	r4, #0			/* check for zero */
+	beq	etm_skip
+etm_restore:
+	ldrne	r5, [r3], #4		/* get saved value */
+	strne	r5, [r6, #ETMMR_OSSRR]	/* restore saved value */
+	subnes	r4, r4, #1		/* decrement loop */
+	bne	etm_restore		/* loop till done */
+etm_skip:
+	str	r6, [r6, #ETMMR_OSLAR]	/* remove OS lock */
+#endif
+
 	/* Restore cpsr */
 	ldmia	r3!,{r4}	/*load CPSR from SDRAM*/
 	msr	cpsr, r4	/*store cpsr */
@@ -506,6 +557,48 @@ l1_logic_lost:
 	mrc	p15, 0, r5, c10, c2, 1
 	stmia	r8!,{r4-r5}
 
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	/*
+	 * Save Coresight debug registers
+	 */
+	ldr	r4, do_etm_save
+	cmp	r4, #0
+	streq	r4, [r8], #4		/* 0 for coresight saved size */
+	streq	r4, [r8], #4		/* 0 for ETM saved size */
+	beq	etm_skip_save
+	ldr	r6, debug_vbase		/* base vaddr of CortexA8-Debug */
+	ldr	r4, debug_xlar_key	/* get lock key for OSLAR */
+	bl	unlock_debug		/* force global unlock */
+	str	r4, [r6, #ETMMR_OSLAR]	/* lock debug access */
+	ldr	r4, [r6, #ETMMR_OSSRR]	/* OSSRR returns size on first read */
+	str	r4, [r8], #4		/* push item to save area */
+	cmp	r4, #0			/* zero check */
+debug_save:
+	ittt	ne			/* thumb 2 compat if-then block */
+	ldrne	r5, [r6, #ETMMR_OSSRR]	/* get reg value */
+	strne	r5, [r8], #4		/* push item to save area */
+	subnes	r4, r4, #1		/* decrement size */
+	bne	debug_save		/* loop till done */
+	str	r6, [r6, #ETMMR_OSLAR]	/* unlock debug access */
+	/*
+	 * Save etm registers
+	 */
+	ldr	r6, etm_vbase		/* base vaddr of ETM */
+	ldr	r4, debug_xlar_key	/* get lock key for OSLAR */
+	bl	unlock_debug		/* force global unlock */
+	str	r4, [r6, #ETMMR_OSLAR]	/* lock OS access to trace regs */
+	ldr	r4, [r6, #ETMMR_OSSRR]	/* OSSRR returns size on first read */
+	str	r4, [r8], #4		/* push size to save area */
+	cmp	r4, #0			/* zero check */
+etm_save:
+	ldrne	r5, [r6, #ETMMR_OSSRR]	/* get reg value */
+	strne	r5, [r8], #4		/* push item to save area */
+	subnes	r4, r4, #1		/* decrement size */
+	bne	etm_save		/* loop till done */
+	str	r6, [r6, #ETMMR_OSLAR]	/* unlock debug access */
+etm_skip_save:
+#endif
+
 	/* Store current cpsr*/
 	mrs	r2, cpsr
 	stmia	r8!, {r2}
@@ -520,6 +613,7 @@ clean_caches:
 	cmp	r9, #1 /* Check whether L2 inval is required or not*/
 	bne	skip_l2_inval
 clean_l2:
+#ifndef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
 	/* read clidr */
 	mrc     p15, 1, r0, c0, c0, 1
 	/* extract loc from clidr */
@@ -586,6 +680,12 @@ finished:
 	/* select current cache level in cssr */
 	mcr     p15, 2, r10, c0, c0, 0
 	isb
+#else
+	ldr	r1, kernel_flush	/* get 32 bit addr of flush */
+	mov	lr, pc			/* prepare for return */
+	bx	r1			/* do it */
+#endif
+
 skip_l2_inval:
 	/* Data memory barrier and Data sync barrier */
 	mov     r1, #0
@@ -632,6 +732,36 @@ wait_dll_lock:
         bne     wait_dll_lock
         bx      lr
 
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+	/*
+	 * unlock debug:
+	 *  Input:
+	 *      r6 has base address of emulation
+	 *      r4 has unlock key
+	 *  Output
+	 *      r5 has PDS value (1=accessable)
+	 */
+unlock_debug:
+	ldr	r5, [r6, #CSMR_LOCKSTATUS]	/* get LSR */
+	cmp	r5, #0x3			/* need unlocking? */
+	streq	r4, [r6, #CSMR_LOCKACCESS]	/* unlock if so */
+	ldr	r5, [r6, #ETMMR_PDSR]		/* clear power status */
+	bx	lr				/* back to caller */
+
+debug_vbase:
+	.word OMAP34XX_DBG_VIRT
+debug_pbase:
+	.word OMAP34XX_DBG_PHYS
+etm_vbase:
+	.word OMAP34XX_ETM_VIRT
+etm_pbase:
+	.word OMAP34XX_ETM_PHYS
+debug_xlar_key:
+	.word UNLOCK_MAGIC
+#endif
+
+kernel_flush:
+	.word v7_flush_dcache_all
 cm_idlest1_core:
 	.word	CM_IDLEST1_CORE_V
 sdrc_dlla_status:
@@ -668,5 +798,10 @@ cache_pred_disable_mask:
 	.word	0xFFFFE7FB
 control_stat:
 	.word	CONTROL_STAT
+/* this word needs to be at the end */
+#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
+do_etm_save:
+	.word   0
+#endif
 ENTRY(omap34xx_cpu_suspend_sz)
 	.word	. - omap34xx_cpu_suspend
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 131bf40..537acbe 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -362,7 +362,7 @@ extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
 extern u32 *get_restore_pointer(void);
 extern u32 *get_es3_restore_pointer(void);
-extern u32 omap3_arm_context[128];
+extern u32 omap3_arm_context[256];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);
 
-- 
1.7.1