[PATCH v3 0/6] OMAP4: Smartreflex and Voltage layer support

[PATCH v3 0/6] OMAP4: Smartreflex and Voltage layer support

[Thara Gopinath]

This patch series adds support for OMAP4 support in the
smartreflex and voltage layer. The series involves extensions
to voltage layer and smartreflex layer for supporting OMAP4.
All these patches might not be dependent on voltage and
smartreflex layer but is required for the correct
functionality of these layers for OMAP4.

This series in based off lo-master and is dependent on the
"OMAP3: Adding Smartreflex and Voltage driver support" series
the link to which is below.

All these patches are also available at 
	http://dev.omapzoom.org/?p=thara/omap-dvfs.git;a=summary
	head: thara-pm-sr

This patch series has been tested on OMAP4430 SDP with omap2plus_defconfig
with the following menuconfig options enabled
        System type -> TI OMAP Implementations -> Smartreflex Support
        System type -> TI OMAP Implementations ->
                Class 3 mode of Smartreflex Implementation

Benoit Cousson (1):
  OMAP4: hwmod: Add inital data for smartreflex modules.

Thara Gopinath (5):
  OMAP4: Add the new voltage to vsel calculation formula
  OMAP4: Adding voltage driver support
  OMAP4: PM: Program correct init voltages for scalable VDDs
  OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data
  OMAP4: Smartreflex framework extensions

 arch/arm/mach-omap2/Makefile               |    2 +-
 arch/arm/mach-omap2/control.h              |   13 ++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  219 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/pm.c                   |    4 +
 arch/arm/mach-omap2/smartreflex.c          |    8 +-
 arch/arm/mach-omap2/sr_device.c            |   12 ++-
 arch/arm/mach-omap2/voltage.c              |  208 ++++++++++++++++++++++++++-
 arch/arm/plat-omap/Kconfig                 |    2 +-
 arch/arm/plat-omap/include/plat/voltage.h  |   20 +++-
 arch/arm/plat-omap/opp_twl_tps.c           |   71 +++++++++
 10 files changed, 552 insertions(+), 7 deletions(-)

[PATCH v3 1/6] OMAP4: Add the new voltage to vsel calculation formula

[Thara Gopinath]

TWL6030 the power IC used along with OMAP4 in OMAP4 SDPs,
blaze boards and panda boards has a different formula
from that of TWL4030 for voltage to vsel and
vsel to voltage calculation. This patch implements the new
formula depending on the PMIC type.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/plat-omap/opp_twl_tps.c |   71 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/opp_twl_tps.c b/arch/arm/plat-omap/opp_twl_tps.c
index 4448fc5..358b67b 100644
--- a/arch/arm/plat-omap/opp_twl_tps.c
+++ b/arch/arm/plat-omap/opp_twl_tps.c
@@ -15,9 +15,16 @@
 
 #include <linux/module.h>
 
+#include <linux/i2c/twl.h>
+
 #include <plat/opp_twl_tps.h>
 #include <plat/voltage.h>
 
+static bool is_offset_valid;
+static u8 smps_offset;
+
+#define REG_SMPS_OFFSET         0xE0
+
 /**
  * omap_twl_vsel_to_vdc - convert TWL/TPS VSEL value to microvolts DC
  * @vsel: TWL/TPS VSEL value to convert
@@ -27,6 +34,38 @@
  */
 unsigned long omap_twl_vsel_to_uv(const u8 vsel)
 {
+	if (twl_class_is_6030()) {
+		/*
+		 * In TWL6030 depending on the value of SMPS_OFFSET
+		 * efuse register the voltage range supported in
+		 * standard mode can be either between 0.6V - 1.3V or
+		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+		 * is programmed to all 0's where as starting from
+		 * TWL6030 ES1.1 the efuse is programmed to 1
+		 */
+		if (!is_offset_valid) {
+			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, 0xE0);
+			is_offset_valid = true;
+		}
+
+		if (smps_offset & 0x8) {
+			return ((((vsel - 1) * 125) + 7000)) * 100;
+		} else {
+			/*
+			 * In case of the supported voltage range being
+			 * between 0.6V - 1.3V, there is not specific
+			 * formula for voltage to vsel conversion above
+			 * 1.3V. There are special hardcoded values for
+			 * voltages above 1.3V. Currently we are hardcodig
+			 * only for 1.35 V which is used for 1GH OPP for
+			 * OMAP4430.
+			 */
+			if (vsel == 0x3A)
+				return 1350000;
+			return ((((vsel - 1) * 125) + 6000)) * 100;
+		}
+	}
+
 	return (((vsel * 125) + 6000)) * 100;
 }
 
@@ -40,6 +79,38 @@ unsigned long omap_twl_vsel_to_uv(const u8 vsel)
 u8 omap_twl_uv_to_vsel(unsigned long uv)
 {
 	/* Round up to higher voltage */
+	if (twl_class_is_6030()) {
+		/*
+		 * In TWL6030 depending on the value of SMPS_OFFSET
+		 * efuse register the voltage range supported in
+		 * standard mode can be either between 0.6V - 1.3V or
+		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+		 * is programmed to all 0's where as starting from
+		 * TWL6030 ES1.1 the efuse is programmed to 1
+		 */
+		if (!is_offset_valid) {
+			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, 0xE0);
+			is_offset_valid = true;
+		}
+
+		if (smps_offset & 0x8) {
+			return DIV_ROUND_UP(uv - 700000, 12500) + 1;
+		} else {
+			/*
+			 * In case of the supported voltage range being
+			 * between 0.6V - 1.3V, there is not specific
+			 * formula for voltage to vsel conversion above
+			 * 1.3V. There are special hardcoded values for
+			 * voltages above 1.3V. Currently we are hardcodig
+			 * only for 1.35 V which is used for 1GH OPP for
+			 * OMAP4430.
+			 */
+			if (uv == 1350000)
+				return 0x3A;
+			return DIV_ROUND_UP(uv - 600000, 12500) + 1;
+		}
+	}
+
 	return DIV_ROUND_UP(uv - 600000, 12500);
 }
 
-- 
1.7.0.4

[PATCH v3 2/6] OMAP4: Adding voltage driver support

[Thara Gopinath]

OMAP4 has three scalable voltage domains vdd_mpu, vdd_iva
and vdd_core. This patch adds the voltage tables and other
configurable voltage processor and voltage controller
settings to control these three scalable domains in OMAP4.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/Makefile              |    2 +-
 arch/arm/mach-omap2/voltage.c             |  208 ++++++++++++++++++++++++++++-
 arch/arm/plat-omap/include/plat/voltage.h |   20 +++-
 3 files changed, 227 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e194830..5cf2bcc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -53,7 +53,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o voltage.o \
 					   cpuidle34xx.o pm_bus.o
-obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o voltage.o pm_bus.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index ac81ace..45b0958 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -29,6 +29,8 @@
 #include <plat/voltage.h>
 
 #include "prm-regbits-34xx.h"
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
 
 #define VP_IDLE_TIMEOUT		200
 #define VP_TRANXDONE_TIMEOUT	300
@@ -151,7 +153,50 @@ static struct omap_vdd_info omap3_vdd_info[] = {
 
 #define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info)
 
-/* TODO: OMAP4 register offsets */
+/* OMAP4 VDD sturctures */
+static struct omap_vdd_info omap4_vdd_info[] = {
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "mpu",
+		},
+	},
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "iva",
+		},
+	},
+	{
+		.vp_offs = {
+			.vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+			.vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+			.vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
+			.vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
+			.vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
+			.voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
+		},
+		.voltdm = {
+			.name = "core",
+		},
+	},
+};
+
+#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info)
 
 /*
  * Default voltage controller settings.
@@ -215,6 +260,29 @@ static struct omap_volt_data omap36xx_vdd2_volt_data[] = {
 	{.volt_nominal = 1137500, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
 };
 
+/*
+ * Structures containing OMAP4430 voltage supported and various
+ * data associated with it per voltage domain basis. Smartreflex Ntarget
+ * values are left as 0 as they have to be populated by smartreflex
+ * driver after reading the efuse.
+ */
+static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
+	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
+	{.volt_nominal = 1260000, .sr_errminlimit = 0xFA, .vp_errgain = 0x23},
+	{.volt_nominal = 1350000, .sr_errminlimit = 0xFA, .vp_errgain = 0x27},
+};
+
+static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
+	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
+	{.volt_nominal = 1260000, .sr_errminlimit = 0xFA, .vp_errgain = 0x23},
+};
+
+static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
+	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
+};
 
 /* By default VPFORCEUPDATE is the chosen method of voltage scaling */
 static bool voltscale_vpforceupdate = true;
@@ -525,6 +593,130 @@ static void __init omap3_vdd_data_configure(struct omap_vdd_info *vdd)
 	vdd->vp_reg.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT;
 }
 
+/* OMAP4 specific voltage init functions */
+static void __init omap4_init_voltagecontroller(void)
+{
+	voltage_write_reg(OMAP4_PRM_VC_SMPS_SA_OFFSET,
+			(OMAP4_SRI2C_SLAVE_ADDR <<
+			 OMAP4430_SA_VDD_CORE_L_0_6_SHIFT) |
+			(OMAP4_SRI2C_SLAVE_ADDR <<
+			 OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT) |
+			(OMAP4_SRI2C_SLAVE_ADDR <<
+			 OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT));
+	voltage_write_reg(OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
+			(OMAP4_VDD_MPU_SR_VOLT_REG <<
+			 OMAP4430_VOLRA_VDD_MPU_L_SHIFT) |
+			(OMAP4_VDD_IVA_SR_VOLT_REG <<
+			 OMAP4430_VOLRA_VDD_IVA_L_SHIFT) |
+			(OMAP4_VDD_CORE_SR_VOLT_REG <<
+			 OMAP4430_VOLRA_VDD_CORE_L_SHIFT));
+	voltage_write_reg(OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
+			OMAP4430_RAV_VDD_MPU_L_MASK |
+			OMAP4430_CMD_VDD_MPU_L_MASK |
+			OMAP4430_RAV_VDD_IVA_L_MASK |
+			OMAP4430_CMD_VDD_IVA_L_MASK |
+			OMAP4430_RAV_VDD_CORE_L_MASK |
+			OMAP4430_CMD_VDD_CORE_L_MASK);
+
+	voltage_write_reg(OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET,
+			(0x60 << OMAP4430_SCLL_SHIFT |
+			0x26 << OMAP4430_SCLH_SHIFT));
+	/* TODO: Configure setup times and CMD_VAL values*/
+}
+
+/* Sets up all the VDD related info for OMAP4 */
+static void __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
+{
+	struct clk *sys_ck;
+	u32 sys_clk_speed, timeout_val, waittime;
+
+	if (!strcmp(vdd->voltdm.name, "mpu")) {
+		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN;
+		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX;
+		vdd->volt_data = omap44xx_vdd_mpu_volt_data;
+		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_mpu_volt_data);
+		vdd->vp_reg.tranxdone_status =
+				OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
+		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
+		vdd->vdd_sr_reg = OMAP4_VDD_MPU_SR_VOLT_REG;
+	} else if (!strcmp(vdd->voltdm.name, "core")) {
+		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN;
+		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX;
+		vdd->volt_data = omap44xx_vdd_core_volt_data;
+		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_core_volt_data);
+		vdd->vp_reg.tranxdone_status =
+				OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
+		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
+		vdd->vdd_sr_reg = OMAP4_VDD_CORE_SR_VOLT_REG;
+	} else if (!strcmp(vdd->voltdm.name, "iva")) {
+		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN;
+		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX;
+		vdd->volt_data = omap44xx_vdd_iva_volt_data;
+		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_iva_volt_data);
+		vdd->vp_reg.tranxdone_status =
+			OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
+		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
+		vdd->vdd_sr_reg = OMAP4_VDD_IVA_SR_VOLT_REG;
+	} else {
+		pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
+			__func__, vdd->voltdm.name);
+		return;
+	}
+
+	/*
+	 * Sys clk rate is require to calculate vp timeout value and
+	 * smpswaittimemin and smpswaittimemax.
+	 */
+	sys_ck = clk_get(NULL, "sys_clkin_ck");
+	if (IS_ERR(sys_ck)) {
+		pr_warning("%s: Could not get the sys clk to calculate"
+			"various vdd_%s params\n", __func__, vdd->voltdm.name);
+		return;
+	}
+	sys_clk_speed = clk_get_rate(sys_ck);
+	clk_put(sys_ck);
+
+	/* Divide to avoid overflow */
+	sys_clk_speed /= 1000;
+
+	/* Nominal/Reset voltage of the VDD */
+	vdd->nominal_volt = vdd->curr_volt = 1200000;
+
+	/* VPCONFIG bit fields */
+	vdd->vp_reg.vpconfig_erroroffset =
+				(OMAP4_VP_CONFIG_ERROROFFSET <<
+				 OMAP4430_ERROROFFSET_SHIFT);
+	vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK;
+	vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT;
+	vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT;
+	vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK;
+	vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK;
+	vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK;
+	vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK;
+	vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK;
+
+	/* VSTEPMIN VSTEPMAX bit fields */
+	waittime = ((volt_pmic_info.step_size / volt_pmic_info.slew_rate) *
+				sys_clk_speed) / 1000;
+	vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
+	vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
+	vdd->vp_reg.vstepmin_stepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN;
+	vdd->vp_reg.vstepmax_stepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX;
+	vdd->vp_reg.vstepmin_smpswaittimemin_shift =
+		OMAP4430_SMPSWAITTIMEMIN_SHIFT;
+	vdd->vp_reg.vstepmax_smpswaittimemax_shift =
+		OMAP4430_SMPSWAITTIMEMAX_SHIFT;
+	vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT;
+	vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT;
+
+	/* VLIMITTO bit fields */
+	timeout_val = (sys_clk_speed * OMAP4_VP_VLIMITTO_TIMEOUT_US) / 1000;
+	vdd->vp_reg.vlimitto_timeout = timeout_val;
+	vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT;
+	vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT;
+	vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT;
+}
+
 /* Generic voltage init functions */
 static void __init init_voltageprocessor(struct omap_vdd_info *vdd)
 {
@@ -753,6 +945,14 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
 		vc_cmd_on_mask = OMAP3430_VC_CMD_ON_MASK;
 		prm_irqst_reg_offs = OMAP3_PRM_IRQSTATUS_MPU_OFFSET;
 		ocp_mod = OCP_MOD;
+	} else if (cpu_is_omap44xx()) {
+		vc_cmd_on_shift = OMAP4430_ON_SHIFT;
+		vc_cmd_on_mask = OMAP4430_ON_MASK;
+		if (!strcmp(vdd->voltdm.name, "mpu"))
+			prm_irqst_reg_offs = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
+		else
+			prm_irqst_reg_offs = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
+		ocp_mod = OMAP4430_PRM_OCP_SOCKET_MOD;
 	} else {
 		pr_warning("%s: Voltage scaling not yet enabled for"
 			"this chip\n", __func__);
@@ -1348,6 +1548,12 @@ static int __init omap_voltage_init(void)
 		nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD;
 		init_voltagecontroller = omap3_init_voltagecontroller;
 		vdd_data_configure = omap3_vdd_data_configure;
+	} else if (cpu_is_omap44xx()) {
+		volt_mod = OMAP4430_PRM_DEVICE_MOD;
+		vdd_info = omap4_vdd_info;
+		nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
+		init_voltagecontroller = omap4_init_voltagecontroller;
+		vdd_data_configure = omap4_vdd_data_configure;
 	} else {
 		pr_warning("%s: voltage driver support not added\n", __func__);
 		return 0;
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
index 5677544..812266e 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -22,6 +22,12 @@
 #define OMAP3_VDD1_SR_CONTROL_REG		0x00
 #define OMAP3_VDD2_SR_CONTROL_REG		0x01
 
+/* Voltage SR parameters for OMAP4 */
+#define OMAP4_SRI2C_SLAVE_ADDR			0x12
+#define OMAP4_VDD_MPU_SR_VOLT_REG		0x55
+#define OMAP4_VDD_IVA_SR_VOLT_REG		0x5B
+#define OMAP4_VDD_CORE_SR_VOLT_REG		0x61
+
 /*
  * Omap3 VP register specific values. Maybe these need to come from
  * board file or PMIC data structure
@@ -51,7 +57,19 @@
 #define OMAP3630_VP2_VLIMITTO_VDDMIN		0x18
 #define OMAP3630_VP2_VLIMITTO_VDDMAX		0x30
 
-/* TODO OMAP4 VP register values if the same file is used for OMAP4*/
+/* OMAP4 VP register values */
+#define OMAP4_VP_CONFIG_ERROROFFSET		0x00
+#define	OMAP4_VP_VSTEPMIN_SMPSWAITTIMEMIN	0x3C
+#define OMAP4_VP_VSTEPMIN_VSTEPMIN		0x1
+#define OMAP4_VP_VSTEPMAX_SMPSWAITTIMEMAX	0x3C
+#define OMAP4_VP_VSTEPMAX_VSTEPMAX		0x04
+#define OMAP4_VP_VLIMITTO_TIMEOUT_US		0x200
+#define OMAP4_VP_MPU_VLIMITTO_VDDMIN		0x18
+#define OMAP4_VP_MPU_VLIMITTO_VDDMAX		0x3C
+#define OMAP4_VP_IVA_VLIMITTO_VDDMIN		0x18
+#define OMAP4_VP_IVA_VLIMITTO_VDDMAX		0x3C
+#define OMAP4_VP_CORE_VLIMITTO_VDDMIN		0x18
+#define OMAP4_VP_CORE_VLIMITTO_VDDMAX		0x30
 
 /**
  * struct voltagedomain - omap voltage domain global structure.
-- 
1.7.0.4

[PATCH v3 3/6] OMAP4: PM: Program correct init voltages for scalable VDDs

[Thara Gopinath]

By default the system boots up at nominal voltage for every
voltage domain in the system. This patch puts vdd_mpu, vdd_iva
and vdd_core to the correct boot up voltage as per the opp tables
specified. This patch implements this by matching the rate of
the main clock of the voltage domain with the opp table and
picking up the correct voltage.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/pm.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 353e155..0651667 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -211,6 +211,10 @@ static int __init omap2_common_pm_init(void)
 	if (cpu_is_omap34xx()) {
 		omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
 		omap2_set_init_voltage("core", "l3_ick", l3_dev);
+	} else if (cpu_is_omap44xx()) {
+		omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
+		omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
+		omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
 	}
 
 	omap_pm_if_init();
-- 
1.7.0.4

[PATCH v3 4/6] OMAP4: hwmod: Add inital data for smartreflex modules.

[Thara Gopinath]

From: Benoit Cousson <b-cousson@ti.com>

This patch adds the hwmod details for OMAP4 smartreflex modules.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  163 ++++++++++++++++++++++++++++
 1 files changed, 163 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0d5c6eb..959c3f9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1043,6 +1043,165 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/*
+ * 'smartreflex' class
+ * smartreflex module (monitor silicon performance and outputs a measure of
+ * performance error)
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+	.sidle_shift	= 24,
+	.enwkup_shift	= 26,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
+	.sysc_offs	= 0x0038,
+	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
+	.name = "smartreflex",
+	.sysc = &omap44xx_smartreflex_sysc,
+};
+
+/* smartreflex_core */
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
+	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+	{
+		.pa_start	= 0x4a0dd000,
+		.pa_end		= 0x4a0dd03f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_core_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_core_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_core slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_core,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+	.name		= "smartreflex_core",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
+	.main_clk	= "smartreflex_core_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_core_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_iva */
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
+	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+	{
+		.pa_start	= 0x4a0db000,
+		.pa_end		= 0x4a0db03f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_iva_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_iva_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_iva slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_iva,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+	.name		= "smartreflex_iva",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
+	.main_clk	= "smartreflex_iva_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_iva_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_mpu */
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
+	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+	{
+		.pa_start	= 0x4a0d9000,
+		.pa_end		= 0x4a0d903f,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_smartreflex_mpu_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_smartreflex_mpu_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_mpu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
+	&omap44xx_l4_cfg__smartreflex_mpu,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+	.name		= "smartreflex_mpu",
+	.class		= &omap44xx_smartreflex_hwmod_class,
+	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
+	.main_clk	= "smartreflex_mpu_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_smartreflex_mpu_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	/* dmm class */
 	&omap44xx_dmm_hwmod,
@@ -1077,6 +1236,10 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	&omap44xx_uart2_hwmod,
 	&omap44xx_uart3_hwmod,
 	&omap44xx_uart4_hwmod,
+
+	&omap44xx_smartreflex_core_hwmod,
+	&omap44xx_smartreflex_iva_hwmod,
+	&omap44xx_smartreflex_mpu_hwmod,
 	NULL,
 };
 
-- 
1.7.0.4

[PATCH v3 5/6] OMAP4: Adding dev atrributes to OMAP4 smartreflex hwmod data

[Thara Gopinath]

This patch adds dev attributes for smartreflex modules
in the OMAP4 hwmod database. This patch also updates the
smartreflex rev in the smartreflex class data structure
in the OMAP4 hwmod database.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/control.h              |   13 ++++++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   56 ++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d9b5bed..7061419 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -181,6 +181,19 @@
 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
 
+/* OMAP44xx control efuse offsets */
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
+
+
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 959c3f9..5b981aa 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,11 +22,13 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
+#include <plat/smartreflex.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "cm.h"
 #include "prm-regbits-44xx.h"
+#include "control.h"
 
 /* Base offset for all OMAP4 interrupts external to MPUSS */
 #define OMAP44XX_IRQ_GIC_START	32
@@ -1065,6 +1067,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
 	.name = "smartreflex",
 	.sysc = &omap44xx_smartreflex_sysc,
+	.rev  = 2,
 };
 
 /* smartreflex_core */
@@ -1096,6 +1099,22 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
 	&omap44xx_l4_cfg__smartreflex_core,
 };
 
+static u32 omap44xx_sr_core_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_CORE_OPP50, OMAP44XX_CONTROL_FUSE_CORE_OPP100,
+};
+
+static u32 omap44xx_sr_core_test_nvalues[] = {
+	0x0, 0x0
+};
+
+static struct omap_sr_dev_data omap44xx_sr_core_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_core_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_core_test_nvalues,
+	.vdd_name		= "core"
+};
+
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
 	.name		= "smartreflex_core",
 	.class		= &omap44xx_smartreflex_hwmod_class,
@@ -1109,6 +1128,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
 	},
 	.slaves		= omap44xx_smartreflex_core_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+	.dev_attr	= &omap44xx_sr_core_dev_attr,
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -1141,6 +1161,23 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
 	&omap44xx_l4_cfg__smartreflex_iva,
 };
 
+static u32 omap44xx_sr_iva_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_IVA_OPP50, OMAP44XX_CONTROL_FUSE_IVA_OPP100,
+	OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO,
+};
+
+static u32 omap44xx_sr_iva_test_nvalues[] = {
+	0x0, 0x0, 0x0, 0x0
+};
+
+static struct omap_sr_dev_data omap44xx_sr_iva_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_iva_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_iva_test_nvalues,
+	.vdd_name		= "iva"
+};
+
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
 	.name		= "smartreflex_iva",
 	.class		= &omap44xx_smartreflex_hwmod_class,
@@ -1154,6 +1191,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
 	},
 	.slaves		= omap44xx_smartreflex_iva_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+	.dev_attr	= &omap44xx_sr_iva_dev_attr,
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
@@ -1186,6 +1224,23 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
 	&omap44xx_l4_cfg__smartreflex_mpu,
 };
 
+static u32 omap44xx_sr_mpu_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_MPU_OPP50, OMAP44XX_CONTROL_FUSE_MPU_OPP100,
+	OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO,
+};
+
+static u32 omap44xx_sr_mpu_test_nvalues[] = {
+	0x0, 0x0, 0x0, 0x0
+};
+
+static struct omap_sr_dev_data omap44xx_sr_mpu_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_mpu_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_mpu_test_nvalues,
+	.vdd_name		= "mpu"
+};
+
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
 	.name		= "smartreflex_mpu",
 	.class		= &omap44xx_smartreflex_hwmod_class,
@@ -1199,6 +1254,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
 	},
 	.slaves		= omap44xx_smartreflex_mpu_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+	.dev_attr	= &omap44xx_sr_mpu_dev_attr,
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-- 
1.7.0.4

[PATCH v3 6/6] OMAP4: Smartreflex framework extensions

[Thara Gopinath]

This patch extends the smartreflex framework to support
OMAP4. The changes are minor like compiling smartreflex Kconfig
option for OMAP4 also, and a couple of OMAP4 checks in
the smartreflex framework.

The change in sr_device.c where new logic has to be introduced
for reading the efuse registers is due to the fact that in OMAP4
the efuse registers are 24 bit aligned. A __raw_readl will
fail for non-32 bit aligned address and hence the 8-bit read
and shift.

Signed-off-by: Thara Gopinath <thara@ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |    8 ++++++--
 arch/arm/mach-omap2/sr_device.c   |   12 +++++++++++-
 arch/arm/plat-omap/Kconfig        |    2 +-
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 2669584..23e14c0 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -149,7 +149,11 @@ static void sr_set_clk_length(struct omap_sr *sr)
 	struct clk *sys_ck;
 	u32 sys_clk_speed;
 
-	sys_ck = clk_get(NULL, "sys_ck");
+	if (cpu_is_omap34xx())
+		sys_ck = clk_get(NULL, "sys_ck");
+	else
+		sys_ck = clk_get(NULL, "sys_clkin_ck");
+
 	if (IS_ERR(sys_ck)) {
 		dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
 			__func__);
@@ -189,7 +193,7 @@ static void sr_set_regfields(struct omap_sr *sr)
 	 * file or pmic specific data structure. In that case these structure
 	 * fields will have to be populated using the pdata or pmic structure.
 	 */
-	if (cpu_is_omap34xx()) {
+	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
 		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
 		sr->accum_data = OMAP3430_SR_ACCUMDATA;
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index b7e2d10..c157392 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -20,6 +20,7 @@
 
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <linux/io.h>
 
 #include <plat/omap_device.h>
 #include <plat/smartreflex.h>
@@ -101,7 +102,16 @@ static void __init sr_set_nvalues(struct omap_sr_dev_data *dev_data,
 	}
 
 	for (i = 0; i < dev_data->volts_supported; i++) {
-		u32 v = omap_ctrl_readl(dev_data->efuse_nvalues_offs[i]);
+		u32 v;
+		if (cpu_is_omap44xx()) {
+			u16 offset = dev_data->efuse_nvalues_offs[i];
+
+			v = omap_ctrl_readb(offset) |
+				omap_ctrl_readb(offset + 1) << 8 |
+				omap_ctrl_readb(offset + 2) << 16;
+		} else {
+			v = omap_ctrl_readl(dev_data->efuse_nvalues_offs[i]);
+		}
 
 		dev_data->volt_data[i].sr_nvalue = v;
 	}
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 7ba92c2..afc6fed 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -37,7 +37,7 @@ config OMAP_DEBUG_LEDS
 
 config OMAP_SMARTREFLEX
 	bool "SmartReflex support"
-	depends on ARCH_OMAP3 && PM
+	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
 	help
 	  Say Y if you want to enable SmartReflex.
 
-- 
1.7.0.4

Re: [PATCH v3 3/6] OMAP4: PM: Program correct init voltages for scalable VDDs

[Tony Lindgren]

Hi Thara,

* Thara Gopinath <thara@ti.com> [101027 09:08]:
> By default the system boots up at nominal voltage for every
> voltage domain in the system. This patch puts vdd_mpu, vdd_iva
> and vdd_core to the correct boot up voltage as per the opp tables
> specified. This patch implements this by matching the rate of
> the main clock of the voltage domain with the opp table and
> picking up the correct voltage.
> 
> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
>  arch/arm/mach-omap2/pm.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
> index 353e155..0651667 100644
> --- a/arch/arm/mach-omap2/pm.c
> +++ b/arch/arm/mach-omap2/pm.c
> @@ -211,6 +211,10 @@ static int __init omap2_common_pm_init(void)
>  	if (cpu_is_omap34xx()) {
>  		omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
>  		omap2_set_init_voltage("core", "l3_ick", l3_dev);
> +	} else if (cpu_is_omap44xx()) {
> +		omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
> +		omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
> +		omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
>  	}
>  
>  	omap_pm_if_init();

In general, we want to avoid adding these "if cpu_is_ompa34xx else if"
things all over the place. That makes the code hard to maintain and
requires patching all over the place to add support for new omaps.

Instead, please do something like this:

static int __init omap_common_whatever_init(struct whatever_data *d)
{
	...

	return 0;
}

static int __init omap3_whatever_init(void)
{
	struct whatever_data *d;

	if (!cpu_is_omap34xx())
		return -ENODEV;

	/* Initialize omap3 specific things */
	...

	return omap_common_whatever_init(d);
}
device_initcall(omap3_whatever_init);

static int __init omap4_whatever_init(void)
{
	struct whatever_data *d;

	if (!cpu_is_omap44xx())
		return -ENODEV;

	/* Initialize omap4 specific things */
	...

	return omap_common_whatever_init(d);
}
device_initcall(omap4_whatever_init);
...

This way the common code stays readable and does not need
to be patched when support for new omaps is added. Also the
code for unselected omaps gets optimized out and an extra
level of code indentation is left out.

Regards,

Tony

Re: [PATCH v3 1/6] OMAP4: Add the new voltage to vsel calculation formula

[Tony Lindgren]

* Thara Gopinath <thara@ti.com> [101027 09:07]:
> TWL6030 the power IC used along with OMAP4 in OMAP4 SDPs,
> blaze boards and panda boards has a different formula
> from that of TWL4030 for voltage to vsel and
> vsel to voltage calculation. This patch implements the new
> formula depending on the PMIC type.
> 
> Signed-off-by: Thara Gopinath <thara@ti.com>
> ---
>  arch/arm/plat-omap/opp_twl_tps.c |   71 ++++++++++++++++++++++++++++++++++++++
>  1 files changed, 71 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/opp_twl_tps.c b/arch/arm/plat-omap/opp_twl_tps.c
> index 4448fc5..358b67b 100644
> --- a/arch/arm/plat-omap/opp_twl_tps.c
> +++ b/arch/arm/plat-omap/opp_twl_tps.c
> @@ -15,9 +15,16 @@
>  
>  #include <linux/module.h>
>  
> +#include <linux/i2c/twl.h>
> +
>  #include <plat/opp_twl_tps.h>
>  #include <plat/voltage.h>
>  
> +static bool is_offset_valid;
> +static u8 smps_offset;
> +
> +#define REG_SMPS_OFFSET         0xE0
> +
>  /**
>   * omap_twl_vsel_to_vdc - convert TWL/TPS VSEL value to microvolts DC
>   * @vsel: TWL/TPS VSEL value to convert
> @@ -27,6 +34,38 @@
>   */
>  unsigned long omap_twl_vsel_to_uv(const u8 vsel)
>  {
> +	if (twl_class_is_6030()) {
> +		/*
> +		 * In TWL6030 depending on the value of SMPS_OFFSET
> +		 * efuse register the voltage range supported in
> +		 * standard mode can be either between 0.6V - 1.3V or
> +		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
> +		 * is programmed to all 0's where as starting from
> +		 * TWL6030 ES1.1 the efuse is programmed to 1
> +		 */
> +		if (!is_offset_valid) {
> +			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, 0xE0);
> +			is_offset_valid = true;
> +		}
> +
> +		if (smps_offset & 0x8) {
> +			return ((((vsel - 1) * 125) + 7000)) * 100;
> +		} else {
> +			/*
> +			 * In case of the supported voltage range being
> +			 * between 0.6V - 1.3V, there is not specific
> +			 * formula for voltage to vsel conversion above
> +			 * 1.3V. There are special hardcoded values for
> +			 * voltages above 1.3V. Currently we are hardcodig
> +			 * only for 1.35 V which is used for 1GH OPP for
> +			 * OMAP4430.
> +			 */
> +			if (vsel == 0x3A)
> +				return 1350000;
> +			return ((((vsel - 1) * 125) + 6000)) * 100;
> +		}
> +	}
> +
>  	return (((vsel * 125) + 6000)) * 100;
>  }

Here too you will want to restructure things a bit so you can avoid
adding the "if twl_class_is_whatever else if" tests. Usually the best
way is to set separate functions for different chips during the init.

Regards,

Tony

Re: [PATCH v3 2/6] OMAP4: Adding voltage driver support

[Kevin Hilman]

Thara Gopinath <thara@ti.com> writes:

> OMAP4 has three scalable voltage domains vdd_mpu, vdd_iva
> and vdd_core. This patch adds the voltage tables and other
> configurable voltage processor and voltage controller
> settings to control these three scalable domains in OMAP4.
>
> Signed-off-by: Thara Gopinath <thara@ti.com>

[...]

> +/*
> + * Structures containing OMAP4430 voltage supported and various
> + * data associated with it per voltage domain basis. Smartreflex Ntarget
> + * values are left as 0 as they have to be populated by smartreflex
> + * driver after reading the efuse.
> + */
> +static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
> +	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
> +	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
> +	{.volt_nominal = 1260000, .sr_errminlimit = 0xFA, .vp_errgain = 0x23},
> +	{.volt_nominal = 1350000, .sr_errminlimit = 0xFA, .vp_errgain = 0x27},
> +};
> +
> +static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
> +	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
> +	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
> +	{.volt_nominal = 1260000, .sr_errminlimit = 0xFA, .vp_errgain = 0x23},
> +};
> +
> +static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
> +	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
> +	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
> +};

As mentioned in previous reviews, the standard is to write hex value
using lower case letters.   Please fix this up in the both OMAP3 & 4 series.

[...]

> +/* Sets up all the VDD related info for OMAP4 */
> +static void __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
> +{
> +	struct clk *sys_ck;
> +	u32 sys_clk_speed, timeout_val, waittime;
> +
> +	if (!strcmp(vdd->voltdm.name, "mpu")) {
> +		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN;
> +		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX;
> +		vdd->volt_data = omap44xx_vdd_mpu_volt_data;
> +		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_mpu_volt_data);
> +		vdd->vp_reg.tranxdone_status =
> +				OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
> +		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
> +		vdd->vdd_sr_reg = OMAP4_VDD_MPU_SR_VOLT_REG;
> +	} else if (!strcmp(vdd->voltdm.name, "core")) {
> +		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN;
> +		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX;
> +		vdd->volt_data = omap44xx_vdd_core_volt_data;
> +		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_core_volt_data);
> +		vdd->vp_reg.tranxdone_status =
> +				OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
> +		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
> +		vdd->vdd_sr_reg = OMAP4_VDD_CORE_SR_VOLT_REG;
> +	} else if (!strcmp(vdd->voltdm.name, "iva")) {
> +		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN;
> +		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX;
> +		vdd->volt_data = omap44xx_vdd_iva_volt_data;
> +		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_iva_volt_data);
> +		vdd->vp_reg.tranxdone_status =
> +			OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
> +		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
> +		vdd->vdd_sr_reg = OMAP4_VDD_IVA_SR_VOLT_REG;
> +	} else {
> +		pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
> +			__func__, vdd->voltdm.name);
> +		return;
> +	}
> +
> +	/*
> +	 * Sys clk rate is require to calculate vp timeout value and
> +	 * smpswaittimemin and smpswaittimemax.
> +	 */
> +	sys_ck = clk_get(NULL, "sys_clkin_ck");
> +	if (IS_ERR(sys_ck)) {
> +		pr_warning("%s: Could not get the sys clk to calculate"
> +			"various vdd_%s params\n", __func__, vdd->voltdm.name);
> +		return;
> +	}
> +	sys_clk_speed = clk_get_rate(sys_ck);
> +	clk_put(sys_ck);
> +
> +	/* Divide to avoid overflow */
> +	sys_clk_speed /= 1000;
> +
> +	/* Nominal/Reset voltage of the VDD */
> +	vdd->nominal_volt = vdd->curr_volt = 1200000;

same comment as from  OMAP3 series.

[...]

>  /* Generic voltage init functions */
>  static void __init init_voltageprocessor(struct omap_vdd_info *vdd)
>  {
> @@ -753,6 +945,14 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
>  		vc_cmd_on_mask = OMAP3430_VC_CMD_ON_MASK;
>  		prm_irqst_reg_offs = OMAP3_PRM_IRQSTATUS_MPU_OFFSET;
>  		ocp_mod = OCP_MOD;
> +	} else if (cpu_is_omap44xx()) {
> +		vc_cmd_on_shift = OMAP4430_ON_SHIFT;
> +		vc_cmd_on_mask = OMAP4430_ON_MASK;
> +		if (!strcmp(vdd->voltdm.name, "mpu"))
> +			prm_irqst_reg_offs = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
> +		else
> +			prm_irqst_reg_offs = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
> +		ocp_mod = OMAP4430_PRM_OCP_SOCKET_MOD;

again, please no cpu_is_* outside of init functions.

>  	} else {
>  		pr_warning("%s: Voltage scaling not yet enabled for"
>  			"this chip\n", __func__);
> @@ -1348,6 +1548,12 @@ static int __init omap_voltage_init(void)
>  		nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD;
>  		init_voltagecontroller = omap3_init_voltagecontroller;
>  		vdd_data_configure = omap3_vdd_data_configure;
> +	} else if (cpu_is_omap44xx()) {
> +		volt_mod = OMAP4430_PRM_DEVICE_MOD;
> +		vdd_info = omap4_vdd_info;
> +		nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
> +		init_voltagecontroller = omap4_init_voltagecontroller;
> +		vdd_data_configure = omap4_vdd_data_configure;
>  	} else {
>  		pr_warning("%s: voltage driver support not added\n", __func__);
>  		return 0;

Kevin

RE: [PATCH v3 2/6] OMAP4: Adding voltage driver support

[Gopinath, Thara]

>>-----Original Message-----
>>From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
>>Sent: Thursday, November 11, 2010 12:52 AM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; paul@pwsan.com; Cousson, Benoit; Sripathy,
>>Vishwanath; Sawant, Anand
>>Subject: Re: [PATCH v3 2/6] OMAP4: Adding voltage driver support
>>
>>Thara Gopinath <thara@ti.com> writes:
>>
>>> OMAP4 has three scalable voltage domains vdd_mpu, vdd_iva
>>> and vdd_core. This patch adds the voltage tables and other
>>> configurable voltage processor and voltage controller
>>> settings to control these three scalable domains in OMAP4.
>>>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>
>>[...]
>>
>>> +/*
>>> + * Structures containing OMAP4430 voltage supported and various
>>> + * data associated with it per voltage domain basis. Smartreflex Ntarget
>>> + * values are left as 0 as they have to be populated by smartreflex
>>> + * driver after reading the efuse.
>>> + */
>>> +static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
>>> +	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
>>> +	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
>>> +	{.volt_nominal = 1260000, .sr_errminlimit = 0xFA, .vp_errgain = 0x23},
>>> +	{.volt_nominal = 1350000, .sr_errminlimit = 0xFA, .vp_errgain = 0x27},
>>> +};
>>> +
>>> +static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
>>> +	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
>>> +	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
>>> +	{.volt_nominal = 1260000, .sr_errminlimit = 0xFA, .vp_errgain = 0x23},
>>> +};
>>> +
>>> +static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
>>> +	{.volt_nominal = 930000, .sr_errminlimit = 0xF4, .vp_errgain = 0x0C},
>>> +	{.volt_nominal = 1100000, .sr_errminlimit = 0xF9, .vp_errgain = 0x16},
>>> +};
>>
>>As mentioned in previous reviews, the standard is to write hex value
>>using lower case letters.   Please fix this up in the both OMAP3 & 4 series.

Ok. Sorry for missing this.

>>
>>[...]
>>
>>> +/* Sets up all the VDD related info for OMAP4 */
>>> +static void __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
>>> +{
>>> +	struct clk *sys_ck;
>>> +	u32 sys_clk_speed, timeout_val, waittime;
>>> +
>>> +	if (!strcmp(vdd->voltdm.name, "mpu")) {
>>> +		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN;
>>> +		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX;
>>> +		vdd->volt_data = omap44xx_vdd_mpu_volt_data;
>>> +		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_mpu_volt_data);
>>> +		vdd->vp_reg.tranxdone_status =
>>> +				OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
>>> +		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
>>> +		vdd->vdd_sr_reg = OMAP4_VDD_MPU_SR_VOLT_REG;
>>> +	} else if (!strcmp(vdd->voltdm.name, "core")) {
>>> +		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN;
>>> +		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX;
>>> +		vdd->volt_data = omap44xx_vdd_core_volt_data;
>>> +		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_core_volt_data);
>>> +		vdd->vp_reg.tranxdone_status =
>>> +				OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
>>> +		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
>>> +		vdd->vdd_sr_reg = OMAP4_VDD_CORE_SR_VOLT_REG;
>>> +	} else if (!strcmp(vdd->voltdm.name, "iva")) {
>>> +		vdd->vp_reg.vlimitto_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN;
>>> +		vdd->vp_reg.vlimitto_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX;
>>> +		vdd->volt_data = omap44xx_vdd_iva_volt_data;
>>> +		vdd->volt_data_count = ARRAY_SIZE(omap44xx_vdd_iva_volt_data);
>>> +		vdd->vp_reg.tranxdone_status =
>>> +			OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
>>> +		vdd->cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
>>> +		vdd->vdd_sr_reg = OMAP4_VDD_IVA_SR_VOLT_REG;
>>> +	} else {
>>> +		pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
>>> +			__func__, vdd->voltdm.name);
>>> +		return;
>>> +	}
>>> +
>>> +	/*
>>> +	 * Sys clk rate is require to calculate vp timeout value and
>>> +	 * smpswaittimemin and smpswaittimemax.
>>> +	 */
>>> +	sys_ck = clk_get(NULL, "sys_clkin_ck");
>>> +	if (IS_ERR(sys_ck)) {
>>> +		pr_warning("%s: Could not get the sys clk to calculate"
>>> +			"various vdd_%s params\n", __func__, vdd->voltdm.name);
>>> +		return;
>>> +	}
>>> +	sys_clk_speed = clk_get_rate(sys_ck);
>>> +	clk_put(sys_ck);
>>> +
>>> +	/* Divide to avoid overflow */
>>> +	sys_clk_speed /= 1000;
>>> +
>>> +	/* Nominal/Reset voltage of the VDD */
>>> +	vdd->nominal_volt = vdd->curr_volt = 1200000;
>>
>>same comment as from  OMAP3 series.

Will take care

>>
>>[...]
>>
>>>  /* Generic voltage init functions */
>>>  static void __init init_voltageprocessor(struct omap_vdd_info *vdd)
>>>  {
>>> @@ -753,6 +945,14 @@ static int vp_forceupdate_scale_voltage(struct
>>omap_vdd_info *vdd,
>>>  		vc_cmd_on_mask = OMAP3430_VC_CMD_ON_MASK;
>>>  		prm_irqst_reg_offs = OMAP3_PRM_IRQSTATUS_MPU_OFFSET;
>>>  		ocp_mod = OCP_MOD;
>>> +	} else if (cpu_is_omap44xx()) {
>>> +		vc_cmd_on_shift = OMAP4430_ON_SHIFT;
>>> +		vc_cmd_on_mask = OMAP4430_ON_MASK;
>>> +		if (!strcmp(vdd->voltdm.name, "mpu"))
>>> +			prm_irqst_reg_offs = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
>>> +		else
>>> +			prm_irqst_reg_offs = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
>>> +		ocp_mod = OMAP4430_PRM_OCP_SOCKET_MOD;
>>
>>again, please no cpu_is_* outside of init functions.

I had a concern regarding this explained in my reply to your omap3 review.

[...]

Regards
Thara

RE: [PATCH v3 1/6] OMAP4: Add the new voltage to vsel calculation formula

[Gopinath, Thara]

>>-----Original Message-----
>>From: Tony Lindgren [mailto:tony@atomide.com]
>>Sent: Thursday, November 04, 2010 10:54 PM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; paul@pwsan.com; khilman@deeprootsystems.com;
>>Cousson, Benoit; Sripathy, Vishwanath; Sawant, Anand
>>Subject: Re: [PATCH v3 1/6] OMAP4: Add the new voltage to vsel calculation
>>formula
>>
>>* Thara Gopinath <thara@ti.com> [101027 09:07]:
>>> TWL6030 the power IC used along with OMAP4 in OMAP4 SDPs,
>>> blaze boards and panda boards has a different formula
>>> from that of TWL4030 for voltage to vsel and
>>> vsel to voltage calculation. This patch implements the new
>>> formula depending on the PMIC type.
>>>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>> ---
>>>  arch/arm/plat-omap/opp_twl_tps.c |   71
>>++++++++++++++++++++++++++++++++++++++
>>>  1 files changed, 71 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/plat-omap/opp_twl_tps.c b/arch/arm/plat-
>>omap/opp_twl_tps.c
>>> index 4448fc5..358b67b 100644
>>> --- a/arch/arm/plat-omap/opp_twl_tps.c
>>> +++ b/arch/arm/plat-omap/opp_twl_tps.c
>>> @@ -15,9 +15,16 @@
>>>
>>>  #include <linux/module.h>
>>>
>>> +#include <linux/i2c/twl.h>
>>> +
>>>  #include <plat/opp_twl_tps.h>
>>>  #include <plat/voltage.h>
>>>
>>> +static bool is_offset_valid;
>>> +static u8 smps_offset;
>>> +
>>> +#define REG_SMPS_OFFSET         0xE0
>>> +
>>>  /**
>>>   * omap_twl_vsel_to_vdc - convert TWL/TPS VSEL value to microvolts DC
>>>   * @vsel: TWL/TPS VSEL value to convert
>>> @@ -27,6 +34,38 @@
>>>   */
>>>  unsigned long omap_twl_vsel_to_uv(const u8 vsel)
>>>  {
>>> +	if (twl_class_is_6030()) {
>>> +		/*
>>> +		 * In TWL6030 depending on the value of SMPS_OFFSET
>>> +		 * efuse register the voltage range supported in
>>> +		 * standard mode can be either between 0.6V - 1.3V or
>>> +		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
>>> +		 * is programmed to all 0's where as starting from
>>> +		 * TWL6030 ES1.1 the efuse is programmed to 1
>>> +		 */
>>> +		if (!is_offset_valid) {
>>> +			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, 0xE0);
>>> +			is_offset_valid = true;
>>> +		}
>>> +
>>> +		if (smps_offset & 0x8) {
>>> +			return ((((vsel - 1) * 125) + 7000)) * 100;
>>> +		} else {
>>> +			/*
>>> +			 * In case of the supported voltage range being
>>> +			 * between 0.6V - 1.3V, there is not specific
>>> +			 * formula for voltage to vsel conversion above
>>> +			 * 1.3V. There are special hardcoded values for
>>> +			 * voltages above 1.3V. Currently we are hardcodig
>>> +			 * only for 1.35 V which is used for 1GH OPP for
>>> +			 * OMAP4430.
>>> +			 */
>>> +			if (vsel == 0x3A)
>>> +				return 1350000;
>>> +			return ((((vsel - 1) * 125) + 6000)) * 100;
>>> +		}
>>> +	}
>>> +
>>>  	return (((vsel * 125) + 6000)) * 100;
>>>  }
>>
>>Here too you will want to restructure things a bit so you can avoid
>>adding the "if twl_class_is_whatever else if" tests. Usually the best
>>way is to set separate functions for different chips during the init.
Hello Tony,

Thanks for the review.
There is another comment for this patch to drop this file all-together
and move this code to drivers/mfd/twl-core.c. Will take care of your
comment in the new location

Regards
Thara

RE: [PATCH v3 3/6] OMAP4: PM: Program correct init voltages for scalable VDDs

[Gopinath, Thara]

>>-----Original Message-----
>>From: Tony Lindgren [mailto:tony@atomide.com]
>>Sent: Thursday, November 04, 2010 10:50 PM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; paul@pwsan.com; khilman@deeprootsystems.com;
>>Cousson, Benoit; Sripathy, Vishwanath; Sawant, Anand
>>Subject: Re: [PATCH v3 3/6] OMAP4: PM: Program correct init voltages for
>>scalable VDDs
>>
>>Hi Thara,
>>
>>* Thara Gopinath <thara@ti.com> [101027 09:08]:
>>> By default the system boots up at nominal voltage for every
>>> voltage domain in the system. This patch puts vdd_mpu, vdd_iva
>>> and vdd_core to the correct boot up voltage as per the opp tables
>>> specified. This patch implements this by matching the rate of
>>> the main clock of the voltage domain with the opp table and
>>> picking up the correct voltage.
>>>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>> ---
>>>  arch/arm/mach-omap2/pm.c |    4 ++++
>>>  1 files changed, 4 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
>>> index 353e155..0651667 100644
>>> --- a/arch/arm/mach-omap2/pm.c
>>> +++ b/arch/arm/mach-omap2/pm.c
>>> @@ -211,6 +211,10 @@ static int __init omap2_common_pm_init(void)
>>>  	if (cpu_is_omap34xx()) {
>>>  		omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
>>>  		omap2_set_init_voltage("core", "l3_ick", l3_dev);
>>> +	} else if (cpu_is_omap44xx()) {
>>> +		omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
>>> +		omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
>>> +		omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
>>>  	}
>>>
>>>  	omap_pm_if_init();
>>
>>In general, we want to avoid adding these "if cpu_is_ompa34xx else if"
>>things all over the place. That makes the code hard to maintain and
>>requires patching all over the place to add support for new omaps.
>>
>>Instead, please do something like this:
>>
>>static int __init omap_common_whatever_init(struct whatever_data *d)
>>{
>>	...
>>
>>	return 0;
>>}
>>
>>static int __init omap3_whatever_init(void)
>>{
>>	struct whatever_data *d;
>>
>>	if (!cpu_is_omap34xx())
>>		return -ENODEV;
>>
>>	/* Initialize omap3 specific things */
>>	...
>>
>>	return omap_common_whatever_init(d);
>>}
>>device_initcall(omap3_whatever_init);
>>
>>static int __init omap4_whatever_init(void)
>>{
>>	struct whatever_data *d;
>>
>>	if (!cpu_is_omap44xx())
>>		return -ENODEV;
>>
>>	/* Initialize omap4 specific things */
>>	...
>>
>>	return omap_common_whatever_init(d);
>>}
>>device_initcall(omap4_whatever_init);
>>...
>>
>>This way the common code stays readable and does not need
>>to be patched when support for new omaps is added. Also the
>>code for unselected omaps gets optimized out and an extra
>>level of code indentation is left out.

Yes. Will take care of this in the next version

Regards
Thara