From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jarkko Nikula <jhnikula@gmail.com>
Subject: Re: [PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
Date: Wed, 16 Feb 2011 14:31:12 +0200
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To: "Gulati, Shweta" <shweta.gulati@ti.com>
Cc: linux-omap@vger.kernel.org, Thara Gopinath <thara@ti.com>, Nishanth Menon <nm@ti.com>, linux-arm-kernel@lists.infradead.org

On Wed, 16 Feb 2011 17:24:30 +0530
"Gulati, Shweta" <shweta.gulati@ti.com> wrote:

> > Note proof of concept patch only. I omitted the comments and don't do
> > explicit SR disable and I'd clean up the error paths in twl4030_power_init
> > a bit before this (e.g. printing error codes). Not sure either is the
> > twl4030-power.c right place for this or core.
> You missed commit log which says that "T2 bit is required to enable I2C_SR
> path of voltage control" it is not at all enabling SR, voltage scale
> APIs VPforceupdate/ VCbypass
> needs this path to be enabled.
> And calling APIs twl_i2c_read/write in driver codebase does n't ensure correct
> ordering of flag changes and twl_read/write.

Ah, yeah. I forgot to comment that I tried shortly also to run this
enable code from workqueue ~60 s after bootup and indeed SR didn't work
if those autocomp sysfs nodes were set before setting the TWL SR bit and
I believe same holds for voltage scaling too as you say.

What I'm thinking is there actually need for some higher level
control for these that quarantees the right order independently from
when each module are initialized.

-- 
Jarkko