[PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M]

Some of the omap2, omap3 peripherals support software reset. This
can be done through the softreset bit in sysconfig register.
The reset status can be checked through resetdone bit of
sysstatus register. syss_has_reset_status is added to the hwmod
database of peripherals which have resetdone bit in sysstatus register.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Reviewed-by: Govindraj.R <govindraj.raja@ti.com>
Signed-off-by: Avinash.H.M <avinashhm@ti.com>
---
The patch is based on linux-omap tree, master branch on commit:
e10eed954a2525c5d0b6dc361cdcbb46fea69d50

Testing:
build testing   : omap2plus_defconfig
boot testing    : 2420h4, 2430sdp.
[ boot test was done on omap-fixes-for-linus branch, commit
1232a185ddd500b61b8dc389ad1a357e6b425548 , since master branch wasn't booting
on 2420 and 2430 ].

pm testing      : tested core off in cpuidle patch in 3430sdp.
[ kevins 'i2c: OMAP: fix static suspend vs. runtime suspend' fix was needed to
have core off working. ]. core off works in cpuidle patch.

below configurations needed for core off in cpuidle:
echo 1 > /debug/pm_debug/sleep_while_idle
echo 1 > /debug/pm_debug/enable_off_mode
echo 5 > /sys/devices/platform/omap/omap_uart.0/sleep_timeout
echo 5 > /sys/devices/platform/omap/omap_uart.1/sleep_timeout
echo 5 > /sys/devices/platform/omap/omap_uart.2/sleep_timeout
echo enabled > /sys/devices/platform/omap/omap_uart.0/tty/ttyO0/power/wakeup
echo enabled > /sys/devices/platform/omap/omap_uart.1/tty/ttyO1/power/wakeup
echo enabled > /sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup

 arch/arm/mach-omap2/omap_hwmod_2420_data.c |   11 ++++++-----
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |   12 +++++++-----
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   13 ++++++++-----
 3 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b85c630..e8046b4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -308,7 +308,7 @@ static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
-			   SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
@@ -349,7 +349,7 @@ static struct omap_hwmod_class_sysconfig uart_sysc = {
 	.syss_offs	= 0x58,
 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-			   SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -475,7 +475,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 	.rev_offs	= 0x00,
 	.sysc_offs	= 0x20,
 	.syss_offs	= 0x10,
-	.sysc_flags	= SYSC_HAS_SOFTRESET,
+	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 
@@ -647,7 +647,8 @@ static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -789,7 +790,7 @@ static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
 	.syss_offs	= 0x0028,
 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
-			   SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 8ecfbcd..115eed5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -307,7 +307,7 @@ static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
-			   SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
@@ -348,7 +348,7 @@ static struct omap_hwmod_class_sysconfig uart_sysc = {
 	.syss_offs	= 0x58,
 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-			   SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -474,7 +474,8 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 	.rev_offs	= 0x00,
 	.sysc_offs	= 0x20,
 	.syss_offs	= 0x10,
-	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
 
@@ -672,7 +673,8 @@ static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -844,7 +846,7 @@ static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
 	.syss_offs	= 0x0028,
 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
-			   SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8d81813..acf0d54 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -447,7 +447,8 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-			   SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
+			   SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+			   SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -459,7 +460,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 	.syss_offs	= 0x10,
 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-			   SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -501,7 +502,7 @@ static struct omap_hwmod_class_sysconfig uart_sysc = {
 	.syss_offs	= 0x58,
 	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-			   SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -902,7 +903,8 @@ static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
 	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 	.sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -1156,7 +1158,8 @@ static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
 	.syss_offs	= 0x0028,
 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 			   SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
-			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
-- 
1.7.1

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Paul Walmsley]

On Thu, 24 Feb 2011, Avinash.H.M wrote:

> Some of the omap2, omap3 peripherals support software reset. This
> can be done through the softreset bit in sysconfig register.
> The reset status can be checked through resetdone bit of
> sysstatus register. syss_has_reset_status is added to the hwmod
> database of peripherals which have resetdone bit in sysstatus register.
> 
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Paul Walmsley <paul@pwsan.com>
> Cc: Benoit Cousson <b-cousson@ti.com>
> Cc: Kevin Hilman <khilman@ti.com>
> Reviewed-by: Govindraj.R <govindraj.raja@ti.com>
> Signed-off-by: Avinash.H.M <avinashhm@ti.com>

Thanks, queued for 2.6.39.


- Paul

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

On Thu, Mar 03, 2011 at 02:28:21PM -0700, Paul Walmsley wrote:
> On Thu, 24 Feb 2011, Avinash.H.M wrote:
> 
> > Some of the omap2, omap3 peripherals support software reset. This
> > can be done through the softreset bit in sysconfig register.
> > The reset status can be checked through resetdone bit of
> > sysstatus register. syss_has_reset_status is added to the hwmod
> > database of peripherals which have resetdone bit in sysstatus register.
> > 
> > Cc: Rajendra Nayak <rnayak@ti.com>
> > Cc: Paul Walmsley <paul@pwsan.com>
> > Cc: Benoit Cousson <b-cousson@ti.com>
> > Cc: Kevin Hilman <khilman@ti.com>
> > Reviewed-by: Govindraj.R <govindraj.raja@ti.com>
> > Signed-off-by: Avinash.H.M <avinashhm@ti.com>
> 
> Thanks, queued for 2.6.39.

Thanks very much Paul.

br
- avinash

> 
> 
> - Paul

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Paul Walmsley]

Hi Avinash,

> > On Thu, 24 Feb 2011, Avinash.H.M wrote:
> > 
> > > Some of the omap2, omap3 peripherals support software reset. This
> > > can be done through the softreset bit in sysconfig register.
> > > The reset status can be checked through resetdone bit of
> > > sysstatus register. syss_has_reset_status is added to the hwmod
> > > database of peripherals which have resetdone bit in sysstatus register.
> > > 
> > > Cc: Rajendra Nayak <rnayak@ti.com>
> > > Cc: Paul Walmsley <paul@pwsan.com>
> > > Cc: Benoit Cousson <b-cousson@ti.com>
> > > Cc: Kevin Hilman <khilman@ti.com>
> > > Reviewed-by: Govindraj.R <govindraj.raja@ti.com>
> > > Signed-off-by: Avinash.H.M <avinashhm@ti.com>

This patch is causing I2C softreset timeouts in the hwmod layer on OMAP2 
and 3.  Could you please take a look at this and figure out what is going 
on?

thanks,

- Paul

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

On Thu, Mar 24, 2011 at 11:38:15PM -0600, Paul Walmsley wrote:
> Hi Avinash,

Hi Paul, 

> 
> > > On Thu, 24 Feb 2011, Avinash.H.M wrote:
> > > 
> > > > Some of the omap2, omap3 peripherals support software reset. This
> > > > can be done through the softreset bit in sysconfig register.
> > > > The reset status can be checked through resetdone bit of
> > > > sysstatus register. syss_has_reset_status is added to the hwmod
> > > > database of peripherals which have resetdone bit in sysstatus register.
> > > > 
> > > > Cc: Rajendra Nayak <rnayak@ti.com>
> > > > Cc: Paul Walmsley <paul@pwsan.com>
> > > > Cc: Benoit Cousson <b-cousson@ti.com>
> > > > Cc: Kevin Hilman <khilman@ti.com>
> > > > Reviewed-by: Govindraj.R <govindraj.raja@ti.com>
> > > > Signed-off-by: Avinash.H.M <avinashhm@ti.com>
> 
> This patch is causing I2C softreset timeouts in the hwmod layer on OMAP2 
> and 3.  Could you please take a look at this and figure out what is going 
> on?

I ll start looking at this. I have a 3430 ES3.1 SDP, where i will check the
difference in behaviour with this patch. 

BTW, is there a test case which i should run to produce 'I2C softreset
timeouts' ? Can you give more information on how to reproduce the issue
?.

br,

- avinash

> 
> thanks,
> 
> - Paul

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

On Fri, Mar 25, 2011 at 11:56:34AM +0530, Avinash.H.M. wrote:
> On Thu, Mar 24, 2011 at 11:38:15PM -0600, Paul Walmsley wrote:

[snip]

> This patch is causing I2C softreset timeouts in the hwmod layer on OMAP2 
> > and 3.  Could you please take a look at this and figure out what is going 
> > on?
> 
> I ll start looking at this. I have a 3430 ES3.1 SDP, where i will check the
> difference in behaviour with this patch. 
> 
> BTW, is there a test case which i should run to produce 'I2C softreset
> timeouts' ? Can you give more information on how to reproduce the issue
> ?.

Hi paul, 

I am able to reproduce the issue. I am seeing the timeout prints for
i2c, gpio during bootup. I ll check why softreset is failing.

[    0.208892] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
[    0.223114] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
[    0.237335] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
[    0.251525] omap_hwmod: gpio2: softreset failed (waited 10000 usec)
[    0.265594] omap_hwmod: gpio3: softreset failed (waited 10000 usec)
[    0.279693] omap_hwmod: gpio4: softreset failed (waited 10000 usec)
[    0.293762] omap_hwmod: gpio5: softreset failed (waited 10000 usec)
[    0.307861] omap_hwmod: gpio6: softreset failed (waited 10000 usec)

br,

- avinash

> 

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Cousson, Benoit]

Hi Paul,

On 3/25/2011 6:38 AM, Paul Walmsley wrote:
> Hi Avinash,
>
>>> On Thu, 24 Feb 2011, Avinash.H.M wrote:
>>>
>>>> Some of the omap2, omap3 peripherals support software reset. This
>>>> can be done through the softreset bit in sysconfig register.
>>>> The reset status can be checked through resetdone bit of
>>>> sysstatus register. syss_has_reset_status is added to the hwmod
>>>> database of peripherals which have resetdone bit in sysstatus register.
>>>>
>>>> Cc: Rajendra Nayak<rnayak@ti.com>
>>>> Cc: Paul Walmsley<paul@pwsan.com>
>>>> Cc: Benoit Cousson<b-cousson@ti.com>
>>>> Cc: Kevin Hilman<khilman@ti.com>
>>>> Reviewed-by: Govindraj.R<govindraj.raja@ti.com>
>>>> Signed-off-by: Avinash.H.M<avinashhm@ti.com>
>
> This patch is causing I2C softreset timeouts in the hwmod layer on OMAP2
> and 3.  Could you please take a look at this and figure out what is going
> on?

I think this is probably due to the nasty I2C softreset bug with 
discussed last year with Paul Brady.

AFAIR, the I2C cannot be reset by just writing to the SYSCONFIG 
softreset bit. You need to play with other registers too.

Avinash,
You should try to look at 3430 or 3630 errata. You will probably find 
the bug I'm referring to.


Benoit

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 1544 bytes --]

Hi,

On Fri, 25 Mar 2011, Cousson, Benoit wrote:

> On 3/25/2011 6:38 AM, Paul Walmsley wrote:
> > > > On Thu, 24 Feb 2011, Avinash.H.M wrote:
> > > > > Some of the omap2, omap3 peripherals support software reset. This
> > > > > can be done through the softreset bit in sysconfig register.
> > > > > The reset status can be checked through resetdone bit of
> > > > > sysstatus register. syss_has_reset_status is added to the hwmod
> > > > > database of peripherals which have resetdone bit in sysstatus
> > > > > register.
> > > > > 
> > > > > Cc: Rajendra Nayak<rnayak@ti.com>
> > > > > Cc: Paul Walmsley<paul@pwsan.com>
> > > > > Cc: Benoit Cousson<b-cousson@ti.com>
> > > > > Cc: Kevin Hilman<khilman@ti.com>
> > > > > Reviewed-by: Govindraj.R<govindraj.raja@ti.com>
> > > > > Signed-off-by: Avinash.H.M<avinashhm@ti.com>
> > 
> > This patch is causing I2C softreset timeouts in the hwmod layer on OMAP2
> > and 3.  Could you please take a look at this and figure out what is going
> > on?
> 
> I think this is probably due to the nasty I2C softreset bug with discussed
> last year with Paul Brady.
> 
> AFAIR, the I2C cannot be reset by just writing to the SYSCONFIG softreset bit.
> You need to play with other registers too.

Thanks Benoît.

So then, Avinash, you might need to create a custom hwmod class 
reset function for the I2C block (viz., struct omap_hwmod_class.reset)

> Avinash,
> You should try to look at 3430 or 3630 errata. You will probably find the bug
> I'm referring to.


- Paul

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Paul Walmsley]

On Fri, 25 Mar 2011, Avinash.H.M. wrote:

> On Fri, Mar 25, 2011 at 11:56:34AM +0530, Avinash.H.M. wrote:
> 
> I am able to reproduce the issue. I am seeing the timeout prints for
> i2c, gpio during bootup. I ll check why softreset is failing.
> 
> [    0.208892] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
> [    0.223114] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
> [    0.237335] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
> [    0.251525] omap_hwmod: gpio2: softreset failed (waited 10000 usec)
> [    0.265594] omap_hwmod: gpio3: softreset failed (waited 10000 usec)
> [    0.279693] omap_hwmod: gpio4: softreset failed (waited 10000 usec)
> [    0.293762] omap_hwmod: gpio5: softreset failed (waited 10000 usec)
> [    0.307861] omap_hwmod: gpio6: softreset failed (waited 10000 usec)

Just FYI, I don't see the gpio softreset failures on my boards here.


- Paul

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

On Fri, Mar 25, 2011 at 11:23:38AM -0600, Paul Walmsley wrote:
> Hi,
> 
> On Fri, 25 Mar 2011, Cousson, Benoit wrote:
> 
> > On 3/25/2011 6:38 AM, Paul Walmsley wrote:
> > > > > On Thu, 24 Feb 2011, Avinash.H.M wrote:
> > > > > > Some of the omap2, omap3 peripherals support software reset. This
> > > > > > can be done through the softreset bit in sysconfig register.
> > > > > > The reset status can be checked through resetdone bit of
> > > > > > sysstatus register. syss_has_reset_status is added to the hwmod
> > > > > > database of peripherals which have resetdone bit in sysstatus
> > > > > > register.
> > > > > > 
> > > > > > Cc: Rajendra Nayak<rnayak@ti.com>
> > > > > > Cc: Paul Walmsley<paul@pwsan.com>
> > > > > > Cc: Benoit Cousson<b-cousson@ti.com>
> > > > > > Cc: Kevin Hilman<khilman@ti.com>
> > > > > > Reviewed-by: Govindraj.R<govindraj.raja@ti.com>
> > > > > > Signed-off-by: Avinash.H.M<avinashhm@ti.com>
> > > 
> > > This patch is causing I2C softreset timeouts in the hwmod layer on OMAP2
> > > and 3.  Could you please take a look at this and figure out what is going
> > > on?
> > 
> > I think this is probably due to the nasty I2C softreset bug with discussed
> > last year with Paul Brady.
> > 
> > AFAIR, the I2C cannot be reset by just writing to the SYSCONFIG softreset bit.
> > You need to play with other registers too.

Thanks Benoit. You are right. 

The TRM Section '18.3.1.3.2 Software Reset' explains the steps for
softresetting I2C. The steps are below:

1. Ensure that the module is disabled (clear the I2Ci.I2C_CON[15] I2C_EN
bit to 0).
2. Set the I2Ci.I2C_SYSC[1] SRST bit to 1.
3. Enable the module by setting I2Ci.I2C_CON[15] I2C_EN bit to 1.
4. Check the I2Ci.I2C_SYSS[0] RDONE bit until it is set to 1 to indicate
the software reset is complete.

> 
> Thanks Benoît.
> 
> So then, Avinash, you might need to create a custom hwmod class 
> reset function for the I2C block (viz., struct omap_hwmod_class.reset)

OK Paul. I'll add the I2C_CON register and follow the above sequence as
suggested in the TRM in the custom I2C reset function.

br,

- Avinash

> 
> > Avinash,
> > You should try to look at 3430 or 3630 errata. You will probably find the bug
> > I'm referring to.
> 
> 
> - Paul

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Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

On Fri, Mar 25, 2011 at 11:24:31AM -0600, Paul Walmsley wrote:
> On Fri, 25 Mar 2011, Avinash.H.M. wrote:
> 
> > On Fri, Mar 25, 2011 at 11:56:34AM +0530, Avinash.H.M. wrote:
> > 
> > I am able to reproduce the issue. I am seeing the timeout prints for
> > i2c, gpio during bootup. I ll check why softreset is failing.
> > 
> > [    0.208892] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
> > [    0.223114] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
> > [    0.237335] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
> > [    0.251525] omap_hwmod: gpio2: softreset failed (waited 10000 usec)
> > [    0.265594] omap_hwmod: gpio3: softreset failed (waited 10000 usec)
> > [    0.279693] omap_hwmod: gpio4: softreset failed (waited 10000 usec)
> > [    0.293762] omap_hwmod: gpio5: softreset failed (waited 10000 usec)
> > [    0.307861] omap_hwmod: gpio6: softreset failed (waited 10000 usec)
> 
> Just FYI, I don't see the gpio softreset failures on my boards here.
> 

Hi Paul,

Which boards are you testing? 

To be doubly sure, i ll confirm if the issue is board specific or not,
by testing on another 3430 sdp.

- Avinash

> 
> - Paul

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Paul Walmsley]

On Sat, 26 Mar 2011, Avinash.H.M. wrote:

> Which boards are you testing? 

GPIO softreset warnings don't show up on either N800 or BeagleBoard 35xx 
as of commit 4047185.


- Paul

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

> Thanks Benoit. You are right. 
> 
> The TRM Section '18.3.1.3.2 Software Reset' explains the steps for
> softresetting I2C. The steps are below:
> 
> 1. Ensure that the module is disabled (clear the I2Ci.I2C_CON[15] I2C_EN
> bit to 0).
> 2. Set the I2Ci.I2C_SYSC[1] SRST bit to 1.
> 3. Enable the module by setting I2Ci.I2C_CON[15] I2C_EN bit to 1.
> 4. Check the I2Ci.I2C_SYSS[0] RDONE bit until it is set to 1 to indicate
> the software reset is complete.

Hi paul, 

I have been able to implement the function. It took a while because,
even after implementing the above sequence, i was seeing the I2C wasn't
resetting. 

The issue turned out that i was doing '32 bit data access' which was
corrupting the i2c register contents. I missed the TRM section where it
tells, "i2c registers are limited to 8-bit or 16-bit access". Special
thanks to balaji.t.k for helping me debug this and pointing this was the
issue. On correcting this, the function worked cleanly and i2c was
reset.

I ll send out the patch tomorrow.

br ,
- avinash

> 
> > 
> > Thanks Benoît.
> > 
> > So then, Avinash, you might need to create a custom hwmod class 
> > reset function for the I2C block (viz., struct omap_hwmod_class.reset)
> 
> OK Paul. I'll add the I2C_CON register and follow the above sequence as
> suggested in the TRM in the custom I2C reset function.
> 
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Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

> > > [    0.208892] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
> > > [    0.223114] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
> > > [    0.237335] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
> > > [    0.251525] omap_hwmod: gpio2: softreset failed (waited 10000 usec)
> > > [    0.265594] omap_hwmod: gpio3: softreset failed (waited 10000 usec)
> > > [    0.279693] omap_hwmod: gpio4: softreset failed (waited 10000 usec)
> > > [    0.293762] omap_hwmod: gpio5: softreset failed (waited 10000 usec)
> > > [    0.307861] omap_hwmod: gpio6: softreset failed (waited 10000 usec)

Hi Paul, 

I tested this on one more board and still got these softreset warnings.
So this wasn't a board specific issue and debugged into what is causing
these.

The problem is the FCLK isn't enabled for these gpios(2..6) while
resetting.  So the GPIO's are not resetting properly. Once i enable FCLK
for them and then set the SYSCONFIG.SOFTRESET, then they are resetting
and it is reflected in RESETDONE bit.

That being said, I was looking for accessing gpio2_fck in the
gpio2_hwmod. But i find the structure as below, 

static struct omap_hwmod omap3xxx_gpio2_hwmod = {
	.name		= "gpio2",
	.mpu_irqs	= omap3xxx_gpio2_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap3xxx_gpio2_irqs),
	.main_clk	= "gpio2_ick",

Is there any reason, why 'iclk' is set as the 'main_clk' and not 'fclk'.
Also 'fclk' is structured as 'gpio2_dbck' and made as an optional clock.
I wasn't very sure, why the name 'dbck'? 

> > 
> > Just FYI, I don't see the gpio softreset failures on my boards here.

Most likely you aren't seeing this in N800 and beagle because the
bootloader may be enabling the clocks.

I am sorry if the above question seems silly. I am fairly new to this
frameworks and hence the question :-). Please clarify.

br ,
- avinash


 

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Kevin Hilman]

"Avinash.H.M." <avinashhm@ti.com> writes:

>> > > [    0.208892] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
>> > > [    0.223114] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
>> > > [    0.237335] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
>> > > [    0.251525] omap_hwmod: gpio2: softreset failed (waited 10000 usec)
>> > > [    0.265594] omap_hwmod: gpio3: softreset failed (waited 10000 usec)
>> > > [    0.279693] omap_hwmod: gpio4: softreset failed (waited 10000 usec)
>> > > [    0.293762] omap_hwmod: gpio5: softreset failed (waited 10000 usec)
>> > > [    0.307861] omap_hwmod: gpio6: softreset failed (waited 10000 usec)
>
> Hi Paul, 
>
> I tested this on one more board and still got these softreset warnings.
> So this wasn't a board specific issue and debugged into what is causing
> these.
>
> The problem is the FCLK isn't enabled for these gpios(2..6) while
> resetting.  So the GPIO's are not resetting properly. Once i enable FCLK
> for them and then set the SYSCONFIG.SOFTRESET, then they are resetting
> and it is reflected in RESETDONE bit.

What do you mean by fclk here.  GPIO doesn't have an fclk.  The
interface clock provides the functional clock, and the optional debounce
clock (dbclk) is needed only when GPIO debounce is enabled.

I suggest you look at the "integration" sub chapter of the TRM for the
GPIO module.

> That being said, I was looking for accessing gpio2_fck in the
> gpio2_hwmod. But i find the structure as below, 
>
> static struct omap_hwmod omap3xxx_gpio2_hwmod = {
> 	.name		= "gpio2",
> 	.mpu_irqs	= omap3xxx_gpio2_irqs,
> 	.mpu_irqs_cnt	= ARRAY_SIZE(omap3xxx_gpio2_irqs),
> 	.main_clk	= "gpio2_ick",
>
> Is there any reason, why 'iclk' is set as the 'main_clk' and not 'fclk'.

There are no GPIO fclks.

> Also 'fclk' is structured as 'gpio2_dbck' and made as an optional
> clock.  I wasn't very sure, why the name 'dbck'?

dbck == debounce clock

Kevin

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

> > The problem is the FCLK isn't enabled for these gpios(2..6) while
> > resetting.  So the GPIO's are not resetting properly. Once i enable FCLK
> > for them and then set the SYSCONFIG.SOFTRESET, then they are resetting
> > and it is reflected in RESETDONE bit.
> 
> What do you mean by fclk here.  GPIO doesn't have an fclk.  The
> interface clock provides the functional clock, and the optional debounce
> clock (dbclk) is needed only when GPIO debounce is enabled.
> 
> I suggest you look at the "integration" sub chapter of the TRM for the
> GPIO module.

Hi Kevin , 

I looked at this section. Now i am clear about the code. I meant fclk as
functional clocks which is described by register CM_FCLKEN_PER, bit 12
to bit 17. These bits are described as they control 'GPIO x functional
clock'.

Looking at the GPIO chapter, i understood that this is same as the gpio
dbck. This was confirmed by section 'PER Power Domain Clock Controls'
where he says CM_FCLKEN_PER[12-17] control PER_32K_ALWON_FCLK which is
routed as GPIOx_DBCLK.

[...]

> 
> There are no GPIO fclks.
> 
> > Also 'fclk' is structured as 'gpio2_dbck' and made as an optional
> > clock.  I wasn't very sure, why the name 'dbck'?
> 
> dbck == debounce clock

I got it. Thanks for the clarification. 

Looks like without this clock, GPIO module isn't resetting even on
writing to SYSCONFIG register. Should we provide a seperate reset
function for gpio, like the way it was suggested for i2c ?

br ,
- Avinash

> 
> Kevin

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Cousson, Benoit]

On 3/31/2011 5:51 PM, Mahadeva, Avinash wrote:
>>> The problem is the FCLK isn't enabled for these gpios(2..6) while
>>> resetting.  So the GPIO's are not resetting properly. Once i enable FCLK
>>> for them and then set the SYSCONFIG.SOFTRESET, then they are resetting
>>> and it is reflected in RESETDONE bit.
>>
>> What do you mean by fclk here.  GPIO doesn't have an fclk.  The
>> interface clock provides the functional clock, and the optional debounce
>> clock (dbclk) is needed only when GPIO debounce is enabled.
>>
>> I suggest you look at the "integration" sub chapter of the TRM for the
>> GPIO module.
>
> Hi Kevin ,
>
> I looked at this section. Now i am clear about the code. I meant fclk as
> functional clocks which is described by register CM_FCLKEN_PER, bit 12
> to bit 17. These bits are described as they control 'GPIO x functional
> clock'.
>
> Looking at the GPIO chapter, i understood that this is same as the gpio
> dbck. This was confirmed by section 'PER Power Domain Clock Controls'
> where he says CM_FCLKEN_PER[12-17] control PER_32K_ALWON_FCLK which is
> routed as GPIOx_DBCLK.
>
> [...]
>
>>
>> There are no GPIO fclks.
>>
>>> Also 'fclk' is structured as 'gpio2_dbck' and made as an optional
>>> clock.  I wasn't very sure, why the name 'dbck'?
>>
>> dbck == debounce clock
>
> I got it. Thanks for the clarification.
>
> Looks like without this clock, GPIO module isn't resetting even on
> writing to SYSCONFIG register. Should we provide a seperate reset
> function for gpio, like the way it was suggested for i2c ?

No need for that, it is already working like that on OMAP4.
We have a nice flag that handle that clock during reset.

	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,

Regards,
Benoit

Re: [PATCH] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods

[Avinash.H.M.]

> >Looks like without this clock, GPIO module isn't resetting even on
> >writing to SYSCONFIG register. Should we provide a seperate reset
> >function for gpio, like the way it was suggested for i2c ?
> 
> No need for that, it is already working like that on OMAP4.
> We have a nice flag that handle that clock during reset.
> 
> 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,

Thanks benoit. I'll use this flag and try resetting GPIO module.

br ,
- avinash

> 
> Regards,
> Benoit
> 
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