[PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[Benoit Cousson]

Hi Paul,

Here is the second part of the modulemode series. 
The goal here is to do the cleanup on the clock nodes and PRCM macros
that are not needed anymore by the hwmod data.
Some macros are still needed because of clock data. It should be removed
once the clock data will be cleaned.

Moreover, in order to get rid of static clkdev, omap_device is trying to
create dynamically an "fck" alias if a main_clk is defined in hwmod data.

As usual, because of drivers non-adapted to pm_runtime, some temp hacks
are needed for both MMC and timer1.
If the drivers are fixes before these series, these temp patches could be
dropped.

The series is based on for_3.0.1/5_hwmod_clkdm_fixes and tested
on OMAP4430 ES2.1 + SDP. It should not affect OMAP2 & 3, but some testing
are definitively needed.

The patches are available here:
git://gitorious.org/omap-pm/linux.git for_3.0.1/6_hwmod_modulemode

Regards,
Benoit


Benoit Cousson (7):
  OMAP: hwmod: Add warnings if enable failed
  OMAP: omap_device: Create clkdev entry for hwmod main_clk
  OMAP4: hwmod data: TEMP: Do not idle MMC1 & MMC2 after boot
  OMAP4: hwmod data: Replace main_clk with the real input clock
  OMAP4: clock data: Remove leaf clock nodes
  OMAP4: hwmod data: TEMP: Fix timer1 main_clk
  OMAP4: prcm: Remove macros with absolute address

 arch/arm/mach-omap2/clock44xx_data.c       | 1730 ++++++++--------------------
 arch/arm/mach-omap2/cm1_44xx.h             |   24 -
 arch/arm/mach-omap2/cm2_44xx.h             |   55 -
 arch/arm/mach-omap2/omap_hwmod.c           |    2 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  111 +-
 arch/arm/mach-omap2/prm44xx.h              |  269 -----
 arch/arm/plat-omap/omap_device.c           |   84 +-
 7 files changed, 610 insertions(+), 1665 deletions(-)

[PATCH 1/7] OMAP: hwmod: Add warnings if enable failed

[Benoit Cousson]

Change the debug into warning to check what IPs are failing.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 3538805..51a13f3 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1023,6 +1023,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
 
 	if (!ret)
 		oh->_state = _HWMOD_STATE_CLKS_INITED;
+	else
+		pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
 
 	return ret;
 }
-- 
1.7.0.4

[PATCH 2/7] OMAP: omap_device: Create clkdev entry for hwmod main_clk

[Benoit Cousson]

Extend the existing function to create clkdev for every optional
clocks to add a well one "fck" alias for the main_clk of the
omap_hwmod.
It will allow to remove these static clkdev entries from the
clockXXX_data.c file.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/plat-omap/omap_device.c |   84 ++++++++++++++++++++++----------------
 1 files changed, 49 insertions(+), 35 deletions(-)

diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 49fc0df..8a854a3 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -241,56 +241,70 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
 	return container_of(pdev, struct omap_device, pdev);
 }
 
+static void _add_clkdev(struct omap_device *od, const char *clk_alias,
+		       const char *clk_name)
+{
+	struct clk *r;
+	struct clk_lookup *l;
+
+	if (!clk_alias || !clk_name)
+		return;
+
+	pr_debug("omap_device: %s: Creating %s -> %s\n",
+		 dev_name(&od->pdev.dev), clk_alias, clk_name);
+
+	r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
+	if (!IS_ERR(r)) {
+		pr_warning("omap_device: %s: %s already exist\n",
+			   dev_name(&od->pdev.dev), clk_alias);
+		return;
+	}
+
+	r = omap_clk_get_by_name(clk_name);
+	if (IS_ERR(r)) {
+		pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
+		       dev_name(&od->pdev.dev), clk_name);
+		return;
+	}
+
+	l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
+	if (!l) {
+		pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
+		       dev_name(&od->pdev.dev), clk_alias);
+		return;
+	}
+
+	clkdev_add(l);
+}
+
 /**
- * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
+ * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks
+ * and main clock
  * @od: struct omap_device *od
+ * @oh: struct omap_hwmod *oh
  *
- * For every optional clock present per hwmod per omap_device, this function
- * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
- * if it does not exist already.
+ * For the main clock and every optional clock present per hwmod per
+ * omap_device, this function adds an entry in the clkdev table of the
+ * form <dev-id=dev_name, con-id=role> if it does not exist already.
  *
  * The function is called from inside omap_device_build_ss(), after
  * omap_device_register.
  *
  * This allows drivers to get a pointer to its optional clocks based on its role
  * by calling clk_get(<dev*>, <role>).
+ * In the case of the main clock, a "fck" alias is used.
  *
  * No return value.
  */
-static void _add_optional_clock_clkdev(struct omap_device *od,
-				      struct omap_hwmod *oh)
+static void _add_hwmod_clocks_clkdev(struct omap_device *od,
+				     struct omap_hwmod *oh)
 {
 	int i;
 
-	for (i = 0; i < oh->opt_clks_cnt; i++) {
-		struct omap_hwmod_opt_clk *oc;
-		struct clk *r;
-		struct clk_lookup *l;
-
-		oc = &oh->opt_clks[i];
-
-		if (!oc->_clk)
-			continue;
-
-		r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
-		if (!IS_ERR(r))
-			continue; /* clkdev entry exists */
+	_add_clkdev(od, "fck", oh->main_clk);
 
-		r = omap_clk_get_by_name((char *)oc->clk);
-		if (IS_ERR(r)) {
-			pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
-			       dev_name(&od->pdev.dev), oc->clk);
-			continue;
-		}
-
-		l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
-		if (!l) {
-			pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
-			       dev_name(&od->pdev.dev), oc->role);
-			return;
-		}
-		clkdev_add(l);
-	}
+	for (i = 0; i < oh->opt_clks_cnt; i++)
+		_add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
 }
 
 
@@ -497,7 +511,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
 
 	for (i = 0; i < oh_cnt; i++) {
 		hwmods[i]->od = od;
-		_add_optional_clock_clkdev(od, hwmods[i]);
+		_add_hwmod_clocks_clkdev(od, hwmods[i]);
 	}
 
 	if (ret)
-- 
1.7.0.4

Re: [PATCH 2/7] OMAP: omap_device: Create clkdev entry for hwmod main_clk

[Todd Poynor]

On Mon, Jun 27, 2011 at 06:33:06PM +0200, Benoit Cousson wrote:
...
> +	r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
> +	if (!IS_ERR(r)) {
> +		pr_warning("omap_device: %s: %s already exist\n",
> +			   dev_name(&od->pdev.dev), clk_alias);

I believe a clk_put(r) is appropriate here.

> +		return;
> +	}
> +
> +	r = omap_clk_get_by_name(clk_name);
> +	if (IS_ERR(r)) {
> +		pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
> +		       dev_name(&od->pdev.dev), clk_name);
> +		return;
> +	}
> +
> +	l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
> +	if (!l) {
> +		pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
> +		       dev_name(&od->pdev.dev), clk_alias);

And here.

> +		return;
> +	}
> +
> +	clkdev_add(l);

And here.


Todd

Re: [PATCH 2/7] OMAP: omap_device: Create clkdev entry for hwmod main_clk

[Cousson, Benoit]

On 6/27/2011 8:56 PM, Todd Poynor wrote:
> On Mon, Jun 27, 2011 at 06:33:06PM +0200, Benoit Cousson wrote:
> ...
>> +	r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
>> +	if (!IS_ERR(r)) {
>> +		pr_warning("omap_device: %s: %s already exist\n",
>> +			   dev_name(&od->pdev.dev), clk_alias);
>
> I believe a clk_put(r) is appropriate here.

Appropriate I don't know, but useless for sure :-)
This clk_put is a no-op for every ARM platforms (I found one exception).

I do not know why it was originally done like that, but that api is 
clearly not a put/get kind of API.

I'm OK to add that, but I think it is a little bit misleading.

>
>> +		return;
>> +	}
>> +
>> +	r = omap_clk_get_by_name(clk_name);
>> +	if (IS_ERR(r)) {
>> +		pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
>> +		       dev_name(&od->pdev.dev), clk_name);
>> +		return;
>> +	}
>> +
>> +	l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
>> +	if (!l) {
>> +		pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
>> +		       dev_name(&od->pdev.dev), clk_alias);
>
> And here.

No, it is not needed in that case because the omap_clk_get_by_name is 
not using the clk_get API.

>
>> +		return;
>> +	}
>> +
>> +	clkdev_add(l);
>
> And here.

Not needed either, no clk_get used.

Benoit

Re: [PATCH 2/7] OMAP: omap_device: Create clkdev entry for hwmod main_clk

[Todd Poynor]

On Tue, Jun 28, 2011 at 04:10:55PM +0200, Cousson, Benoit wrote:
> On 6/27/2011 8:56 PM, Todd Poynor wrote:
> >On Mon, Jun 27, 2011 at 06:33:06PM +0200, Benoit Cousson wrote:
> >...
> >>+	r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
> >>+	if (!IS_ERR(r)) {
> >>+		pr_warning("omap_device: %s: %s already exist\n",
> >>+			   dev_name(&od->pdev.dev), clk_alias);
> >
> >I believe a clk_put(r) is appropriate here.
> 
> Appropriate I don't know, but useless for sure :-)
> This clk_put is a no-op for every ARM platforms (I found one exception).

I haven't followed the design of common struct clk closely, but it
probably will do ref counting on these, so it's best to keep these
matched up.

> >>+	r = omap_clk_get_by_name(clk_name);
> >>+	if (IS_ERR(r)) {
> >>+		pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
> >>+		       dev_name(&od->pdev.dev), clk_name);
> >>+		return;
> >>+	}
> >>+
> >>+	l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
> >>+	if (!l) {
> >>+		pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
> >>+		       dev_name(&od->pdev.dev), clk_alias);
> >
> >And here.
> 
> No, it is not needed in that case because the omap_clk_get_by_name
> is not using the clk_get API.

Ah, didn't check that one, sorry.  That's an unfortunate use of "get"
in the API name IMO.  When common struct clk takes over, this may need
some tweaking.


Todd

Re: [PATCH 2/7] OMAP: omap_device: Create clkdev entry for hwmod main_clk

[Cousson, Benoit]

On 6/28/2011 8:21 PM, Todd Poynor wrote:
> On Tue, Jun 28, 2011 at 04:10:55PM +0200, Cousson, Benoit wrote:
>> On 6/27/2011 8:56 PM, Todd Poynor wrote:
>>> On Mon, Jun 27, 2011 at 06:33:06PM +0200, Benoit Cousson wrote:
>>> ...
>>>> +	r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
>>>> +	if (!IS_ERR(r)) {
>>>> +		pr_warning("omap_device: %s: %s already exist\n",
>>>> +			   dev_name(&od->pdev.dev), clk_alias);
>>>
>>> I believe a clk_put(r) is appropriate here.
>>
>> Appropriate I don't know, but useless for sure :-)
>> This clk_put is a no-op for every ARM platforms (I found one exception).
>
> I haven't followed the design of common struct clk closely, but it
> probably will do ref counting on these, so it's best to keep these
> matched up.

I didn't follow the design either, but it was posted in 2008, and still 
nobody is doing any reference counting...

That being said we can expect the common clock fmwk to use that and even 
Paul might want to do some stuff with that.

Let's start using it.

>
>>>> +	r = omap_clk_get_by_name(clk_name);
>>>> +	if (IS_ERR(r)) {
>>>> +		pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
>>>> +		       dev_name(&od->pdev.dev), clk_name);
>>>> +		return;
>>>> +	}
>>>> +
>>>> +	l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
>>>> +	if (!l) {
>>>> +		pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
>>>> +		       dev_name(&od->pdev.dev), clk_alias);
>>>
>>> And here.
>>
>> No, it is not needed in that case because the omap_clk_get_by_name
>> is not using the clk_get API.
>
> Ah, didn't check that one, sorry.  That's an unfortunate use of "get"
> in the API name IMO.  When common struct clk takes over, this may need
> some tweaking.

Yep, I do agree.

Benoit

[PATCH 3/7] OMAP4: hwmod data: TEMP: Do not idle MMC1 & MMC2 after boot

[Benoit Cousson]

Since the MMC driver is not pm_runtime adapted, do not put
them in idle after boot.
It will allow the driver to work as expected until the migration
to pm_runtime.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 850ac39..e10d3f7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -3658,6 +3658,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
 	.name		= "mmc1",
 	.class		= &omap44xx_mmc_hwmod_class,
 	.clkdm_name	= "l3_init_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 	.mpu_irqs	= omap44xx_mmc1_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mmc1_irqs),
 	.sdma_reqs	= omap44xx_mmc1_sdma_reqs,
@@ -3720,6 +3721,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
 	.name		= "mmc2",
 	.class		= &omap44xx_mmc_hwmod_class,
 	.clkdm_name	= "l3_init_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 	.mpu_irqs	= omap44xx_mmc2_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mmc2_irqs),
 	.sdma_reqs	= omap44xx_mmc2_sdma_reqs,
-- 
1.7.0.4

Re: [PATCH 3/7] OMAP4: hwmod data: TEMP: Do not idle MMC1 & MMC2 after boot

[Kevin Hilman]

Benoit Cousson <b-cousson@ti.com> writes:

> Since the MMC driver is not pm_runtime adapted, do not put
> them in idle after boot.
> It will allow the driver to work as expected until the migration
> to pm_runtime.
>
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> Cc: Paul Walmsley <paul@pwsan.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)

Similar is needed for OMAP3 as well to boot this series.

Kevin




diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/om
index dec1a38..aaa3201 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3500,6 +3500,7 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
        .class          = &omap34xx_mmc_class,
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+       .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 };
 
 /* MMC/SD/SDIO2 */
@@ -3543,6 +3544,7 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
        .class          = &omap34xx_mmc_class,
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+       .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 };
 

Re: [PATCH 3/7] OMAP4: hwmod data: TEMP: Do not idle MMC1 & MMC2 after boot

[Cousson, Benoit]

On 6/28/2011 2:17 AM, Hilman, Kevin wrote:
> Benoit Cousson<b-cousson@ti.com>  writes:
>
>> Since the MMC driver is not pm_runtime adapted, do not put
>> them in idle after boot.
>> It will allow the driver to work as expected until the migration
>> to pm_runtime.
>>
>> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
>> Cc: Paul Walmsley<paul@pwsan.com>
>> Cc: Rajendra Nayak<rnayak@ti.com>
>> ---
>>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    2 ++
>>   1 files changed, 2 insertions(+), 0 deletions(-)
>
> Similar is needed for OMAP3 as well to boot this series.

I'm still hoping to base that on top of the MMC pm_runtime series Balaji 
did to avoid all these hacks that Russell did not like:-)

Thanks for the test and fix. I'll update the series with your patch.

Benoit


>
> Kevin
>
>
>
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/om
> index dec1a38..aaa3201 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
> @@ -3500,6 +3500,7 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
>          .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
>          .class          =&omap34xx_mmc_class,
>          .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
> +       .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
>   };
>
>   /* MMC/SD/SDIO2 */
> @@ -3543,6 +3544,7 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
>          .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
>          .class          =&omap34xx_mmc_class,
>          .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
> +       .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
>   };
>

[PATCH 4/7] OMAP4: hwmod data: Replace main_clk with the real input clock

[Benoit Cousson]

Previously, main_clk was a fake clock node that was accessing the
PRCM modulemode register. Since the module mode is directly
controlled by the hwmod fmwk, these fake clock node are not
needed anymore. The hwmod main_clk will point directly to the
input clock node if applicable.
For example, some IPs, like the GPIOs, do not have any functional
clock and are using only the iclk. In that case, the main_clk
field will be empty.

In the case of the DSS, we can now consider all the optional clock as
main clock.
That will simplify greatly the driver management and the integration
with hwmod.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  111 +++++++++++++---------------
 1 files changed, 51 insertions(+), 60 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e10d3f7..5c196a1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -814,7 +814,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_aess_irqs),
 	.sdma_reqs	= omap44xx_aess_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_aess_sdma_reqs),
-	.main_clk	= "aess_fck",
+	.main_clk	= "aess_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
@@ -1086,7 +1086,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dmic_irqs),
 	.sdma_reqs	= omap44xx_dmic_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
-	.main_clk	= "dmic_fck",
+	.main_clk	= "func_dmic_abe_gfclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
@@ -1172,7 +1172,7 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dsp_irqs),
 	.rst_lines	= omap44xx_dsp_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
-	.main_clk	= "dsp_fck",
+	.main_clk	= "dpll_iva_m4x2_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
@@ -1263,7 +1263,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
 	.name		= "dss_core",
 	.class		= &omap44xx_dss_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
-	.main_clk	= "dss_fck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1363,7 +1362,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_irqs),
 	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
-	.main_clk	= "dss_fck",
+	.main_clk	= "dss_dss_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1456,7 +1455,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
 	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
-	.main_clk	= "dss_fck",
+	.main_clk	= "dss_sys_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1528,7 +1527,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
 	.sdma_reqs	= omap44xx_dss_dsi2_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
-	.main_clk	= "dss_fck",
+	.main_clk	= "dss_sys_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1620,7 +1619,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
 	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
-	.main_clk	= "dss_fck",
+	.main_clk	= "dss_48mhz_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1706,7 +1705,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 	.clkdm_name	= "l3_dss_clkdm",
 	.sdma_reqs	= omap44xx_dss_rfbi_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
-	.main_clk	= "dss_fck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1775,7 +1773,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap44xx_venc_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
-	.main_clk	= "dss_fck",
+	.main_clk	= "dss_tv_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1855,7 +1853,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
 	.clkdm_name	= "l4_wkup_clkdm",
 	.mpu_irqs	= omap44xx_gpio1_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio1_irqs),
-	.main_clk	= "gpio1_ick",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
@@ -1911,7 +1908,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= omap44xx_gpio2_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio2_irqs),
-	.main_clk	= "gpio2_ick",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
@@ -1967,7 +1963,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= omap44xx_gpio3_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio3_irqs),
-	.main_clk	= "gpio3_ick",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
@@ -2023,7 +2018,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= omap44xx_gpio4_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio4_irqs),
-	.main_clk	= "gpio4_ick",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
@@ -2079,7 +2073,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= omap44xx_gpio5_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio5_irqs),
-	.main_clk	= "gpio5_ick",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
@@ -2135,7 +2128,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.mpu_irqs	= omap44xx_gpio6_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio6_irqs),
-	.main_clk	= "gpio6_ick",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
@@ -2216,7 +2208,7 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
 	.clkdm_name	= "l3_init_clkdm",
 	.mpu_irqs	= omap44xx_hsi_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_hsi_irqs),
-	.main_clk	= "hsi_fck",
+	.main_clk	= "hsi_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
@@ -2295,7 +2287,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_irqs),
 	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
-	.main_clk	= "i2c1_fck",
+	.main_clk	= "func_96m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
@@ -2351,7 +2343,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_irqs),
 	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
-	.main_clk	= "i2c2_fck",
+	.main_clk	= "func_96m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
@@ -2407,7 +2399,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_irqs),
 	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
-	.main_clk	= "i2c3_fck",
+	.main_clk	= "func_96m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
@@ -2463,7 +2455,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_irqs),
 	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
-	.main_clk	= "i2c4_fck",
+	.main_clk	= "func_96m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
@@ -2560,7 +2552,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_ipu_irqs),
 	.rst_lines	= omap44xx_ipu_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_resets),
-	.main_clk	= "ipu_fck",
+	.main_clk	= "ducati_clk_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
@@ -2649,7 +2641,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_iss_irqs),
 	.sdma_reqs	= omap44xx_iss_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_iss_sdma_reqs),
-	.main_clk	= "iss_fck",
+	.main_clk	= "ducati_clk_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
@@ -2764,7 +2756,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_iva_irqs),
 	.rst_lines	= omap44xx_iva_resets,
 	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_resets),
-	.main_clk	= "iva_fck",
+	.main_clk	= "dpll_iva_m5x2_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
@@ -2837,7 +2829,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
 	.clkdm_name	= "l4_wkup_clkdm",
 	.mpu_irqs	= omap44xx_kbd_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_kbd_irqs),
-	.main_clk	= "kbd_fck",
+	.main_clk	= "sys_32k_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
@@ -2998,7 +2990,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcbsp1_irqs),
 	.sdma_reqs	= omap44xx_mcbsp1_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
-	.main_clk	= "mcbsp1_fck",
+	.main_clk	= "func_mcbsp1_gfclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
@@ -3074,7 +3066,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcbsp2_irqs),
 	.sdma_reqs	= omap44xx_mcbsp2_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
-	.main_clk	= "mcbsp2_fck",
+	.main_clk	= "func_mcbsp2_gfclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
@@ -3150,7 +3142,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcbsp3_irqs),
 	.sdma_reqs	= omap44xx_mcbsp3_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
-	.main_clk	= "mcbsp3_fck",
+	.main_clk	= "func_mcbsp3_gfclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
@@ -3205,7 +3197,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcbsp4_irqs),
 	.sdma_reqs	= omap44xx_mcbsp4_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
-	.main_clk	= "mcbsp4_fck",
+	.main_clk	= "per_mcbsp4_gfclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
@@ -3300,7 +3292,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcpdm_irqs),
 	.sdma_reqs	= omap44xx_mcpdm_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
-	.main_clk	= "mcpdm_fck",
+	.main_clk	= "pad_clks_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
@@ -3388,7 +3380,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi1_irqs),
 	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
-	.main_clk	= "mcspi1_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
@@ -3451,7 +3443,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi2_irqs),
 	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
-	.main_clk	= "mcspi2_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
@@ -3514,7 +3506,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi3_irqs),
 	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
-	.main_clk	= "mcspi3_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
@@ -3575,7 +3567,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi4_irqs),
 	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
-	.main_clk	= "mcspi4_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
@@ -3663,7 +3655,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mmc1_irqs),
 	.sdma_reqs	= omap44xx_mmc1_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
-	.main_clk	= "mmc1_fck",
+	.main_clk	= "hsmmc1_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
@@ -3726,7 +3718,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mmc2_irqs),
 	.sdma_reqs	= omap44xx_mmc2_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
-	.main_clk	= "mmc2_fck",
+	.main_clk	= "hsmmc2_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
@@ -3783,7 +3775,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mmc3_irqs),
 	.sdma_reqs	= omap44xx_mmc3_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
-	.main_clk	= "mmc3_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
@@ -3838,7 +3830,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mmc4_irqs),
 	.sdma_reqs	= omap44xx_mmc4_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
-	.main_clk	= "mmc4_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
@@ -3893,7 +3885,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mmc5_irqs),
 	.sdma_reqs	= omap44xx_mmc5_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
-	.main_clk	= "mmc5_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
@@ -4009,7 +4001,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
 	.clkdm_name	= "l4_ao_clkdm",
 	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
-	.main_clk	= "smartreflex_core_fck",
+	.main_clk	= "l4_wkup_clk_mux_ck",
 	.vdd_name	= "core",
 	.prcm = {
 		.omap4 = {
@@ -4058,7 +4050,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
 	.clkdm_name	= "l4_ao_clkdm",
 	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
-	.main_clk	= "smartreflex_iva_fck",
+	.main_clk	= "l4_wkup_clk_mux_ck",
 	.vdd_name	= "iva",
 	.prcm = {
 		.omap4 = {
@@ -4107,7 +4099,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
 	.clkdm_name	= "l4_ao_clkdm",
 	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
-	.main_clk	= "smartreflex_mpu_fck",
+	.main_clk	= "l4_wkup_clk_mux_ck",
 	.vdd_name	= "mpu",
 	.prcm = {
 		.omap4 = {
@@ -4257,7 +4249,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
 	.clkdm_name	= "l4_wkup_clkdm",
 	.mpu_irqs	= omap44xx_timer1_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer1_irqs),
-	.main_clk	= "timer1_fck",
+	.main_clk	= "dmt1_clk_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
@@ -4305,7 +4297,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
 	.clkdm_name	= "l4_per_clkdm",
 	.mpu_irqs	= omap44xx_timer2_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer2_irqs),
-	.main_clk	= "timer2_fck",
+	.main_clk	= "cm2_dm2_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
@@ -4353,7 +4345,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
 	.clkdm_name	= "l4_per_clkdm",
 	.mpu_irqs	= omap44xx_timer3_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer3_irqs),
-	.main_clk	= "timer3_fck",
+	.main_clk	= "cm2_dm3_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
@@ -4401,7 +4393,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
 	.clkdm_name	= "l4_per_clkdm",
 	.mpu_irqs	= omap44xx_timer4_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer4_irqs),
-	.main_clk	= "timer4_fck",
+	.main_clk	= "cm2_dm4_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
@@ -4468,7 +4460,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
 	.clkdm_name	= "abe_clkdm",
 	.mpu_irqs	= omap44xx_timer5_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer5_irqs),
-	.main_clk	= "timer5_fck",
+	.main_clk	= "timer5_sync_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
@@ -4535,7 +4527,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
 	.clkdm_name	= "abe_clkdm",
 	.mpu_irqs	= omap44xx_timer6_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer6_irqs),
-	.main_clk	= "timer6_fck",
+	.main_clk	= "timer6_sync_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
@@ -4602,7 +4594,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
 	.clkdm_name	= "abe_clkdm",
 	.mpu_irqs	= omap44xx_timer7_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer7_irqs),
-	.main_clk	= "timer7_fck",
+	.main_clk	= "timer7_sync_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
@@ -4669,7 +4661,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
 	.clkdm_name	= "abe_clkdm",
 	.mpu_irqs	= omap44xx_timer8_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer8_irqs),
-	.main_clk	= "timer8_fck",
+	.main_clk	= "timer8_sync_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
@@ -4717,7 +4709,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
 	.clkdm_name	= "l4_per_clkdm",
 	.mpu_irqs	= omap44xx_timer9_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer9_irqs),
-	.main_clk	= "timer9_fck",
+	.main_clk	= "cm2_dm9_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
@@ -4765,7 +4757,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
 	.clkdm_name	= "l4_per_clkdm",
 	.mpu_irqs	= omap44xx_timer10_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer10_irqs),
-	.main_clk	= "timer10_fck",
+	.main_clk	= "cm2_dm10_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
@@ -4813,7 +4805,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
 	.clkdm_name	= "l4_per_clkdm",
 	.mpu_irqs	= omap44xx_timer11_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer11_irqs),
-	.main_clk	= "timer11_fck",
+	.main_clk	= "cm2_dm11_mux_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
@@ -4890,7 +4882,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_uart1_irqs),
 	.sdma_reqs	= omap44xx_uart1_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
-	.main_clk	= "uart1_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
@@ -4945,7 +4937,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_uart2_irqs),
 	.sdma_reqs	= omap44xx_uart2_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
-	.main_clk	= "uart2_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
@@ -5001,7 +4993,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_uart3_irqs),
 	.sdma_reqs	= omap44xx_uart3_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
-	.main_clk	= "uart3_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
@@ -5056,7 +5048,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_uart4_irqs),
 	.sdma_reqs	= omap44xx_uart4_sdma_reqs,
 	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
-	.main_clk	= "uart4_fck",
+	.main_clk	= "func_48m_fclk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
@@ -5137,7 +5129,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 	.mpu_irqs	= omap44xx_usb_otg_hs_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
-	.main_clk	= "usb_otg_hs_ick",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
@@ -5212,7 +5203,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 	.clkdm_name	= "l4_wkup_clkdm",
 	.mpu_irqs	= omap44xx_wd_timer2_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_wd_timer2_irqs),
-	.main_clk	= "wd_timer2_fck",
+	.main_clk	= "sys_32k_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
@@ -5279,7 +5270,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 	.clkdm_name	= "abe_clkdm",
 	.mpu_irqs	= omap44xx_wd_timer3_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_wd_timer3_irqs),
-	.main_clk	= "wd_timer3_fck",
+	.main_clk	= "sys_32k_ck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
-- 
1.7.0.4

Re: [PATCH 4/7] OMAP4: hwmod data: Replace main_clk with the real input clock

[Tomi Valkeinen]

On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
> Previously, main_clk was a fake clock node that was accessing the
> PRCM modulemode register. Since the module mode is directly
> controlled by the hwmod fmwk, these fake clock node are not
> needed anymore. The hwmod main_clk will point directly to the
> input clock node if applicable.
> For example, some IPs, like the GPIOs, do not have any functional
> clock and are using only the iclk. In that case, the main_clk
> field will be empty.
> 
> In the case of the DSS, we can now consider all the optional clock as
> main clock.
> That will simplify greatly the driver management and the integration
> with hwmod.
> 
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Paul Walmsley <paul@pwsan.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  111 +++++++++++++---------------
>  1 files changed, 51 insertions(+), 60 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index e10d3f7..5c196a1 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c

<snip>

> @@ -1263,7 +1263,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
>  	.name		= "dss_core",
>  	.class		= &omap44xx_dss_hwmod_class,
>  	.clkdm_name	= "l3_dss_clkdm",
> -	.main_clk	= "dss_fck",
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,

Why dss_core doesn't need a mainclock? Shouldn't it have dss_dss_clk as
a mainclock?

> @@ -1363,7 +1362,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
>  	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_irqs),
>  	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
>  	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
> -	.main_clk	= "dss_fck",
> +	.main_clk	= "dss_dss_clk",
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
> @@ -1456,7 +1455,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
>  	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
>  	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
>  	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
> -	.main_clk	= "dss_fck",
> +	.main_clk	= "dss_sys_clk",
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,

Hmm... I don't think this is right. By default the DSI uses dss_dss_clk
as the functional clock. sys_clk goes to the DSI PLL, and the output of
which can be later used as the fclk for DSI. But that requires setup.

> @@ -1528,7 +1527,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
>  	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
>  	.sdma_reqs	= omap44xx_dss_dsi2_sdma_reqs,
>  	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
> -	.main_clk	= "dss_fck",
> +	.main_clk	= "dss_sys_clk",
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,

Same here.

 Tomi

Re: [PATCH 4/7] OMAP4: hwmod data: Replace main_clk with the real input clock

[Cousson, Benoit]

Hi Tomi,

On 6/28/2011 8:40 AM, Valkeinen, Tomi wrote:
> On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
>> Previously, main_clk was a fake clock node that was accessing the
>> PRCM modulemode register. Since the module mode is directly
>> controlled by the hwmod fmwk, these fake clock node are not
>> needed anymore. The hwmod main_clk will point directly to the
>> input clock node if applicable.
>> For example, some IPs, like the GPIOs, do not have any functional
>> clock and are using only the iclk. In that case, the main_clk
>> field will be empty.
>>
>> In the case of the DSS, we can now consider all the optional clock as
>> main clock.
>> That will simplify greatly the driver management and the integration
>> with hwmod.
>>
>> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
>> Cc: Tomi Valkeinen<tomi.valkeinen@ti.com>
>> Cc: Paul Walmsley<paul@pwsan.com>
>> Cc: Rajendra Nayak<rnayak@ti.com>
>> ---
>>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  111 +++++++++++++---------------
>>   1 files changed, 51 insertions(+), 60 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> index e10d3f7..5c196a1 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>
> <snip>
>
>> @@ -1263,7 +1263,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
>>   	.name		= "dss_core",
>>   	.class		=&omap44xx_dss_hwmod_class,
>>   	.clkdm_name	= "l3_dss_clkdm",
>> -	.main_clk	= "dss_fck",
>>   	.prcm = {
>>   		.omap4 = {
>>   			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
>
> Why dss_core doesn't need a mainclock? Shouldn't it have dss_dss_clk as
> a mainclock?

Yep, good point.

>
>> @@ -1363,7 +1362,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
>>   	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_irqs),
>>   	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
>>   	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
>> -	.main_clk	= "dss_fck",
>> +	.main_clk	= "dss_dss_clk",
>>   	.prcm = {
>>   		.omap4 = {
>>   			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
>> @@ -1456,7 +1455,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
>>   	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
>>   	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
>>   	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
>> -	.main_clk	= "dss_fck",
>> +	.main_clk	= "dss_sys_clk",
>>   	.prcm = {
>>   		.omap4 = {
>>   			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
>
> Hmm... I don't think this is right. By default the DSI uses dss_dss_clk
> as the functional clock. sys_clk goes to the DSI PLL, and the output of
> which can be later used as the fclk for DSI. But that requires setup.

OK, it was not super clear from the DSS clock tree which one should be 
the main one.
So you'd prefer to have the dss_dss_clk as main clock and keep the 
dss_sys_clk as a opt_clock?

Benoit

Re: [PATCH 4/7] OMAP4: hwmod data: Replace main_clk with the real input clock

[Tomi Valkeinen]

On Tue, 2011-06-28 at 10:10 +0200, Cousson, Benoit wrote:
> Hi Tomi,
> 
> On 6/28/2011 8:40 AM, Valkeinen, Tomi wrote:
> > On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
> >> Previously, main_clk was a fake clock node that was accessing the
> >> PRCM modulemode register. Since the module mode is directly
> >> controlled by the hwmod fmwk, these fake clock node are not
> >> needed anymore. The hwmod main_clk will point directly to the
> >> input clock node if applicable.
> >> For example, some IPs, like the GPIOs, do not have any functional
> >> clock and are using only the iclk. In that case, the main_clk
> >> field will be empty.
> >>
> >> In the case of the DSS, we can now consider all the optional clock as
> >> main clock.
> >> That will simplify greatly the driver management and the integration
> >> with hwmod.
> >>
> >> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
> >> Cc: Tomi Valkeinen<tomi.valkeinen@ti.com>
> >> Cc: Paul Walmsley<paul@pwsan.com>
> >> Cc: Rajendra Nayak<rnayak@ti.com>
> >> ---
> >>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  111 +++++++++++++---------------
> >>   1 files changed, 51 insertions(+), 60 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> >> index e10d3f7..5c196a1 100644
> >> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> >> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> >
> > <snip>

> >> @@ -1456,7 +1455,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
> >>   	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
> >>   	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
> >>   	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
> >> -	.main_clk	= "dss_fck",
> >> +	.main_clk	= "dss_sys_clk",
> >>   	.prcm = {
> >>   		.omap4 = {
> >>   			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
> >
> > Hmm... I don't think this is right. By default the DSI uses dss_dss_clk
> > as the functional clock. sys_clk goes to the DSI PLL, and the output of
> > which can be later used as the fclk for DSI. But that requires setup.
> 
> OK, it was not super clear from the DSS clock tree which one should be 
> the main one.
> So you'd prefer to have the dss_dss_clk as main clock and keep the 
> dss_sys_clk as a opt_clock?

Yes, I think that makes more sense.

My patch set had dss_dss_clk as the mainclock for all DSS blocks. You
have it a bit differently for venc, hdmi, rfbi. It's a bit difficult to
verify those, as the DSS and DISPC are anyway enabled before
venc/hdmi/rfbi, so the dss_dss_clk is anyway enabled. But they do make
sense by looking at the clock tree.

 Tomi

Re: [PATCH 4/7] OMAP4: hwmod data: Replace main_clk with the real input clock

[Cousson, Benoit]

On 6/28/2011 10:14 AM, Valkeinen, Tomi wrote:
> On Tue, 2011-06-28 at 10:10 +0200, Cousson, Benoit wrote:
>> Hi Tomi,
>>
>> On 6/28/2011 8:40 AM, Valkeinen, Tomi wrote:
>>> On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
>>>> Previously, main_clk was a fake clock node that was accessing the
>>>> PRCM modulemode register. Since the module mode is directly
>>>> controlled by the hwmod fmwk, these fake clock node are not
>>>> needed anymore. The hwmod main_clk will point directly to the
>>>> input clock node if applicable.
>>>> For example, some IPs, like the GPIOs, do not have any functional
>>>> clock and are using only the iclk. In that case, the main_clk
>>>> field will be empty.
>>>>
>>>> In the case of the DSS, we can now consider all the optional clock as
>>>> main clock.
>>>> That will simplify greatly the driver management and the integration
>>>> with hwmod.
>>>>
>>>> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
>>>> Cc: Tomi Valkeinen<tomi.valkeinen@ti.com>
>>>> Cc: Paul Walmsley<paul@pwsan.com>
>>>> Cc: Rajendra Nayak<rnayak@ti.com>
>>>> ---
>>>>    arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  111 +++++++++++++---------------
>>>>    1 files changed, 51 insertions(+), 60 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>>> index e10d3f7..5c196a1 100644
>>>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>>>
>>> <snip>
>
>>>> @@ -1456,7 +1455,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
>>>>    	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
>>>>    	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
>>>>    	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
>>>> -	.main_clk	= "dss_fck",
>>>> +	.main_clk	= "dss_sys_clk",
>>>>    	.prcm = {
>>>>    		.omap4 = {
>>>>    			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
>>>
>>> Hmm... I don't think this is right. By default the DSI uses dss_dss_clk
>>> as the functional clock. sys_clk goes to the DSI PLL, and the output of
>>> which can be later used as the fclk for DSI. But that requires setup.
>>
>> OK, it was not super clear from the DSS clock tree which one should be
>> the main one.
>> So you'd prefer to have the dss_dss_clk as main clock and keep the
>> dss_sys_clk as a opt_clock?
>
> Yes, I think that makes more sense.
>
> My patch set had dss_dss_clk as the mainclock for all DSS blocks. You
> have it a bit differently for venc, hdmi, rfbi.

Yep, I saw that but, I don't think it should be done like that.

> It's a bit difficult to
> verify those, as the DSS and DISPC are anyway enabled before
> venc/hdmi/rfbi, so the dss_dss_clk is anyway enabled. But they do make
> sense by looking at the clock tree.

Mmm, I'm not sure of that. In theory the dss_dss_clk is mainly the 
functional clock for the DISPC. It can be used as the source clock for 
some other module like DSI, but it is not mandatory.
In the case of venc, rfbi and hdmi, that dss_dss_clk is not even 
connected to them.
You do have a functional dependency between the DISPC and all the DSS 
IPs, but that does not mean that the dss_dss_clk should be affected to 
all the sub IPs.
This is up to your driver stack to handle that functional dependency.
That's why here I was trying to focus only on the main functionnal clock 
for each IP. There is no point to expose the dss_dss_clk to every hwmod 
if the driver does not have anything to do with them.

Regards,
Benoit

Re: [PATCH 4/7] OMAP4: hwmod data: Replace main_clk with the real input clock

[Tomi Valkeinen]

On Tue, 2011-06-28 at 10:27 +0200, Cousson, Benoit wrote:
> On 6/28/2011 10:14 AM, Valkeinen, Tomi wrote:
> > On Tue, 2011-06-28 at 10:10 +0200, Cousson, Benoit wrote:
> >> Hi Tomi,
> >>
> >> On 6/28/2011 8:40 AM, Valkeinen, Tomi wrote:
> >>> On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
> >>>> Previously, main_clk was a fake clock node that was accessing the
> >>>> PRCM modulemode register. Since the module mode is directly
> >>>> controlled by the hwmod fmwk, these fake clock node are not
> >>>> needed anymore. The hwmod main_clk will point directly to the
> >>>> input clock node if applicable.
> >>>> For example, some IPs, like the GPIOs, do not have any functional
> >>>> clock and are using only the iclk. In that case, the main_clk
> >>>> field will be empty.
> >>>>
> >>>> In the case of the DSS, we can now consider all the optional clock as
> >>>> main clock.
> >>>> That will simplify greatly the driver management and the integration
> >>>> with hwmod.
> >>>>
> >>>> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
> >>>> Cc: Tomi Valkeinen<tomi.valkeinen@ti.com>
> >>>> Cc: Paul Walmsley<paul@pwsan.com>
> >>>> Cc: Rajendra Nayak<rnayak@ti.com>
> >>>> ---
> >>>>    arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  111 +++++++++++++---------------
> >>>>    1 files changed, 51 insertions(+), 60 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> >>>> index e10d3f7..5c196a1 100644
> >>>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> >>>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> >>>
> >>> <snip>
> >
> >>>> @@ -1456,7 +1455,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
> >>>>    	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
> >>>>    	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
> >>>>    	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
> >>>> -	.main_clk	= "dss_fck",
> >>>> +	.main_clk	= "dss_sys_clk",
> >>>>    	.prcm = {
> >>>>    		.omap4 = {
> >>>>    			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
> >>>
> >>> Hmm... I don't think this is right. By default the DSI uses dss_dss_clk
> >>> as the functional clock. sys_clk goes to the DSI PLL, and the output of
> >>> which can be later used as the fclk for DSI. But that requires setup.
> >>
> >> OK, it was not super clear from the DSS clock tree which one should be
> >> the main one.
> >> So you'd prefer to have the dss_dss_clk as main clock and keep the
> >> dss_sys_clk as a opt_clock?
> >
> > Yes, I think that makes more sense.
> >
> > My patch set had dss_dss_clk as the mainclock for all DSS blocks. You
> > have it a bit differently for venc, hdmi, rfbi.
> 
> Yep, I saw that but, I don't think it should be done like that.
> 
> > It's a bit difficult to
> > verify those, as the DSS and DISPC are anyway enabled before
> > venc/hdmi/rfbi, so the dss_dss_clk is anyway enabled. But they do make
> > sense by looking at the clock tree.
> 
> Mmm, I'm not sure of that. In theory the dss_dss_clk is mainly the 
> functional clock for the DISPC. It can be used as the source clock for 
> some other module like DSI, but it is not mandatory.

It is not mandatory for DSS/DISPC either, in the same way it's not
mandatory for DSI. But I think, for the time being, having dss_dss_clk
as the main_clk is the only way to get things working properly. (And I
mean for the hwmods that require it, not venc/rfbi/hdmi).

> In the case of venc, rfbi and hdmi, that dss_dss_clk is not even 
> connected to them.
> You do have a functional dependency between the DISPC and all the DSS 
> IPs, but that does not mean that the dss_dss_clk should be affected to 
> all the sub IPs.

Yep, I agree. It does look correct to me also. I just wanted to point
out the difference, which may cause problems if your analysis is not
correct.

And I also don't know how to test it, as it won't be visible in normal
use (as the DISPC is always enabled first, enabling dss_dss_clk).
Perhaps it'd be possible with lauterbach, or perhaps hacking around,
enabling only certain clks and DSS parts, to see if the modules wake up
correctly.

> This is up to your driver stack to handle that functional dependency.
> That's why here I was trying to focus only on the main functionnal clock 
> for each IP. There is no point to expose the dss_dss_clk to every hwmod 
> if the driver does not have anything to do with them.

Yep. No disagreement =).

 Tomi

[PATCH 5/7] OMAP4: clock data: Remove leaf clock nodes

[Benoit Cousson]

Since the modulemode is now handled by the hwmod, the clock leaf
nodes are not needed anymore.

Remove them.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
c: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock44xx_data.c | 1732 ++++++++++------------------------
 1 files changed, 506 insertions(+), 1226 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 684ae8b..547f02b 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1267,511 +1267,548 @@ static struct clk syc_clk_div_ck = {
 
 /* Leaf clocks controlled by modules */
 
-static struct clk aes1_fck = {
-	.name		= "aes1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk aes2_fck = {
-	.name		= "aes2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk aess_fck = {
-	.name		= "aess_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_AESS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &aess_fclk,
-	.recalc		= &followparent_recalc,
-};
-
 static struct clk bandgap_fclk = {
 	.name		= "bandgap_fclk",
+	.parent		= &sys_32k_ck,
 	.ops		= &clkops_omap2_dflt,
+	.recalc		= &followparent_recalc,
 	.enable_reg	= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 	.enable_bit	= OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
 	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
 };
 
-static struct clk des3des_fck = {
-	.name		= "des3des_fck",
+static struct clk dss_48mhz_clk = {
+	.name		= "dss_48mhz_clk",
+	.parent		= &func_48mc_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
+	.clkdm_name	= "l3_dss_clkdm",
 };
 
-static const struct clksel dmic_sync_mux_sel[] = {
-	{ .parent = &abe_24m_fclk, .rates = div_1_0_rates },
-	{ .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
-	{ .parent = &func_24m_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static struct clk dmic_sync_mux_ck = {
-	.name		= "dmic_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-/* Merged func_dmic_abe_gfclk into dmic */
-static struct clk dmic_fck = {
-	.name		= "dmic_fck",
-	.parent		= &dmic_sync_mux_ck,
-	.clksel		= func_dmic_abe_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
-
-static struct clk dsp_fck = {
-	.name		= "dsp_fck",
+static struct clk dss_dss_clk = {
+	.name		= "dss_dss_clk",
+	.parent		= &dpll_per_m5x2_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "tesla_clkdm",
-	.parent		= &dpll_iva_m4x2_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
+	.clkdm_name	= "l3_dss_clkdm",
 };
 
 static struct clk dss_sys_clk = {
 	.name		= "dss_sys_clk",
+	.parent		= &syc_clk_div_ck,
 	.ops		= &clkops_omap2_dflt,
+	.recalc		= &followparent_recalc,
 	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
 	.enable_bit	= OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
 	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &syc_clk_div_ck,
-	.recalc		= &followparent_recalc,
 };
 
 static struct clk dss_tv_clk = {
 	.name		= "dss_tv_clk",
+	.parent		= &extalt_clkin_ck,
 	.ops		= &clkops_omap2_dflt,
+	.recalc		= &followparent_recalc,
 	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
 	.enable_bit	= OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
 	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &extalt_clkin_ck,
-	.recalc		= &followparent_recalc,
 };
 
-static struct clk dss_dss_clk = {
-	.name		= "dss_dss_clk",
+static struct clk gpio1_dbclk = {
+	.name		= "gpio1_dbclk",
+	.parent		= &sys_32k_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &dpll_per_m5x2_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+	.clkdm_name	= "l4_wkup_clkdm",
 };
 
-static struct clk dss_48mhz_clk = {
-	.name		= "dss_48mhz_clk",
+static struct clk gpio2_dbclk = {
+	.name		= "gpio2_dbclk",
+	.parent		= &sys_32k_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &func_48mc_fclk,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+	.clkdm_name	= "l4_per_clkdm",
 };
 
-static struct clk dss_fck = {
-	.name		= "dss_fck",
+static struct clk gpio3_dbclk = {
+	.name		= "gpio3_dbclk",
+	.parent		= &sys_32k_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &l3_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+	.clkdm_name	= "l4_per_clkdm",
 };
 
-static struct clk efuse_ctrl_cust_fck = {
-	.name		= "efuse_ctrl_cust_fck",
+static struct clk gpio4_dbclk = {
+	.name		= "gpio4_dbclk",
+	.parent		= &sys_32k_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_cefuse_clkdm",
-	.parent		= &sys_clkin_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+	.clkdm_name	= "l4_per_clkdm",
 };
 
-static struct clk emif1_fck = {
-	.name		= "emif1_fck",
+static struct clk gpio5_dbclk = {
+	.name		= "gpio5_dbclk",
+	.parent		= &sys_32k_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_emif_clkdm",
-	.parent		= &ddrphy_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+	.clkdm_name	= "l4_per_clkdm",
 };
 
-static struct clk emif2_fck = {
-	.name		= "emif2_fck",
+static struct clk gpio6_dbclk = {
+	.name		= "gpio6_dbclk",
+	.parent		= &sys_32k_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_emif_clkdm",
-	.parent		= &ddrphy_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+	.clkdm_name	= "l4_per_clkdm",
 };
 
-static const struct clksel fdif_fclk_div[] = {
-	{ .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
-
-/* Merged fdif_fclk into fdif */
-static struct clk fdif_fck = {
-	.name		= "fdif_fck",
-	.parent		= &dpll_per_m4x2_ck,
-	.clksel		= fdif_fclk_div,
-	.clksel_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_FCLK_MASK,
+static struct clk iss_ctrlclk = {
+	.name		= "iss_ctrlclk",
+	.parent		= &func_96m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-	.enable_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
+	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
 	.clkdm_name	= "iss_clkdm",
 };
 
-static struct clk fpka_fck = {
-	.name		= "fpka_fck",
+static struct clk ocp2scp_usb_phy_phy_48m_ck = {
+	.name		= "ocp2scp_usb_phy_phy_48m_ck",
+	.parent		= &func_48m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk gpio1_dbclk = {
-	.name		= "gpio1_dbclk",
+static struct clk slimbus1_fclk_0_ck = {
+	.name		= "slimbus1_fclk_0_ck",
+	.parent		= &abe_24m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
+	.clkdm_name	= "abe_clkdm",
 };
 
-static struct clk gpio1_ick = {
-	.name		= "gpio1_ick",
+static struct clk slimbus1_fclk_1_ck = {
+	.name		= "slimbus1_fclk_1_ck",
+	.parent		= &func_24m_clk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
+	.clkdm_name	= "abe_clkdm",
 };
 
-static struct clk gpio2_dbclk = {
-	.name		= "gpio2_dbclk",
+static struct clk slimbus1_fclk_2_ck = {
+	.name		= "slimbus1_fclk_2_ck",
+	.parent		= &pad_clks_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
+	.clkdm_name	= "abe_clkdm",
 };
 
-static struct clk gpio2_ick = {
-	.name		= "gpio2_ick",
+static struct clk slimbus1_slimbus_clk = {
+	.name		= "slimbus1_slimbus_clk",
+	.parent		= &slimbus_clk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
+	.clkdm_name	= "abe_clkdm",
 };
 
-static struct clk gpio3_dbclk = {
-	.name		= "gpio3_dbclk",
+static struct clk slimbus2_fclk_0_ck = {
+	.name		= "slimbus2_fclk_0_ck",
+	.parent		= &func_24mc_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
 	.recalc		= &followparent_recalc,
-};
-
-static struct clk gpio3_ick = {
-	.name		= "gpio3_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
+	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
 	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
 };
 
-static struct clk gpio4_dbclk = {
-	.name		= "gpio4_dbclk",
+static struct clk slimbus2_fclk_1_ck = {
+	.name		= "slimbus2_fclk_1_ck",
+	.parent		= &per_abe_24m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
+	.clkdm_name	= "l4_per_clkdm",
 };
 
-static struct clk gpio4_ick = {
-	.name		= "gpio4_ick",
+static struct clk slimbus2_slimbus_clk = {
+	.name		= "slimbus2_slimbus_clk",
+	.parent		= &pad_slimbus_core_clks_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
+	.clkdm_name	= "l4_per_clkdm",
 };
 
-static struct clk gpio5_dbclk = {
-	.name		= "gpio5_dbclk",
+static struct clk usb_host_hs_func48mclk_ck = {
+	.name		= "usb_host_hs_func48mclk_ck",
+	.parent		= &func_48mc_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk gpio5_ick = {
-	.name		= "gpio5_ick",
+static struct clk usb_host_hs_hsic480m_p1_clk = {
+	.name		= "usb_host_hs_hsic480m_p1_clk",
+	.parent		= &dpll_usb_m2_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk gpio6_dbclk = {
-	.name		= "gpio6_dbclk",
+static struct clk usb_host_hs_hsic480m_p2_clk = {
+	.name		= "usb_host_hs_hsic480m_p2_clk",
+	.parent		= &dpll_usb_m2_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk gpio6_ick = {
-	.name		= "gpio6_ick",
+static struct clk usb_host_hs_hsic60m_p1_clk = {
+	.name		= "usb_host_hs_hsic60m_p1_clk",
+	.parent		= &init_60m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk gpmc_ick = {
-	.name		= "gpmc_ick",
+static struct clk usb_host_hs_hsic60m_p2_clk = {
+	.name		= "usb_host_hs_hsic60m_p2_clk",
+	.parent		= &init_60m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3_2_GPMC_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_2_clkdm",
-	.parent		= &l3_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static const struct clksel sgx_clk_mux_sel[] = {
-	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
+static const struct clksel utmi_p1_gfclk_sel[] = {
+	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
+	{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
 	{ .parent = NULL },
 };
 
-/* Merged sgx_clk_mux into gpu */
-static struct clk gpu_fck = {
-	.name		= "gpu_fck",
-	.parent		= &dpll_core_m7x2_ck,
-	.clksel		= sgx_clk_mux_sel,
+static struct clk utmi_p1_gfclk = {
+	.name		= "utmi_p1_gfclk",
+	.parent		= &init_60m_fclk,
+	.clksel		= utmi_p1_gfclk_sel,
 	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SGX_FCLK_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P1_MASK,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_gfx_clkdm",
 };
 
-static struct clk hdq1w_fck = {
-	.name		= "hdq1w_fck",
+static struct clk usb_host_hs_utmi_p1_clk = {
+	.name		= "usb_host_hs_utmi_p1_clk",
+	.parent		= &utmi_p1_gfclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_12m_fclk,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static const struct clksel hsi_fclk_div[] = {
-	{ .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
+static const struct clksel utmi_p2_gfclk_sel[] = {
+	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
+	{ .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
 	{ .parent = NULL },
 };
 
-/* Merged hsi_fclk into hsi */
-static struct clk hsi_fck = {
-	.name		= "hsi_fck",
-	.parent		= &dpll_per_m2x2_ck,
-	.clksel		= hsi_fclk_div,
-	.clksel_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_24_25_MASK,
-	.ops		= &clkops_omap2_dflt,
+static struct clk utmi_p2_gfclk = {
+	.name		= "utmi_p2_gfclk",
+	.parent		= &init_60m_fclk,
+	.clksel		= utmi_p2_gfclk_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P2_MASK,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-	.enable_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk i2c1_fck = {
-	.name		= "i2c1_fck",
+static struct clk usb_host_hs_utmi_p2_clk = {
+	.name		= "usb_host_hs_utmi_p2_clk",
+	.parent		= &utmi_p2_gfclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk i2c2_fck = {
-	.name		= "i2c2_fck",
+static struct clk usb_host_hs_utmi_p3_clk = {
+	.name		= "usb_host_hs_utmi_p3_clk",
+	.parent		= &init_60m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk i2c3_fck = {
-	.name		= "i2c3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
+static const struct clksel otg_60m_gfclk_sel[] = {
+	{ .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
+	{ .parent = &xclk60motg_ck, .rates = div_1_1_rates },
+	{ .parent = NULL },
 };
 
-static struct clk i2c4_fck = {
-	.name		= "i2c4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
+static struct clk otg_60m_gfclk = {
+	.name		= "otg_60m_gfclk",
+	.parent		= &utmi_phy_clkout_ck,
+	.clksel		= otg_60m_gfclk_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_60M_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
 };
 
-static struct clk ipu_fck = {
-	.name		= "ipu_fck",
+static struct clk usb_otg_hs_xclk = {
+	.name		= "usb_otg_hs_xclk",
+	.parent		= &otg_60m_gfclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ducati_clkdm",
-	.parent		= &ducati_clk_mux_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_XCLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk iss_ctrlclk = {
-	.name		= "iss_ctrlclk",
+static struct clk usb_phy_cm_clk32k_ck = {
+	.name		= "usb_phy_cm_clk32k_ck",
+	.parent		= &sys_32k_ck,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-	.clkdm_name	= "iss_clkdm",
-	.parent		= &func_96m_fclk,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
+	.clkdm_name	= "l4_ao_clkdm",
 };
 
-static struct clk iss_fck = {
-	.name		= "iss_fck",
+static struct clk usb_tll_hs_usb_ch0_clk = {
+	.name		= "usb_tll_hs_usb_ch0_clk",
+	.parent		= &init_60m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "iss_clkdm",
-	.parent		= &ducati_clk_mux_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk iva_fck = {
-	.name		= "iva_fck",
+static struct clk usb_tll_hs_usb_ch1_clk = {
+	.name		= "usb_tll_hs_usb_ch1_clk",
+	.parent		= &init_60m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5x2_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk kbd_fck = {
-	.name		= "kbd_fck",
+static struct clk usb_tll_hs_usb_ch2_clk = {
+	.name		= "usb_tll_hs_usb_ch2_clk",
+	.parent		= &init_60m_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
+	.clkdm_name	= "l3_init_clkdm",
 };
 
-static struct clk l3_instr_ick = {
-	.name		= "l3_instr_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_instr_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
+static const struct clksel_rate div2_14to18_rates[] = {
+	{ .div = 14, .val = 0, .flags = RATE_IN_44XX },
+	{ .div = 18, .val = 1, .flags = RATE_IN_44XX },
+	{ .div = 0 },
+};
+
+static const struct clksel usim_fclk_div[] = {
+	{ .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
+	{ .parent = NULL },
+};
+
+static struct clk usim_fclk = {
+	.name		= "usim_fclk",
+	.parent		= &dpll_per_m4x2_ck,
+	.clksel		= usim_fclk_div,
+	.clksel_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_DIV_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+	.round_rate	= &omap2_clksel_round_rate,
+	.set_rate	= &omap2_clksel_set_rate,
 };
 
-static struct clk l3_main_3_ick = {
-	.name		= "l3_main_3_ick",
+static struct clk usim_clk = {
+	.name		= "usim_clk",
+	.parent		= &usim_fclk,
 	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_instr_clkdm",
-	.parent		= &l3_div_ck,
 	.recalc		= &followparent_recalc,
+	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
+	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK_SHIFT,
+	.clkdm_name	= "l4_wkup_clkdm",
+};
+
+static struct clk cm2_dm10_mux_ck = {
+	.name		= "cm2_dm10_mux_ck",
+	.parent		= &sys_clkin_ck,
+	.clksel		= abe_dpll_bypass_clk_mux_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk cm2_dm11_mux_ck = {
+	.name		= "cm2_dm11_mux_ck",
+	.parent		= &sys_clkin_ck,
+	.clksel		= abe_dpll_bypass_clk_mux_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk cm2_dm2_mux_ck = {
+	.name		= "cm2_dm2_mux_ck",
+	.parent		= &sys_clkin_ck,
+	.clksel		= abe_dpll_bypass_clk_mux_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk cm2_dm3_mux_ck = {
+	.name		= "cm2_dm3_mux_ck",
+	.parent		= &sys_clkin_ck,
+	.clksel		= abe_dpll_bypass_clk_mux_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk cm2_dm4_mux_ck = {
+	.name		= "cm2_dm4_mux_ck",
+	.parent		= &sys_clkin_ck,
+	.clksel		= abe_dpll_bypass_clk_mux_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk cm2_dm9_mux_ck = {
+	.name		= "cm2_dm9_mux_ck",
+	.parent		= &sys_clkin_ck,
+	.clksel		= abe_dpll_bypass_clk_mux_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static const struct clksel dmic_sync_mux_sel[] = {
+	{ .parent = &abe_24m_fclk, .rates = div_1_0_rates },
+	{ .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
+	{ .parent = &func_24m_clk, .rates = div_1_2_rates },
+	{ .parent = NULL },
+};
+
+static struct clk dmic_sync_mux_ck = {
+	.name		= "dmic_sync_mux_ck",
+	.parent		= &abe_24m_fclk,
+	.clksel		= dmic_sync_mux_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk dmt1_clk_mux_ck = {
+	.name		= "dmt1_clk_mux_ck",
+	.parent		= &sys_clkin_ck,
+	.clksel		= abe_dpll_bypass_clk_mux_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static const struct clksel fdif_fclk_div[] = {
+	{ .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
+	{ .parent = NULL },
+};
+
+static struct clk fdif_fclk = {
+	.name		= "fdif_fclk",
+	.parent		= &dpll_per_m4x2_ck,
+	.clksel		= fdif_fclk_div,
+	.clksel_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_FCLK_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
+	.round_rate	= &omap2_clksel_round_rate,
+	.set_rate	= &omap2_clksel_set_rate,
+};
+
+static const struct clksel func_dmic_abe_gfclk_sel[] = {
+	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
+	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
+	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
+	{ .parent = NULL },
+};
+
+static struct clk func_dmic_abe_gfclk = {
+	.name		= "func_dmic_abe_gfclk",
+	.parent		= &dmic_sync_mux_ck,
+	.clksel		= func_dmic_abe_gfclk_sel,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
+	.ops		= &clkops_null,
+	.recalc		= &omap2_clksel_recalc,
 };
 
 static struct clk mcasp_sync_mux_ck = {
@@ -1792,19 +1829,15 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = {
 	{ .parent = NULL },
 };
 
-/* Merged func_mcasp_abe_gfclk into mcasp */
-static struct clk mcasp_fck = {
-	.name		= "mcasp_fck",
+static struct clk func_mcasp_abe_gfclk = {
+	.name		= "func_mcasp_abe_gfclk",
 	.parent		= &mcasp_sync_mux_ck,
 	.clksel		= func_mcasp_abe_gfclk_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
 };
 
 static struct clk mcbsp1_sync_mux_ck = {
@@ -1825,19 +1858,15 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = {
 	{ .parent = NULL },
 };
 
-/* Merged func_mcbsp1_gfclk into mcbsp1 */
-static struct clk mcbsp1_fck = {
-	.name		= "mcbsp1_fck",
+static struct clk func_mcbsp1_gfclk = {
+	.name		= "func_mcbsp1_gfclk",
 	.parent		= &mcbsp1_sync_mux_ck,
 	.clksel		= func_mcbsp1_gfclk_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
 };
 
 static struct clk mcbsp2_sync_mux_ck = {
@@ -1858,19 +1887,15 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = {
 	{ .parent = NULL },
 };
 
-/* Merged func_mcbsp2_gfclk into mcbsp2 */
-static struct clk mcbsp2_fck = {
-	.name		= "mcbsp2_fck",
+static struct clk func_mcbsp2_gfclk = {
+	.name		= "func_mcbsp2_gfclk",
 	.parent		= &mcbsp2_sync_mux_ck,
 	.clksel		= func_mcbsp2_gfclk_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
 };
 
 static struct clk mcbsp3_sync_mux_ck = {
@@ -1891,107 +1916,32 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = {
 	{ .parent = NULL },
 };
 
-/* Merged func_mcbsp3_gfclk into mcbsp3 */
-static struct clk mcbsp3_fck = {
-	.name		= "mcbsp3_fck",
+static struct clk func_mcbsp3_gfclk = {
+	.name		= "func_mcbsp3_gfclk",
 	.parent		= &mcbsp3_sync_mux_ck,
 	.clksel		= func_mcbsp3_gfclk_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
-
-static const struct clksel mcbsp4_sync_mux_sel[] = {
-	{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
-	{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk mcbsp4_sync_mux_ck = {
-	.name		= "mcbsp4_sync_mux_ck",
-	.parent		= &func_96m_fclk,
-	.clksel		= mcbsp4_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
 	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
 };
 
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
+static const struct clksel hsi_fclk_div[] = {
+	{ .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
 	{ .parent = NULL },
 };
 
-/* Merged per_mcbsp4_gfclk into mcbsp4 */
-static struct clk mcbsp4_fck = {
-	.name		= "mcbsp4_fck",
-	.parent		= &mcbsp4_sync_mux_ck,
-	.clksel		= per_mcbsp4_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_24_24_MASK,
-	.ops		= &clkops_omap2_dflt,
+static struct clk hsi_fclk = {
+	.name		= "hsi_fclk",
+	.parent		= &dpll_per_m2x2_ck,
+	.clksel		= hsi_fclk_div,
+	.clksel_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_24_25_MASK,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
-
-static struct clk mcpdm_fck = {
-	.name		= "mcpdm_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_PDM_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &pad_clks_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk mcspi1_fck = {
-	.name		= "mcspi1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk mcspi2_fck = {
-	.name		= "mcspi2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk mcspi3_fck = {
-	.name		= "mcspi3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk mcspi4_fck = {
-	.name		= "mcspi4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
+	.round_rate	= &omap2_clksel_round_rate,
+	.set_rate	= &omap2_clksel_set_rate,
 };
 
 static const struct clksel hsmmc1_fclk_sel[] = {
@@ -2000,335 +1950,94 @@ static const struct clksel hsmmc1_fclk_sel[] = {
 	{ .parent = NULL },
 };
 
-/* Merged hsmmc1_fclk into mmc1 */
-static struct clk mmc1_fck = {
-	.name		= "mmc1_fck",
+static struct clk hsmmc1_fclk = {
+	.name		= "hsmmc1_fclk",
 	.parent		= &func_64m_fclk,
 	.clksel		= hsmmc1_fclk_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
 };
 
-/* Merged hsmmc2_fclk into mmc2 */
-static struct clk mmc2_fck = {
-	.name		= "mmc2_fck",
+static struct clk hsmmc2_fclk = {
+	.name		= "hsmmc2_fclk",
 	.parent		= &func_64m_fclk,
 	.clksel		= hsmmc1_fclk_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-};
-
-static struct clk mmc3_fck = {
-	.name		= "mmc3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk mmc4_fck = {
-	.name		= "mmc4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk mmc5_fck = {
-	.name		= "mmc5_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk ocp2scp_usb_phy_phy_48m = {
-	.name		= "ocp2scp_usb_phy_phy_48m",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk ocp2scp_usb_phy_ick = {
-	.name		= "ocp2scp_usb_phy_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk ocp_wp_noc_ick = {
-	.name		= "ocp_wp_noc_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_instr_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk rng_ick = {
-	.name		= "rng_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_RNG_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk sha2md5_fck = {
-	.name		= "sha2md5_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk sl2if_ick = {
-	.name		= "sl2if_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5x2_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus1_fclk_1 = {
-	.name		= "slimbus1_fclk_1",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &func_24m_clk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus1_fclk_0 = {
-	.name		= "slimbus1_fclk_0",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &abe_24m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus1_fclk_2 = {
-	.name		= "slimbus1_fclk_2",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &pad_clks_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus1_slimbus_clk = {
-	.name		= "slimbus1_slimbus_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &slimbus_clk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus1_fck = {
-	.name		= "slimbus1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &ocp_abe_iclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus2_fclk_1 = {
-	.name		= "slimbus2_fclk_1",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &per_abe_24m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus2_fclk_0 = {
-	.name		= "slimbus2_fclk_0",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_24mc_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus2_slimbus_clk = {
-	.name		= "slimbus2_slimbus_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &pad_slimbus_core_clks_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk slimbus2_fck = {
-	.name		= "slimbus2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk smartreflex_core_fck = {
-	.name		= "smartreflex_core_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk smartreflex_iva_fck = {
-	.name		= "smartreflex_iva_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
 };
 
-static struct clk smartreflex_mpu_fck = {
-	.name		= "smartreflex_mpu_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
+static const struct clksel mcbsp4_sync_mux_sel[] = {
+	{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
+	{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
+	{ .parent = NULL },
 };
 
-/* Merged dmt1_clk_mux into timer1 */
-static struct clk timer1_fck = {
-	.name		= "timer1_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
+static struct clk mcbsp4_sync_mux_ck = {
+	.name		= "mcbsp4_sync_mux_ck",
+	.parent		= &func_96m_fclk,
+	.clksel		= mcbsp4_sync_mux_sel,
 	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
 };
 
-/* Merged cm2_dm10_mux into timer10 */
-static struct clk timer10_fck = {
-	.name		= "timer10_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
+static const struct clksel per_mcbsp4_gfclk_sel[] = {
+	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
+	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
+	{ .parent = NULL },
 };
 
-/* Merged cm2_dm11_mux into timer11 */
-static struct clk timer11_fck = {
-	.name		= "timer11_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
+static struct clk per_mcbsp4_gfclk = {
+	.name		= "per_mcbsp4_gfclk",
+	.parent		= &mcbsp4_sync_mux_ck,
+	.clksel		= per_mcbsp4_gfclk_sel,
 	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_24_24_MASK,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
 };
 
-/* Merged cm2_dm2_mux into timer2 */
-static struct clk timer2_fck = {
-	.name		= "timer2_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
+static const struct clksel sgx_clk_mux_sel[] = {
+	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
+	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
+	{ .parent = NULL },
 };
 
-/* Merged cm2_dm3_mux into timer3 */
-static struct clk timer3_fck = {
-	.name		= "timer3_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
+static struct clk sgx_clk_mux_ck = {
+	.name		= "sgx_clk_mux_ck",
+	.parent		= &dpll_core_m7x2_ck,
+	.clksel		= sgx_clk_mux_sel,
 	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.clksel_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_SGX_FCLK_MASK,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
 };
 
-/* Merged cm2_dm4_mux into timer4 */
-static struct clk timer4_fck = {
-	.name		= "timer4_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+static const struct clksel stm_clk_div_div[] = {
+	{ .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
+	{ .parent = NULL },
+};
+
+static struct clk stm_clk_div_ck = {
+	.name		= "stm_clk_div_ck",
+	.parent		= &pmd_stm_clock_mux_ck,
+	.clksel		= stm_clk_div_div,
+	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+	.clksel_mask	= OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
+	.round_rate	= &omap2_clksel_round_rate,
+	.set_rate	= &omap2_clksel_set_rate,
 };
 
 static const struct clksel timer5_sync_mux_sel[] = {
@@ -2337,420 +2046,48 @@ static const struct clksel timer5_sync_mux_sel[] = {
 	{ .parent = NULL },
 };
 
-/* Merged timer5_sync_mux into timer5 */
-static struct clk timer5_fck = {
-	.name		= "timer5_fck",
+static struct clk timer5_sync_mux_ck = {
+	.name		= "timer5_sync_mux_ck",
 	.parent		= &syc_clk_div_ck,
 	.clksel		= timer5_sync_mux_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
 };
 
-/* Merged timer6_sync_mux into timer6 */
-static struct clk timer6_fck = {
-	.name		= "timer6_fck",
+static struct clk timer6_sync_mux_ck = {
+	.name		= "timer6_sync_mux_ck",
 	.parent		= &syc_clk_div_ck,
 	.clksel		= timer5_sync_mux_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
 };
 
-/* Merged timer7_sync_mux into timer7 */
-static struct clk timer7_fck = {
-	.name		= "timer7_fck",
+static struct clk timer7_sync_mux_ck = {
+	.name		= "timer7_sync_mux_ck",
 	.parent		= &syc_clk_div_ck,
 	.clksel		= timer5_sync_mux_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
 };
 
-/* Merged timer8_sync_mux into timer8 */
-static struct clk timer8_fck = {
-	.name		= "timer8_fck",
+static struct clk timer8_sync_mux_ck = {
+	.name		= "timer8_sync_mux_ck",
 	.parent		= &syc_clk_div_ck,
 	.clksel		= timer5_sync_mux_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
-
-/* Merged cm2_dm9_mux into timer9 */
-static struct clk timer9_fck = {
-	.name		= "timer9_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
-
-static struct clk uart1_fck = {
-	.name		= "uart1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk uart2_fck = {
-	.name		= "uart2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk uart3_fck = {
-	.name		= "uart3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk uart4_fck = {
-	.name		= "uart4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_host_fs_fck = {
-	.name		= "usb_host_fs_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48mc_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static const struct clksel utmi_p1_gfclk_sel[] = {
-	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
-	{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk utmi_p1_gfclk = {
-	.name		= "utmi_p1_gfclk",
-	.parent		= &init_60m_fclk,
-	.clksel		= utmi_p1_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P1_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
-
-static struct clk usb_host_hs_utmi_p1_clk = {
-	.name		= "usb_host_hs_utmi_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &utmi_p1_gfclk,
-	.recalc		= &followparent_recalc,
-};
-
-static const struct clksel utmi_p2_gfclk_sel[] = {
-	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
-	{ .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk utmi_p2_gfclk = {
-	.name		= "utmi_p2_gfclk",
-	.parent		= &init_60m_fclk,
-	.clksel		= utmi_p2_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P2_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
-
-static struct clk usb_host_hs_utmi_p2_clk = {
-	.name		= "usb_host_hs_utmi_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &utmi_p2_gfclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_host_hs_utmi_p3_clk = {
-	.name		= "usb_host_hs_utmi_p3_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic480m_p1_clk = {
-	.name		= "usb_host_hs_hsic480m_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &dpll_usb_m2_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic60m_p1_clk = {
-	.name		= "usb_host_hs_hsic60m_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic60m_p2_clk = {
-	.name		= "usb_host_hs_hsic60m_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic480m_p2_clk = {
-	.name		= "usb_host_hs_hsic480m_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &dpll_usb_m2_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_host_hs_func48mclk = {
-	.name		= "usb_host_hs_func48mclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48mc_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_host_hs_fck = {
-	.name		= "usb_host_hs_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static const struct clksel otg_60m_gfclk_sel[] = {
-	{ .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
-	{ .parent = &xclk60motg_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk otg_60m_gfclk = {
-	.name		= "otg_60m_gfclk",
-	.parent		= &utmi_phy_clkout_ck,
-	.clksel		= otg_60m_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_60M_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
-
-static struct clk usb_otg_hs_xclk = {
-	.name		= "usb_otg_hs_xclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_XCLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &otg_60m_gfclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_otg_hs_ick = {
-	.name		= "usb_otg_hs_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_phy_cm_clk32k = {
-	.name		= "usb_phy_cm_clk32k",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_tll_hs_usb_ch2_clk = {
-	.name		= "usb_tll_hs_usb_ch2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_tll_hs_usb_ch0_clk = {
-	.name		= "usb_tll_hs_usb_ch0_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_tll_hs_usb_ch1_clk = {
-	.name		= "usb_tll_hs_usb_ch1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usb_tll_hs_ick = {
-	.name		= "usb_tll_hs_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static const struct clksel_rate div2_14to18_rates[] = {
-	{ .div = 14, .val = 0, .flags = RATE_IN_44XX },
-	{ .div = 18, .val = 1, .flags = RATE_IN_44XX },
-	{ .div = 0 },
-};
-
-static const struct clksel usim_fclk_div[] = {
-	{ .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
-	{ .parent = NULL },
-};
-
-static struct clk usim_ck = {
-	.name		= "usim_ck",
-	.parent		= &dpll_per_m4x2_ck,
-	.clksel		= usim_fclk_div,
-	.clksel_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_DIV_MASK,
 	.ops		= &clkops_null,
 	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
-
-static struct clk usim_fclk = {
-	.name		= "usim_fclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &usim_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk usim_fck = {
-	.name		= "usim_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk wd_timer2_fck = {
-	.name		= "wd_timer2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_WDT2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static struct clk wd_timer3_fck = {
-	.name		= "wd_timer3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_WDT3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
-
-static const struct clksel stm_clk_div_div[] = {
-	{ .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk stm_clk_div_ck = {
-	.name		= "stm_clk_div_ck",
-	.parent		= &pmd_stm_clock_mux_ck,
-	.clksel		= stm_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
 };
 
 static const struct clksel trace_clk_div_div[] = {
@@ -3145,130 +2482,73 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"pmd_stm_clock_mux_ck",		&pmd_stm_clock_mux_ck,	CK_44XX),
 	CLK(NULL,	"pmd_trace_clk_mux_ck",		&pmd_trace_clk_mux_ck,	CK_44XX),
 	CLK(NULL,	"syc_clk_div_ck",		&syc_clk_div_ck,	CK_44XX),
-	CLK(NULL,	"aes1_fck",			&aes1_fck,	CK_44XX),
-	CLK(NULL,	"aes2_fck",			&aes2_fck,	CK_44XX),
-	CLK(NULL,	"aess_fck",			&aess_fck,	CK_44XX),
 	CLK(NULL,	"bandgap_fclk",			&bandgap_fclk,	CK_44XX),
-	CLK(NULL,	"des3des_fck",			&des3des_fck,	CK_44XX),
-	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck,	CK_44XX),
-	CLK(NULL,	"dmic_fck",			&dmic_fck,	CK_44XX),
-	CLK(NULL,	"dsp_fck",			&dsp_fck,	CK_44XX),
+	CLK("omapdss_dss",	"video_clk",		&dss_48mhz_clk,	CK_44XX),
+	CLK("omapdss_dss",	"fck",			&dss_dss_clk,	CK_44XX),
 	CLK("omapdss_dss",	"sys_clk",		&dss_sys_clk,	CK_44XX),
 	CLK("omapdss_dss",	"tv_clk",		&dss_tv_clk,	CK_44XX),
-	CLK("omapdss_dss",	"fck",			&dss_dss_clk,	CK_44XX),
-	CLK("omapdss_dss",	"video_clk",		&dss_48mhz_clk,	CK_44XX),
-	CLK("omapdss_dss",	"ick",			&dss_fck,	CK_44XX),
-	CLK(NULL,	"efuse_ctrl_cust_fck",		&efuse_ctrl_cust_fck,	CK_44XX),
-	CLK(NULL,	"emif1_fck",			&emif1_fck,	CK_44XX),
-	CLK(NULL,	"emif2_fck",			&emif2_fck,	CK_44XX),
-	CLK(NULL,	"fdif_fck",			&fdif_fck,	CK_44XX),
-	CLK(NULL,	"fpka_fck",			&fpka_fck,	CK_44XX),
 	CLK(NULL,	"gpio1_dbclk",			&gpio1_dbclk,	CK_44XX),
-	CLK(NULL,	"gpio1_ick",			&gpio1_ick,	CK_44XX),
 	CLK(NULL,	"gpio2_dbclk",			&gpio2_dbclk,	CK_44XX),
-	CLK(NULL,	"gpio2_ick",			&gpio2_ick,	CK_44XX),
 	CLK(NULL,	"gpio3_dbclk",			&gpio3_dbclk,	CK_44XX),
-	CLK(NULL,	"gpio3_ick",			&gpio3_ick,	CK_44XX),
 	CLK(NULL,	"gpio4_dbclk",			&gpio4_dbclk,	CK_44XX),
-	CLK(NULL,	"gpio4_ick",			&gpio4_ick,	CK_44XX),
 	CLK(NULL,	"gpio5_dbclk",			&gpio5_dbclk,	CK_44XX),
-	CLK(NULL,	"gpio5_ick",			&gpio5_ick,	CK_44XX),
 	CLK(NULL,	"gpio6_dbclk",			&gpio6_dbclk,	CK_44XX),
-	CLK(NULL,	"gpio6_ick",			&gpio6_ick,	CK_44XX),
-	CLK(NULL,	"gpmc_ick",			&gpmc_ick,	CK_44XX),
-	CLK(NULL,	"gpu_fck",			&gpu_fck,	CK_44XX),
-	CLK("omap2_hdq.0",	"fck",			&hdq1w_fck,	CK_44XX),
-	CLK(NULL,	"hsi_fck",			&hsi_fck,	CK_44XX),
-	CLK("omap_i2c.1",	"fck",			&i2c1_fck,	CK_44XX),
-	CLK("omap_i2c.2",	"fck",			&i2c2_fck,	CK_44XX),
-	CLK("omap_i2c.3",	"fck",			&i2c3_fck,	CK_44XX),
-	CLK("omap_i2c.4",	"fck",			&i2c4_fck,	CK_44XX),
-	CLK(NULL,	"ipu_fck",			&ipu_fck,	CK_44XX),
 	CLK(NULL,	"iss_ctrlclk",			&iss_ctrlclk,	CK_44XX),
-	CLK(NULL,	"iss_fck",			&iss_fck,	CK_44XX),
-	CLK(NULL,	"iva_fck",			&iva_fck,	CK_44XX),
-	CLK(NULL,	"kbd_fck",			&kbd_fck,	CK_44XX),
-	CLK(NULL,	"l3_instr_ick",			&l3_instr_ick,	CK_44XX),
-	CLK(NULL,	"l3_main_3_ick",		&l3_main_3_ick,	CK_44XX),
-	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck,	CK_44XX),
-	CLK(NULL,	"mcasp_fck",			&mcasp_fck,	CK_44XX),
-	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck,	CK_44XX),
-	CLK("omap-mcbsp.1",	"fck",			&mcbsp1_fck,	CK_44XX),
-	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck,	CK_44XX),
-	CLK("omap-mcbsp.2",	"fck",			&mcbsp2_fck,	CK_44XX),
-	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck,	CK_44XX),
-	CLK("omap-mcbsp.3",	"fck",			&mcbsp3_fck,	CK_44XX),
-	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck,	CK_44XX),
-	CLK("omap-mcbsp.4",	"fck",			&mcbsp4_fck,	CK_44XX),
-	CLK(NULL,	"mcpdm_fck",			&mcpdm_fck,	CK_44XX),
-	CLK("omap2_mcspi.1",	"fck",			&mcspi1_fck,	CK_44XX),
-	CLK("omap2_mcspi.2",	"fck",			&mcspi2_fck,	CK_44XX),
-	CLK("omap2_mcspi.3",	"fck",			&mcspi3_fck,	CK_44XX),
-	CLK("omap2_mcspi.4",	"fck",			&mcspi4_fck,	CK_44XX),
-	CLK("omap_hsmmc.0",	"fck",			&mmc1_fck,	CK_44XX),
-	CLK("omap_hsmmc.1",	"fck",			&mmc2_fck,	CK_44XX),
-	CLK("omap_hsmmc.2",	"fck",			&mmc3_fck,	CK_44XX),
-	CLK("omap_hsmmc.3",	"fck",			&mmc4_fck,	CK_44XX),
-	CLK("omap_hsmmc.4",	"fck",			&mmc5_fck,	CK_44XX),
-	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m,	CK_44XX),
-	CLK(NULL,	"ocp2scp_usb_phy_ick",		&ocp2scp_usb_phy_ick,	CK_44XX),
-	CLK(NULL,	"ocp_wp_noc_ick",		&ocp_wp_noc_ick,	CK_44XX),
-	CLK("omap_rng",	"ick",				&rng_ick,	CK_44XX),
-	CLK(NULL,	"sha2md5_fck",			&sha2md5_fck,	CK_44XX),
-	CLK(NULL,	"sl2if_ick",			&sl2if_ick,	CK_44XX),
-	CLK(NULL,	"slimbus1_fclk_1",		&slimbus1_fclk_1,	CK_44XX),
-	CLK(NULL,	"slimbus1_fclk_0",		&slimbus1_fclk_0,	CK_44XX),
-	CLK(NULL,	"slimbus1_fclk_2",		&slimbus1_fclk_2,	CK_44XX),
+	CLK(NULL,	"ocp2scp_usb_phy_phy_48m_ck",	&ocp2scp_usb_phy_phy_48m_ck,	CK_44XX),
+	CLK(NULL,	"slimbus1_fclk_0_ck",		&slimbus1_fclk_0_ck,	CK_44XX),
+	CLK(NULL,	"slimbus1_fclk_1_ck",		&slimbus1_fclk_1_ck,	CK_44XX),
+	CLK(NULL,	"slimbus1_fclk_2_ck",		&slimbus1_fclk_2_ck,	CK_44XX),
 	CLK(NULL,	"slimbus1_slimbus_clk",		&slimbus1_slimbus_clk,	CK_44XX),
-	CLK(NULL,	"slimbus1_fck",			&slimbus1_fck,	CK_44XX),
-	CLK(NULL,	"slimbus2_fclk_1",		&slimbus2_fclk_1,	CK_44XX),
-	CLK(NULL,	"slimbus2_fclk_0",		&slimbus2_fclk_0,	CK_44XX),
+	CLK(NULL,	"slimbus2_fclk_0_ck",		&slimbus2_fclk_0_ck,	CK_44XX),
+	CLK(NULL,	"slimbus2_fclk_1_ck",		&slimbus2_fclk_1_ck,	CK_44XX),
 	CLK(NULL,	"slimbus2_slimbus_clk",		&slimbus2_slimbus_clk,	CK_44XX),
-	CLK(NULL,	"slimbus2_fck",			&slimbus2_fck,	CK_44XX),
-	CLK(NULL,	"smartreflex_core_fck",		&smartreflex_core_fck,	CK_44XX),
-	CLK(NULL,	"smartreflex_iva_fck",		&smartreflex_iva_fck,	CK_44XX),
-	CLK(NULL,	"smartreflex_mpu_fck",		&smartreflex_mpu_fck,	CK_44XX),
-	CLK(NULL,	"gpt1_fck",			&timer1_fck,	CK_44XX),
-	CLK(NULL,	"gpt10_fck",			&timer10_fck,	CK_44XX),
-	CLK(NULL,	"gpt11_fck",			&timer11_fck,	CK_44XX),
-	CLK(NULL,	"gpt2_fck",			&timer2_fck,	CK_44XX),
-	CLK(NULL,	"gpt3_fck",			&timer3_fck,	CK_44XX),
-	CLK(NULL,	"gpt4_fck",			&timer4_fck,	CK_44XX),
-	CLK(NULL,	"gpt5_fck",			&timer5_fck,	CK_44XX),
-	CLK(NULL,	"gpt6_fck",			&timer6_fck,	CK_44XX),
-	CLK(NULL,	"gpt7_fck",			&timer7_fck,	CK_44XX),
-	CLK(NULL,	"gpt8_fck",			&timer8_fck,	CK_44XX),
-	CLK(NULL,	"gpt9_fck",			&timer9_fck,	CK_44XX),
-	CLK(NULL,	"uart1_fck",			&uart1_fck,	CK_44XX),
-	CLK(NULL,	"uart2_fck",			&uart2_fck,	CK_44XX),
-	CLK(NULL,	"uart3_fck",			&uart3_fck,	CK_44XX),
-	CLK(NULL,	"uart4_fck",			&uart4_fck,	CK_44XX),
-	CLK("usbhs-omap.0",	"fs_fck",		&usb_host_fs_fck,	CK_44XX),
+	CLK(NULL,	"usb_host_hs_func48mclk_ck",	&usb_host_hs_func48mclk_ck,	CK_44XX),
+	CLK(NULL,	"usb_host_hs_hsic480m_p1_clk",	&usb_host_hs_hsic480m_p1_clk,	CK_44XX),
+	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk,	CK_44XX),
+	CLK(NULL,	"usb_host_hs_hsic60m_p1_clk",	&usb_host_hs_hsic60m_p1_clk,	CK_44XX),
+	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk,	CK_44XX),
 	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk,	CK_44XX),
 	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk,	CK_44XX),
 	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk,	CK_44XX),
 	CLK(NULL,	"usb_host_hs_utmi_p2_clk",	&usb_host_hs_utmi_p2_clk,	CK_44XX),
 	CLK(NULL,	"usb_host_hs_utmi_p3_clk",	&usb_host_hs_utmi_p3_clk,	CK_44XX),
-	CLK(NULL,	"usb_host_hs_hsic480m_p1_clk",	&usb_host_hs_hsic480m_p1_clk,	CK_44XX),
-	CLK(NULL,	"usb_host_hs_hsic60m_p1_clk",	&usb_host_hs_hsic60m_p1_clk,	CK_44XX),
-	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk,	CK_44XX),
-	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk,	CK_44XX),
-	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk,	CK_44XX),
-	CLK("usbhs-omap.0",	"hs_fck",		&usb_host_hs_fck,	CK_44XX),
 	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk,	CK_44XX),
 	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk,	CK_44XX),
-	CLK("musb-omap2430",	"ick",			&usb_otg_hs_ick,	CK_44XX),
-	CLK(NULL,	"usb_phy_cm_clk32k",		&usb_phy_cm_clk32k,	CK_44XX),
-	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk,	CK_44XX),
+	CLK(NULL,	"usb_phy_cm_clk32k_ck",		&usb_phy_cm_clk32k_ck,	CK_44XX),
 	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk,	CK_44XX),
 	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk,	CK_44XX),
-	CLK("usbhs-omap.0",	"usbtll_ick",		&usb_tll_hs_ick,	CK_44XX),
-	CLK(NULL,	"usim_ck",			&usim_ck,	CK_44XX),
+	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk,	CK_44XX),
 	CLK(NULL,	"usim_fclk",			&usim_fclk,	CK_44XX),
-	CLK(NULL,	"usim_fck",			&usim_fck,	CK_44XX),
-	CLK("omap_wdt",	"fck",				&wd_timer2_fck,	CK_44XX),
-	CLK(NULL,	"wd_timer3_fck",		&wd_timer3_fck,	CK_44XX),
+	CLK(NULL,	"usim_clk",			&usim_clk,	CK_44XX),
+	CLK(NULL,	"cm2_dm10_mux_ck",		&cm2_dm10_mux_ck,	CK_44XX),
+	CLK(NULL,	"cm2_dm11_mux_ck",		&cm2_dm11_mux_ck,	CK_44XX),
+	CLK(NULL,	"cm2_dm2_mux_ck",		&cm2_dm2_mux_ck,	CK_44XX),
+	CLK(NULL,	"cm2_dm3_mux_ck",		&cm2_dm3_mux_ck,	CK_44XX),
+	CLK(NULL,	"cm2_dm4_mux_ck",		&cm2_dm4_mux_ck,	CK_44XX),
+	CLK(NULL,	"cm2_dm9_mux_ck",		&cm2_dm9_mux_ck,	CK_44XX),
+	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"dmt1_clk_mux_ck",		&dmt1_clk_mux_ck,	CK_44XX),
+	CLK(NULL,	"fdif_fclk",			&fdif_fclk,	CK_44XX),
+	CLK(NULL,	"func_dmic_abe_gfclk",		&func_dmic_abe_gfclk,	CK_44XX),
+	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"func_mcasp_abe_gfclk",		&func_mcasp_abe_gfclk,	CK_44XX),
+	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"func_mcbsp1_gfclk",		&func_mcbsp1_gfclk,	CK_44XX),
+	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"func_mcbsp2_gfclk",		&func_mcbsp2_gfclk,	CK_44XX),
+	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"func_mcbsp3_gfclk",		&func_mcbsp3_gfclk,	CK_44XX),
+	CLK(NULL,	"hsi_fclk",			&hsi_fclk,	CK_44XX),
+	CLK(NULL,	"hsmmc1_fclk",			&hsmmc1_fclk,	CK_44XX),
+	CLK(NULL,	"hsmmc2_fclk",			&hsmmc2_fclk,	CK_44XX),
+	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"per_mcbsp4_gfclk",		&per_mcbsp4_gfclk,	CK_44XX),
+	CLK(NULL,	"sgx_clk_mux_ck",		&sgx_clk_mux_ck,	CK_44XX),
 	CLK(NULL,	"stm_clk_div_ck",		&stm_clk_div_ck,	CK_44XX),
+	CLK(NULL,	"gpt5_sync_mux_ck",		&timer5_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"gpt6_sync_mux_ck",		&timer6_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"gpt7_sync_mux_ck",		&timer7_sync_mux_ck,	CK_44XX),
+	CLK(NULL,	"gpt8_sync_mux_ck",		&timer8_sync_mux_ck,	CK_44XX),
 	CLK(NULL,	"trace_clk_div_ck",		&trace_clk_div_ck,	CK_44XX),
 	CLK(NULL,	"auxclk0_src_ck",		&auxclk0_src_ck,	CK_44XX),
 	CLK(NULL,	"auxclk0_ck",			&auxclk0_ck,	CK_44XX),
-- 
1.7.0.4

[PATCH 6/7] OMAP4: hwmod data: TEMP: Fix timer1 main_clk

[Benoit Cousson]

Since the timer is still not pm_runtime adapted, it is still
using directly the physical clock nodes at init time.

Replace the clock node by the original one in the clock data
file.

Keep the original name until the driver is fixed.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock44xx_data.c       |   12 ++++++++----
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    2 +-
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 547f02b..f1cfa3c 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1765,15 +1765,19 @@ static struct clk dmic_sync_mux_ck = {
 	.recalc		= &omap2_clksel_recalc,
 };
 
-static struct clk dmt1_clk_mux_ck = {
-	.name		= "dmt1_clk_mux_ck",
+/* Merged dmt1_clk_mux into timer1 */
+static struct clk timer1_fck = {
+	.name		= "timer1_fck",
 	.parent		= &sys_clkin_ck,
 	.clksel		= abe_dpll_bypass_clk_mux_sel,
 	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
 	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap2_dflt,
 	.recalc		= &omap2_clksel_recalc,
+	.enable_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
+	.clkdm_name	= "l4_wkup_clkdm",
 };
 
 static const struct clksel fdif_fclk_div[] = {
@@ -2527,7 +2531,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"cm2_dm4_mux_ck",		&cm2_dm4_mux_ck,	CK_44XX),
 	CLK(NULL,	"cm2_dm9_mux_ck",		&cm2_dm9_mux_ck,	CK_44XX),
 	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck,	CK_44XX),
-	CLK(NULL,	"dmt1_clk_mux_ck",		&dmt1_clk_mux_ck,	CK_44XX),
+	CLK(NULL,	"gpt1_fck",			&timer1_fck,	CK_44XX),
 	CLK(NULL,	"fdif_fclk",			&fdif_fclk,	CK_44XX),
 	CLK(NULL,	"func_dmic_abe_gfclk",		&func_dmic_abe_gfclk,	CK_44XX),
 	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck,	CK_44XX),
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 5c196a1..729b371 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -4249,7 +4249,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
 	.clkdm_name	= "l4_wkup_clkdm",
 	.mpu_irqs	= omap44xx_timer1_irqs,
 	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_timer1_irqs),
-	.main_clk	= "dmt1_clk_mux_ck",
+	.main_clk	= "timer1_fck",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
-- 
1.7.0.4

Re: [PATCH 6/7] OMAP4: hwmod data: TEMP: Fix timer1 main_clk

[Kevin Hilman]

Benoit Cousson <b-cousson@ti.com> writes:

> Since the timer is still not pm_runtime adapted, it is still
> using directly the physical clock nodes at init time.
>
> Replace the clock node by the original one in the clock data
> file.
>
> Keep the original name until the driver is fixed.

Is this still needed when used with Tony's devel-timer branch?  

I assume not.

Kevin

Re: [PATCH 6/7] OMAP4: hwmod data: TEMP: Fix timer1 main_clk

[Cousson, Benoit]

On 6/28/2011 2:19 AM, Hilman, Kevin wrote:
> Benoit Cousson<b-cousson@ti.com>  writes:
> 
>> Since the timer is still not pm_runtime adapted, it is still
>> using directly the physical clock nodes at init time.
>>
>> Replace the clock node by the original one in the clock data
>> file.
>>
>> Keep the original name until the driver is fixed.
> 
> Is this still needed when used with Tony's devel-timer branch?

I didn't follow what Tony did, but I'm not sure he is fixing that part.
 
> I assume not.

After checking the new timer.c file, we still have the problematic part. Only the migration to hwmod will fix that:

static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
						int gptimer_id,
						const char *fck_source)
{

[...]

	/* After the dmtimer is using hwmod these clocks won't be needed */
	sprintf(name, "gpt%d_fck", gptimer_id);
	timer->fclk = clk_get(NULL, name);
	if (IS_ERR(timer->fclk))
		return -ENODEV;

	sprintf(name, "gpt%d_ick", gptimer_id);
	timer->iclk = clk_get(NULL, name);
	if (IS_ERR(timer->iclk)) {
		clk_put(timer->fclk);
		return -ENODEV;
	}

There is even a comment that confirm the issue:-)

Regards,
Benoit

Re: [PATCH 6/7] OMAP4: hwmod data: TEMP: Fix timer1 main_clk

[Kevin Hilman]

"Cousson, Benoit" <b-cousson@ti.com> writes:

> On 6/28/2011 2:19 AM, Hilman, Kevin wrote:
>> Benoit Cousson<b-cousson@ti.com>  writes:
>> 
>>> Since the timer is still not pm_runtime adapted, it is still
>>> using directly the physical clock nodes at init time.
>>>
>>> Replace the clock node by the original one in the clock data
>>> file.
>>>
>>> Keep the original name until the driver is fixed.
>> 
>> Is this still needed when used with Tony's devel-timer branch?
>
> I didn't follow what Tony did, but I'm not sure he is fixing that part.
>  
>> I assume not.
>
> After checking the new timer.c file, we still have the problematic part. Only the migration to hwmod will fix that:
>
> static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
> 						int gptimer_id,
> 						const char *fck_source)
> {
>
> [...]
>
> 	/* After the dmtimer is using hwmod these clocks won't be needed */
> 	sprintf(name, "gpt%d_fck", gptimer_id);
> 	timer->fclk = clk_get(NULL, name);
> 	if (IS_ERR(timer->fclk))
> 		return -ENODEV;
>
> 	sprintf(name, "gpt%d_ick", gptimer_id);
> 	timer->iclk = clk_get(NULL, name);
> 	if (IS_ERR(timer->iclk)) {
> 		clk_put(timer->fclk);
> 		return -ENODEV;
> 	}
>
> There is even a comment that confirm the issue:-)

Well, I'm not sure that comment is correct either.

Tony's series converts the driver to use hwmod.  The problem is the
clocks are still needed for changing the parent, so there is still
a clk_disable, clk_set_parent, clk_enable sequence used.

Kevin

[PATCH 7/7] OMAP4: prcm: Remove macros with absolute address

[Benoit Cousson]

Remove partially macros using the absolute address.
The new API should use the XXXX_OFFSET version.

Keep some macros since the clock nodes are still
relying on them.

Once the clocks will be cleaned, all these remaining
macros will be removed.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/cm1_44xx.h |   24 ----
 arch/arm/mach-omap2/cm2_44xx.h |   55 --------
 arch/arm/mach-omap2/prm44xx.h  |  269 ----------------------------------------
 3 files changed, 0 insertions(+), 348 deletions(-)

diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 1bc00dc..31d90a5 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -49,7 +49,6 @@
 
 /* CM1.OCP_SOCKET_CM1 register offsets */
 #define OMAP4_REVISION_CM1_OFFSET			0x0000
-#define OMAP4430_REVISION_CM1				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
 #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET		0x0040
 #define OMAP4430_CM_CM1_PROFILING_CLKCTRL		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
 
@@ -59,7 +58,6 @@
 #define OMAP4_CM_CLKSEL_ABE_OFFSET			0x0008
 #define OMAP4430_CM_CLKSEL_ABE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
 #define OMAP4_CM_DLL_CTRL_OFFSET			0x0010
-#define OMAP4430_CM_DLL_CTRL				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
 #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET		0x0020
 #define OMAP4430_CM_CLKMODE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
 #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET		0x0024
@@ -81,11 +79,8 @@
 #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET		0x0044
 #define OMAP4430_CM_DIV_M7_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0048
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x004c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
 #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET		0x0050
-#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
 #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET		0x0060
 #define OMAP4430_CM_CLKMODE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
 #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET			0x0064
@@ -97,9 +92,7 @@
 #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET			0x0070
 #define OMAP4430_CM_DIV_M2_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET		0x0088
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET		0x008c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
 #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET			0x009c
 #define OMAP4430_CM_BYPCLK_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
 #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET		0x00a0
@@ -115,9 +108,7 @@
 #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET			0x00bc
 #define OMAP4430_CM_DIV_M5_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET		0x00c8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET		0x00cc
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
 #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET			0x00dc
 #define OMAP4430_CM_BYPCLK_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
 #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET		0x00e0
@@ -133,9 +124,7 @@
 #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET			0x00f4
 #define OMAP4430_CM_DIV_M3_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET		0x0108
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET		0x010c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
 #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET		0x0120
 #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
 #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET		0x0124
@@ -153,41 +142,28 @@
 #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET		0x0140
 #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET	0x0148
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET	0x014c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
 #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET		0x0160
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG1			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
 #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET		0x0164
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG2			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
 #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET			0x0170
-#define OMAP4430_CM_DYN_DEP_PRESCAL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
 #define OMAP4_CM_RESTORE_ST_OFFSET			0x0180
-#define OMAP4430_CM_RESTORE_ST				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
 
 /* CM1.MPU_CM1 register offsets */
 #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_MPU_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
 #define OMAP4_CM_MPU_STATICDEP_OFFSET			0x0004
-#define OMAP4430_CM_MPU_STATICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
 #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET			0x0008
-#define OMAP4430_CM_MPU_DYNAMICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
 #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET			0x0020
 #define OMAP4430_CM_MPU_MPU_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
 
 /* CM1.TESLA_CM1 register offsets */
 #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_TESLA_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
 #define OMAP4_CM_TESLA_STATICDEP_OFFSET			0x0004
-#define OMAP4430_CM_TESLA_STATICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
 #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET		0x0008
-#define OMAP4430_CM_TESLA_DYNAMICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
 #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET		0x0020
 #define OMAP4430_CM_TESLA_TESLA_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
 
 /* CM1.ABE_CM1 register offsets */
 #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM1_ABE_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
 #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET		0x0020
 #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
 #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET		0x0028
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index 50a5771..bdc7026 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -69,7 +69,6 @@
 
 /* CM2.OCP_SOCKET_CM2 register offsets */
 #define OMAP4_REVISION_CM2_OFFSET			0x0000
-#define OMAP4430_REVISION_CM2				OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
 #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET		0x0040
 #define OMAP4430_CM_CM2_PROFILING_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
 
@@ -81,23 +80,14 @@
 #define OMAP4_CM_SCALE_FCLK_OFFSET			0x0008
 #define OMAP4430_CM_SCALE_FCLK				OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
 #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET			0x0010
-#define OMAP4430_CM_CORE_DVFS_PERF1			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
 #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET			0x0014
-#define OMAP4430_CM_CORE_DVFS_PERF2			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
 #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET			0x0018
-#define OMAP4430_CM_CORE_DVFS_PERF3			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
 #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET			0x001c
-#define OMAP4430_CM_CORE_DVFS_PERF4			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
 #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET		0x0024
-#define OMAP4430_CM_CORE_DVFS_CURRENT			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
 #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET		0x0028
-#define OMAP4430_CM_IVA_DVFS_PERF_TESLA			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
 #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET		0x002c
-#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
 #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET		0x0030
-#define OMAP4430_CM_IVA_DVFS_PERF_ABE			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
 #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET		0x0038
-#define OMAP4430_CM_IVA_DVFS_CURRENT			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
 #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET		0x0040
 #define OMAP4430_CM_CLKMODE_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
 #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET			0x0044
@@ -119,9 +109,7 @@
 #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET			0x0064
 #define OMAP4430_CM_DIV_M7_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET		0x0068
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x006c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
 #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET		0x0080
 #define OMAP4430_CM_CLKMODE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
 #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET			0x0084
@@ -133,9 +121,7 @@
 #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET			0x0090
 #define OMAP4430_CM_DIV_M2_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET		0x00a8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET		0x00ac
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
 #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET		0x00b4
 #define OMAP4430_CM_CLKDCOLDO_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
 #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET		0x00c0
@@ -149,13 +135,10 @@
 #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET		0x00d0
 #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET	0x00e8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET	0x00ec
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
 
 /* CM2.ALWAYS_ON_CM2 register offsets */
 #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_ALWON_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
 #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET		0x0028
 #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
 #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET		0x0030
@@ -167,15 +150,11 @@
 
 /* CM2.CORE_CM2 register offsets */
 #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_L3_1_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
 #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET			0x0008
-#define OMAP4430_CM_L3_1_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
 #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET		0x0020
 #define OMAP4430_CM_L3_1_L3_1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
 #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET			0x0100
-#define OMAP4430_CM_L3_2_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
 #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET			0x0108
-#define OMAP4430_CM_L3_2_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
 #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET		0x0120
 #define OMAP4430_CM_L3_2_L3_2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
 #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET		0x0128
@@ -183,23 +162,16 @@
 #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET		0x0130
 #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130)
 #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET		0x0200
-#define OMAP4430_CM_DUCATI_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200)
 #define OMAP4_CM_DUCATI_STATICDEP_OFFSET		0x0204
-#define OMAP4430_CM_DUCATI_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204)
 #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET		0x0208
-#define OMAP4430_CM_DUCATI_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208)
 #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET		0x0220
 #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220)
 #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET			0x0300
-#define OMAP4430_CM_SDMA_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300)
 #define OMAP4_CM_SDMA_STATICDEP_OFFSET			0x0304
-#define OMAP4430_CM_SDMA_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304)
 #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET			0x0308
-#define OMAP4430_CM_SDMA_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308)
 #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET		0x0320
 #define OMAP4430_CM_SDMA_SDMA_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320)
 #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET			0x0400
-#define OMAP4430_CM_MEMIF_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400)
 #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET		0x0420
 #define OMAP4430_CM_MEMIF_DMM_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420)
 #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET		0x0428
@@ -213,11 +185,8 @@
 #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET		0x0460
 #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460)
 #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET			0x0500
-#define OMAP4430_CM_D2D_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500)
 #define OMAP4_CM_D2D_STATICDEP_OFFSET			0x0504
-#define OMAP4430_CM_D2D_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504)
 #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET			0x0508
-#define OMAP4430_CM_D2D_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
 #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET		0x0520
 #define OMAP4430_CM_D2D_SAD2D_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
 #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET		0x0528
@@ -225,9 +194,7 @@
 #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET		0x0530
 #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
 #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET			0x0600
-#define OMAP4430_CM_L4CFG_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600)
 #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET		0x0608
-#define OMAP4430_CM_L4CFG_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608)
 #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET		0x0620
 #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620)
 #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET		0x0628
@@ -237,7 +204,6 @@
 #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET		0x0638
 #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638)
 #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET		0x0700
-#define OMAP4430_CM_L3INSTR_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700)
 #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET		0x0720
 #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720)
 #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET	0x0728
@@ -247,11 +213,8 @@
 
 /* CM2.IVAHD_CM2 register offsets */
 #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_IVAHD_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000)
 #define OMAP4_CM_IVAHD_STATICDEP_OFFSET			0x0004
-#define OMAP4430_CM_IVAHD_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004)
 #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET		0x0008
-#define OMAP4430_CM_IVAHD_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008)
 #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET		0x0020
 #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020)
 #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET		0x0028
@@ -259,11 +222,8 @@
 
 /* CM2.CAM_CM2 register offsets */
 #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_CAM_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000)
 #define OMAP4_CM_CAM_STATICDEP_OFFSET			0x0004
-#define OMAP4430_CM_CAM_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004)
 #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET			0x0008
-#define OMAP4430_CM_CAM_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008)
 #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET			0x0020
 #define OMAP4430_CM_CAM_ISS_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020)
 #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET		0x0028
@@ -271,31 +231,22 @@
 
 /* CM2.DSS_CM2 register offsets */
 #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_DSS_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000)
 #define OMAP4_CM_DSS_STATICDEP_OFFSET			0x0004
-#define OMAP4430_CM_DSS_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004)
 #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET			0x0008
-#define OMAP4430_CM_DSS_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008)
 #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET			0x0020
 #define OMAP4430_CM_DSS_DSS_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020)
 
 /* CM2.GFX_CM2 register offsets */
 #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_GFX_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000)
 #define OMAP4_CM_GFX_STATICDEP_OFFSET			0x0004
-#define OMAP4430_CM_GFX_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004)
 #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET			0x0008
-#define OMAP4430_CM_GFX_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008)
 #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET			0x0020
 #define OMAP4430_CM_GFX_GFX_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020)
 
 /* CM2.L3INIT_CM2 register offsets */
 #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET		0x0000
-#define OMAP4430_CM_L3INIT_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000)
 #define OMAP4_CM_L3INIT_STATICDEP_OFFSET		0x0004
-#define OMAP4430_CM_L3INIT_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004)
 #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET		0x0008
-#define OMAP4430_CM_L3INIT_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008)
 #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET		0x0028
 #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028)
 #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET		0x0030
@@ -315,9 +266,7 @@
 
 /* CM2.L4PER_CM2 register offsets */
 #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_L4PER_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000)
 #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET		0x0008
-#define OMAP4430_CM_L4PER_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008)
 #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET		0x0028
 #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028)
 #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET		0x0030
@@ -383,11 +332,8 @@
 #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET		0x0168
 #define OMAP4430_CM_L4PER_I2C5_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
 #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET			0x0180
-#define OMAP4430_CM_L4SEC_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
 #define OMAP4_CM_L4SEC_STATICDEP_OFFSET			0x0184
-#define OMAP4430_CM_L4SEC_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
 #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET		0x0188
-#define OMAP4430_CM_L4SEC_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
 #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET		0x01a0
 #define OMAP4430_CM_L4SEC_AES1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
 #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET		0x01a8
@@ -405,7 +351,6 @@
 
 /* CM2.CEFUSE_CM2 register offsets */
 #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
-#define OMAP4430_CM_CEFUSE_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
 
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index a3887b8..1b4cab3 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -72,23 +72,14 @@
 
 /* PRM.OCP_SOCKET_PRM register offsets */
 #define OMAP4_REVISION_PRM_OFFSET			0x0000
-#define OMAP4430_REVISION_PRM				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
 #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
-#define OMAP4430_PRM_IRQSTATUS_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
 #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
-#define OMAP4430_PRM_IRQSTATUS_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
 #define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
-#define OMAP4430_PRM_IRQENABLE_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
 #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
-#define OMAP4430_PRM_IRQENABLE_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
 #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
-#define OMAP4430_PRM_IRQSTATUS_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
 #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
-#define OMAP4430_PRM_IRQENABLE_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
 #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
-#define OMAP4430_PRM_IRQSTATUS_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
 #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
-#define OMAP4430_PRM_IRQENABLE_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
 #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
 #define OMAP4430_CM_PRM_PROFILING_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
 
@@ -104,415 +95,223 @@
 
 /* PRM.MPU_PRM register offsets */
 #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_MPU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
 #define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_MPU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
 #define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
-#define OMAP4430_RM_MPU_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
 #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
-#define OMAP4430_RM_MPU_MPU_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
 
 /* PRM.TESLA_PRM register offsets */
 #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_TESLA_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
 #define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_TESLA_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
 #define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
-#define OMAP4430_RM_TESLA_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
 #define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
-#define OMAP4430_RM_TESLA_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
 #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_TESLA_TESLA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
 
 /* PRM.ABE_PRM register offsets */
 #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_ABE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
 #define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_ABE_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
 #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_ABE_AESS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
 #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
-#define OMAP4430_PM_ABE_PDM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
 #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
-#define OMAP4430_RM_ABE_PDM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
 #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
-#define OMAP4430_PM_ABE_DMIC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
 #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_ABE_DMIC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
 #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
-#define OMAP4430_PM_ABE_MCASP_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
 #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
-#define OMAP4430_RM_ABE_MCASP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
 #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
-#define OMAP4430_PM_ABE_MCBSP1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
 #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
-#define OMAP4430_RM_ABE_MCBSP1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
 #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
-#define OMAP4430_PM_ABE_MCBSP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
 #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
-#define OMAP4430_RM_ABE_MCBSP2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
 #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
-#define OMAP4430_PM_ABE_MCBSP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
 #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
-#define OMAP4430_RM_ABE_MCBSP3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
 #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
-#define OMAP4430_PM_ABE_SLIMBUS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
 #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
-#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
 #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
-#define OMAP4430_PM_ABE_TIMER5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
 #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
-#define OMAP4430_RM_ABE_TIMER5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
 #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
-#define OMAP4430_PM_ABE_TIMER6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
 #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
-#define OMAP4430_RM_ABE_TIMER6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
 #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
-#define OMAP4430_PM_ABE_TIMER7_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
 #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
-#define OMAP4430_RM_ABE_TIMER7_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
 #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
-#define OMAP4430_PM_ABE_TIMER8_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
 #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
-#define OMAP4430_RM_ABE_TIMER8_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
 #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
-#define OMAP4430_PM_ABE_WDT3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
 #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
-#define OMAP4430_RM_ABE_WDT3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
 
 /* PRM.ALWAYS_ON_PRM register offsets */
 #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
-#define OMAP4430_PM_ALWON_SR_MPU_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
 #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
 #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
-#define OMAP4430_PM_ALWON_SR_IVA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
 #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
-#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
 #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
-#define OMAP4430_PM_ALWON_SR_CORE_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
 #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
 
 /* PRM.CORE_PRM register offsets */
 #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_CORE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
 #define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_CORE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
 #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_L3_1_L3_1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
 #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
-#define OMAP4430_RM_L3_2_L3_2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
 #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
-#define OMAP4430_RM_L3_2_GPMC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
 #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
-#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
 #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
-#define OMAP4430_RM_DUCATI_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
 #define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
-#define OMAP4430_RM_DUCATI_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
 #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
-#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
 #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
-#define OMAP4430_RM_SDMA_SDMA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
 #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
-#define OMAP4430_RM_MEMIF_DMM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
 #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
-#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
 #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
-#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
 #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
-#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
 #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
-#define OMAP4430_RM_MEMIF_DLL_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
 #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
-#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
 #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
-#define OMAP4430_RM_D2D_SAD2D_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
 #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
-#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
 #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
-#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
 #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
-#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
 #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
-#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
 #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
-#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
 #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
-#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
 #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
-#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
 #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
-#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
 #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
-#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
 
 /* PRM.IVAHD_PRM register offsets */
 #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_IVAHD_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
 #define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_IVAHD_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
 #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
-#define OMAP4430_RM_IVAHD_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
 #define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
-#define OMAP4430_RM_IVAHD_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
 #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
 #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_IVAHD_SL2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
 
 /* PRM.CAM_PRM register offsets */
 #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_CAM_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
 #define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_CAM_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
 #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
-#define OMAP4430_RM_CAM_ISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
 #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_CAM_FDIF_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
 
 /* PRM.DSS_PRM register offsets */
 #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_DSS_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
 #define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_DSS_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
 #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
-#define OMAP4430_PM_DSS_DSS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
 #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
-#define OMAP4430_RM_DSS_DSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
 
 /* PRM.GFX_PRM register offsets */
 #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_GFX_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
 #define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_GFX_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
 #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
-#define OMAP4430_RM_GFX_GFX_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
 
 /* PRM.L3INIT_PRM register offsets */
 #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
-#define OMAP4430_PM_L3INIT_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
 #define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_L3INIT_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
 #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
-#define OMAP4430_PM_L3INIT_MMC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
 #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_L3INIT_MMC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
 #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
-#define OMAP4430_PM_L3INIT_MMC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
 #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
-#define OMAP4430_RM_L3INIT_MMC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
 #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
-#define OMAP4430_PM_L3INIT_HSI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
 #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_L3INIT_HSI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
 #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
-#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
 #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
-#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
 #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
-#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
 #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
-#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
 #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
-#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
 #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
-#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
 #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
-#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
 #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
-#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
 #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
-#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
 
 /* PRM.L4PER_PRM register offsets */
 #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_L4PER_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
 #define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_L4PER_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
 #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
-#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
 #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
 #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
-#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
 #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
-#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
 #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
-#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
 #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
 #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
-#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
 #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
-#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
 #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
-#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
 #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
-#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
 #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
-#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
 #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
-#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
 #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
-#define OMAP4430_RM_L4PER_ELM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
 #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
-#define OMAP4430_PM_L4PER_GPIO2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
 #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
-#define OMAP4430_RM_L4PER_GPIO2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
 #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
-#define OMAP4430_PM_L4PER_GPIO3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
 #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
-#define OMAP4430_RM_L4PER_GPIO3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
 #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
-#define OMAP4430_PM_L4PER_GPIO4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
 #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
-#define OMAP4430_RM_L4PER_GPIO4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
 #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
-#define OMAP4430_PM_L4PER_GPIO5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
 #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
-#define OMAP4430_RM_L4PER_GPIO5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
 #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
-#define OMAP4430_PM_L4PER_GPIO6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
 #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
-#define OMAP4430_RM_L4PER_GPIO6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
 #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
-#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
 #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
-#define OMAP4430_PM_L4PER_I2C1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
 #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
-#define OMAP4430_RM_L4PER_I2C1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
 #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
-#define OMAP4430_PM_L4PER_I2C2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
 #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
-#define OMAP4430_RM_L4PER_I2C2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
 #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
-#define OMAP4430_PM_L4PER_I2C3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
 #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
-#define OMAP4430_RM_L4PER_I2C3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
 #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
-#define OMAP4430_PM_L4PER_I2C4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
 #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
-#define OMAP4430_RM_L4PER_I2C4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
 #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
-#define OMAP4430_RM_L4PER_L4_PER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
 #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
-#define OMAP4430_PM_L4PER_MCBSP4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
 #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
-#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
 #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
-#define OMAP4430_PM_L4PER_MCSPI1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
 #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
-#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
 #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
-#define OMAP4430_PM_L4PER_MCSPI2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
 #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
-#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
 #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
-#define OMAP4430_PM_L4PER_MCSPI3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
 #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
-#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
 #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
-#define OMAP4430_PM_L4PER_MCSPI4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
 #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
-#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
 #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
-#define OMAP4430_PM_L4PER_MMCSD3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
 #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
-#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
 #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
-#define OMAP4430_PM_L4PER_MMCSD4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
 #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
-#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
 #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
-#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
 #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
-#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
 #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
-#define OMAP4430_PM_L4PER_UART1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
 #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
-#define OMAP4430_RM_L4PER_UART1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
 #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
-#define OMAP4430_PM_L4PER_UART2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
 #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
-#define OMAP4430_RM_L4PER_UART2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
 #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
-#define OMAP4430_PM_L4PER_UART3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
 #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
-#define OMAP4430_RM_L4PER_UART3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
 #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
-#define OMAP4430_PM_L4PER_UART4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
 #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
-#define OMAP4430_RM_L4PER_UART4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
 #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
-#define OMAP4430_PM_L4PER_MMCSD5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
 #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
-#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
 #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
-#define OMAP4430_PM_L4PER_I2C5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
 #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
-#define OMAP4430_RM_L4PER_I2C5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
 #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
-#define OMAP4430_RM_L4SEC_AES1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
 #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
-#define OMAP4430_RM_L4SEC_AES2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
 #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
-#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
 #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
-#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
 #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
-#define OMAP4430_RM_L4SEC_RNG_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
 #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
-#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
 #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
-#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
 
 /* PRM.CEFUSE_PRM register offsets */
 #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
-#define OMAP4430_PM_CEFUSE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
 #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_CEFUSE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
 #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
 
 /* PRM.WKUP_PRM register offsets */
 #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
 #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
-#define OMAP4430_RM_WKUP_WDT1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
 #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
-#define OMAP4430_PM_WKUP_WDT2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
 #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
-#define OMAP4430_RM_WKUP_WDT2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
 #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
-#define OMAP4430_PM_WKUP_GPIO1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
 #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
-#define OMAP4430_RM_WKUP_GPIO1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
 #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
-#define OMAP4430_PM_WKUP_TIMER1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
 #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
-#define OMAP4430_RM_WKUP_TIMER1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
 #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
-#define OMAP4430_PM_WKUP_TIMER12_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
 #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
-#define OMAP4430_RM_WKUP_TIMER12_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
 #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
-#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
 #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
-#define OMAP4430_PM_WKUP_USIM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
 #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
-#define OMAP4430_RM_WKUP_USIM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
 #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
-#define OMAP4430_RM_WKUP_SARRAM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
 #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
-#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
 #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
-#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
 
 /* PRM.WKUP_CM register offsets */
 #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_WKUP_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
 #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
 #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
 #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
@@ -538,147 +337,79 @@
 
 /* PRM.EMU_PRM register offsets */
 #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
-#define OMAP4430_PM_EMU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
 #define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
-#define OMAP4430_PM_EMU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
 #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
-#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
 
 /* PRM.EMU_CM register offsets */
 #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
-#define OMAP4430_CM_EMU_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
 #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
-#define OMAP4430_CM_EMU_DYNAMICDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
 #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
 #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
 
 /* PRM.DEVICE_PRM register offsets */
 #define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
-#define OMAP4430_PRM_RSTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
 #define OMAP4_PRM_RSTST_OFFSET				0x0004
-#define OMAP4430_PRM_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
 #define OMAP4_PRM_RSTTIME_OFFSET			0x0008
-#define OMAP4430_PRM_RSTTIME				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
 #define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
-#define OMAP4430_PRM_CLKREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
 #define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
-#define OMAP4430_PRM_VOLTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
 #define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
-#define OMAP4430_PRM_PWRREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
 #define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
-#define OMAP4430_PRM_PSCON_COUNT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
 #define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
-#define OMAP4430_PRM_IO_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
 #define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
-#define OMAP4430_PRM_IO_PMCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
 #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
-#define OMAP4430_PRM_VOLTSETUP_WARMRESET		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
 #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
-#define OMAP4430_PRM_VOLTSETUP_CORE_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
 #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
-#define OMAP4430_PRM_VOLTSETUP_MPU_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
 #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
-#define OMAP4430_PRM_VOLTSETUP_IVA_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
 #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
-#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
 #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
-#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
 #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
-#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
 #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
-#define OMAP4430_PRM_VP_CORE_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
 #define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
-#define OMAP4430_PRM_VP_CORE_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
 #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
-#define OMAP4430_PRM_VP_CORE_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
 #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
-#define OMAP4430_PRM_VP_CORE_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
 #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
-#define OMAP4430_PRM_VP_CORE_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
 #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
-#define OMAP4430_PRM_VP_CORE_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
 #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
-#define OMAP4430_PRM_VP_MPU_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
 #define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
-#define OMAP4430_PRM_VP_MPU_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
 #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
-#define OMAP4430_PRM_VP_MPU_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
 #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
-#define OMAP4430_PRM_VP_MPU_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
 #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
-#define OMAP4430_PRM_VP_MPU_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
 #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
-#define OMAP4430_PRM_VP_MPU_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
 #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
-#define OMAP4430_PRM_VP_IVA_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
 #define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
-#define OMAP4430_PRM_VP_IVA_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
 #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
-#define OMAP4430_PRM_VP_IVA_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
 #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
-#define OMAP4430_PRM_VP_IVA_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
 #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
-#define OMAP4430_PRM_VP_IVA_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
 #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
-#define OMAP4430_PRM_VP_IVA_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
 #define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
-#define OMAP4430_PRM_VC_SMPS_SA				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
 #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
-#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
 #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
-#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
 #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
-#define OMAP4430_PRM_VC_VAL_BYPASS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
-#define OMAP4430_PRM_VC_CFG_CHANNEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
 #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
-#define OMAP4430_PRM_VC_CFG_I2C_MODE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
 #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
-#define OMAP4430_PRM_VC_CFG_I2C_CLK			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
 #define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
-#define OMAP4430_PRM_SRAM_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
 #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
-#define OMAP4430_PRM_SRAM_WKUP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
 #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
-#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
 #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
-#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
 #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
-#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
 #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
-#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
 #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
-#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
 #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
-#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
 #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
-#define OMAP4430_PRM_LDO_ABB_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
 #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
-#define OMAP4430_PRM_LDO_ABB_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
 #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
-#define OMAP4430_PRM_LDO_ABB_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
 #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
-#define OMAP4430_PRM_LDO_ABB_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
 #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET		0x00e0
-#define OMAP4430_PRM_LDO_BANDGAP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
 #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
-#define OMAP4430_PRM_DEVICE_OFF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
 #define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
-#define OMAP4430_PRM_PHASE1_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
 #define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
-#define OMAP4430_PRM_PHASE2A_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
 #define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
-#define OMAP4430_PRM_PHASE2B_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
 #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
-#define OMAP4430_PRM_MODEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
 #define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
-#define OMAP4430_PRM_VC_ERRST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
 
 /* Function prototypes */
 # ifndef __ASSEMBLER__
-- 
1.7.0.4

Re: [PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[Kevin Hilman]

Hi Benoit,

Benoit Cousson <b-cousson@ti.com> writes:

> Here is the second part of the modulemode series. 
> The goal here is to do the cleanup on the clock nodes and PRCM macros
> that are not needed anymore by the hwmod data.
> Some macros are still needed because of clock data. It should be removed
> once the clock data will be cleaned.
>
> Moreover, in order to get rid of static clkdev, omap_device is trying to
> create dynamically an "fck" alias if a main_clk is defined in hwmod data.
>
> As usual, because of drivers non-adapted to pm_runtime, some temp hacks
> are needed for both MMC and timer1.
> If the drivers are fixes before these series, these temp patches could be
> dropped.
>
> The series is based on for_3.0.1/5_hwmod_clkdm_fixes and tested
> on OMAP4430 ES2.1 + SDP. It should not affect OMAP2 & 3, but some testing
> are definitively needed.

Yes, more OMAP2/3 testing is needed.

I just posted a couple patches in response to this series for some
easy-to-fix boot problems for OMAP3, but it's still not booting for me
on OMAP3 (haven't tried OMAP2.)  I didn't debug this any further, but
wanted to report the problems. 

NOTE: I'm testing your for_3.0.1/6_hwmod_modulemode branch merged with
my PM branch.

With those couple patches I posted and '#define DEBUG' in omap_hwmod.c,
it seems to hang doing some SR hwmod activity on 3430/n900 and
3530/Overo:

[...]
[    5.950836] omap_hwmod: i2c1: enabling                                       
[    5.954803] omap_hwmod: i2c1: enabling clocks                                
[    5.959777] omap_hwmod: i2c1: idling                                         
[    5.963531] omap_hwmod: i2c1: disabling clocks                               
[    5.968353] omap_hwmod: i2c1: enabling                                       
[    5.972290] omap_hwmod: i2c1: enabling clocks                                
[    5.977081] omap_hwmod: i2c1: idling                                         
[    5.980865] omap_hwmod: i2c1: disabling clocks                               
[    5.987579] omap_hwmod: omap_hwmod_for_each_by_class: looking for modules of class smartreflex                                                               
[    5.996765] omap_hwmod: omap_hwmod_for_each_by_class: sr1_hwmod: calling callback fn                                                                         
[    6.006500] omap_hwmod: omap_hwmod_for_each_by_class: sr2_hwmod: calling callback fn                                                                         

but on 3630/Zoom3, it hang in GPIO triggering (although both are hanging
right after some I2C activity):

[...]
[    5.707672] omap_hwmod: i2c1: enabling
[    5.711425] omap_hwmod: i2c1: enabling clocks
[    5.716003] omap_hwmod: i2c1: idling
[    5.719573] omap_hwmod: i2c1: disabling clocks
[    5.724090] omap_hwmod: i2c1: enabling
[    5.727844] omap_hwmod: i2c1: enabling clocks
[    5.732604] omap_hwmod: i2c1: idling
[    5.736206] omap_hwmod: i2c1: disabling clocks
[    5.740783] twl_rtc twl_rtc: setting system clock to 2000-03-09 00:38:08 UTC (952562288)
[    5.751129] IP-Config: Failed to open eth0
[    5.755249] IP-Config: No network devices available.
[    5.762634] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfb054040
[    5.770324] Internal error: : 1028 [#1] SMP
[    5.774505] Modules linked in:
[    5.777557] CPU: 0    Not tainted  (3.0.0-rc4-pm+initramfs+debug+cmdline-14171-gbcb3984-dirty #10)
[    5.786560] PC is at _set_gpio_triggering+0x38/0x198
[    5.791534] LR is at _set_gpio_triggering+0x2c/0x198
[    5.796508] pc : [<c047dda8>]    lr : [<c047dd9c>]    psr: 80000093
[    5.796508] sp : c7825cd0  ip : c09249dc  fp : c7242000
[    5.807983] r10: 00000066  r9 : 00000002  r8 : c787ba28
[    5.813232] r7 : 00000040  r6 : 00000001  r5 : fb054000  r4 : c787ba28
[    5.819763] r3 : c0870708  r2 : 00000001  r1 : 00000006  r0 : 00000034
[    5.826293] Flags: Nzcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[    5.833679] Control: 10c5387d  Table: 87238019  DAC: 00000017
[    5.839447] Process swapper (pid: 1, stack limit = 0xc78242f8)
[    5.845275] Stack: (0xc7825cd0 to 0xc7826000)
[    5.849639] 5cc0:                                     00000060 00000001 c07fe5c0 c787ba5c
[    5.857818] 5ce0: 60000093 c047e780 00000001 c07fe5c0 c047e6d8 00000000 c0853c24 00000106
[    5.866027] 5d00: 00000001 c02df938 00000001 c724fc20 c07fe5c0 00000106 00000000 c07fe60c
[    5.874206] 5d20: 60000013 c02dfd00 000080d0 c03372e0 60000093 00000006 c7237ba0 c7237ba0
[    5.882385] 5d40: c04b7ea8 00000000 00000106 c07fe5c0 c724fc20 c02dfe14 c78233c0 00000081
[    5.890594] 5d60: 00000000 c7237ba0 c0db96a8 00000000 c7237bac c0db97a8 00000080 c04b72e8
[    5.898773] 5d80: c0763fcc c7237ba0 20000013 c0db96a8 00000002 20000013 00000002 c7242120
[    5.906951] 5da0: 00000000 c04b76a4 c7980000 c0db96a8 00000000 c7242000 c7242120 c04b2d18
[    5.915161] 5dc0: 00000001 c7980000 c7242000 c79800b0 c7848e60 c7824000 c08556b0 c04b3c30
[    5.923339] 5de0: 00000000 00500001 c7848e60 00000001 c7824000 c049c24c c084c858 c74eddb0
[    5.931518] 5e00: 00000001 00000000 c0db854c 00000000 c0db8520 00000000 c74eddb0 00000000
[    5.939727] 5e20: 00000000 c7848e60 c033dd58 c033de48 00000000 00000000 00000000 c7848e60
[    5.947906] 5e40: c74ec6c0 c74eddb0 00000000 00000000 c7814940 c0338680 00000000 c781c820
[    5.956085] 5e60: 00000000 c7848e60 c7825f38 00000000 00000000 00000000 00000000 c03395c8
[    5.964263] 5e80: c781c820 00000002 00000000 c7825f38 00000002 00000000 00000026 c03474dc
[    5.972473] 5ea0: c79f8005 00000000 00000000 c7814940 c74ec800 c74eddb0 c03458f8 c7825f38
[    5.980651] 5ec0: c7825fb8 00000000 c7825efc c7824000 00000000 00000000 00000000 c03478c4
[    5.988830] 5ee0: c7825f04 00000000 00000000 00000002 00000000 00000000 00000000 c7814940
[    5.997039] 5f00: c74ec6c0 00000000 c781eeb0 c7825fb8 00000001 c79f8000 ffffff9c ffffff9c
[    6.005218] 5f20: 00000000 00000000 00000000 c0347c10 00000041 c03537fc c7814940 c74ec6c0
[    6.013397] 5f40: 05b6719b 00000007 c79f8005 00000000 c7401940 c74eddb0 00000101 00000004
[    6.021606] 5f60: 00000000 00000000 00000000 c781eea0 c781ee68 00000000 c781eea0 00000002
[    6.029785] 5f80: 00000000 c781ee60 c781ee68 00000003 00000000 00000000 c025afe0 c79f8000
[    6.037963] 5fa0: 00000002 00000000 00000001 c03396ac 00000000 3539b9a0 00000002 00000000
[    6.046173] 5fc0: 00000026 00000100 c00351ec c00351ec c00351ec c025afe0 00000013 00000000
[    6.054351] 5fe0: 00000000 c0008b68 00000004 00000000 c0008ac8 c025afe0 ffbfffff ffffffff
[    6.062561] [<c047dda8>] (_set_gpio_triggering+0x38/0x198) from [<c047e780>] (gpio_irq_type+0xa8/0x144)
[    6.071960] [<c047e780>] (gpio_irq_type+0xa8/0x144) from [<c02df938>] (__irq_set_trigger+0x5c/0xfc)
[    6.081024] [<c02df938>] (__irq_set_trigger+0x5c/0xfc) from [<c02dfd00>] (__setup_irq+0x328/0x36c)
[    6.090026] [<c02dfd00>] (__setup_irq+0x328/0x36c) from [<c02dfe14>] (request_threaded_irq+0xd0/0x12c)
[    6.099334] [<c02dfe14>] (request_threaded_irq+0xd0/0x12c) from [<c04b72e8>] (serial_link_irq_chain+0x12c/0x250)
[    6.109527] [<c04b72e8>] (serial_link_irq_chain+0x12c/0x250) from [<c04b76a4>] (serial8250_startup+0x298/0x700)
[    6.119659] [<c04b76a4>] (serial8250_startup+0x298/0x700) from [<c04b2d18>] (uart_startup+0x5c/0x1ac)
[    6.128875] [<c04b2d18>] (uart_startup+0x5c/0x1ac) from [<c04b3c30>] (uart_open+0xf8/0x174)
[    6.137268] [<c04b3c30>] (uart_open+0xf8/0x174) from [<c049c24c>] (tty_open+0x150/0x3d8)
[    6.145355] [<c049c24c>] (tty_open+0x150/0x3d8) from [<c033de48>] (chrdev_open+0xf0/0x1e4)
[    6.153656] [<c033de48>] (chrdev_open+0xf0/0x1e4) from [<c0338680>] (__dentry_open+0x168/0x2ec)
[    6.162384] [<c0338680>] (__dentry_open+0x168/0x2ec) from [<c03395c8>] (nameidata_to_filp+0x60/0x68)
[    6.171539] [<c03395c8>] (nameidata_to_filp+0x60/0x68) from [<c03474dc>] (do_last.clone.15+0x2c8/0x574)
[    6.180938] [<c03474dc>] (do_last.clone.15+0x2c8/0x574) from [<c03478c4>] (path_openat+0xb8/0x3d8)
[    6.189910] [<c03478c4>] (path_openat+0xb8/0x3d8) from [<c0347c10>] (do_filp_open+0x2c/0x80)
[    6.198364] [<c0347c10>] (do_filp_open+0x2c/0x80) from [<c03396ac>] (do_sys_open+0xdc/0x178)
[    6.206817] [<c03396ac>] (do_sys_open+0xdc/0x178) from [<c0008b68>] (kernel_init+0xa0/0x134)
[    6.215270] [<c0008b68>] (kernel_init+0xa0/0x134) from [<c025afe0>] (kernel_thread_exit+0x0/0x8)
[    6.224090] Code: ebf7a61c e6ef0070 e3500044 0a00003c (e5953040) 
[    6.230194] ------------[ cut here ]------------
[    6.234832] WARNING: at /work/kernel/omap/pm/arch/arm/mach-omap2/omap_l3_smx.c:162 omap3_l3_app_irq+0x108/0x164()
[    6.245086] In-band Error seen by MPU  at address 0
[    6.249969] Modules linked in:
[    6.253051] [<c0261218>] (unwind_backtrace+0x0/0xf0) from [<c02978f8>] (warn_slowpath_common+0x4c/0x64)
[    6.262481] [<c02978f8>] (warn_slowpath_common+0x4c/0x64) from [<c02979a4>] (warn_slowpath_fmt+0x30/0x40)
[    6.272064] [<c02979a4>] (warn_slowpath_fmt+0x30/0x40) from [<c0277b28>] (omap3_l3_app_irq+0x108/0x164)
[    6.281463] [<c0277b28>] (omap3_l3_app_irq+0x108/0x164) from [<c02de900>] (handle_irq_event_percpu+0x5c/0x22c)
[    6.291503] [<c02de900>] (handle_irq_event_percpu+0x5c/0x22c) from [<c02deb0c>] (handle_irq_event+0x3c/0x5c)
[    6.301330] [<c02deb0c>] (handle_irq_event+0x3c/0x5c) from [<c02e0948>] (handle_level_irq+0xac/0x130)
[    6.310577] [<c02e0948>] (handle_level_irq+0xac/0x130) from [<c02de218>] (generic_handle_irq+0x30/0x48)
[    6.319976] [<c02de218>] (generic_handle_irq+0x30/0x48) from [<c024f04c>] (asm_do_IRQ+0x4c/0xac)
[    6.328796] [<c024f04c>] (asm_do_IRQ+0x4c/0xac) from [<c064c9dc>] (__irq_svc+0x3c/0x120)
[    6.336883] Exception stack(0xc7825b80 to 0xc7825bc8)
[    6.341949] 5b80: c064c6e0 00000001 00000000 c7824000 c080a238 c7825c88 00000001 00001028
[    6.350128] 5ba0: c080a4b4 00000193 00000066 c7242000 00000000 c7825bc8 c064c6e0 c064c6e4
[    6.358337] 5bc0: 60000113 ffffffff
[    6.361816] [<c064c9dc>] (__irq_svc+0x3c/0x120) from [<c064c6e4>] (_raw_spin_unlock_irq+0x28/0x2c)
[    6.370788] [<c064c6e4>] (_raw_spin_unlock_irq+0x28/0x2c) from [<c025e100>] (die+0x8c/0xfc)
[    6.379180] [<c025e100>] (die+0x8c/0xfc) from [<c024f418>] (do_DataAbort+0x8c/0x9c)
[    6.386840] [<c024f418>] (do_DataAbort+0x8c/0x9c) from [<c064c974>] (__dabt_svc+0x54/0x80)
[    6.395111] Exception stack(0xc7825c88 to 0xc7825cd0)
[    6.400177] 5c80:                   00000034 00000006 00000001 c0870708 c787ba28 fb054000
[    6.408355] 5ca0: 00000001 00000040 c787ba28 00000002 00000066 c7242000 c09249dc c7825cd0
[    6.416534] 5cc0: c047dd9c c047dda8 80000093 ffffffff
[    6.421600] [<c064c974>] (__dabt_svc+0x54/0x80) from [<c047dda8>] (_set_gpio_triggering+0x38/0x198)
[    6.430664] [<c047dda8>] (_set_gpio_triggering+0x38/0x198) from [<c047e780>] (gpio_irq_type+0xa8/0x144)
[    6.440093] [<c047e780>] (gpio_irq_type+0xa8/0x144) from [<c02df938>] (__irq_set_trigger+0x5c/0xfc)
[    6.449157] [<c02df938>] (__irq_set_trigger+0x5c/0xfc) from [<c02dfd00>] (__setup_irq+0x328/0x36c)
[    6.458129] [<c02dfd00>] (__setup_irq+0x328/0x36c) from [<c02dfe14>] (request_threaded_irq+0xd0/0x12c)
[    6.467468] [<c02dfe14>] (request_threaded_irq+0xd0/0x12c) from [<c04b72e8>] (serial_link_irq_chain+0x12c/0x250)
[    6.477661] [<c04b72e8>] (serial_link_irq_chain+0x12c/0x250) from [<c04b76a4>] (serial8250_startup+0x298/0x700)
[    6.487762] [<c04b76a4>] (serial8250_startup+0x298/0x700) from [<c04b2d18>] (uart_startup+0x5c/0x1ac)
[    6.496978] [<c04b2d18>] (uart_startup+0x5c/0x1ac) from [<c04b3c30>] (uart_open+0xf8/0x174)
[    6.505371] [<c04b3c30>] (uart_open+0xf8/0x174) from [<c049c24c>] (tty_open+0x150/0x3d8)
[    6.513458] [<c049c24c>] (tty_open+0x150/0x3d8) from [<c033de48>] (chrdev_open+0xf0/0x1e4)
[    6.521759] [<c033de48>] (chrdev_open+0xf0/0x1e4) from [<c0338680>] (__dentry_open+0x168/0x2ec)
[    6.530456] [<c0338680>] (__dentry_open+0x168/0x2ec) from [<c03395c8>] (nameidata_to_filp+0x60/0x68)
[    6.539611] [<c03395c8>] (nameidata_to_filp+0x60/0x68) from [<c03474dc>] (do_last.clone.15+0x2c8/0x574)
[    6.549041] [<c03474dc>] (do_last.clone.15+0x2c8/0x574) from [<c03478c4>] (path_openat+0xb8/0x3d8)
[    6.558013] [<c03478c4>] (path_openat+0xb8/0x3d8) from [<c0347c10>] (do_filp_open+0x2c/0x80)
[    6.566467] [<c0347c10>] (do_filp_open+0x2c/0x80) from [<c03396ac>] (do_sys_open+0xdc/0x178)
[    6.574920] [<c03396ac>] (do_sys_open+0xdc/0x178) from [<c0008b68>] (kernel_init+0xa0/0x134)
[    6.583374] [<c0008b68>] (kernel_init+0xa0/0x134) from [<c025afe0>] (kernel_thread_exit+0x0/0x8)
[    6.592163] ---[ end trace a7607918ffc5bc16 ]---
[    6.596893] ---[ end trace a7607918ffc5bc17 ]---
[    6.601593] Kernel panic - not syncing: Attempted to kill init!


Kevin

Re: [PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[Cousson, Benoit]

Hi Kevin,

On 6/28/2011 2:30 AM, Hilman, Kevin wrote:
> Hi Benoit,
>
> Benoit Cousson<b-cousson@ti.com>  writes:
>
>> Here is the second part of the modulemode series.
>> The goal here is to do the cleanup on the clock nodes and PRCM macros
>> that are not needed anymore by the hwmod data.
>> Some macros are still needed because of clock data. It should be removed
>> once the clock data will be cleaned.
>>
>> Moreover, in order to get rid of static clkdev, omap_device is trying to
>> create dynamically an "fck" alias if a main_clk is defined in hwmod data.
>>
>> As usual, because of drivers non-adapted to pm_runtime, some temp hacks
>> are needed for both MMC and timer1.
>> If the drivers are fixes before these series, these temp patches could be
>> dropped.
>>
>> The series is based on for_3.0.1/5_hwmod_clkdm_fixes and tested
>> on OMAP4430 ES2.1 + SDP. It should not affect OMAP2&  3, but some testing
>> are definitively needed.
>
> Yes, more OMAP2/3 testing is needed.
>
> I just posted a couple patches in response to this series for some
> easy-to-fix boot problems for OMAP3, but it's still not booting for me
> on OMAP3 (haven't tried OMAP2.)  I didn't debug this any further, but
> wanted to report the problems.

Thanks for the tests.

OK, in theory, it was "just" supposed to add some functionality to OMAP4 
only, but it looks like some of the clockdomain patches are probably 
removing some important things.


Rajendra,
Do you have any clue on that?

Regards,
Benoit


>
> NOTE: I'm testing your for_3.0.1/6_hwmod_modulemode branch merged with
> my PM branch.
>
> With those couple patches I posted and '#define DEBUG' in omap_hwmod.c,
> it seems to hang doing some SR hwmod activity on 3430/n900 and
> 3530/Overo:
>
> [...]
> [    5.950836] omap_hwmod: i2c1: enabling
> [    5.954803] omap_hwmod: i2c1: enabling clocks
> [    5.959777] omap_hwmod: i2c1: idling
> [    5.963531] omap_hwmod: i2c1: disabling clocks
> [    5.968353] omap_hwmod: i2c1: enabling
> [    5.972290] omap_hwmod: i2c1: enabling clocks
> [    5.977081] omap_hwmod: i2c1: idling
> [    5.980865] omap_hwmod: i2c1: disabling clocks
> [    5.987579] omap_hwmod: omap_hwmod_for_each_by_class: looking for modules of class smartreflex
> [    5.996765] omap_hwmod: omap_hwmod_for_each_by_class: sr1_hwmod: calling callback fn
> [    6.006500] omap_hwmod: omap_hwmod_for_each_by_class: sr2_hwmod: calling callback fn
>
> but on 3630/Zoom3, it hang in GPIO triggering (although both are hanging
> right after some I2C activity):
>
> [...]
> [    5.707672] omap_hwmod: i2c1: enabling
> [    5.711425] omap_hwmod: i2c1: enabling clocks
> [    5.716003] omap_hwmod: i2c1: idling
> [    5.719573] omap_hwmod: i2c1: disabling clocks
> [    5.724090] omap_hwmod: i2c1: enabling
> [    5.727844] omap_hwmod: i2c1: enabling clocks
> [    5.732604] omap_hwmod: i2c1: idling
> [    5.736206] omap_hwmod: i2c1: disabling clocks
> [    5.740783] twl_rtc twl_rtc: setting system clock to 2000-03-09 00:38:08 UTC (952562288)
> [    5.751129] IP-Config: Failed to open eth0
> [    5.755249] IP-Config: No network devices available.
> [    5.762634] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfb054040
> [    5.770324] Internal error: : 1028 [#1] SMP
> [    5.774505] Modules linked in:
> [    5.777557] CPU: 0    Not tainted  (3.0.0-rc4-pm+initramfs+debug+cmdline-14171-gbcb3984-dirty #10)
> [    5.786560] PC is at _set_gpio_triggering+0x38/0x198
> [    5.791534] LR is at _set_gpio_triggering+0x2c/0x198
> [    5.796508] pc : [<c047dda8>]    lr : [<c047dd9c>]    psr: 80000093
> [    5.796508] sp : c7825cd0  ip : c09249dc  fp : c7242000
> [    5.807983] r10: 00000066  r9 : 00000002  r8 : c787ba28
> [    5.813232] r7 : 00000040  r6 : 00000001  r5 : fb054000  r4 : c787ba28
> [    5.819763] r3 : c0870708  r2 : 00000001  r1 : 00000006  r0 : 00000034
> [    5.826293] Flags: Nzcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
> [    5.833679] Control: 10c5387d  Table: 87238019  DAC: 00000017
> [    5.839447] Process swapper (pid: 1, stack limit = 0xc78242f8)
> [    5.845275] Stack: (0xc7825cd0 to 0xc7826000)
> [    5.849639] 5cc0:                                     00000060 00000001 c07fe5c0 c787ba5c
> [    5.857818] 5ce0: 60000093 c047e780 00000001 c07fe5c0 c047e6d8 00000000 c0853c24 00000106
> [    5.866027] 5d00: 00000001 c02df938 00000001 c724fc20 c07fe5c0 00000106 00000000 c07fe60c
> [    5.874206] 5d20: 60000013 c02dfd00 000080d0 c03372e0 60000093 00000006 c7237ba0 c7237ba0
> [    5.882385] 5d40: c04b7ea8 00000000 00000106 c07fe5c0 c724fc20 c02dfe14 c78233c0 00000081
> [    5.890594] 5d60: 00000000 c7237ba0 c0db96a8 00000000 c7237bac c0db97a8 00000080 c04b72e8
> [    5.898773] 5d80: c0763fcc c7237ba0 20000013 c0db96a8 00000002 20000013 00000002 c7242120
> [    5.906951] 5da0: 00000000 c04b76a4 c7980000 c0db96a8 00000000 c7242000 c7242120 c04b2d18
> [    5.915161] 5dc0: 00000001 c7980000 c7242000 c79800b0 c7848e60 c7824000 c08556b0 c04b3c30
> [    5.923339] 5de0: 00000000 00500001 c7848e60 00000001 c7824000 c049c24c c084c858 c74eddb0
> [    5.931518] 5e00: 00000001 00000000 c0db854c 00000000 c0db8520 00000000 c74eddb0 00000000
> [    5.939727] 5e20: 00000000 c7848e60 c033dd58 c033de48 00000000 00000000 00000000 c7848e60
> [    5.947906] 5e40: c74ec6c0 c74eddb0 00000000 00000000 c7814940 c0338680 00000000 c781c820
> [    5.956085] 5e60: 00000000 c7848e60 c7825f38 00000000 00000000 00000000 00000000 c03395c8
> [    5.964263] 5e80: c781c820 00000002 00000000 c7825f38 00000002 00000000 00000026 c03474dc
> [    5.972473] 5ea0: c79f8005 00000000 00000000 c7814940 c74ec800 c74eddb0 c03458f8 c7825f38
> [    5.980651] 5ec0: c7825fb8 00000000 c7825efc c7824000 00000000 00000000 00000000 c03478c4
> [    5.988830] 5ee0: c7825f04 00000000 00000000 00000002 00000000 00000000 00000000 c7814940
> [    5.997039] 5f00: c74ec6c0 00000000 c781eeb0 c7825fb8 00000001 c79f8000 ffffff9c ffffff9c
> [    6.005218] 5f20: 00000000 00000000 00000000 c0347c10 00000041 c03537fc c7814940 c74ec6c0
> [    6.013397] 5f40: 05b6719b 00000007 c79f8005 00000000 c7401940 c74eddb0 00000101 00000004
> [    6.021606] 5f60: 00000000 00000000 00000000 c781eea0 c781ee68 00000000 c781eea0 00000002
> [    6.029785] 5f80: 00000000 c781ee60 c781ee68 00000003 00000000 00000000 c025afe0 c79f8000
> [    6.037963] 5fa0: 00000002 00000000 00000001 c03396ac 00000000 3539b9a0 00000002 00000000
> [    6.046173] 5fc0: 00000026 00000100 c00351ec c00351ec c00351ec c025afe0 00000013 00000000
> [    6.054351] 5fe0: 00000000 c0008b68 00000004 00000000 c0008ac8 c025afe0 ffbfffff ffffffff
> [    6.062561] [<c047dda8>] (_set_gpio_triggering+0x38/0x198) from [<c047e780>] (gpio_irq_type+0xa8/0x144)
> [    6.071960] [<c047e780>] (gpio_irq_type+0xa8/0x144) from [<c02df938>] (__irq_set_trigger+0x5c/0xfc)
> [    6.081024] [<c02df938>] (__irq_set_trigger+0x5c/0xfc) from [<c02dfd00>] (__setup_irq+0x328/0x36c)
> [    6.090026] [<c02dfd00>] (__setup_irq+0x328/0x36c) from [<c02dfe14>] (request_threaded_irq+0xd0/0x12c)
> [    6.099334] [<c02dfe14>] (request_threaded_irq+0xd0/0x12c) from [<c04b72e8>] (serial_link_irq_chain+0x12c/0x250)
> [    6.109527] [<c04b72e8>] (serial_link_irq_chain+0x12c/0x250) from [<c04b76a4>] (serial8250_startup+0x298/0x700)
> [    6.119659] [<c04b76a4>] (serial8250_startup+0x298/0x700) from [<c04b2d18>] (uart_startup+0x5c/0x1ac)
> [    6.128875] [<c04b2d18>] (uart_startup+0x5c/0x1ac) from [<c04b3c30>] (uart_open+0xf8/0x174)
> [    6.137268] [<c04b3c30>] (uart_open+0xf8/0x174) from [<c049c24c>] (tty_open+0x150/0x3d8)
> [    6.145355] [<c049c24c>] (tty_open+0x150/0x3d8) from [<c033de48>] (chrdev_open+0xf0/0x1e4)
> [    6.153656] [<c033de48>] (chrdev_open+0xf0/0x1e4) from [<c0338680>] (__dentry_open+0x168/0x2ec)
> [    6.162384] [<c0338680>] (__dentry_open+0x168/0x2ec) from [<c03395c8>] (nameidata_to_filp+0x60/0x68)
> [    6.171539] [<c03395c8>] (nameidata_to_filp+0x60/0x68) from [<c03474dc>] (do_last.clone.15+0x2c8/0x574)
> [    6.180938] [<c03474dc>] (do_last.clone.15+0x2c8/0x574) from [<c03478c4>] (path_openat+0xb8/0x3d8)
> [    6.189910] [<c03478c4>] (path_openat+0xb8/0x3d8) from [<c0347c10>] (do_filp_open+0x2c/0x80)
> [    6.198364] [<c0347c10>] (do_filp_open+0x2c/0x80) from [<c03396ac>] (do_sys_open+0xdc/0x178)
> [    6.206817] [<c03396ac>] (do_sys_open+0xdc/0x178) from [<c0008b68>] (kernel_init+0xa0/0x134)
> [    6.215270] [<c0008b68>] (kernel_init+0xa0/0x134) from [<c025afe0>] (kernel_thread_exit+0x0/0x8)
> [    6.224090] Code: ebf7a61c e6ef0070 e3500044 0a00003c (e5953040)
> [    6.230194] ------------[ cut here ]------------
> [    6.234832] WARNING: at /work/kernel/omap/pm/arch/arm/mach-omap2/omap_l3_smx.c:162 omap3_l3_app_irq+0x108/0x164()
> [    6.245086] In-band Error seen by MPU  at address 0
> [    6.249969] Modules linked in:
> [    6.253051] [<c0261218>] (unwind_backtrace+0x0/0xf0) from [<c02978f8>] (warn_slowpath_common+0x4c/0x64)
> [    6.262481] [<c02978f8>] (warn_slowpath_common+0x4c/0x64) from [<c02979a4>] (warn_slowpath_fmt+0x30/0x40)
> [    6.272064] [<c02979a4>] (warn_slowpath_fmt+0x30/0x40) from [<c0277b28>] (omap3_l3_app_irq+0x108/0x164)
> [    6.281463] [<c0277b28>] (omap3_l3_app_irq+0x108/0x164) from [<c02de900>] (handle_irq_event_percpu+0x5c/0x22c)
> [    6.291503] [<c02de900>] (handle_irq_event_percpu+0x5c/0x22c) from [<c02deb0c>] (handle_irq_event+0x3c/0x5c)
> [    6.301330] [<c02deb0c>] (handle_irq_event+0x3c/0x5c) from [<c02e0948>] (handle_level_irq+0xac/0x130)
> [    6.310577] [<c02e0948>] (handle_level_irq+0xac/0x130) from [<c02de218>] (generic_handle_irq+0x30/0x48)
> [    6.319976] [<c02de218>] (generic_handle_irq+0x30/0x48) from [<c024f04c>] (asm_do_IRQ+0x4c/0xac)
> [    6.328796] [<c024f04c>] (asm_do_IRQ+0x4c/0xac) from [<c064c9dc>] (__irq_svc+0x3c/0x120)
> [    6.336883] Exception stack(0xc7825b80 to 0xc7825bc8)
> [    6.341949] 5b80: c064c6e0 00000001 00000000 c7824000 c080a238 c7825c88 00000001 00001028
> [    6.350128] 5ba0: c080a4b4 00000193 00000066 c7242000 00000000 c7825bc8 c064c6e0 c064c6e4
> [    6.358337] 5bc0: 60000113 ffffffff
> [    6.361816] [<c064c9dc>] (__irq_svc+0x3c/0x120) from [<c064c6e4>] (_raw_spin_unlock_irq+0x28/0x2c)
> [    6.370788] [<c064c6e4>] (_raw_spin_unlock_irq+0x28/0x2c) from [<c025e100>] (die+0x8c/0xfc)
> [    6.379180] [<c025e100>] (die+0x8c/0xfc) from [<c024f418>] (do_DataAbort+0x8c/0x9c)
> [    6.386840] [<c024f418>] (do_DataAbort+0x8c/0x9c) from [<c064c974>] (__dabt_svc+0x54/0x80)
> [    6.395111] Exception stack(0xc7825c88 to 0xc7825cd0)
> [    6.400177] 5c80:                   00000034 00000006 00000001 c0870708 c787ba28 fb054000
> [    6.408355] 5ca0: 00000001 00000040 c787ba28 00000002 00000066 c7242000 c09249dc c7825cd0
> [    6.416534] 5cc0: c047dd9c c047dda8 80000093 ffffffff
> [    6.421600] [<c064c974>] (__dabt_svc+0x54/0x80) from [<c047dda8>] (_set_gpio_triggering+0x38/0x198)
> [    6.430664] [<c047dda8>] (_set_gpio_triggering+0x38/0x198) from [<c047e780>] (gpio_irq_type+0xa8/0x144)
> [    6.440093] [<c047e780>] (gpio_irq_type+0xa8/0x144) from [<c02df938>] (__irq_set_trigger+0x5c/0xfc)
> [    6.449157] [<c02df938>] (__irq_set_trigger+0x5c/0xfc) from [<c02dfd00>] (__setup_irq+0x328/0x36c)
> [    6.458129] [<c02dfd00>] (__setup_irq+0x328/0x36c) from [<c02dfe14>] (request_threaded_irq+0xd0/0x12c)
> [    6.467468] [<c02dfe14>] (request_threaded_irq+0xd0/0x12c) from [<c04b72e8>] (serial_link_irq_chain+0x12c/0x250)
> [    6.477661] [<c04b72e8>] (serial_link_irq_chain+0x12c/0x250) from [<c04b76a4>] (serial8250_startup+0x298/0x700)
> [    6.487762] [<c04b76a4>] (serial8250_startup+0x298/0x700) from [<c04b2d18>] (uart_startup+0x5c/0x1ac)
> [    6.496978] [<c04b2d18>] (uart_startup+0x5c/0x1ac) from [<c04b3c30>] (uart_open+0xf8/0x174)
> [    6.505371] [<c04b3c30>] (uart_open+0xf8/0x174) from [<c049c24c>] (tty_open+0x150/0x3d8)
> [    6.513458] [<c049c24c>] (tty_open+0x150/0x3d8) from [<c033de48>] (chrdev_open+0xf0/0x1e4)
> [    6.521759] [<c033de48>] (chrdev_open+0xf0/0x1e4) from [<c0338680>] (__dentry_open+0x168/0x2ec)
> [    6.530456] [<c0338680>] (__dentry_open+0x168/0x2ec) from [<c03395c8>] (nameidata_to_filp+0x60/0x68)
> [    6.539611] [<c03395c8>] (nameidata_to_filp+0x60/0x68) from [<c03474dc>] (do_last.clone.15+0x2c8/0x574)
> [    6.549041] [<c03474dc>] (do_last.clone.15+0x2c8/0x574) from [<c03478c4>] (path_openat+0xb8/0x3d8)
> [    6.558013] [<c03478c4>] (path_openat+0xb8/0x3d8) from [<c0347c10>] (do_filp_open+0x2c/0x80)
> [    6.566467] [<c0347c10>] (do_filp_open+0x2c/0x80) from [<c03396ac>] (do_sys_open+0xdc/0x178)
> [    6.574920] [<c03396ac>] (do_sys_open+0xdc/0x178) from [<c0008b68>] (kernel_init+0xa0/0x134)
> [    6.583374] [<c0008b68>] (kernel_init+0xa0/0x134) from [<c025afe0>] (kernel_thread_exit+0x0/0x8)
> [    6.592163] ---[ end trace a7607918ffc5bc16 ]---
> [    6.596893] ---[ end trace a7607918ffc5bc17 ]---
> [    6.601593] Kernel panic - not syncing: Attempted to kill init!
>
>
> Kevin

Re: [PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[Tomi Valkeinen]

On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
> Hi Paul,
> 
> Here is the second part of the modulemode series. 
> The goal here is to do the cleanup on the clock nodes and PRCM macros
> that are not needed anymore by the hwmod data.
> Some macros are still needed because of clock data. It should be removed
> once the clock data will be cleaned.
> 
> Moreover, in order to get rid of static clkdev, omap_device is trying to
> create dynamically an "fck" alias if a main_clk is defined in hwmod data.
> 
> As usual, because of drivers non-adapted to pm_runtime, some temp hacks
> are needed for both MMC and timer1.
> If the drivers are fixes before these series, these temp patches could be
> dropped.
> 
> The series is based on for_3.0.1/5_hwmod_clkdm_fixes and tested
> on OMAP4430 ES2.1 + SDP. It should not affect OMAP2 & 3, but some testing
> are definitively needed.
> 
> The patches are available here:
> git://gitorious.org/omap-pm/linux.git for_3.0.1/6_hwmod_modulemode

I tested the branch on Blaze, but DSS doesn't work as the clock aliases
have changed, leading to crash. And as only OMAP4 clocks/hwmods were
changed, this makes me believe OMAP2/3 DSS would still work.

I think the OMAP2/3/4 changes need to be done in sync, and at the same
time keeping the peripherals working.

 Tomi

Re: [PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[Cousson, Benoit]

On 6/28/2011 8:56 AM, Valkeinen, Tomi wrote:
> On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
>> Hi Paul,
>>
>> Here is the second part of the modulemode series.
>> The goal here is to do the cleanup on the clock nodes and PRCM macros
>> that are not needed anymore by the hwmod data.
>> Some macros are still needed because of clock data. It should be removed
>> once the clock data will be cleaned.
>>
>> Moreover, in order to get rid of static clkdev, omap_device is trying to
>> create dynamically an "fck" alias if a main_clk is defined in hwmod data.
>>
>> As usual, because of drivers non-adapted to pm_runtime, some temp hacks
>> are needed for both MMC and timer1.
>> If the drivers are fixes before these series, these temp patches could be
>> dropped.
>>
>> The series is based on for_3.0.1/5_hwmod_clkdm_fixes and tested
>> on OMAP4430 ES2.1 + SDP. It should not affect OMAP2&  3, but some testing
>> are definitively needed.
>>
>> The patches are available here:
>> git://gitorious.org/omap-pm/linux.git for_3.0.1/6_hwmod_modulemode
>
> I tested the branch on Blaze, but DSS doesn't work as the clock aliases
> have changed, leading to crash. And as only OMAP4 clocks/hwmods were
> changed, this makes me believe OMAP2/3 DSS would still work.

Mmm, so what alias are you using today? The one from the opt_clock role?
In theory, that main_clock should be named "fck" and the secondary or 
optional clocks will have the name from the role.

> I think the OMAP2/3/4 changes need to be done in sync, and at the same
> time keeping the peripherals working.

Sure, but first we need to figure out what will be the proper clock alias.

Regards,
Benoit

Re: [PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[Tomi Valkeinen]

On Tue, 2011-06-28 at 10:14 +0200, Cousson, Benoit wrote:
> On 6/28/2011 8:56 AM, Valkeinen, Tomi wrote:
> > On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
> >> Hi Paul,
> >>
> >> Here is the second part of the modulemode series.
> >> The goal here is to do the cleanup on the clock nodes and PRCM macros
> >> that are not needed anymore by the hwmod data.
> >> Some macros are still needed because of clock data. It should be removed
> >> once the clock data will be cleaned.
> >>
> >> Moreover, in order to get rid of static clkdev, omap_device is trying to
> >> create dynamically an "fck" alias if a main_clk is defined in hwmod data.
> >>
> >> As usual, because of drivers non-adapted to pm_runtime, some temp hacks
> >> are needed for both MMC and timer1.
> >> If the drivers are fixes before these series, these temp patches could be
> >> dropped.
> >>
> >> The series is based on for_3.0.1/5_hwmod_clkdm_fixes and tested
> >> on OMAP4430 ES2.1 + SDP. It should not affect OMAP2&  3, but some testing
> >> are definitively needed.
> >>
> >> The patches are available here:
> >> git://gitorious.org/omap-pm/linux.git for_3.0.1/6_hwmod_modulemode
> >
> > I tested the branch on Blaze, but DSS doesn't work as the clock aliases
> > have changed, leading to crash. And as only OMAP4 clocks/hwmods were
> > changed, this makes me believe OMAP2/3 DSS would still work.
> 
> Mmm, so what alias are you using today? The one from the opt_clock role?
> In theory, that main_clock should be named "fck" and the secondary or 
> optional clocks will have the name from the role.

You can see the clocks from drivers/video/dss/dss.c:dss_get_clocks(). It
currently gets these via the clkdev aliases:

- ick
- fck
- sys_clk
- tv_clk
- video_clk

> > I think the OMAP2/3/4 changes need to be done in sync, and at the same
> > time keeping the peripherals working.
> 
> Sure, but first we need to figure out what will be the proper clock alias.

My current pm_runtime patch set removes the omapdss clock aliases from
arch/arm/mach-omap2/clock44xx_data.c, as the driver uses the opt-clock
names. Isn't that correct way?

The opt-clocks that my patch set gets are:

- dss_clk
- sys_clk
- hdmi_clk
- rfbi_iclk
- tv_clk
- tv_dac_clk

Additionally these are used to configure the clk rates:
- dpll4_m4_ck
- dpll_per_m5x2_ck

The "dss_clk" opt-clock is a bit of an odd-ball. The same clock is used
as a main-clk and an opt-clock. The driver uses the clock to change the
clock rates. If the driver can get the main-clock with some built-in
alias, like "fck", then this opt-clock is not needed. But I wasn't aware
of such a method.

You can see how the are setup in the following patches:

  OMAP4: HWMOD: Modify DSS opt clocks
  OMAP3: HWMOD: Add DSS opt clocks
  OMAP2420: HWMOD: Add DSS opt clocks
  OMAP2430: HWMOD: Add DSS opt clocks

Then, after the main runtime PM patch, there's a small cleanup:

  OMAP4: HWMOD: Remove unneeded DSS opt clocks
  OMAP4: CLKDEV: Remove omapdss clock aliases

 Tomi

Re: [PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[Cousson, Benoit]

On 6/28/2011 10:29 AM, Valkeinen, Tomi wrote:
> On Tue, 2011-06-28 at 10:14 +0200, Cousson, Benoit wrote:
>> On 6/28/2011 8:56 AM, Valkeinen, Tomi wrote:
>>> On Mon, 2011-06-27 at 18:33 +0200, Benoit Cousson wrote:
>>>> Hi Paul,
>>>>
>>>> Here is the second part of the modulemode series.
>>>> The goal here is to do the cleanup on the clock nodes and PRCM macros
>>>> that are not needed anymore by the hwmod data.
>>>> Some macros are still needed because of clock data. It should be removed
>>>> once the clock data will be cleaned.
>>>>
>>>> Moreover, in order to get rid of static clkdev, omap_device is trying to
>>>> create dynamically an "fck" alias if a main_clk is defined in hwmod data.
>>>>
>>>> As usual, because of drivers non-adapted to pm_runtime, some temp hacks
>>>> are needed for both MMC and timer1.
>>>> If the drivers are fixes before these series, these temp patches could be
>>>> dropped.
>>>>
>>>> The series is based on for_3.0.1/5_hwmod_clkdm_fixes and tested
>>>> on OMAP4430 ES2.1 + SDP. It should not affect OMAP2&   3, but some testing
>>>> are definitively needed.
>>>>
>>>> The patches are available here:
>>>> git://gitorious.org/omap-pm/linux.git for_3.0.1/6_hwmod_modulemode
>>>
>>> I tested the branch on Blaze, but DSS doesn't work as the clock aliases
>>> have changed, leading to crash. And as only OMAP4 clocks/hwmods were
>>> changed, this makes me believe OMAP2/3 DSS would still work.
>>
>> Mmm, so what alias are you using today? The one from the opt_clock role?
>> In theory, that main_clock should be named "fck" and the secondary or
>> optional clocks will have the name from the role.
>
> You can see the clocks from drivers/video/dss/dss.c:dss_get_clocks(). It
> currently gets these via the clkdev aliases:
>
> - ick
> - fck
> - sys_clk
> - tv_clk
> - video_clk
>
>>> I think the OMAP2/3/4 changes need to be done in sync, and at the same
>>> time keeping the peripherals working.
>>
>> Sure, but first we need to figure out what will be the proper clock alias.
>
> My current pm_runtime patch set removes the omapdss clock aliases from
> arch/arm/mach-omap2/clock44xx_data.c, as the driver uses the opt-clock
> names. Isn't that correct way?

Yes, it is, but we need to take care of the name. The names are local to 
the device, so previously I had to prefix with dss_ every clocks 
affected to the dss_core. Since now, most of them are connected only to 
the relevant hwmod, we can use alias like "fck" if the role of the clock 
is the functional one.

> The opt-clocks that my patch set gets are:
>
> - dss_clk

So that one was the DSS PRCM modulemode and will not exist anymore.

> - sys_clk

That one is OK.

> - hdmi_clk

I guess that one should be name "fck", since only the HDMI hwmod will 
use it.

> - rfbi_iclk

Should be named "ick", but I'm not even sure that one is needed.

> - tv_clk
> - tv_dac_clk

Why do you have two clocks for the tv? I can only see the dss_tv_fclk in 
the spec.

> Additionally these are used to configure the clk rates:
> - dpll4_m4_ck
> - dpll_per_m5x2_ck
>
> The "dss_clk" opt-clock is a bit of an odd-ball. The same clock is used
> as a main-clk and an opt-clock. The driver uses the clock to change the
> clock rates. If the driver can get the main-clock with some built-in
> alias, like "fck", then this opt-clock is not needed. But I wasn't aware
> of such a method.

Maybe because I've just introduced it :-)
OMAP: omap_device: Create clkdev entry for hwmod main_clk

It was not done like that before. Only the opt_clk were used, because 
the main_clk was not relevant. With that series, the main_clk represents 
real clock, and thus can be exposed with "fck" alias.

Benoit

Re: [PATCH 0/7] OMAP4: Add modulemode support to hwmod framework (part 2)

[Tomi Valkeinen]

On Tue, 2011-06-28 at 11:14 +0200, Cousson, Benoit wrote:
> On 6/28/2011 10:29 AM, Valkeinen, Tomi wrote:

> > My current pm_runtime patch set removes the omapdss clock aliases from
> > arch/arm/mach-omap2/clock44xx_data.c, as the driver uses the opt-clock
> > names. Isn't that correct way?
> 
> Yes, it is, but we need to take care of the name. The names are local to 
> the device, so previously I had to prefix with dss_ every clocks 
> affected to the dss_core. Since now, most of them are connected only to 
> the relevant hwmod, we can use alias like "fck" if the role of the clock 
> is the functional one.

Ok.

> > The opt-clocks that my patch set gets are:
> >
> > - dss_clk
> 
> So that one was the DSS PRCM modulemode and will not exist anymore.

No, that was dss_dss_clk. It was named "dss_clk", as that is what the
TRM's clock tree shows. All the names in my patch set are from the clock
tree image.

> > - sys_clk
> 
> That one is OK.
> 
> > - hdmi_clk
> 
> I guess that one should be name "fck", since only the HDMI hwmod will 
> use it.

Ok. So the names shouldn't be the ones in the TRM, but more general
ones?

> > - rfbi_iclk
> 
> Should be named "ick", but I'm not even sure that one is needed.

rfbi needs to know the rate of the clock, so it needs to clk_get() it.

> > - tv_clk
> > - tv_dac_clk
> 
> Why do you have two clocks for the tv? I can only see the dss_tv_fclk in 
> the spec.

OMAP3430 has a separate dac clock.

> > Additionally these are used to configure the clk rates:
> > - dpll4_m4_ck
> > - dpll_per_m5x2_ck
> >
> > The "dss_clk" opt-clock is a bit of an odd-ball. The same clock is used
> > as a main-clk and an opt-clock. The driver uses the clock to change the
> > clock rates. If the driver can get the main-clock with some built-in
> > alias, like "fck", then this opt-clock is not needed. But I wasn't aware
> > of such a method.
> 
> Maybe because I've just introduced it :-)
> OMAP: omap_device: Create clkdev entry for hwmod main_clk
> 
> It was not done like that before. Only the opt_clk were used, because 
> the main_clk was not relevant. With that series, the main_clk represents 
> real clock, and thus can be exposed with "fck" alias.

Ok. This will allow removal of the "dss_clk" opt-clocks in my patch set.

 Tomi