[PATCH 0/2] ARM: OMAP5: Enable local timer support

[PATCH 0/2] ARM: OMAP5: Enable local timer support

[Santosh Shilimkar]

Below are the couple of patches which enables the architected cpu local timer
support for OMAP5 devices.

Santosh Shilimkar (2):
  ARM: OMAP: Add initialisation for the real-time counter.
  ARM: OMAP5: Enable arch timer support

 arch/arm/boot/dts/omap5.dtsi |    6 +++
 arch/arm/mach-omap2/Kconfig  |    5 +++
 arch/arm/mach-omap2/timer.c  |   96 +++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 106 insertions(+), 1 deletion(-)

-- 
1.7.9.5

[PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter.

[Santosh Shilimkar]

The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.

The ratio registers needs to be configured based on system clock
only onetime. After initialisation, hardware takes care of adjusting
the clock in different low power modes to keep counter rate constant.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/Kconfig |    4 ++
 arch/arm/mach-omap2/timer.c |   89 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 92 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dd2db02..2120f90 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -24,6 +24,9 @@ config ARCH_OMAP2PLUS_TYPICAL
 config SOC_HAS_OMAP2_SDRC
 	bool "OMAP2 SDRAM Controller support"
 
+config SOC_HAS_REALTIME_COUNTER
+	bool "Real time free running counter"
+
 config ARCH_OMAP2
 	bool "TI OMAP2"
 	depends on ARCH_OMAP2PLUS
@@ -69,6 +72,7 @@ config SOC_OMAP5
 	select CPU_V7
 	select ARM_GIC
 	select HAVE_SMP
+	select SOC_HAS_REALTIME_COUNTER
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2ff6d41..9b17e6c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -69,6 +69,11 @@
 #define OMAP3_SECURE_TIMER	1
 #endif
 
+#define REALTIME_COUNTER_BASE				0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET			0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET		0x14
+#define NUMERATOR_DENUMERATOR_MASK			0xfffff000
+
 /* Clockevent code */
 
 static struct omap_dm_timer clkev;
@@ -339,6 +344,83 @@ static void __init omap2_clocksource_init(int gptimer_id,
 		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }
 
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in the MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static void __init realtime_counter_init(void)
+{
+	void __iomem *base;
+	static struct clk *sys_clk;
+	unsigned long rate;
+	unsigned int reg, num, den;
+
+	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
+	if (!base) {
+		pr_err("%s: ioremap failed\n", __func__);
+		return;
+	}
+	sys_clk = clk_get(NULL, "sys_clkin_ck");
+	if (!sys_clk) {
+		pr_err("%s: failed to get system clock handle\n", __func__);
+		return;
+	}
+
+	rate = clk_get_rate(sys_clk);
+	switch (rate) {
+	case 1200000:
+		num = 64;
+		den = 125;
+		break;
+	case 1300000:
+		num = 768;
+		den = 1625;
+		break;
+	case 19200000:
+		num = 8;
+		den = 25;
+		break;
+	case 2600000:
+		num = 384;
+		den = 1625;
+		break;
+	case 2700000:
+		num = 256;
+		den = 1125;
+		break;
+	case 38400000:
+		num = 4;
+		den = 25;
+		break;
+	default:
+		/* Program it for 38.4 MHz */
+		num = 4;
+		den = 25;
+		break;
+	}
+
+	/* Program numerator and denumerator registers */
+	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+			NUMERATOR_DENUMERATOR_MASK;
+	reg |= num;
+	__raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+
+	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+			NUMERATOR_DENUMERATOR_MASK;
+	reg |= den;
+	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+}
+#else
+static inline void __init realtime_counter_init(void)
+{}
+#endif
+
 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
 				clksrc_nr, clksrc_src)			\
 static void __init omap##name##_timer_init(void)			\
@@ -396,7 +478,12 @@ OMAP_SYS_TIMER(4)
 #endif
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+static void __init omap5_timer_init(void)
+{
+	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
+	realtime_counter_init();
+}
 OMAP_SYS_TIMER(5)
 #endif
 
-- 
1.7.9.5

[PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Santosh Shilimkar]

Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |    6 ++++++
 arch/arm/mach-omap2/Kconfig  |    1 +
 arch/arm/mach-omap2/timer.c  |    7 +++++++
 3 files changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e5270..9686056 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -73,6 +73,12 @@
 			      <0x48212000 0x1000>;
 		};
 
+		arch-timer {
+			compatible = "arm,armv7-timer";
+			interrupts = <1 14 0x304>;
+			clock-frequency = <6140000>;
+		};
+
 		gpio1: gpio@4ae10000 {
 			compatible = "ti,omap4-gpio";
 			ti,hwmods = "gpio1";
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2120f90..53fb77c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -73,6 +73,7 @@ config SOC_OMAP5
 	select ARM_GIC
 	select HAVE_SMP
 	select SOC_HAS_REALTIME_COUNTER
+	select ARM_ARCH_TIMER
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 9b17e6c..f74dbb2 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -41,6 +41,7 @@
 #include <plat/dmtimer.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
+#include <asm/arch_timer.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -480,9 +481,15 @@ OMAP_SYS_TIMER(4)
 #ifdef CONFIG_SOC_OMAP5
 static void __init omap5_timer_init(void)
 {
+	int err;
+
 	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 	realtime_counter_init();
+
+	err = arch_timer_of_register();
+	if (err)
+		pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 }
 OMAP_SYS_TIMER(5)
 #endif
-- 
1.7.9.5

Re: [PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter.

[Vaibhav Hiremath]

On 8/13/2012 4:37 PM, Santosh Shilimkar wrote:
> The real time counter also called master counter, is a free-running
> counter. It produces the count used by the CPU local timer peripherals
> in the MPU cluster. The timer counts at a rate of 6.144 MHz.
> 
> The ratio registers needs to be configured based on system clock
> only onetime. After initialisation, hardware takes care of adjusting
> the clock in different low power modes to keep counter rate constant.
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/mach-omap2/Kconfig |    4 ++
>  arch/arm/mach-omap2/timer.c |   89 ++++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 92 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index dd2db02..2120f90 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -24,6 +24,9 @@ config ARCH_OMAP2PLUS_TYPICAL
>  config SOC_HAS_OMAP2_SDRC
>  	bool "OMAP2 SDRAM Controller support"
>  
> +config SOC_HAS_REALTIME_COUNTER
> +	bool "Real time free running counter"
> +
>  config ARCH_OMAP2
>  	bool "TI OMAP2"
>  	depends on ARCH_OMAP2PLUS
> @@ -69,6 +72,7 @@ config SOC_OMAP5
>  	select CPU_V7
>  	select ARM_GIC
>  	select HAVE_SMP
> +	select SOC_HAS_REALTIME_COUNTER
>  
>  comment "OMAP Core Type"
>  	depends on ARCH_OMAP2
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 2ff6d41..9b17e6c 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -69,6 +69,11 @@
>  #define OMAP3_SECURE_TIMER	1
>  #endif
>  
> +#define REALTIME_COUNTER_BASE				0x48243200
> +#define INCREMENTER_NUMERATOR_OFFSET			0x10
> +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET		0x14
> +#define NUMERATOR_DENUMERATOR_MASK			0xfffff000
> +
>  /* Clockevent code */
>  
>  static struct omap_dm_timer clkev;
> @@ -339,6 +344,83 @@ static void __init omap2_clocksource_init(int gptimer_id,
>  		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
>  }
>  
> +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
> +/*
> + * The realtime counter also called master counter, is a free-running
> + * counter, which is related to real time. It produces the count used
> + * by the CPU local timer peripherals in the MPU cluster. The timer counts
> + * at a rate of 6.144 MHz. Because the device operates on different clocks
> + * in different power modes, the master counter shifts operation between
> + * clocks, adjusting the increment per clock in hardware accordingly to
> + * maintain a constant count rate.
> + */
> +static void __init realtime_counter_init(void)
> +{
> +	void __iomem *base;
> +	static struct clk *sys_clk;
> +	unsigned long rate;
> +	unsigned int reg, num, den;
> +
> +	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
> +	if (!base) {
> +		pr_err("%s: ioremap failed\n", __func__);
> +		return;
> +	}
> +	sys_clk = clk_get(NULL, "sys_clkin_ck");
> +	if (!sys_clk) {
> +		pr_err("%s: failed to get system clock handle\n", __func__);
> +		return;

Don't want to unmap the ioremap'ed space?

> +	}
> +
> +	rate = clk_get_rate(sys_clk);
> +	switch (rate) {
> +	case 1200000:
> +		num = 64;
> +		den = 125;
> +		break;
> +	case 1300000:
> +		num = 768;
> +		den = 1625;
> +		break;
> +	case 19200000:
> +		num = 8;
> +		den = 25;
> +		break;
> +	case 2600000:
> +		num = 384;
> +		den = 1625;
> +		break;
> +	case 2700000:
> +		num = 256;
> +		den = 1125;
> +		break;
> +	case 38400000:
> +		num = 4;
> +		den = 25;
> +		break;
> +	default:
> +		/* Program it for 38.4 MHz */
> +		num = 4;
> +		den = 25;
> +		break;

You can simply do something like,

	case 38400000:
	/* Program it for 38.4 MHz */
	default:
		num = 4;
		den = 25;
		break;

Also, suggest to mention about why 38.4MHz as default? I believe it is
reset value, right?

Also, does it make sense to get rid of hardcoded values above?


Thanks,
Vaibhav
> +	}
> +
> +	/* Program numerator and denumerator registers */
> +	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
> +			NUMERATOR_DENUMERATOR_MASK;
> +	reg |= num;
> +	__raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
> +
> +	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
> +			NUMERATOR_DENUMERATOR_MASK;
> +	reg |= den;
> +	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
> +}
> +#else
> +static inline void __init realtime_counter_init(void)
> +{}
> +#endif
> +
>  #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
>  				clksrc_nr, clksrc_src)			\
>  static void __init omap##name##_timer_init(void)			\
> @@ -396,7 +478,12 @@ OMAP_SYS_TIMER(4)
>  #endif
>  
>  #ifdef CONFIG_SOC_OMAP5
> -OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
> +static void __init omap5_timer_init(void)
> +{
> +	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
> +	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
> +	realtime_counter_init();
> +}
>  OMAP_SYS_TIMER(5)
>  #endif
>  
> 

Re: [PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter.

[Shilimkar, Santosh]

On Mon, Aug 13, 2012 at 11:05 PM, Vaibhav Hiremath <hvaibhav@ti.com> wrote:
>
>
>
> On 8/13/2012 4:37 PM, Santosh Shilimkar wrote:
> > The real time counter also called master counter, is a free-running
> > counter. It produces the count used by the CPU local timer peripherals
> > in the MPU cluster. The timer counts at a rate of 6.144 MHz.
> >
> > The ratio registers needs to be configured based on system clock
> > only onetime. After initialisation, hardware takes care of adjusting
> > the clock in different low power modes to keep counter rate constant.
> >
> > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > ---
> >  arch/arm/mach-omap2/Kconfig |    4 ++
> >  arch/arm/mach-omap2/timer.c |   89
> > ++++++++++++++++++++++++++++++++++++++++++-
> >  2 files changed, 92 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> > index dd2db02..2120f90 100644
> > --- a/arch/arm/mach-omap2/Kconfig
> > +++ b/arch/arm/mach-omap2/Kconfig
> > @@ -24,6 +24,9 @@ config ARCH_OMAP2PLUS_TYPICAL
> >  config SOC_HAS_OMAP2_SDRC
> >       bool "OMAP2 SDRAM Controller support"
> >
> > +config SOC_HAS_REALTIME_COUNTER
> > +     bool "Real time free running counter"
> > +
> >  config ARCH_OMAP2
> >       bool "TI OMAP2"
> >       depends on ARCH_OMAP2PLUS
> > @@ -69,6 +72,7 @@ config SOC_OMAP5
> >       select CPU_V7
> >       select ARM_GIC
> >       select HAVE_SMP
> > +     select SOC_HAS_REALTIME_COUNTER
> >
> >  comment "OMAP Core Type"
> >       depends on ARCH_OMAP2
> > diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> > index 2ff6d41..9b17e6c 100644
> > --- a/arch/arm/mach-omap2/timer.c
> > +++ b/arch/arm/mach-omap2/timer.c
> > @@ -69,6 +69,11 @@
> >  #define OMAP3_SECURE_TIMER   1
> >  #endif
> >
> > +#define REALTIME_COUNTER_BASE                                0x48243200
> > +#define INCREMENTER_NUMERATOR_OFFSET                 0x10
> > +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET                0x14
> > +#define NUMERATOR_DENUMERATOR_MASK                   0xfffff000
> > +
> >  /* Clockevent code */
> >
> >  static struct omap_dm_timer clkev;
> > @@ -339,6 +344,83 @@ static void __init omap2_clocksource_init(int
> > gptimer_id,
> >               omap2_gptimer_clocksource_init(gptimer_id, fck_source);
> >  }
> >
> > +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
> > +/*
> > + * The realtime counter also called master counter, is a free-running
> > + * counter, which is related to real time. It produces the count used
> > + * by the CPU local timer peripherals in the MPU cluster. The timer
> > counts
> > + * at a rate of 6.144 MHz. Because the device operates on different
> > clocks
> > + * in different power modes, the master counter shifts operation
> > between
> > + * clocks, adjusting the increment per clock in hardware accordingly to
> > + * maintain a constant count rate.
> > + */
> > +static void __init realtime_counter_init(void)
> > +{
> > +     void __iomem *base;
> > +     static struct clk *sys_clk;
> > +     unsigned long rate;
> > +     unsigned int reg, num, den;
> > +
> > +     base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
> > +     if (!base) {
> > +             pr_err("%s: ioremap failed\n", __func__);
> > +             return;
> > +     }
> > +     sys_clk = clk_get(NULL, "sys_clkin_ck");
> > +     if (!sys_clk) {
> > +             pr_err("%s: failed to get system clock handle\n",
> > __func__);
> > +             return;
>
> Don't want to unmap the ioremap'ed space?
>
yep. Infact at the end of this function I wanted to unmap the
space since this is one time init. Will fix that in next version.

> > +     }
> > +
> > +     rate = clk_get_rate(sys_clk);
> > +     switch (rate) {
> > +     case 1200000:
> > +             num = 64;
> > +             den = 125;
> > +             break;
> > +     case 1300000:
> > +             num = 768;
> > +             den = 1625;
> > +             break;
> > +     case 19200000:
> > +             num = 8;
> > +             den = 25;
> > +             break;
> > +     case 2600000:
> > +             num = 384;
> > +             den = 1625;
> > +             break;
> > +     case 2700000:
> > +             num = 256;
> > +             den = 1125;
> > +             break;
> > +     case 38400000:
> > +             num = 4;
> > +             den = 25;
> > +             break;
> > +     default:
> > +             /* Program it for 38.4 MHz */
> > +             num = 4;
> > +             den = 25;
> > +             break;
>
> You can simply do something like,
>
>         case 38400000:
>         /* Program it for 38.4 MHz */
>         default:
>                 num = 4;
>                 den = 25;
>                 break;
>
Yes.

> Also, suggest to mention about why 38.4MHz as default? I believe it is
> reset value, right?
>
This is the default sys clock rate assumed in most of the documentation
and also expected to be a default sys clock rate. Reset values as you
said in many other registers also assume 38.4 MHz.

> Also, does it make sense to get rid of hardcoded values above?
>
Actually not. Because the values are fixed since the counter
clock-rate is hardwired to be 6.144 MHz and hence all the
other numbers becomes constant. All these numbers are
coming from TRM and not from any formula. I don't wanted
to go on mathematical equation path since all the values
are well documented.

Thanks for comment.

Regards
santosh

RE: [PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter.

[Hiremath, Vaibhav]

On Tue, Aug 14, 2012 at 11:46:35, Shilimkar, Santosh wrote:
> On Mon, Aug 13, 2012 at 11:05 PM, Vaibhav Hiremath <hvaibhav@ti.com> wrote:
> >
> >
> >
> > On 8/13/2012 4:37 PM, Santosh Shilimkar wrote:
> > > The real time counter also called master counter, is a free-running
> > > counter. It produces the count used by the CPU local timer peripherals
> > > in the MPU cluster. The timer counts at a rate of 6.144 MHz.
> > >
> > > The ratio registers needs to be configured based on system clock
> > > only onetime. After initialisation, hardware takes care of adjusting
> > > the clock in different low power modes to keep counter rate constant.
> > >
> > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > > ---
> > >  arch/arm/mach-omap2/Kconfig |    4 ++
> > >  arch/arm/mach-omap2/timer.c |   89
> > > ++++++++++++++++++++++++++++++++++++++++++-
> > >  2 files changed, 92 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> > > index dd2db02..2120f90 100644
> > > --- a/arch/arm/mach-omap2/Kconfig
> > > +++ b/arch/arm/mach-omap2/Kconfig
> > > @@ -24,6 +24,9 @@ config ARCH_OMAP2PLUS_TYPICAL
> > >  config SOC_HAS_OMAP2_SDRC
> > >       bool "OMAP2 SDRAM Controller support"
> > >
> > > +config SOC_HAS_REALTIME_COUNTER
> > > +     bool "Real time free running counter"
> > > +
> > >  config ARCH_OMAP2
> > >       bool "TI OMAP2"
> > >       depends on ARCH_OMAP2PLUS
> > > @@ -69,6 +72,7 @@ config SOC_OMAP5
> > >       select CPU_V7
> > >       select ARM_GIC
> > >       select HAVE_SMP
> > > +     select SOC_HAS_REALTIME_COUNTER
> > >
> > >  comment "OMAP Core Type"
> > >       depends on ARCH_OMAP2
> > > diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> > > index 2ff6d41..9b17e6c 100644
> > > --- a/arch/arm/mach-omap2/timer.c
> > > +++ b/arch/arm/mach-omap2/timer.c
> > > @@ -69,6 +69,11 @@
> > >  #define OMAP3_SECURE_TIMER   1
> > >  #endif
> > >
> > > +#define REALTIME_COUNTER_BASE                                0x48243200
> > > +#define INCREMENTER_NUMERATOR_OFFSET                 0x10
> > > +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET                0x14
> > > +#define NUMERATOR_DENUMERATOR_MASK                   0xfffff000
> > > +
> > >  /* Clockevent code */
> > >
> > >  static struct omap_dm_timer clkev;
> > > @@ -339,6 +344,83 @@ static void __init omap2_clocksource_init(int
> > > gptimer_id,
> > >               omap2_gptimer_clocksource_init(gptimer_id, fck_source);
> > >  }
> > >
> > > +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
> > > +/*
> > > + * The realtime counter also called master counter, is a free-running
> > > + * counter, which is related to real time. It produces the count used
> > > + * by the CPU local timer peripherals in the MPU cluster. The timer
> > > counts
> > > + * at a rate of 6.144 MHz. Because the device operates on different
> > > clocks
> > > + * in different power modes, the master counter shifts operation
> > > between
> > > + * clocks, adjusting the increment per clock in hardware accordingly to
> > > + * maintain a constant count rate.
> > > + */
> > > +static void __init realtime_counter_init(void)
> > > +{
> > > +     void __iomem *base;
> > > +     static struct clk *sys_clk;
> > > +     unsigned long rate;
> > > +     unsigned int reg, num, den;
> > > +
> > > +     base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
> > > +     if (!base) {
> > > +             pr_err("%s: ioremap failed\n", __func__);
> > > +             return;
> > > +     }
> > > +     sys_clk = clk_get(NULL, "sys_clkin_ck");
> > > +     if (!sys_clk) {
> > > +             pr_err("%s: failed to get system clock handle\n",
> > > __func__);
> > > +             return;
> >
> > Don't want to unmap the ioremap'ed space?
> >
> yep. Infact at the end of this function I wanted to unmap the
> space since this is one time init. Will fix that in next version.
> 
> > > +     }
> > > +
> > > +     rate = clk_get_rate(sys_clk);
> > > +     switch (rate) {
> > > +     case 1200000:
> > > +             num = 64;
> > > +             den = 125;
> > > +             break;
> > > +     case 1300000:
> > > +             num = 768;
> > > +             den = 1625;
> > > +             break;
> > > +     case 19200000:
> > > +             num = 8;
> > > +             den = 25;
> > > +             break;
> > > +     case 2600000:
> > > +             num = 384;
> > > +             den = 1625;
> > > +             break;
> > > +     case 2700000:
> > > +             num = 256;
> > > +             den = 1125;
> > > +             break;
> > > +     case 38400000:
> > > +             num = 4;
> > > +             den = 25;
> > > +             break;
> > > +     default:
> > > +             /* Program it for 38.4 MHz */
> > > +             num = 4;
> > > +             den = 25;
> > > +             break;
> >
> > You can simply do something like,
> >
> >         case 38400000:
> >         /* Program it for 38.4 MHz */
> >         default:
> >                 num = 4;
> >                 den = 25;
> >                 break;
> >
> Yes.
> 
> > Also, suggest to mention about why 38.4MHz as default? I believe it is
> > reset value, right?
> >
> This is the default sys clock rate assumed in most of the documentation
> and also expected to be a default sys clock rate. Reset values as you
> said in many other registers also assume 38.4 MHz.
> 
> > Also, does it make sense to get rid of hardcoded values above?
> >
> Actually not. Because the values are fixed since the counter
> clock-rate is hardwired to be 6.144 MHz and hence all the
> other numbers becomes constant. All these numbers are
> coming from TRM and not from any formula. I don't wanted
> to go on mathematical equation path since all the values
> are well documented.
> 

Yes, I looked at the TRM and they are well documented there.
I would atleast suggest you to state that, these values are coming directly 
from TRM and possibly give reference to the TRM section here.

Thanks,
Vaibhav

Re: [PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter.

[Shilimkar, Santosh]

On Tue, Aug 14, 2012 at 11:52 AM, Hiremath, Vaibhav <hvaibhav@ti.com> wrote:
>
> On Tue, Aug 14, 2012 at 11:46:35, Shilimkar, Santosh wrote:
> > On Mon, Aug 13, 2012 at 11:05 PM, Vaibhav Hiremath <hvaibhav@ti.com>
> > wrote:
> > >

[...]

> > > Also, does it make sense to get rid of hardcoded values above?
> > >
> > Actually not. Because the values are fixed since the counter
> > clock-rate is hardwired to be 6.144 MHz and hence all the
> > other numbers becomes constant. All these numbers are
> > coming from TRM and not from any formula. I don't wanted
> > to go on mathematical equation path since all the values
> > are well documented.
> >
>
> Yes, I looked at the TRM and they are well documented there.
> I would atleast suggest you to state that, these values are coming
> directly
> from TRM and possibly give reference to the TRM section here.
>
Added the TRM chapter information and iounmap() change.
Updated patch at end of the email.

Regards
Santosh

>From aae85431b1a0e985bbc5611972642e96a1501368 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Mon, 13 Aug 2012 14:24:24 +0530
Subject: [PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter.

The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.

The ratio registers needs to be configured based on system clock
only onetime. After initialisation, hardware takes care of adjusting
the clock in different low power modes to keep counter rate constant.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/Kconfig |    4 ++
 arch/arm/mach-omap2/timer.c |   90 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dd2db02..2120f90 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -24,6 +24,9 @@ config ARCH_OMAP2PLUS_TYPICAL
 config SOC_HAS_OMAP2_SDRC
 	bool "OMAP2 SDRAM Controller support"

+config SOC_HAS_REALTIME_COUNTER
+	bool "Real time free running counter"
+
 config ARCH_OMAP2
 	bool "TI OMAP2"
 	depends on ARCH_OMAP2PLUS
@@ -69,6 +72,7 @@ config SOC_OMAP5
 	select CPU_V7
 	select ARM_GIC
 	select HAVE_SMP
+	select SOC_HAS_REALTIME_COUNTER

 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2ff6d41..fd5c048 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -69,6 +69,11 @@
 #define OMAP3_SECURE_TIMER	1
 #endif

+#define REALTIME_COUNTER_BASE				0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET			0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET		0x14
+#define NUMERATOR_DENUMERATOR_MASK			0xfffff000
+
 /* Clockevent code */

 static struct omap_dm_timer clkev;
@@ -339,6 +344,84 @@ static void __init omap2_clocksource_init(int gptimer_id,
 		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }

+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in the MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static void __init realtime_counter_init(void)
+{
+	void __iomem *base;
+	static struct clk *sys_clk;
+	unsigned long rate;
+	unsigned int reg, num, den;
+
+	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
+	if (!base) {
+		pr_err("%s: ioremap failed\n", __func__);
+		return;
+	}
+	sys_clk = clk_get(NULL, "sys_clkin_ck");
+	if (!sys_clk) {
+		pr_err("%s: failed to get system clock handle\n", __func__);
+		iounmap(base);
+		return;
+	}
+
+	rate = clk_get_rate(sys_clk);
+	/* Numerator/denumerator values refer TRM Realtime Counter section */
+	switch (rate) {
+	case 1200000:
+		num = 64;
+		den = 125;
+		break;
+	case 1300000:
+		num = 768;
+		den = 1625;
+		break;
+	case 19200000:
+		num = 8;
+		den = 25;
+		break;
+	case 2600000:
+		num = 384;
+		den = 1625;
+		break;
+	case 2700000:
+		num = 256;
+		den = 1125;
+		break;
+	case 38400000:
+	default:
+		/* Program it for 38.4 MHz */
+		num = 4;
+		den = 25;
+		break;
+	}
+
+	/* Program numerator and denumerator registers */
+	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+			NUMERATOR_DENUMERATOR_MASK;
+	reg |= num;
+	__raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+
+	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+			NUMERATOR_DENUMERATOR_MASK;
+	reg |= den;
+	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+
+	iounmap(base);
+}
+#else
+static inline void __init realtime_counter_init(void)
+{}
+#endif
+
 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
 				clksrc_nr, clksrc_src)			\
 static void __init omap##name##_timer_init(void)			\
@@ -396,7 +479,12 @@ OMAP_SYS_TIMER(4)
 #endif

 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+static void __init omap5_timer_init(void)
+{
+	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
+	realtime_counter_init();
+}
 OMAP_SYS_TIMER(5)
 #endif

-- 
1.7.9.5

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

Benoit,

On Mon, Aug 13, 2012 at 4:37 PM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> The CPU local timers run on the free running real time counter clock.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/boot/dts/omap5.dtsi |    6 ++++++
>  arch/arm/mach-omap2/Kconfig  |    1 +
>  arch/arm/mach-omap2/timer.c  |    7 +++++++
>  3 files changed, 14 insertions(+)
>
Missed to copy you on this patch. Your comments/ack
on the DT part.

Regards
Santosh

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Benoit Cousson]

Hi Santosh,

On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> The CPU local timers run on the free running real time counter clock.
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/boot/dts/omap5.dtsi |    6 ++++++
>  arch/arm/mach-omap2/Kconfig  |    1 +
>  arch/arm/mach-omap2/timer.c  |    7 +++++++
>  3 files changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index 57e5270..9686056 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -73,6 +73,12 @@
>  			      <0x48212000 0x1000>;
>  		};
>  
> +		arch-timer {

arch-timer is the ARM specific name, so I guess here it should be named
with the generic timer name.

> +			compatible = "arm,armv7-timer";
> +			interrupts = <1 14 0x304>;

Could you add some comment, because these hexa value are a little bit
hard to understand.

> +			clock-frequency = <6140000>;
> +		};
> +

That node does not even have a base address?
If this is located inside the MPU, it should not be in the OCP node.

Silly question: Don't we have one arch-timer per CPU?

Regards,
Benoit


>  		gpio1: gpio@4ae10000 {
>  			compatible = "ti,omap4-gpio";
>  			ti,hwmods = "gpio1";
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 2120f90..53fb77c 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -73,6 +73,7 @@ config SOC_OMAP5
>  	select ARM_GIC
>  	select HAVE_SMP
>  	select SOC_HAS_REALTIME_COUNTER
> +	select ARM_ARCH_TIMER
>  
>  comment "OMAP Core Type"
>  	depends on ARCH_OMAP2
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 9b17e6c..f74dbb2 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -41,6 +41,7 @@
>  #include <plat/dmtimer.h>
>  #include <asm/smp_twd.h>
>  #include <asm/sched_clock.h>
> +#include <asm/arch_timer.h>
>  #include "common.h"
>  #include <plat/omap_hwmod.h>
>  #include <plat/omap_device.h>
> @@ -480,9 +481,15 @@ OMAP_SYS_TIMER(4)
>  #ifdef CONFIG_SOC_OMAP5
>  static void __init omap5_timer_init(void)
>  {
> +	int err;
> +
>  	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
>  	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
>  	realtime_counter_init();
> +
> +	err = arch_timer_of_register();
> +	if (err)
> +		pr_err("%s: arch_timer_register failed %d\n", __func__, err);
>  }
>  OMAP_SYS_TIMER(5)
>  #endif
> 

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

On Mon, Sep 10, 2012 at 6:17 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>
> Hi Santosh,
>
> On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
> > Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> > The CPU local timers run on the free running real time counter clock.
> >
> > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > ---
> >  arch/arm/boot/dts/omap5.dtsi |    6 ++++++
> >  arch/arm/mach-omap2/Kconfig  |    1 +
> >  arch/arm/mach-omap2/timer.c  |    7 +++++++
> >  3 files changed, 14 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> > index 57e5270..9686056 100644
> > --- a/arch/arm/boot/dts/omap5.dtsi
> > +++ b/arch/arm/boot/dts/omap5.dtsi
> > @@ -73,6 +73,12 @@
> >                             <0x48212000 0x1000>;
> >               };
> >
> > +             arch-timer {
>
> arch-timer is the ARM specific name, so I guess here it should be named
> with the generic timer name.
>
is "local_timer" name fine then?

> > +                     compatible = "arm,armv7-timer";
> > +                     interrupts = <1 14 0x304>;
>
> Could you add some comment, because these hexa value are a little bit
> hard to understand.
>
OK. Will add some comments.

> > +                     clock-frequency = <6140000>;
> > +             };
> > +
>
> That node does not even have a base address?
> If this is located inside the MPU, it should not be in the OCP node.
>
Its inside MPU and Cp15 control based. No OCP node.

> Silly question: Don't we have one arch-timer per CPU?
>
It is per CPU just like A9 TWD

Regards
santosh

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Benoit Cousson]

On 09/10/2012 03:01 PM, Shilimkar, Santosh wrote:
> On Mon, Sep 10, 2012 at 6:17 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>
>> Hi Santosh,
>>
>> On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
>>> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
>>> The CPU local timers run on the free running real time counter clock.
>>>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> ---
>>>  arch/arm/boot/dts/omap5.dtsi |    6 ++++++
>>>  arch/arm/mach-omap2/Kconfig  |    1 +
>>>  arch/arm/mach-omap2/timer.c  |    7 +++++++
>>>  3 files changed, 14 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
>>> index 57e5270..9686056 100644
>>> --- a/arch/arm/boot/dts/omap5.dtsi
>>> +++ b/arch/arm/boot/dts/omap5.dtsi
>>> @@ -73,6 +73,12 @@
>>>                             <0x48212000 0x1000>;
>>>               };
>>>
>>> +             arch-timer {
>>
>> arch-timer is the ARM specific name, so I guess here it should be named
>> with the generic timer name.
>>
> is "local_timer" name fine then?

No, *timer* is fine. The point here is to provide the generic name when
it exists. That name is supposed to be the general class of the device.

Potentially you can add a label to give an unique name, but since that
label will not be used elsewhere it is not even needed.

arch-timer: timer { ... }

> 
>>> +                     compatible = "arm,armv7-timer";
>>> +                     interrupts = <1 14 0x304>;
>>
>> Could you add some comment, because these hexa value are a little bit
>> hard to understand.
>>
> OK. Will add some comments.
> 
>>> +                     clock-frequency = <6140000>;
>>> +             };
>>> +
>>
>> That node does not even have a base address?
>> If this is located inside the MPU, it should not be in the OCP node.
>>
> Its inside MPU and Cp15 control based. No OCP node.

OK, so you must move it inside the CPU node.

>> Silly question: Don't we have one arch-timer per CPU?
>>
> It is per CPU just like A9 TWD

Shouldn't we have two nodes then?

Regards,
Benoit

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>
> On 09/10/2012 03:01 PM, Shilimkar, Santosh wrote:
> > On Mon, Sep 10, 2012 at 6:17 PM, Benoit Cousson <b-cousson@ti.com>
> > wrote:
> >>
> >> Hi Santosh,
> >>
> >> On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
> >>> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> >>> The CPU local timers run on the free running real time counter clock.
> >>>
> >>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> >>> ---
> >>>  arch/arm/boot/dts/omap5.dtsi |    6 ++++++
> >>>  arch/arm/mach-omap2/Kconfig  |    1 +
> >>>  arch/arm/mach-omap2/timer.c  |    7 +++++++
> >>>  3 files changed, 14 insertions(+)
> >>>
> >>> diff --git a/arch/arm/boot/dts/omap5.dtsi
> >>> b/arch/arm/boot/dts/omap5.dtsi
> >>> index 57e5270..9686056 100644
> >>> --- a/arch/arm/boot/dts/omap5.dtsi
> >>> +++ b/arch/arm/boot/dts/omap5.dtsi
> >>> @@ -73,6 +73,12 @@
> >>>                             <0x48212000 0x1000>;
> >>>               };
> >>>
> >>> +             arch-timer {
> >>
> >> arch-timer is the ARM specific name, so I guess here it should be named
> >> with the generic timer name.
> >>
> > is "local_timer" name fine then?
>
> No, *timer* is fine. The point here is to provide the generic name when
> it exists. That name is supposed to be the general class of the device.
>
> Potentially you can add a label to give an unique name, but since that
> label will not be used elsewhere it is not even needed.
>
> arch-timer: timer { ... }
>
Ok. Will use this.

> >
> >>> +                     compatible = "arm,armv7-timer";
> >>> +                     interrupts = <1 14 0x304>;
> >>
> >> Could you add some comment, because these hexa value are a little bit
> >> hard to understand.
> >>
> > OK. Will add some comments.
> >
> >>> +                     clock-frequency = <6140000>;
> >>> +             };
> >>> +
> >>
> >> That node does not even have a base address?
> >> If this is located inside the MPU, it should not be in the OCP node.
> >>
> > Its inside MPU and Cp15 control based. No OCP node.
>
> OK, so you must move it inside the CPU node.
>
OK. Will do.

> >> Silly question: Don't we have one arch-timer per CPU?
> >>
> > It is per CPU just like A9 TWD
>
> Shouldn't we have two nodes then?
>
I need to check this but arch timer DT node should be same
as the twd DT node. May be one node with reference to
each CPU node should do but am not too sure about the DT
nodes and how all that work.

Regards
Santosh

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

[-- Attachment #1: Type: text/plain, Size: 3028 bytes --]

Benoit,

On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
<santosh.shilimkar@ti.com> wrote:
> On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>

[...]

>> >> Silly question: Don't we have one arch-timer per CPU?
>> >>
>> > It is per CPU just like A9 TWD
>>
>> Shouldn't we have two nodes then?
>>
> I need to check this but arch timer DT node should be same
> as the twd DT node. May be one node with reference to
> each CPU node should do but am not too sure about the DT
> nodes and how all that work.
>
Here is an updated patch based on our discussion. Thanks for comments.
Let me know if you are ok with this version.


>From 98f6a3b4b52ef7c76ed8b19bf9257c51ee5d7323 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Mon, 13 Aug 2012 14:39:03 +0530
Subject: [PATCH] ARM: OMAP5: Enable arch timer support

Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   12 ++++++++++++
 arch/arm/mach-omap2/Kconfig  |    1 +
 arch/arm/mach-omap2/timer.c  |    7 +++++++
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e5270..7b986ed 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
 	cpus {
 		cpu@0 {
 			compatible = "arm,cortex-a15";
+			timer {
+				compatible = "arm,armv7-timer";
+				/* 14th PPI IRQ, active low level-sensitive */
+				interrupts = <1 14 0x308>;
+				clock-frequency = <6144000>;
+			};
 		};
 		cpu@1 {
 			compatible = "arm,cortex-a15";
+			timer {
+				compatible = "arm,armv7-timer";
+				/* 14th PPI IRQ, active low level-sensitive */
+				interrupts = <1 14 0x308>;
+				clock-frequency = <6144000>;
+			};
 		};
 	};

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2120f90..53fb77c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -73,6 +73,7 @@ config SOC_OMAP5
 	select ARM_GIC
 	select HAVE_SMP
 	select SOC_HAS_REALTIME_COUNTER
+	select ARM_ARCH_TIMER

 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 8f5b88b..46982d0 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -41,6 +41,7 @@
 #include <plat/dmtimer.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
+#include <asm/arch_timer.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -481,9 +482,15 @@ OMAP_SYS_TIMER(4)
 #ifdef CONFIG_SOC_OMAP5
 static void __init omap5_timer_init(void)
 {
+	int err;
+
 	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 	realtime_counter_init();
+
+	err = arch_timer_of_register();
+	if (err)
+		pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 }
 OMAP_SYS_TIMER(5)
 #endif
-- 
1.7.9.5

[-- Attachment #2: 0001-ARM-OMAP5-Enable-arch-timer-support.patch --]
[-- Type: application/octet-stream, Size: 2376 bytes --]

From 98f6a3b4b52ef7c76ed8b19bf9257c51ee5d7323 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Mon, 13 Aug 2012 14:39:03 +0530
Subject: [PATCH] ARM: OMAP5: Enable arch timer support

Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   12 ++++++++++++
 arch/arm/mach-omap2/Kconfig  |    1 +
 arch/arm/mach-omap2/timer.c  |    7 +++++++
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e5270..7b986ed 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
 	cpus {
 		cpu@0 {
 			compatible = "arm,cortex-a15";
+			timer {
+				compatible = "arm,armv7-timer";
+				/* 14th PPI IRQ, active low level-sensitive */
+				interrupts = <1 14 0x308>;
+				clock-frequency = <6144000>;
+			};
 		};
 		cpu@1 {
 			compatible = "arm,cortex-a15";
+			timer {
+				compatible = "arm,armv7-timer";
+				/* 14th PPI IRQ, active low level-sensitive */
+				interrupts = <1 14 0x308>;
+				clock-frequency = <6144000>;
+			};
 		};
 	};
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2120f90..53fb77c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -73,6 +73,7 @@ config SOC_OMAP5
 	select ARM_GIC
 	select HAVE_SMP
 	select SOC_HAS_REALTIME_COUNTER
+	select ARM_ARCH_TIMER
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 8f5b88b..46982d0 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -41,6 +41,7 @@
 #include <plat/dmtimer.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
+#include <asm/arch_timer.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -481,9 +482,15 @@ OMAP_SYS_TIMER(4)
 #ifdef CONFIG_SOC_OMAP5
 static void __init omap5_timer_init(void)
 {
+	int err;
+
 	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 	realtime_counter_init();
+
+	err = arch_timer_of_register();
+	if (err)
+		pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 }
 OMAP_SYS_TIMER(5)
 #endif
-- 
1.7.9.5

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Benoit Cousson]

Hi Santosh,

On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
> Benoit,
> 
> On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
> <santosh.shilimkar@ti.com> wrote:
>> On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>>
> 
> [...]
> 
>>>>> Silly question: Don't we have one arch-timer per CPU?
>>>>>
>>>> It is per CPU just like A9 TWD
>>>
>>> Shouldn't we have two nodes then?
>>>
>> I need to check this but arch timer DT node should be same
>> as the twd DT node. May be one node with reference to
>> each CPU node should do but am not too sure about the DT
>> nodes and how all that work.
>>
> Here is an updated patch based on our discussion. Thanks for comments.
> Let me know if you are ok with this version.

Cool, thanks for the update.

> From 98f6a3b4b52ef7c76ed8b19bf9257c51ee5d7323 Mon Sep 17 00:00:00 2001
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Date: Mon, 13 Aug 2012 14:39:03 +0530
> Subject: [PATCH] ARM: OMAP5: Enable arch timer support
> 
> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> The CPU local timers run on the free running real time counter clock.
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Acked-by: Benoit Cousson <b-cousson@ti.com>

Tony,

I can potentially add it along with the timer changes in the dts part2
series if you ack the timer patch. We don't have tons of OMAP5 content
in the dts branch so it should not conflict.

Regards,
Benoit

> ---
>  arch/arm/boot/dts/omap5.dtsi |   12 ++++++++++++
>  arch/arm/mach-omap2/Kconfig  |    1 +
>  arch/arm/mach-omap2/timer.c  |    7 +++++++
>  3 files changed, 20 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index 57e5270..7b986ed 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -33,9 +33,21 @@
>  	cpus {
>  		cpu@0 {
>  			compatible = "arm,cortex-a15";
> +			timer {
> +				compatible = "arm,armv7-timer";
> +				/* 14th PPI IRQ, active low level-sensitive */
> +				interrupts = <1 14 0x308>;
> +				clock-frequency = <6144000>;
> +			};
>  		};
>  		cpu@1 {
>  			compatible = "arm,cortex-a15";
> +			timer {
> +				compatible = "arm,armv7-timer";
> +				/* 14th PPI IRQ, active low level-sensitive */
> +				interrupts = <1 14 0x308>;
> +				clock-frequency = <6144000>;
> +			};
>  		};
>  	};
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 2120f90..53fb77c 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -73,6 +73,7 @@ config SOC_OMAP5
>  	select ARM_GIC
>  	select HAVE_SMP
>  	select SOC_HAS_REALTIME_COUNTER
> +	select ARM_ARCH_TIMER
> 
>  comment "OMAP Core Type"
>  	depends on ARCH_OMAP2
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 8f5b88b..46982d0 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -41,6 +41,7 @@
>  #include <plat/dmtimer.h>
>  #include <asm/smp_twd.h>
>  #include <asm/sched_clock.h>
> +#include <asm/arch_timer.h>
>  #include "common.h"
>  #include <plat/omap_hwmod.h>
>  #include <plat/omap_device.h>
> @@ -481,9 +482,15 @@ OMAP_SYS_TIMER(4)
>  #ifdef CONFIG_SOC_OMAP5
>  static void __init omap5_timer_init(void)
>  {
> +	int err;
> +
>  	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
>  	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
>  	realtime_counter_init();
> +
> +	err = arch_timer_of_register();
> +	if (err)
> +		pr_err("%s: arch_timer_register failed %d\n", __func__, err);
>  }
>  OMAP_SYS_TIMER(5)
>  #endif
> 

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson <b-cousson@ti.com> wrote:
> Hi Santosh,
>
> On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
>> Benoit,
>>
>> On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
>> <santosh.shilimkar@ti.com> wrote:
>>> On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>>>
>>
>> [...]
>>
>>>>>> Silly question: Don't we have one arch-timer per CPU?
>>>>>>
>>>>> It is per CPU just like A9 TWD
>>>>
>>>> Shouldn't we have two nodes then?
>>>>
>>> I need to check this but arch timer DT node should be same
>>> as the twd DT node. May be one node with reference to
>>> each CPU node should do but am not too sure about the DT
>>> nodes and how all that work.
>>>
>> Here is an updated patch based on our discussion. Thanks for comments.
>> Let me know if you are ok with this version.
>
> Cool, thanks for the update.
>
>> From 98f6a3b4b52ef7c76ed8b19bf9257c51ee5d7323 Mon Sep 17 00:00:00 2001
>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Date: Mon, 13 Aug 2012 14:39:03 +0530
>> Subject: [PATCH] ARM: OMAP5: Enable arch timer support
>>
>> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
>> The CPU local timers run on the free running real time counter clock.
>>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>
> Acked-by: Benoit Cousson <b-cousson@ti.com>
>
Thanks Benoit.

> Tony,
>
> I can potentially add it along with the timer changes in the dts part2
> series if you ack the timer patch. We don't have tons of OMAP5 content
> in the dts branch so it should not conflict.
>
Yep. let me know what works. if needed I can put these two patches
on a branch and send a pull request.

Regards
santosh

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Benoit Cousson]

On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
> On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>> Hi Santosh,
>>
>> On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
>>> Benoit,
>>>
>>> On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
>>> <santosh.shilimkar@ti.com> wrote:
>>>> On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>>>>
>>>
>>> [...]
>>>
>>>>>>> Silly question: Don't we have one arch-timer per CPU?
>>>>>>>
>>>>>> It is per CPU just like A9 TWD
>>>>>
>>>>> Shouldn't we have two nodes then?
>>>>>
>>>> I need to check this but arch timer DT node should be same
>>>> as the twd DT node. May be one node with reference to
>>>> each CPU node should do but am not too sure about the DT
>>>> nodes and how all that work.
>>>>
>>> Here is an updated patch based on our discussion. Thanks for comments.
>>> Let me know if you are ok with this version.
>>
>> Cool, thanks for the update.
>>
>>> From 98f6a3b4b52ef7c76ed8b19bf9257c51ee5d7323 Mon Sep 17 00:00:00 2001
>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> Date: Mon, 13 Aug 2012 14:39:03 +0530
>>> Subject: [PATCH] ARM: OMAP5: Enable arch timer support
>>>
>>> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
>>> The CPU local timers run on the free running real time counter clock.
>>>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>
>> Acked-by: Benoit Cousson <b-cousson@ti.com>
>>
> Thanks Benoit.
> 
>> Tony,
>>
>> I can potentially add it along with the timer changes in the dts part2
>> series if you ack the timer patch. We don't have tons of OMAP5 content
>> in the dts branch so it should not conflict.
>>
> Yep. let me know what works. if needed I can put these two patches
> on a branch and send a pull request.

It does not apply to the current devel-dt, what base did you used?

Regards,
Benoit

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

[-- Attachment #1: Type: text/plain, Size: 2139 bytes --]

On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson <b-cousson@ti.com> wrote:
> On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
>> On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>> Hi Santosh,
>>>
>>> On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
>>>> Benoit,
>>>>
>>>> On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
>>>> <santosh.shilimkar@ti.com> wrote:
>>>>> On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>>>>>
>>>>
>>>> [...]
>>>>
>>>>>>>> Silly question: Don't we have one arch-timer per CPU?
>>>>>>>>
>>>>>>> It is per CPU just like A9 TWD
>>>>>>
>>>>>> Shouldn't we have two nodes then?
>>>>>>
>>>>> I need to check this but arch timer DT node should be same
>>>>> as the twd DT node. May be one node with reference to
>>>>> each CPU node should do but am not too sure about the DT
>>>>> nodes and how all that work.
>>>>>
>>>> Here is an updated patch based on our discussion. Thanks for comments.
>>>> Let me know if you are ok with this version.
>>>
>>> Cool, thanks for the update.
>>>
>>>> From 98f6a3b4b52ef7c76ed8b19bf9257c51ee5d7323 Mon Sep 17 00:00:00 2001
>>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Date: Mon, 13 Aug 2012 14:39:03 +0530
>>>> Subject: [PATCH] ARM: OMAP5: Enable arch timer support
>>>>
>>>> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
>>>> The CPU local timers run on the free running real time counter clock.
>>>>
>>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>
>>> Acked-by: Benoit Cousson <b-cousson@ti.com>
>>>
>> Thanks Benoit.
>>
>>> Tony,
>>>
>>> I can potentially add it along with the timer changes in the dts part2
>>> series if you ack the timer patch. We don't have tons of OMAP5 content
>>> in the dts branch so it should not conflict.
>>>
>> Yep. let me know what works. if needed I can put these two patches
>> on a branch and send a pull request.
>
> It does not apply to the current devel-dt, what base did you used?
>
Mainline 3.6-rc3. Just refreshed the patches against devel-dt.
The Kconfig file had a minor conflict.  Updated patches
are updated.

Regards
Santosh

[-- Attachment #2: 0001-ARM-OMAP-Add-initialisation-for-the-real-time-counte.patch --]
[-- Type: application/octet-stream, Size: 4569 bytes --]

From 7b72856b70ab2bbc024ab21a8d542ddca928323d Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Mon, 13 Aug 2012 14:24:24 +0530
Subject: [PATCH 1/2] ARM: OMAP: Add initialisation for the real-time counter.

The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.

The ratio registers needs to be configured based on system clock
only onetime. After initialisation, hardware takes care of adjusting
the clock in different low power modes to keep counter rate constant.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/mach-omap2/Kconfig |    4 ++
 arch/arm/mach-omap2/timer.c |   90 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e45bbff..1ef12b2 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -25,6 +25,9 @@ config ARCH_OMAP2PLUS_TYPICAL
 config SOC_HAS_OMAP2_SDRC
 	bool "OMAP2 SDRAM Controller support"
 
+config SOC_HAS_REALTIME_COUNTER
+	bool "Real time free running counter"
+
 config ARCH_OMAP2
 	bool "TI OMAP2"
 	depends on ARCH_OMAP2PLUS
@@ -71,6 +74,7 @@ config SOC_OMAP5
 	select ARM_GIC
 	select HAVE_SMP
 	select ARM_CPU_SUSPEND if PM
+	select SOC_HAS_REALTIME_COUNTER
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 31f9c93..85b85bb 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -70,6 +70,11 @@
 #define OMAP3_SECURE_TIMER	1
 #endif
 
+#define REALTIME_COUNTER_BASE				0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET			0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET		0x14
+#define NUMERATOR_DENUMERATOR_MASK			0xfffff000
+
 /* Clockevent code */
 
 static struct omap_dm_timer clkev;
@@ -340,6 +345,84 @@ static void __init omap2_clocksource_init(int gptimer_id,
 		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }
 
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in the MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static void __init realtime_counter_init(void)
+{
+	void __iomem *base;
+	static struct clk *sys_clk;
+	unsigned long rate;
+	unsigned int reg, num, den;
+
+	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
+	if (!base) {
+		pr_err("%s: ioremap failed\n", __func__);
+		return;
+	}
+	sys_clk = clk_get(NULL, "sys_clkin_ck");
+	if (!sys_clk) {
+		pr_err("%s: failed to get system clock handle\n", __func__);
+		iounmap(base);
+		return;
+	}
+
+	rate = clk_get_rate(sys_clk);
+	/* Numerator/denumerator values refer TRM Realtime Counter section */
+	switch (rate) {
+	case 1200000:
+		num = 64;
+		den = 125;
+		break;
+	case 1300000:
+		num = 768;
+		den = 1625;
+		break;
+	case 19200000:
+		num = 8;
+		den = 25;
+		break;
+	case 2600000:
+		num = 384;
+		den = 1625;
+		break;
+	case 2700000:
+		num = 256;
+		den = 1125;
+		break;
+	case 38400000:
+	default:
+		/* Program it for 38.4 MHz */
+		num = 4;
+		den = 25;
+		break;
+	}
+
+	/* Program numerator and denumerator registers */
+	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+			NUMERATOR_DENUMERATOR_MASK;
+	reg |= num;
+	__raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+
+	reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+			NUMERATOR_DENUMERATOR_MASK;
+	reg |= den;
+	__raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+
+	iounmap(base);
+}
+#else
+static inline void __init realtime_counter_init(void)
+{}
+#endif
+
 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
 				clksrc_nr, clksrc_src)			\
 static void __init omap##name##_timer_init(void)			\
@@ -402,7 +485,12 @@ OMAP_SYS_TIMER(4)
 #endif
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+static void __init omap5_timer_init(void)
+{
+	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
+	realtime_counter_init();
+}
 OMAP_SYS_TIMER(5)
 #endif
 
-- 
1.7.9.5


[-- Attachment #3: 0002-ARM-OMAP5-Enable-arch-timer-support.patch --]
[-- Type: application/octet-stream, Size: 2394 bytes --]

From 705beb9ed800c7a998e4ecb717ad0e6a6ad5e01e Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Mon, 13 Aug 2012 14:39:03 +0530
Subject: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   12 ++++++++++++
 arch/arm/mach-omap2/Kconfig  |    1 +
 arch/arm/mach-omap2/timer.c  |    7 +++++++
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 9ac75b3..5db33f4 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
 	cpus {
 		cpu@0 {
 			compatible = "arm,cortex-a15";
+			timer {
+				compatible = "arm,armv7-timer";
+				/* 14th PPI IRQ, active low level-sensitive */
+				interrupts = <1 14 0x308>;
+				clock-frequency = <6144000>;
+			};
 		};
 		cpu@1 {
 			compatible = "arm,cortex-a15";
+			timer {
+				compatible = "arm,armv7-timer";
+				/* 14th PPI IRQ, active low level-sensitive */
+				interrupts = <1 14 0x308>;
+				clock-frequency = <6144000>;
+			};
 		};
 	};
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1ef12b2..914e9d5 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -75,6 +75,7 @@ config SOC_OMAP5
 	select HAVE_SMP
 	select ARM_CPU_SUSPEND if PM
 	select SOC_HAS_REALTIME_COUNTER
+	select ARM_ARCH_TIMER
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 85b85bb..96a77cc 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -42,6 +42,7 @@
 #include <plat/dmtimer.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
+#include <asm/arch_timer.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -487,9 +488,15 @@ OMAP_SYS_TIMER(4)
 #ifdef CONFIG_SOC_OMAP5
 static void __init omap5_timer_init(void)
 {
+	int err;
+
 	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 	realtime_counter_init();
+
+	err = arch_timer_of_register();
+	if (err)
+		pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 }
 OMAP_SYS_TIMER(5)
 #endif
-- 
1.7.9.5

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

On Thu, Sep 13, 2012 at 3:30 PM, Shilimkar, Santosh
<santosh.shilimkar@ti.com> wrote:
> On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>> On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
>>> On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>>> Hi Santosh,
>>>>
>>>> On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
>>>>> Benoit,
>>>>>
>>>>> On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
>>>>> <santosh.shilimkar@ti.com> wrote:
>>>>>> On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson <b-cousson@ti.com> wrote:
>>>>>>>
>>>>>
>>>>> [...]
>>>>>
>>>>>>>>> Silly question: Don't we have one arch-timer per CPU?
>>>>>>>>>
>>>>>>>> It is per CPU just like A9 TWD
>>>>>>>
>>>>>>> Shouldn't we have two nodes then?
>>>>>>>
>>>>>> I need to check this but arch timer DT node should be same
>>>>>> as the twd DT node. May be one node with reference to
>>>>>> each CPU node should do but am not too sure about the DT
>>>>>> nodes and how all that work.
>>>>>>
>>>>> Here is an updated patch based on our discussion. Thanks for comments.
>>>>> Let me know if you are ok with this version.
>>>>
>>>> Cool, thanks for the update.
>>>>
>>>>> From 98f6a3b4b52ef7c76ed8b19bf9257c51ee5d7323 Mon Sep 17 00:00:00 2001
>>>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>>> Date: Mon, 13 Aug 2012 14:39:03 +0530
>>>>> Subject: [PATCH] ARM: OMAP5: Enable arch timer support
>>>>>
>>>>> Enable Cortex A15 generic timer support for OMAP5 based SOCs.
>>>>> The CPU local timers run on the free running real time counter clock.
>>>>>
>>>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>>
>>>> Acked-by: Benoit Cousson <b-cousson@ti.com>
>>>>
>>> Thanks Benoit.
>>>
>>>> Tony,
>>>>
>>>> I can potentially add it along with the timer changes in the dts part2
>>>> series if you ack the timer patch. We don't have tons of OMAP5 content
>>>> in the dts branch so it should not conflict.
>>>>
>>> Yep. let me know what works. if needed I can put these two patches
>>> on a branch and send a pull request.
>>
>> It does not apply to the current devel-dt, what base did you used?
>>
> Mainline 3.6-rc3. Just refreshed the patches against devel-dt.
> The Kconfig file had a minor conflict.  Updated patches.
Let me know if they apply ok for you ?
Regards
Santosh

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Tony Lindgren]

* Benoit Cousson <b-cousson@ti.com> [120913 01:57]:
> > 
> > Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> > The CPU local timers run on the free running real time counter clock.
> > 
> > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> 
> Acked-by: Benoit Cousson <b-cousson@ti.com>
> 
> Tony,
> 
> I can potentially add it along with the timer changes in the dts part2
> series if you ack the timer patch. We don't have tons of OMAP5 content
> in the dts branch so it should not conflict.

Yes makes sense to me.

Regards,

Tony

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [120917 14:39]:
> * Benoit Cousson <b-cousson@ti.com> [120913 01:57]:
> > > 
> > > Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> > > The CPU local timers run on the free running real time counter clock.
> > > 
> > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > 
> > Acked-by: Benoit Cousson <b-cousson@ti.com>
> > 
> > Tony,
> > 
> > I can potentially add it along with the timer changes in the dts part2
> > series if you ack the timer patch. We don't have tons of OMAP5 content
> > in the dts branch so it should not conflict.
> 
> Yes makes sense to me.

These may cause bad merge conflicts with Jon's timer patches though?

Tony

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

On Tue, Sep 18, 2012 at 3:09 AM, Tony Lindgren <tony@atomide.com> wrote:
>
> * Tony Lindgren <tony@atomide.com> [120917 14:39]:
> > * Benoit Cousson <b-cousson@ti.com> [120913 01:57]:
> > > >
> > > > Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> > > > The CPU local timers run on the free running real time counter
> > > > clock.
> > > >
> > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > >
> > > Acked-by: Benoit Cousson <b-cousson@ti.com>
> > >
> > > Tony,
> > >
> > > I can potentially add it along with the timer changes in the dts part2
> > > series if you ack the timer patch. We don't have tons of OMAP5 content
> > > in the dts branch so it should not conflict.
> >
> > Yes makes sense to me.
>
> These may cause bad merge conflicts with Jon's timer patches though?
>
These patches can be applied against any branch so not necessary to
only apply against the DT tree.

Have you merged Jon's series ? I can refresh the patches
against that branch. Another option is I can split the patch
so that DT change and timer change is seperated.

Let me know what is your preference.

Regards
Santosh

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [120917 23:07]:
> On Tue, Sep 18, 2012 at 3:09 AM, Tony Lindgren <tony@atomide.com> wrote:
> >
> > * Tony Lindgren <tony@atomide.com> [120917 14:39]:
> > > * Benoit Cousson <b-cousson@ti.com> [120913 01:57]:
> > > > >
> > > > > Enable Cortex A15 generic timer support for OMAP5 based SOCs.
> > > > > The CPU local timers run on the free running real time counter
> > > > > clock.
> > > > >
> > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> > > >
> > > > Acked-by: Benoit Cousson <b-cousson@ti.com>
> > > >
> > > > Tony,
> > > >
> > > > I can potentially add it along with the timer changes in the dts part2
> > > > series if you ack the timer patch. We don't have tons of OMAP5 content
> > > > in the dts branch so it should not conflict.
> > >
> > > Yes makes sense to me.
> >
> > These may cause bad merge conflicts with Jon's timer patches though?
> >
> These patches can be applied against any branch so not necessary to
> only apply against the DT tree.
> 
> Have you merged Jon's series ? I can refresh the patches
> against that branch. Another option is I can split the patch
> so that DT change and timer change is seperated.
> 
> Let me know what is your preference.

Maybe do a pull request for the arch timer and dtimer DT changes?

It seems that Jon is still working on the fixes series, so let's
assume that will need to wait a bit.

Regards,

Tony

Re: [PATCH 2/2] ARM: OMAP5: Enable arch timer support

[Shilimkar, Santosh]

On Tue, Sep 18, 2012 at 11:23 PM, Tony Lindgren <tony@atomide.com> wrote:
> * Shilimkar, Santosh <santosh.shilimkar@ti.com> [120917 23:07]:
>> On Tue, Sep 18, 2012 at 3:09 AM, Tony Lindgren <tony@atomide.com> wrote:
>> >
>> > * Tony Lindgren <tony@atomide.com> [120917 14:39]:
>> > > * Benoit Cousson <b-cousson@ti.com> [120913 01:57]:
>> > > > >
>> > > > > Enable Cortex A15 generic timer support for OMAP5 based SOCs.
>> > > > > The CPU local timers run on the free running real time counter
>> > > > > clock.
>> > > > >
>> > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> > > >
>> > > > Acked-by: Benoit Cousson <b-cousson@ti.com>
>> > > >
>> > > > Tony,
>> > > >
>> > > > I can potentially add it along with the timer changes in the dts part2
>> > > > series if you ack the timer patch. We don't have tons of OMAP5 content
>> > > > in the dts branch so it should not conflict.
>> > >
>> > > Yes makes sense to me.
>> >
>> > These may cause bad merge conflicts with Jon's timer patches though?
>> >
>> These patches can be applied against any branch so not necessary to
>> only apply against the DT tree.
>>
>> Have you merged Jon's series ? I can refresh the patches
>> against that branch. Another option is I can split the patch
>> so that DT change and timer change is seperated.
>>
>> Let me know what is your preference.
>
> Maybe do a pull request for the arch timer and dtimer DT changes?
>
Just sent.

> It seems that Jon is still working on the fixes series, so let's
> assume that will need to wait a bit.
>
Ok. Thanks for clarification.

Regards
Santosh