* [PATCH v2 00/26] Move OMAP2+ over to common clk framework
@ 2012-11-08 1:12 Mike Turquette
2012-11-08 1:12 ` [PATCH 01/26] ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap Mike Turquette
` (28 more replies)
0 siblings, 29 replies; 67+ messages in thread
From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw)
To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette
From: Mike Turquette <mturquette@linaro.org>
Hi all,
This series is based on top of Paul's PRM/CM clean-up work. It is a
refresh of the patches Rajendra sent out a while back[1], with the
addition of several fixes for PM regressions[2] across several
platforms.
I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF
patches (delta is zero) and also suspend/resume.
I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming
appears sane. However Panda-ES never comes back from suspend/resume.
This problem exists on the PRM/CM branch I based on and was not
introduced by this series. I am investigating that independently of
this series.
Anyone wanting to pull the work can find it at:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
[1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
[2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015
Mike Turquette (3):
ARM: OMAP4: clock: Convert to common clk
ARM: OMAP2+: clock: remove unnecessary declarations
ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
Paul Walmsley (7):
ARM: OMAP2xxx: clock: add APLL rate recalculation functions
ARM: OMAP2+: clock: add OMAP CCF convenience macros to
mach-omap2/clock.h
ARM: AM33XX: clock: add clock data in common clock format
ARM: OMAP44xx: clock: drop obsolete clock data
ARM: OMAP3xxx: clk: drop obsolete clock data
ARM: AM33xx: clock: drop obsolete clock data
ARM: OMAP2xxx: clock: drop obsolete clock data
Rajendra Nayak (15):
ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap
ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses
ARM: OMAP3: clock: Convert to common clk
ARM: OMAP2: clock: Convert to common clk
ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable
autoidle
ARM: OMAP: clock: Define a function to enable clocks at init
ARM: OMAP: clock: Get rid of some clkdm assocations within clks
ARM: OMAP4: clock: Add 44xx data using common struct clk
ARM: OMAP3: clock: Add 3xxx data using common struct clk
ARM: omap2: clock: Add 24xx data using common struct clk
ARM: OMAP: clock: Switch to COMMON clk
ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: omap3: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts
Vaibhav Hiremath (1):
ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions
arch/arm/mach-omap2/Kconfig | 5 +
arch/arm/mach-omap2/Makefile | 10 +-
arch/arm/mach-omap2/cclock2420_data.c | 1959 ++++++++++++++
arch/arm/mach-omap2/cclock2430_data.c | 2073 +++++++++++++++
arch/arm/mach-omap2/cclock33xx_data.c | 961 +++++++
arch/arm/mach-omap2/cclock3xxx_data.c | 3595 +++++++++++++++++++++++++
arch/arm/mach-omap2/cclock44xx_data.c | 1991 ++++++++++++++
arch/arm/mach-omap2/clkt2xxx_apll.c | 66 +-
arch/arm/mach-omap2/clkt2xxx_dpll.c | 8 +-
arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 12 +-
arch/arm/mach-omap2/clkt2xxx_osc.c | 13 +-
arch/arm/mach-omap2/clkt2xxx_sys.c | 7 +-
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 11 +-
arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 8 +-
arch/arm/mach-omap2/clkt_clksel.c | 194 +-
arch/arm/mach-omap2/clkt_dpll.c | 28 +-
arch/arm/mach-omap2/clkt_iclk.c | 31 +-
arch/arm/mach-omap2/clock.c | 845 ++----
arch/arm/mach-omap2/clock.h | 356 ++-
arch/arm/mach-omap2/clock2420_data.c | 1986 --------------
arch/arm/mach-omap2/clock2430.c | 8 +-
arch/arm/mach-omap2/clock2430_data.c | 2085 ---------------
arch/arm/mach-omap2/clock2xxx.c | 1 +
arch/arm/mach-omap2/clock2xxx.h | 47 +-
arch/arm/mach-omap2/clock33xx_data.c | 1107 --------
arch/arm/mach-omap2/clock34xx.c | 51 +-
arch/arm/mach-omap2/clock3517.c | 24 +-
arch/arm/mach-omap2/clock36xx.c | 22 +-
arch/arm/mach-omap2/clock36xx.h | 2 +-
arch/arm/mach-omap2/clock3xxx.c | 6 +-
arch/arm/mach-omap2/clock3xxx.h | 6 +-
arch/arm/mach-omap2/clock3xxx_data.c | 3613 --------------------------
arch/arm/mach-omap2/clock44xx_data.c | 3398 ------------------------
arch/arm/mach-omap2/clock_common_data.c | 22 +-
arch/arm/mach-omap2/cm-regbits-24xx.h | 5 +
arch/arm/mach-omap2/cm-regbits-34xx.h | 31 +
arch/arm/mach-omap2/cm2xxx_3xxx.h | 1 +
arch/arm/mach-omap2/dpll3xxx.c | 226 +-
arch/arm/mach-omap2/dpll44xx.c | 21 +-
arch/arm/mach-omap2/io.c | 25 +
arch/arm/mach-omap2/omap_hwmod.c | 63 +-
arch/arm/mach-omap2/pm24xx.c | 4 +-
arch/arm/mach-omap2/prm-regbits-24xx.h | 2 +
arch/arm/mach-omap2/prm-regbits-34xx.h | 1 +
arch/arm/mach-omap2/prm2xxx_3xxx.h | 1 +
arch/arm/mach-omap2/scrm44xx.h | 2 +
46 files changed, 11539 insertions(+), 13394 deletions(-)
create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
create mode 100644 arch/arm/mach-omap2/cclock2430_data.c
create mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
create mode 100644 arch/arm/mach-omap2/cclock3xxx_data.c
create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c
delete mode 100644 arch/arm/mach-omap2/clock2420_data.c
delete mode 100644 arch/arm/mach-omap2/clock2430_data.c
delete mode 100644 arch/arm/mach-omap2/clock33xx_data.c
delete mode 100644 arch/arm/mach-omap2/clock3xxx_data.c
delete mode 100644 arch/arm/mach-omap2/clock44xx_data.c
--
1.7.9.5
^ permalink raw reply [flat|nested] 67+ messages in thread* [PATCH 01/26] ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 02/26] ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses Mike Turquette ` (27 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> plat/clock.c which has most of usecounting/locking infrastructure will be used only for OMAP1 until that is moved to use COMMON clk. reuse most of what plat/clock.h has while we move to common clk, and move most of what 'struct clk' was as 'struct clk_hw_omap' which will then be used to define platform specific parameters. All usecounting/locking related variables from 'struct clk' are dropped as they will not be used with 'struct clk_hw_omap'. Based on the original changes from Mike Turquette. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clock.h | 64 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index cfba1ff..1fb9ecb 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -52,6 +52,14 @@ struct omap_clk { #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> + +struct clockdomain; +#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) + +#else + struct module; struct clk; struct clockdomain; @@ -89,6 +97,7 @@ struct clkops { void (*allow_idle)(struct clk *); void (*deny_idle)(struct clk *); }; +#endif /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) @@ -228,6 +237,60 @@ struct dpll_data { #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ #define CLOCK_CLKOUTX2 (1 << 5) +#ifdef CONFIG_COMMON_CLK +/** + * struct clk_hw_omap - OMAP struct clk + * @node: list_head connecting this clock into the full clock list + * @enable_reg: register to write to enable the clock (see @enable_bit) + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) + * @flags: see "struct clk.flags possibilities" above + * @clksel_reg: for clksel clks, register va containing src/divisor select + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector + * @clksel: for clksel clks, pointer to struct clksel for this clock + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock + * @clkdm_name: clockdomain name that this clock is contained in + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) + * @src_offset: bitshift for source selection bitfield (OMAP1 only) + * + * XXX @rate_offset, @src_offset should probably be removed and OMAP1 + * clock code converted to use clksel. + * + */ + +struct clk_hw_omap_ops; + +struct clk_hw_omap { + struct clk_hw hw; + struct list_head node; + unsigned long fixed_rate; + u8 fixed_div; + void __iomem *enable_reg; + u8 enable_bit; + u8 flags; + void __iomem *clksel_reg; + u32 clksel_mask; + const struct clksel *clksel; + struct dpll_data *dpll_data; + const char *clkdm_name; + struct clockdomain *clkdm; + const struct clk_hw_omap_ops *ops; +}; + +struct clk_hw_omap_ops { + void (*find_idlest)(struct clk_hw_omap *oclk, + void __iomem **idlest_reg, + u8 *idlest_bit, u8 *idlest_val); + void (*find_companion)(struct clk_hw_omap *oclk, + void __iomem **other_reg, + u8 *other_bit); + void (*allow_idle)(struct clk_hw_omap *oclk); + void (*deny_idle)(struct clk_hw_omap *oclk); +}; + +unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, + unsigned long parent_rate); +#else /** * struct clk - OMAP struct clk * @node: list_head connecting this clock into the full clock list @@ -484,4 +547,5 @@ extern struct clk virt_26000000_ck; extern int am33xx_clk_init(void); +#endif /* CONFIG_COMMON_CLK */ #endif -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 02/26] ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette 2012-11-08 1:12 ` [PATCH 01/26] ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-12 22:15 ` Paul Walmsley 2012-11-08 1:12 ` [PATCH 03/26] ARM: OMAP4: clock: Convert to common clk Mike Turquette ` (26 subsequent siblings) 28 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> hwmod uses deferencing the clk pointer to acccess the clkdm. With COMMON clk hwoever this will need to be deferenced through the clk_hw_omap pointer, so do the necessary changes. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/omap_hwmod.c | 70 ++++++++++++++++++++++++++++++-------- 1 file changed, 56 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 37eeb45..1754d7e 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -130,7 +130,11 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/io.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/delay.h> #include <linux/err.h> #include <linux/list.h> @@ -617,6 +621,23 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) return 0; } +struct clockdomain *_get_clkdm(struct omap_hwmod *oh) +{ + struct clk_hw_omap *clk; + + if (oh->clkdm) { + return oh->clkdm; + } else if (oh->_clk) { +#ifdef CONFIG_COMMON_CLK + clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); + return clk->clkdm; +#else + return oh->_clk->clkdm; +#endif + } + return NULL; +} + /** * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active * @oh: struct omap_hwmod * @@ -632,13 +653,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) */ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { - if (!oh->_clk) + struct clockdomain *clkdm, *init_clkdm; + + clkdm = _get_clkdm(oh); + init_clkdm = _get_clkdm(init_oh); + + if (!clkdm || !init_clkdm) return -EINVAL; - if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) return 0; - return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); + return clkdm_add_sleepdep(clkdm, init_clkdm); } /** @@ -656,13 +682,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) */ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { - if (!oh->_clk) + struct clockdomain *clkdm, *init_clkdm; + + clkdm = _get_clkdm(oh); + init_clkdm = _get_clkdm(init_oh); + + if (!clkdm || !init_clkdm) return -EINVAL; - if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) return 0; - return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); + return clkdm_del_sleepdep(clkdm, init_clkdm); } /** @@ -696,7 +727,7 @@ static int _init_main_clk(struct omap_hwmod *oh) */ clk_prepare(oh->_clk); - if (!oh->_clk->clkdm) + if (!_get_clkdm(oh)) pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", oh->name, oh->main_clk); @@ -1279,6 +1310,7 @@ static void _enable_sysc(struct omap_hwmod *oh) u8 idlemode, sf; u32 v; bool clkdm_act; + struct clockdomain *clkdm; if (!oh->class->sysc) return; @@ -1286,11 +1318,9 @@ static void _enable_sysc(struct omap_hwmod *oh) v = oh->_sysc_cache; sf = oh->class->sysc->sysc_flags; + clkdm = _get_clkdm(oh); if (sf & SYSC_HAS_SIDLEMODE) { - clkdm_act = ((oh->clkdm && - oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) || - (oh->_clk && oh->_clk->clkdm && - oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU)); + clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); if (clkdm_act && !(oh->class->sysc->idlemodes & (SIDLE_SMART | SIDLE_SMART_WKUP))) idlemode = HWMOD_IDLEMODE_FORCE; @@ -3558,10 +3588,17 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { struct clk *c; struct omap_hwmod_ocp_if *oi; + struct clockdomain *clkdm; +#ifdef CONFIG_COMMON_CLK + struct clk_hw_omap *clk; +#endif if (!oh) return NULL; + if (oh->clkdm) + return oh->clkdm->pwrdm.ptr; + if (oh->_clk) { c = oh->_clk; } else { @@ -3571,11 +3608,16 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) c = oi->_clk; } - if (!c->clkdm) +#ifdef CONFIG_COMMON_CLK + clk = to_clk_hw_omap(__clk_get_hw(c)); + clkdm = clk->clkdm; +#else + clkdm = c->clkdm; +#endif + if (!clkdm) return NULL; - return c->clkdm->pwrdm.ptr; - + return clkdm->pwrdm.ptr; } /** -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 02/26] ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses 2012-11-08 1:12 ` [PATCH 02/26] ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses Mike Turquette @ 2012-11-12 22:15 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-12 22:15 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches This patch needed to be modified to avoid some sparse warnings; updated patch follows. - Paul ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses From: Rajendra Nayak <rnayak@ti.com> hwmod uses deferencing the clk pointer to acccess the clkdm. With COMMON clk hwoever this will need to be deferenced through the clk_hw_omap pointer, so do the necessary changes. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/omap_hwmod.c | 70 ++++++++++++++++++++++++++++++-------- 1 file changed, 56 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 139adca..f38e4ce 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -130,7 +130,11 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/io.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/delay.h> #include <linux/err.h> #include <linux/list.h> @@ -614,6 +618,23 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) return 0; } +static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) +{ + if (oh->clkdm) { + return oh->clkdm; + } else if (oh->_clk) { +#ifdef CONFIG_COMMON_CLK + struct clk_hw_omap *clk; + + clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); + return clk->clkdm; +#else + return oh->_clk->clkdm; +#endif + } + return NULL; +} + /** * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active * @oh: struct omap_hwmod * @@ -629,13 +650,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) */ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { - if (!oh->_clk) + struct clockdomain *clkdm, *init_clkdm; + + clkdm = _get_clkdm(oh); + init_clkdm = _get_clkdm(init_oh); + + if (!clkdm || !init_clkdm) return -EINVAL; - if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) return 0; - return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); + return clkdm_add_sleepdep(clkdm, init_clkdm); } /** @@ -653,13 +679,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) */ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { - if (!oh->_clk) + struct clockdomain *clkdm, *init_clkdm; + + clkdm = _get_clkdm(oh); + init_clkdm = _get_clkdm(init_oh); + + if (!clkdm || !init_clkdm) return -EINVAL; - if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) return 0; - return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); + return clkdm_del_sleepdep(clkdm, init_clkdm); } /** @@ -693,7 +724,7 @@ static int _init_main_clk(struct omap_hwmod *oh) */ clk_prepare(oh->_clk); - if (!oh->_clk->clkdm) + if (!_get_clkdm(oh)) pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", oh->name, oh->main_clk); @@ -1276,6 +1307,7 @@ static void _enable_sysc(struct omap_hwmod *oh) u8 idlemode, sf; u32 v; bool clkdm_act; + struct clockdomain *clkdm; if (!oh->class->sysc) return; @@ -1283,11 +1315,9 @@ static void _enable_sysc(struct omap_hwmod *oh) v = oh->_sysc_cache; sf = oh->class->sysc->sysc_flags; + clkdm = _get_clkdm(oh); if (sf & SYSC_HAS_SIDLEMODE) { - clkdm_act = ((oh->clkdm && - oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) || - (oh->_clk && oh->_clk->clkdm && - oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU)); + clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); if (clkdm_act && !(oh->class->sysc->idlemodes & (SIDLE_SMART | SIDLE_SMART_WKUP))) idlemode = HWMOD_IDLEMODE_FORCE; @@ -3556,10 +3586,17 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { struct clk *c; struct omap_hwmod_ocp_if *oi; + struct clockdomain *clkdm; +#ifdef CONFIG_COMMON_CLK + struct clk_hw_omap *clk; +#endif if (!oh) return NULL; + if (oh->clkdm) + return oh->clkdm->pwrdm.ptr; + if (oh->_clk) { c = oh->_clk; } else { @@ -3569,11 +3606,16 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) c = oi->_clk; } - if (!c->clkdm) +#ifdef CONFIG_COMMON_CLK + clk = to_clk_hw_omap(__clk_get_hw(c)); + clkdm = clk->clkdm; +#else + clkdm = c->clkdm; +#endif + if (!clkdm) return NULL; - return c->clkdm->pwrdm.ptr; - + return clkdm->pwrdm.ptr; } /** ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 03/26] ARM: OMAP4: clock: Convert to common clk 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette 2012-11-08 1:12 ` [PATCH 01/26] ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap Mike Turquette 2012-11-08 1:12 ` [PATCH 02/26] ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-12 22:52 ` Paul Walmsley 2012-11-13 2:17 ` Paul Walmsley 2012-11-08 1:12 ` [PATCH 04/26] ARM: OMAP3: " Mike Turquette ` (25 subsequent siblings) 28 siblings, 2 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette, Mike Turquette From: Mike Turquette <mturquette@linaro.org> Convert all OMAP4 specific platform files to use COMMON clk and keep all the changes under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. This converts all apis which will be called directly from COMMON clk to take a struct clk_hw parameter, and all the internal platform apis to take a struct clk_hw_omap parameter. Changes are based off the original patch from Mike Turquette. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: created new omap2_clksel_find_parent_index() rather than modifying omap2_init_clksel_parent(); moved clkhwops_iclk_wait to clkt_iclk.c to fix OMAP4-only builds; added clk-provider.h include to clock.h to try to fix some 3430-builds] Signed-off-by: Mike Turquette <mturquette@ti.com> [mturquette@ti.com: squash patch for omap2_clkops_{en,dis}able_clkdm] [mturquette@ti.com: omap2_dflt_clk_is_enabled should not enable clocks] --- arch/arm/mach-omap2/clkt_clksel.c | 184 ++++++++++++++++++++++++++- arch/arm/mach-omap2/clkt_dpll.c | 54 +++++++- arch/arm/mach-omap2/clkt_iclk.c | 14 ++- arch/arm/mach-omap2/clock.c | 248 +++++++++++++++++++++++++++++++++++-- arch/arm/mach-omap2/clock.h | 77 +++++++++++- arch/arm/mach-omap2/dpll3xxx.c | 208 ++++++++++++++++++++++++++++++- arch/arm/mach-omap2/dpll44xx.c | 38 ++++++ 7 files changed, 804 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 53646fa..03ceb2e 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -41,7 +41,11 @@ #include <linux/kernel.h> #include <linux/errno.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <linux/bug.h> @@ -58,11 +62,18 @@ * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ +#ifdef CONFIG_COMMON_CLK +static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, +#else static const struct clksel *_get_clksel_by_parent(struct clk *clk, +#endif struct clk *src_clk) { const struct clksel *clks; + if (!src_clk) + return NULL; + for (clks = clk->clksel; clks->parent; clks++) if (clks->parent == src_clk) break; /* Found the requested parent */ @@ -70,7 +81,11 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); +#else __clk_get_name(clk), __clk_get_name(src_clk)); +#endif return NULL; } @@ -92,6 +107,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, * success (in this latter case, the corresponding register bitfield * value is passed back in the variable pointed to by @field_val) */ +#ifndef CONFIG_COMMON_CLK static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, u32 *field_val) { @@ -134,6 +150,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, return max_div; } +#endif /** * _write_clksel_reg() - program a clock's clksel register in hardware @@ -148,7 +165,11 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, * take into account any time the hardware might take to switch the * clock source. */ +#ifdef CONFIG_COMMON_CLK +static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) +#else static void _write_clksel_reg(struct clk *clk, u32 field_val) +#endif { u32 v; @@ -171,13 +192,22 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val) * before calling. Returns 0 on error or returns the actual integer divisor * upon success. */ +#ifdef CONFIG_COMMON_CLK +static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) +#else static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) +#endif { const struct clksel *clks; const struct clksel_rate *clkr; struct clk *parent; +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); +#else parent = __clk_get_parent(clk); +#endif + clks = _get_clksel_by_parent(clk, parent); if (!clks) return 0; @@ -193,7 +223,12 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), field_val, + __clk_get_name(parent)); +#else __clk_get_name(clk), field_val, __clk_get_name(parent)); +#endif return 0; } @@ -210,7 +245,11 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. */ +#ifdef CONFIG_COMMON_CLK +static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) +#else static u32 _divisor_to_clksel(struct clk *clk, u32 div) +#endif { const struct clksel *clks; const struct clksel_rate *clkr; @@ -219,7 +258,11 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) /* should never happen */ WARN_ON(div == 0); +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); +#else parent = __clk_get_parent(clk); +#endif clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -234,7 +277,12 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) if (!clkr->div) { pr_err("clock: %s: could not find divisor %d for parent %s\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), div, + __clk_get_name(parent)); +#else __clk_get_name(clk), div, __clk_get_name(parent)); +#endif return ~0; } @@ -249,7 +297,11 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ +#ifdef CONFIG_COMMON_CLK +static u32 _read_divisor(struct clk_hw_omap *clk) +#else static u32 _read_divisor(struct clk *clk) +#endif { u32 v; @@ -277,7 +329,12 @@ static u32 _read_divisor(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ +#ifdef CONFIG_COMMON_CLK +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, + unsigned long target_rate, +#else u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, +#endif u32 *new_div) { unsigned long test_rate; @@ -288,9 +345,14 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, unsigned long parent_rate; const char *clk_name; +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); + clk_name = __clk_get_name(clk->hw.clk); +#else parent = __clk_get_parent(clk); - parent_rate = __clk_get_rate(parent); clk_name = __clk_get_name(clk); +#endif + parent_rate = __clk_get_rate(parent); if (!clk->clksel || !clk->clksel_mask) return ~0; @@ -340,6 +402,63 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, * (i.e., those used in struct clk field function pointers, etc.) */ +#ifdef CONFIG_COMMON_CLK +/** + * omap2_clksel_find_parent_index() - return the array index of the current + * hardware parent of @hw + * @hw: struct clk_hw * to find the current hardware parent of + * + * Given a struct clk_hw pointer @hw to the 'hw' member of a struct + * clk_hw_omap record representing a source-selectable hardware clock, + * read the hardware register and determine what its parent is + * currently set to. Intended to be called only by the common clock + * framework struct clk_hw_ops.get_parent function pointer. Return + * the array index of this parent clock upon success -- there is no + * way to return an error, so if we encounter an error, just WARN() + * and pretend that we know that we're doing. + */ +u8 omap2_clksel_find_parent_index(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + const struct clksel *clks; + const struct clksel_rate *clkr; + u32 r, found = 0; + struct clk *parent; + const char *clk_name; + int ret = 0, f = 0; + + parent = __clk_get_parent(hw->clk); + clk_name = __clk_get_name(hw->clk); + + /* XXX should be able to return an error */ + WARN((!clk->clksel || !clk->clksel_mask), + "clock: %s: attempt to call on a non-clksel clock", clk_name); + + r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + r >>= __ffs(clk->clksel_mask); + + for (clks = clk->clksel; clks->parent && !found; clks++) { + for (clkr = clks->rates; clkr->div && !found; clkr++) { + if (!(clkr->flags & cpu_mask)) + continue; + + if (clkr->val == r) { + found = 1; + ret = f; + } + } + f++; + } + + /* This indicates a data error */ + WARN(!found, "clock: %s: init parent: could not find regval %0x\n", + clk_name, r); + + return ret; +} + +#else + /** * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr * @clk: OMAP clock struct ptr to use @@ -393,6 +512,8 @@ void omap2_init_clksel_parent(struct clk *clk) return; } +#endif + /** * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field * @clk: struct clk * @@ -402,6 +523,28 @@ void omap2_init_clksel_parent(struct clk *clk) * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) +{ + unsigned long rate; + u32 div = 0; + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + if (!parent_rate) + return 0; + + div = _read_divisor(clk); + if (!div) + rate = parent_rate; + else + rate = parent_rate / div; + + pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__, + __clk_get_name(hw->clk), rate, div); + + return rate; +} +#else unsigned long omap2_clksel_recalc(struct clk *clk) { unsigned long rate; @@ -420,6 +563,7 @@ unsigned long omap2_clksel_recalc(struct clk *clk) return rate; } +#endif /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate @@ -432,8 +576,15 @@ unsigned long omap2_clksel_recalc(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ +#ifdef CONFIG_COMMON_CLK +long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) { +#endif u32 new_div; return omap2_clksel_round_rate_div(clk, target_rate, &new_div); @@ -454,8 +605,15 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) * is changed, they will all be affected without any notification. * Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) { +#endif u32 field_val, validrate, new_div = 0; if (!clk->clksel || !clk->clksel_mask) @@ -471,11 +629,16 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) _write_clksel_reg(clk, field_val); - clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; - +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), + __clk_get_rate(hw->clk)); +#else pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), __clk_get_rate(clk)); + clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; +#endif + return 0; } @@ -499,6 +662,18 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) * affected without any notification. Returns -EINVAL upon error, or * 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + if (!clk->clksel || !clk->clksel_mask) + return -EINVAL; + + _write_clksel_reg(clk, field_val); + return 0; +} +#else int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) { u32 field_val = 0; @@ -510,7 +685,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) parent_div = _get_div_and_fieldval(new_parent, clk, &field_val); if (!parent_div) return -EINVAL; - _write_clksel_reg(clk, field_val); clk_reparent(clk, new_parent); @@ -520,7 +694,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) if (parent_div > 0) __clk_get_rate(clk) /= parent_div; - pr_debug("clock: %s: set parent to %s (new rate %ld)\n", __clk_get_name(clk), __clk_get_name(__clk_get_parent(clk)), @@ -528,3 +701,4 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) return 0; } +#endif diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 8463cc3..f343389 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -16,7 +16,11 @@ #include <linux/kernel.h> #include <linux/errno.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <asm/div64.h> @@ -76,7 +80,11 @@ * (assuming that it is counting N upwards), or -2 if the enclosing loop * should skip to the next iteration (again assuming N is increasing). */ +#ifdef CONFIG_COMMON_CLK +static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) +#else static int _dpll_test_fint(struct clk *clk, u8 n) +#endif { struct dpll_data *dd; long fint, fint_min, fint_max; @@ -85,7 +93,11 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data; /* DPLL divider must result in a valid jitter correction val */ +#ifdef CONFIG_COMMON_CLK + fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; +#else fint = __clk_get_rate(__clk_get_parent(clk)) / n; +#endif if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -186,15 +198,24 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, } /* Public functions */ - +#ifdef CONFIG_COMMON_CLK +u8 omap2_init_dpll_parent(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else void omap2_init_dpll_parent(struct clk *clk) { +#endif u32 v; struct dpll_data *dd; dd = clk->dpll_data; if (!dd) +#ifdef CONFIG_COMMON_CLK + return -EINVAL; +#else return; +#endif v = __raw_readl(dd->control_reg); v &= dd->enable_mask; @@ -204,18 +225,34 @@ void omap2_init_dpll_parent(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } +#ifdef CONFIG_COMMON_CLK + return 0; +#else return; +#endif } /** @@ -232,7 +269,11 @@ void omap2_init_dpll_parent(struct clk *clk) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * if the clock @clk is not a DPLL. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) +#else u32 omap2_get_dpll_rate(struct clk *clk) +#endif { long long dpll_clk; u32 dpll_mult, dpll_div, v; @@ -288,8 +329,15 @@ u32 omap2_get_dpll_rate(struct clk *clk) * (expensive) function again. Returns ~0 if the target rate cannot * be rounded, or the rounded rate upon success. */ +#ifdef CONFIG_COMMON_CLK +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) { +#endif int m, n, r, scaled_max_m; unsigned long scaled_rt_rp; unsigned long new_rate = 0; @@ -303,7 +351,11 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd = clk->dpll_data; ref_rate = __clk_get_rate(dd->clk_ref); +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(hw->clk); +#else clk_name = __clk_get_name(clk); +#endif pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", clk_name, target_rate); diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index 7c8d41e..d9852c9 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -11,7 +11,11 @@ #undef DEBUG #include <linux/kernel.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <plat/prcm.h> @@ -49,6 +53,14 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk) /* Public data */ +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_iclk_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_omap2_iclk_dflt_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, @@ -78,4 +90,4 @@ const struct clkops clkops_omap2_mdmclk_dflt_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, }; - +#endif diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 9205ea7..3a4c1c5 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -20,7 +20,11 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/delay.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <linux/bitops.h> @@ -52,6 +56,30 @@ static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clockfw_lock); +#ifdef CONFIG_COMMON_CLK + +/* + * Used for clocks that have the same value as the parent clock, + * divided by some factor + */ +unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *oclk; + + if (!hw) { + pr_warn("%s: hw is NULL\n", __func__); + return -EINVAL; + } + + oclk = to_clk_hw_omap(hw); + + WARN_ON(!oclk->fixed_div); + + return parent_rate / oclk->fixed_div; +} +#endif + /* * OMAP2+ specific clock functions */ @@ -68,7 +96,11 @@ static DEFINE_SPINLOCK(clockfw_lock); * belong in the clock code and will be moved in the medium term to * module-dependent code. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void _omap2_module_wait_ready(struct clk_hw_omap *clk) +#else static void _omap2_module_wait_ready(struct clk *clk) +#endif { void __iomem *companion_reg, *idlest_reg; u8 other_bit, idlest_bit, idlest_val; @@ -81,9 +113,12 @@ static void _omap2_module_wait_ready(struct clk *clk) } clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); - omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk)); +#else __clk_get_name(clk)); +#endif } /* Public functions */ @@ -96,15 +131,25 @@ static void _omap2_module_wait_ready(struct clk *clk) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap2_init_clk_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else void omap2_init_clk_clkdm(struct clk *clk) { +#endif struct clockdomain *clkdm; const char *clk_name; if (!clk->clkdm_name) return; +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(hw->clk); +#else clk_name = __clk_get_name(clk); +#endif clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { @@ -151,8 +196,12 @@ void __init omap2_clk_disable_clkdm_control(void) * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit) +#ifdef CONFIG_COMMON_CLK +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, +#else +void omap2_clk_dflt_find_companion(struct clk *clk, +#endif + void __iomem **other_reg, u8 *other_bit) { u32 r; @@ -180,8 +229,12 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * register address ID (e.g., that CM_FCLKEN2 corresponds to * CM_IDLEST2). This is not true for all modules. No return value. */ -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val) +#ifdef CONFIG_COMMON_CLK +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, +#else +void omap2_clk_dflt_find_idlest(struct clk *clk, +#endif + void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) { u32 r; @@ -203,6 +256,181 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, } +#ifdef CONFIG_COMMON_CLK +int omap2_dflt_clk_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + u32 v; + int ret = 0; + + clk = to_clk_hw_omap(hw); + + if (clkdm_control && clk->clkdm) { + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, ret); + return ret; + } + } + + if (unlikely(clk->enable_reg == NULL)) { + pr_err("%s: %s missing enable_reg\n", __func__, + __clk_get_name(hw->clk)); + ret = -EINVAL; + goto err; + } + + /* FIXME should not have INVERT_ENABLE bit here */ + v = __raw_readl(clk->enable_reg); + if (clk->flags & INVERT_ENABLE) + v &= ~(1 << clk->enable_bit); + else + v |= (1 << clk->enable_bit); + __raw_writel(v, clk->enable_reg); + v = __raw_readl(clk->enable_reg); /* OCP barrier */ + + if (clk->ops && clk->ops->find_idlest) + _omap2_module_wait_ready(clk); + + return 0; + +err: + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); + return ret; +} + +void omap2_dflt_clk_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + u32 v; + + clk = to_clk_hw_omap(hw); + if (!clk->enable_reg) { + /* + * 'independent' here refers to a clock which is not + * controlled by its parent. + */ + pr_err("%s: independent clock %s has no enable_reg\n", + __func__, __clk_get_name(hw->clk)); + return; + } + + v = __raw_readl(clk->enable_reg); + if (clk->flags & INVERT_ENABLE) + v |= (1 << clk->enable_bit); + else + v &= ~(1 << clk->enable_bit); + __raw_writel(v, clk->enable_reg); + /* No OCP barrier needed here since it is a disable operation */ + + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); +} + +/* XXX kerneldoc */ +int omap2_clkops_enable_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + int ret = 0; + + clk = to_clk_hw_omap(hw); + + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return 0; + } + + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return 0; + } + + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, ret); + return ret; + } + + return 0; +} + +/* XXX kerneldoc */ +void omap2_clkops_disable_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + + clk = to_clk_hw_omap(hw); + + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return; + } + + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return; + } + + clkdm_clk_disable(clk->clkdm, hw->clk); +} + +int omap2_dflt_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 regval32; + + regval32 = __raw_readl(clk->enable_reg); + + if (clk->flags & INVERT_ENABLE) + regval32 ^= BIT(clk->enable_bit); + + regval32 &= BIT(clk->enable_bit); + + return regval32 ? 1 : 0; +} + +int __initdata mpurate; + +/* + * By default we use the rate set by the bootloader. + * You can override this with mpurate= cmdline option. + */ +static int __init omap_clk_setup(char *str) +{ + get_option(&str, &mpurate); + + if (!mpurate) + return 1; + + if (mpurate < 1000) + mpurate *= 1000000; + + return 1; +} +__setup("mpurate=", omap_clk_setup); + +const struct clk_hw_omap_ops clkhwops_wait = { + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else int omap2_dflt_clk_enable(struct clk *clk) { u32 v; @@ -433,6 +661,8 @@ void omap2_clk_disable_unused(struct clk *clk) } #endif +#endif /* CONFIG_COMMON_CLK */ + /** * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument * @mpurate_ck_name: clk name of the clock to change rate @@ -463,13 +693,15 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) r = clk_set_rate(mpurate_ck, mpurate); if (IS_ERR_VALUE(r)) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", - mpurate_ck->name, mpurate, r); + mpurate_ck_name, mpurate, r); clk_put(mpurate_ck); return -EINVAL; } calibrate_delay(); +#ifndef CONFIG_COMMON_CLK recalculate_root_clocks(); +#endif clk_put(mpurate_ck); @@ -515,8 +747,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(mpu_ck) / 1000000)); } +#ifndef CONFIG_COMMON_CLK /* Common data */ - int clk_enable(struct clk *clk) { unsigned long flags; @@ -1023,4 +1255,4 @@ err_out: late_initcall(clk_debugfs_init); #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ - +#endif /* CONFIG_COMMON_CLK */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 1fb9ecb..003520c 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -397,6 +397,7 @@ extern const struct clkops clkops_null; extern struct clk dummy_ck; +#endif /* CONFIG_COMMON_CLK */ /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 @@ -427,11 +428,36 @@ extern struct clk dummy_ck; /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 +#ifndef CONFIG_COMMON_CLK int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); +#endif /* CONFIG_COMMON_CLK */ + +#ifdef CONFIG_COMMON_CLK +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); +int omap3_noncore_dpll_enable(struct clk_hw *hw); +void omap3_noncore_dpll_disable(struct clk_hw *hw); +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); +void omap3_dpll_allow_idle(struct clk_hw_omap *clk); +void omap3_dpll_deny_idle(struct clk_hw_omap *clk); +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate); +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate); +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate); +#else long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); unsigned long omap3_dpll_recalc(struct clk *clk); unsigned long omap3_clkoutx2_recalc(struct clk *clk); @@ -446,17 +472,33 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk); void omap4_dpllmx_deny_gatectrl(struct clk *clk); long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); +#endif #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk); #else #define omap2_clk_disable_unused NULL #endif - +#ifdef CONFIG_COMMON_CLK +void omap2_init_clk_clkdm(struct clk_hw *clk); +#else void omap2_init_clk_clkdm(struct clk *clk); +#endif void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ +#ifdef CONFIG_COMMON_CLK +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, + unsigned long target_rate, + u32 *new_div); +u8 omap2_clksel_find_parent_index(struct clk_hw *hw); +unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); +long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); +#else u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 *new_div); void omap2_init_clksel_parent(struct clk *clk); @@ -464,13 +506,19 @@ unsigned long omap2_clksel_recalc(struct clk *clk); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); +#endif /* clkt_iclk.c public functions */ extern void omap2_clkt_iclk_allow_idle(struct clk *clk); extern void omap2_clkt_iclk_deny_idle(struct clk *clk); +#ifdef CONFIG_COMMON_CLK +u8 omap2_init_dpll_parent(struct clk_hw *hw); +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); +#else u32 omap2_get_dpll_rate(struct clk *clk); void omap2_init_dpll_parent(struct clk *clk); +#endif int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); @@ -499,12 +547,24 @@ static inline void omap4_clk_prepare_for_reboot(void) } #endif +#ifdef CONFIG_COMMON_CLK +int omap2_dflt_clk_enable(struct clk_hw *hw); +void omap2_dflt_clk_disable(struct clk_hw *hw); +int omap2_dflt_clk_is_enabled(struct clk_hw *hw); +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, + u8 *other_bit); +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, u8 *idlest_val); +#else int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, u8 *other_bit); void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); +#endif int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -524,6 +584,13 @@ extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; +#ifdef CONFIG_COMMON_CLK +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; +extern const struct clk_hw_omap_ops clkhwops_iclk_wait; +extern const struct clk_hw_omap_ops clkhwops_wait; +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; +#endif + extern const struct clkops clkops_omap2_iclk_dflt_wait; extern const struct clkops clkops_omap2_iclk_dflt; extern const struct clkops clkops_omap2_iclk_idle_only; @@ -541,11 +608,17 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; +#ifndef CONFIG_COMMON_CLK /* clocks shared between various OMAP SoCs */ extern struct clk virt_19200000_ck; extern struct clk virt_26000000_ck; +#endif extern int am33xx_clk_init(void); -#endif /* CONFIG_COMMON_CLK */ +#ifdef CONFIG_COMMON_CLK +extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); +extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); +#endif + #endif diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index eacf51f..721588f 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -42,7 +42,11 @@ /* Private functions */ /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ +#ifdef CONFIG_COMMON_CLK +static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) +#else static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) +#endif { const struct dpll_data *dd; u32 v; @@ -56,7 +60,11 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) } /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) +#else static int _omap3_wait_dpll_status(struct clk *clk, u8 state) +#endif { const struct dpll_data *dd; int i = 0; @@ -64,7 +72,11 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) const char *clk_name; dd = clk->dpll_data; +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(clk->hw.clk); +#else clk_name = __clk_get_name(clk); +#endif state <<= __ffs(dd->idlest_mask); @@ -88,7 +100,11 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) } /* From 3430 TRM ES2 4.7.6.2 */ +#ifdef CONFIG_COMMON_CLK +static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) +#else static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) +#endif { unsigned long fint; u16 f = 0; @@ -133,14 +149,22 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) * locked successfully, return 0; if the DPLL did not lock in the time * allotted, or DPLL3 was passed in, return -EINVAL. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_lock(struct clk *clk) +#endif { const struct dpll_data *dd; u8 ai; u8 state = 1; int r = 0; +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); +#else pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); +#endif dd = clk->dpll_data; state <<= __ffs(dd->idlest_mask); @@ -178,7 +202,11 @@ done: * DPLL3 was passed in, or the DPLL does not support low-power bypass, * return -EINVAL. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_bypass(struct clk *clk) +#endif { int r; u8 ai; @@ -187,7 +215,11 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) return -EINVAL; pr_debug("clock: configuring DPLL %s for low-power bypass\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk)); +#else __clk_get_name(clk)); +#endif ai = omap3_dpll_autoidle_read(clk); @@ -210,14 +242,22 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) * code. If DPLL3 was passed in, or the DPLL does not support * low-power stop, return -EINVAL; otherwise, return 0. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_stop(struct clk *clk) +#endif { u8 ai; if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) return -EINVAL; +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); +#else pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); +#endif ai = omap3_dpll_autoidle_read(clk); @@ -241,11 +281,19 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ +#ifdef CONFIG_COMMON_CLK +static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) +#else static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) +#endif { unsigned long fint, clkinp; /* watch out for overflow */ +#ifdef CONFIG_COMMON_CLK + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); +#else clkinp = __clk_get_rate(__clk_get_parent(clk)); +#endif fint = (clkinp / n) * m; if (fint < 1000000000) @@ -266,12 +314,20 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ +#ifdef CONFIG_COMMON_CLK +static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) +#else static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) +#endif { unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2; +#ifdef CONFIG_COMMON_CLK + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); +#else clkinp = __clk_get_rate(__clk_get_parent(clk)); +#endif /* * target sigma-delta to near 250MHz @@ -298,7 +354,12 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) * Program the DPLL with the supplied M, N values, and wait for the DPLL to * lock.. Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n, + u16 freqsel) +#else static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) +#endif { struct dpll_data *dd = clk->dpll_data; u8 dco, sd_div; @@ -355,8 +416,14 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * * Recalculate and propagate the DPLL rate. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else unsigned long omap3_dpll_recalc(struct clk *clk) { +#endif return omap2_get_dpll_rate(clk); } @@ -376,8 +443,14 @@ unsigned long omap3_dpll_recalc(struct clk *clk) * support low-power stop, or if the DPLL took too long to enter * bypass or lock, return -EINVAL; otherwise, return 0. */ +#ifdef CONFIG_COMMON_CLK +int omap3_noncore_dpll_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap3_noncore_dpll_enable(struct clk *clk) { +#endif int r; struct dpll_data *dd; struct clk *parent; @@ -386,15 +459,23 @@ int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(hw->clk); + + if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { +#else parent = __clk_get_parent(clk); if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { +#endif WARN_ON(parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); } else { WARN_ON(parent != dd->clk_ref); r = _omap3_noncore_dpll_lock(clk); } + +#ifndef CONFIG_COMMON_CLK /* *FIXME: this is dubious - if clk->rate has changed, what about * propagating? @@ -402,6 +483,7 @@ int omap3_noncore_dpll_enable(struct clk *clk) if (!r) clk->rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); +#endif return r; } @@ -413,8 +495,14 @@ int omap3_noncore_dpll_enable(struct clk *clk) * Instructs a non-CORE DPLL to enter low-power stop. This function is * intended for use in struct clkops. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_noncore_dpll_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else void omap3_noncore_dpll_disable(struct clk *clk) { +#endif _omap3_noncore_dpll_stop(clk); } @@ -432,6 +520,77 @@ void omap3_noncore_dpll_disable(struct clk *clk) * target rate if it hasn't been done already, then program and lock * the DPLL. Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct clk *new_parent = NULL; + u16 freqsel = 0; + struct dpll_data *dd; + int ret; + + if (!hw || !rate) + return -EINVAL; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref); + + if (__clk_get_rate(dd->clk_bypass) == rate && + (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + pr_debug("%s: %s: set rate: entering bypass.\n", + __func__, __clk_get_name(hw->clk)); + + ret = _omap3_noncore_dpll_bypass(clk); + if (!ret) + new_parent = dd->clk_bypass; + } else { + if (dd->last_rounded_rate != rate) + rate = __clk_round_rate(hw->clk, rate); + + if (dd->last_rounded_rate == 0) + return -EINVAL; + + /* No freqsel on OMAP4 and OMAP3630 */ + if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { + freqsel = _omap3_dpll_compute_freqsel(clk, + dd->last_rounded_n); + if (!freqsel) + WARN_ON(1); + } + + pr_debug("%s: %s: set rate: locking rate to %lu.\n", + __func__, __clk_get_name(hw->clk), rate); + + ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, + dd->last_rounded_n, freqsel); + if (!ret) + new_parent = dd->clk_ref; + } + /* + * FIXME - this is all wrong. common code handles reparenting and + * migrating prepare/enable counts. dplls should be a multiplexer + * clock and this should be a set_parent operation so that all of that + * stuff is inherited for free + */ + + if (!ret) + __clk_reparent(hw->clk, new_parent); + + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass); + + return 0; +} +#else int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { struct clk *new_parent = NULL; @@ -509,6 +668,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) return 0; } +#endif /* DPLL autoidle read/set code */ @@ -520,7 +680,11 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) * -EINVAL if passed a null pointer or if the struct clk does not * appear to refer to a DPLL. */ +#ifdef CONFIG_COMMON_CLK +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) +#else u32 omap3_dpll_autoidle_read(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -549,7 +713,11 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) * OMAP3430. The DPLL will enter low-power stop when its downstream * clocks are gated. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_dpll_allow_idle(struct clk_hw_omap *clk) +#else void omap3_dpll_allow_idle(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -560,8 +728,10 @@ void omap3_dpll_allow_idle(struct clk *clk) dd = clk->dpll_data; if (!dd->autoidle_reg) { +#ifndef CONFIG_COMMON_CLK pr_debug("clock: DPLL %s: autoidle not supported\n", __clk_get_name(clk)); +#endif return; } @@ -583,7 +753,11 @@ void omap3_dpll_allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_dpll_deny_idle(struct clk_hw_omap *clk) +#else void omap3_dpll_deny_idle(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -594,8 +768,10 @@ void omap3_dpll_deny_idle(struct clk *clk) dd = clk->dpll_data; if (!dd->autoidle_reg) { +#ifndef CONFIG_COMMON_CLK pr_debug("clock: DPLL %s: autoidle not supported\n", __clk_get_name(clk)); +#endif return; } @@ -615,6 +791,27 @@ void omap3_dpll_deny_idle(struct clk *clk) * Using parent clock DPLL data, look up DPLL state. If locked, set our * rate to the dpll_clk * 2; otherwise, just use dpll_clk. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + const struct dpll_data *dd; + unsigned long rate; + u32 v; + struct clk_hw_omap *pclk = NULL; + struct clk *parent; + + /* Walk up the parents of clk, looking for a DPLL */ + do { + do { + parent = __clk_get_parent(hw->clk); + hw = __clk_get_hw(parent); + } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); + if (!hw) + break; + pclk = to_clk_hw_omap(hw); + } while (pclk && !pclk->dpll_data); +#else unsigned long omap3_clkoutx2_recalc(struct clk *clk) { const struct dpll_data *dd; @@ -628,6 +825,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) while (pclk && !pclk->dpll_data) pclk = __clk_get_parent(pclk); + parent_rate = __clk_get_rate(__clk_get_parent(clk)); +#endif /* clk does not have a DPLL as a parent? error in the clock data */ if (!pclk) { WARN_ON(1); @@ -638,7 +837,6 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) WARN_ON(!dd->enable_mask); - parent_rate = __clk_get_rate(__clk_get_parent(clk)); v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) @@ -649,7 +847,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) } /* OMAP3/4 non-CORE DPLL clkops */ - +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap3_dpll = { + .allow_idle = omap3_dpll_allow_idle, + .deny_idle = omap3_dpll_deny_idle, +}; +#else const struct clkops clkops_omap3_noncore_dpll_ops = { .enable = omap3_noncore_dpll_enable, .disable = omap3_noncore_dpll_disable, @@ -661,3 +864,4 @@ const struct clkops clkops_omap3_core_dpll_ops = { .allow_idle = omap3_dpll_allow_idle, .deny_idle = omap3_dpll_deny_idle, }; +#endif diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 5854da1..aa75a3c 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -21,7 +21,11 @@ #include "cm-regbits-44xx.h" /* Supported only on OMAP4 */ +#ifdef CONFIG_COMMON_CLK +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) +#else int omap4_dpllmx_gatectrl_read(struct clk *clk) +#endif { u32 v; u32 mask; @@ -40,7 +44,11 @@ int omap4_dpllmx_gatectrl_read(struct clk *clk) return v; } +#ifdef CONFIG_COMMON_CLK +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) +#else void omap4_dpllmx_allow_gatectrl(struct clk *clk) +#endif { u32 v; u32 mask; @@ -58,7 +66,11 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } +#ifdef CONFIG_COMMON_CLK +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) +#else void omap4_dpllmx_deny_gatectrl(struct clk *clk) +#endif { u32 v; u32 mask; @@ -76,10 +88,17 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { + .allow_idle = omap4_dpllmx_allow_gatectrl, + .deny_idle = omap4_dpllmx_deny_gatectrl, +}; +#else const struct clkops clkops_omap4_dpllmx_ops = { .allow_idle = omap4_dpllmx_allow_gatectrl, .deny_idle = omap4_dpllmx_deny_gatectrl, }; +#endif /** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit @@ -90,8 +109,15 @@ const struct clkops clkops_omap4_dpllmx_ops = { * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) * upon success, or 0 upon error. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) { +#endif u32 v; unsigned long rate; struct dpll_data *dd; @@ -123,8 +149,16 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or * ~0 if an error occurred in omap2_dpll_round_rate(). */ +#ifdef CONFIG_COMMON_CLK +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) { +#endif u32 v; struct dpll_data *dd; long r; @@ -140,7 +174,11 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) if (v) target_rate = target_rate / OMAP4430_REGM4XEN_MULT; +#ifdef CONFIG_COMMON_CLK + r = omap2_dpll_round_rate(hw, target_rate, NULL); +#else r = omap2_dpll_round_rate(clk, target_rate); +#endif if (r == ~0) return r; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 03/26] ARM: OMAP4: clock: Convert to common clk 2012-11-08 1:12 ` [PATCH 03/26] ARM: OMAP4: clock: Convert to common clk Mike Turquette @ 2012-11-12 22:52 ` Paul Walmsley 2012-11-13 2:17 ` Paul Walmsley 1 sibling, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-12 22:52 UTC (permalink / raw) To: Mike Turquette Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette Fix a compiler warning on clockfw_lock, and add kerneldoc on the new non-trivial functions added by this patch, as is policy. Updated patch follows. - Paul From: Mike Turquette <mturquette@linaro.org> Date: Sat, 10 Nov 2012 16:58:41 -0700 Subject: [PATCH] ARM: OMAP4: clock: Convert to common clk Convert all OMAP4 specific platform files to use COMMON clk and keep all the changes under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. This converts all apis which will be called directly from COMMON clk to take a struct clk_hw parameter, and all the internal platform apis to take a struct clk_hw_omap parameter. Changes are based off the original patch from Mike Turquette. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: created new omap2_clksel_find_parent_index() rather than modifying omap2_init_clksel_parent(); moved clkhwops_iclk_wait to clkt_iclk.c to fix OMAP4-only builds; added clk-provider.h include to clock.h to try to fix some 3430-builds] [mturquette@ti.com: squash patch for omap2_clkops_{en,dis}able_clkdm; omap2_dflt_clk_is_enabled should not enable clocks] Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: fix compiler warning; update to apply; added kerneldoc on non-trivial new functions] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/clkt_clksel.c | 184 ++++++++++++++++++++++- arch/arm/mach-omap2/clkt_dpll.c | 54 ++++++- arch/arm/mach-omap2/clkt_iclk.c | 14 +- arch/arm/mach-omap2/clock.c | 294 ++++++++++++++++++++++++++++++++++++- arch/arm/mach-omap2/clock.h | 77 +++++++++- arch/arm/mach-omap2/dpll3xxx.c | 208 +++++++++++++++++++++++++- arch/arm/mach-omap2/dpll44xx.c | 38 +++++ 7 files changed, 850 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 53646fa..03ceb2e 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -41,7 +41,11 @@ #include <linux/kernel.h> #include <linux/errno.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <linux/bug.h> @@ -58,11 +62,18 @@ * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ +#ifdef CONFIG_COMMON_CLK +static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, +#else static const struct clksel *_get_clksel_by_parent(struct clk *clk, +#endif struct clk *src_clk) { const struct clksel *clks; + if (!src_clk) + return NULL; + for (clks = clk->clksel; clks->parent; clks++) if (clks->parent == src_clk) break; /* Found the requested parent */ @@ -70,7 +81,11 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); +#else __clk_get_name(clk), __clk_get_name(src_clk)); +#endif return NULL; } @@ -92,6 +107,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, * success (in this latter case, the corresponding register bitfield * value is passed back in the variable pointed to by @field_val) */ +#ifndef CONFIG_COMMON_CLK static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, u32 *field_val) { @@ -134,6 +150,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, return max_div; } +#endif /** * _write_clksel_reg() - program a clock's clksel register in hardware @@ -148,7 +165,11 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, * take into account any time the hardware might take to switch the * clock source. */ +#ifdef CONFIG_COMMON_CLK +static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) +#else static void _write_clksel_reg(struct clk *clk, u32 field_val) +#endif { u32 v; @@ -171,13 +192,22 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val) * before calling. Returns 0 on error or returns the actual integer divisor * upon success. */ +#ifdef CONFIG_COMMON_CLK +static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) +#else static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) +#endif { const struct clksel *clks; const struct clksel_rate *clkr; struct clk *parent; +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); +#else parent = __clk_get_parent(clk); +#endif + clks = _get_clksel_by_parent(clk, parent); if (!clks) return 0; @@ -193,7 +223,12 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), field_val, + __clk_get_name(parent)); +#else __clk_get_name(clk), field_val, __clk_get_name(parent)); +#endif return 0; } @@ -210,7 +245,11 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. */ +#ifdef CONFIG_COMMON_CLK +static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) +#else static u32 _divisor_to_clksel(struct clk *clk, u32 div) +#endif { const struct clksel *clks; const struct clksel_rate *clkr; @@ -219,7 +258,11 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) /* should never happen */ WARN_ON(div == 0); +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); +#else parent = __clk_get_parent(clk); +#endif clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -234,7 +277,12 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) if (!clkr->div) { pr_err("clock: %s: could not find divisor %d for parent %s\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), div, + __clk_get_name(parent)); +#else __clk_get_name(clk), div, __clk_get_name(parent)); +#endif return ~0; } @@ -249,7 +297,11 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ +#ifdef CONFIG_COMMON_CLK +static u32 _read_divisor(struct clk_hw_omap *clk) +#else static u32 _read_divisor(struct clk *clk) +#endif { u32 v; @@ -277,7 +329,12 @@ static u32 _read_divisor(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ +#ifdef CONFIG_COMMON_CLK +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, + unsigned long target_rate, +#else u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, +#endif u32 *new_div) { unsigned long test_rate; @@ -288,9 +345,14 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, unsigned long parent_rate; const char *clk_name; +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); + clk_name = __clk_get_name(clk->hw.clk); +#else parent = __clk_get_parent(clk); - parent_rate = __clk_get_rate(parent); clk_name = __clk_get_name(clk); +#endif + parent_rate = __clk_get_rate(parent); if (!clk->clksel || !clk->clksel_mask) return ~0; @@ -340,6 +402,63 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, * (i.e., those used in struct clk field function pointers, etc.) */ +#ifdef CONFIG_COMMON_CLK +/** + * omap2_clksel_find_parent_index() - return the array index of the current + * hardware parent of @hw + * @hw: struct clk_hw * to find the current hardware parent of + * + * Given a struct clk_hw pointer @hw to the 'hw' member of a struct + * clk_hw_omap record representing a source-selectable hardware clock, + * read the hardware register and determine what its parent is + * currently set to. Intended to be called only by the common clock + * framework struct clk_hw_ops.get_parent function pointer. Return + * the array index of this parent clock upon success -- there is no + * way to return an error, so if we encounter an error, just WARN() + * and pretend that we know that we're doing. + */ +u8 omap2_clksel_find_parent_index(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + const struct clksel *clks; + const struct clksel_rate *clkr; + u32 r, found = 0; + struct clk *parent; + const char *clk_name; + int ret = 0, f = 0; + + parent = __clk_get_parent(hw->clk); + clk_name = __clk_get_name(hw->clk); + + /* XXX should be able to return an error */ + WARN((!clk->clksel || !clk->clksel_mask), + "clock: %s: attempt to call on a non-clksel clock", clk_name); + + r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + r >>= __ffs(clk->clksel_mask); + + for (clks = clk->clksel; clks->parent && !found; clks++) { + for (clkr = clks->rates; clkr->div && !found; clkr++) { + if (!(clkr->flags & cpu_mask)) + continue; + + if (clkr->val == r) { + found = 1; + ret = f; + } + } + f++; + } + + /* This indicates a data error */ + WARN(!found, "clock: %s: init parent: could not find regval %0x\n", + clk_name, r); + + return ret; +} + +#else + /** * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr * @clk: OMAP clock struct ptr to use @@ -393,6 +512,8 @@ void omap2_init_clksel_parent(struct clk *clk) return; } +#endif + /** * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field * @clk: struct clk * @@ -402,6 +523,28 @@ void omap2_init_clksel_parent(struct clk *clk) * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) +{ + unsigned long rate; + u32 div = 0; + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + if (!parent_rate) + return 0; + + div = _read_divisor(clk); + if (!div) + rate = parent_rate; + else + rate = parent_rate / div; + + pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__, + __clk_get_name(hw->clk), rate, div); + + return rate; +} +#else unsigned long omap2_clksel_recalc(struct clk *clk) { unsigned long rate; @@ -420,6 +563,7 @@ unsigned long omap2_clksel_recalc(struct clk *clk) return rate; } +#endif /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate @@ -432,8 +576,15 @@ unsigned long omap2_clksel_recalc(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ +#ifdef CONFIG_COMMON_CLK +long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) { +#endif u32 new_div; return omap2_clksel_round_rate_div(clk, target_rate, &new_div); @@ -454,8 +605,15 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) * is changed, they will all be affected without any notification. * Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) { +#endif u32 field_val, validrate, new_div = 0; if (!clk->clksel || !clk->clksel_mask) @@ -471,11 +629,16 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) _write_clksel_reg(clk, field_val); - clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; - +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), + __clk_get_rate(hw->clk)); +#else pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), __clk_get_rate(clk)); + clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; +#endif + return 0; } @@ -499,6 +662,18 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) * affected without any notification. Returns -EINVAL upon error, or * 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + if (!clk->clksel || !clk->clksel_mask) + return -EINVAL; + + _write_clksel_reg(clk, field_val); + return 0; +} +#else int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) { u32 field_val = 0; @@ -510,7 +685,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) parent_div = _get_div_and_fieldval(new_parent, clk, &field_val); if (!parent_div) return -EINVAL; - _write_clksel_reg(clk, field_val); clk_reparent(clk, new_parent); @@ -520,7 +694,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) if (parent_div > 0) __clk_get_rate(clk) /= parent_div; - pr_debug("clock: %s: set parent to %s (new rate %ld)\n", __clk_get_name(clk), __clk_get_name(__clk_get_parent(clk)), @@ -528,3 +701,4 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) return 0; } +#endif diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 8463cc3..f343389 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -16,7 +16,11 @@ #include <linux/kernel.h> #include <linux/errno.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <asm/div64.h> @@ -76,7 +80,11 @@ * (assuming that it is counting N upwards), or -2 if the enclosing loop * should skip to the next iteration (again assuming N is increasing). */ +#ifdef CONFIG_COMMON_CLK +static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) +#else static int _dpll_test_fint(struct clk *clk, u8 n) +#endif { struct dpll_data *dd; long fint, fint_min, fint_max; @@ -85,7 +93,11 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data; /* DPLL divider must result in a valid jitter correction val */ +#ifdef CONFIG_COMMON_CLK + fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; +#else fint = __clk_get_rate(__clk_get_parent(clk)) / n; +#endif if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -186,15 +198,24 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, } /* Public functions */ - +#ifdef CONFIG_COMMON_CLK +u8 omap2_init_dpll_parent(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else void omap2_init_dpll_parent(struct clk *clk) { +#endif u32 v; struct dpll_data *dd; dd = clk->dpll_data; if (!dd) +#ifdef CONFIG_COMMON_CLK + return -EINVAL; +#else return; +#endif v = __raw_readl(dd->control_reg); v &= dd->enable_mask; @@ -204,18 +225,34 @@ void omap2_init_dpll_parent(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } +#ifdef CONFIG_COMMON_CLK + return 0; +#else return; +#endif } /** @@ -232,7 +269,11 @@ void omap2_init_dpll_parent(struct clk *clk) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * if the clock @clk is not a DPLL. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) +#else u32 omap2_get_dpll_rate(struct clk *clk) +#endif { long long dpll_clk; u32 dpll_mult, dpll_div, v; @@ -288,8 +329,15 @@ u32 omap2_get_dpll_rate(struct clk *clk) * (expensive) function again. Returns ~0 if the target rate cannot * be rounded, or the rounded rate upon success. */ +#ifdef CONFIG_COMMON_CLK +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) { +#endif int m, n, r, scaled_max_m; unsigned long scaled_rt_rp; unsigned long new_rate = 0; @@ -303,7 +351,11 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd = clk->dpll_data; ref_rate = __clk_get_rate(dd->clk_ref); +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(hw->clk); +#else clk_name = __clk_get_name(clk); +#endif pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", clk_name, target_rate); diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index fe774a0..3b661ba 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -11,7 +11,11 @@ #undef DEBUG #include <linux/kernel.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> @@ -48,6 +52,14 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk) /* Public data */ +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_iclk_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_omap2_iclk_dflt_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, @@ -77,4 +89,4 @@ const struct clkops clkops_omap2_mdmclk_dflt_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, }; - +#endif diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e381d991..72d7105 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -20,7 +20,11 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/delay.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <linux/bitops.h> @@ -57,7 +61,33 @@ static bool clkdm_control = true; static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); +#ifndef CONFIG_COMMON_CLK static DEFINE_SPINLOCK(clockfw_lock); +#endif + +#ifdef CONFIG_COMMON_CLK + +/* + * Used for clocks that have the same value as the parent clock, + * divided by some factor + */ +unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *oclk; + + if (!hw) { + pr_warn("%s: hw is NULL\n", __func__); + return -EINVAL; + } + + oclk = to_clk_hw_omap(hw); + + WARN_ON(!oclk->fixed_div); + + return parent_rate / oclk->fixed_div; +} +#endif /* * OMAP2+ specific clock functions @@ -109,7 +139,11 @@ static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest, * belong in the clock code and will be moved in the medium term to * module-dependent code. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void _omap2_module_wait_ready(struct clk_hw_omap *clk) +#else static void _omap2_module_wait_ready(struct clk *clk) +#endif { void __iomem *companion_reg, *idlest_reg; u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; @@ -124,12 +158,15 @@ static void _omap2_module_wait_ready(struct clk *clk) } clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); - r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); if (r) { /* IDLEST register not in the CM module */ _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk)); +#else clk->name); +#endif } else { cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); }; @@ -145,15 +182,25 @@ static void _omap2_module_wait_ready(struct clk *clk) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap2_init_clk_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else void omap2_init_clk_clkdm(struct clk *clk) { +#endif struct clockdomain *clkdm; const char *clk_name; if (!clk->clkdm_name) return; +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(hw->clk); +#else clk_name = __clk_get_name(clk); +#endif clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { @@ -200,8 +247,12 @@ void __init omap2_clk_disable_clkdm_control(void) * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit) +#ifdef CONFIG_COMMON_CLK +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, +#else +void omap2_clk_dflt_find_companion(struct clk *clk, +#endif + void __iomem **other_reg, u8 *other_bit) { u32 r; @@ -229,8 +280,12 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * register address ID (e.g., that CM_FCLKEN2 corresponds to * CM_IDLEST2). This is not true for all modules. No return value. */ -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val) +#ifdef CONFIG_COMMON_CLK +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, +#else +void omap2_clk_dflt_find_idlest(struct clk *clk, +#endif + void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) { u32 r; @@ -252,6 +307,225 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, } +#ifdef CONFIG_COMMON_CLK +/** + * omap2_dflt_clk_enable - enable a clock in the hardware + * @hw: struct clk_hw * of the clock to enable + * + * Enable the clock @hw in the hardware. We first call into the OMAP + * clockdomain code to "enable" the corresponding clockdomain if this + * is the first enabled user of the clockdomain. Then program the + * hardware to enable the clock. Then wait for the IP block that uses + * this clock to leave idle (if applicable). Returns the error value + * from clkdm_clk_enable() if it terminated with an error, or -EINVAL + * if @hw has a null clock enable_reg, or zero upon success. + */ +int omap2_dflt_clk_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + u32 v; + int ret = 0; + + clk = to_clk_hw_omap(hw); + + if (clkdm_control && clk->clkdm) { + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, ret); + return ret; + } + } + + if (unlikely(clk->enable_reg == NULL)) { + pr_err("%s: %s missing enable_reg\n", __func__, + __clk_get_name(hw->clk)); + ret = -EINVAL; + goto err; + } + + /* FIXME should not have INVERT_ENABLE bit here */ + v = __raw_readl(clk->enable_reg); + if (clk->flags & INVERT_ENABLE) + v &= ~(1 << clk->enable_bit); + else + v |= (1 << clk->enable_bit); + __raw_writel(v, clk->enable_reg); + v = __raw_readl(clk->enable_reg); /* OCP barrier */ + + if (clk->ops && clk->ops->find_idlest) + _omap2_module_wait_ready(clk); + + return 0; + +err: + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); + return ret; +} + +/** + * omap2_dflt_clk_disable - disable a clock in the hardware + * @hw: struct clk_hw * of the clock to disable + * + * Disable the clock @hw in the hardware, and call into the OMAP + * clockdomain code to "disable" the corresponding clockdomain if all + * clocks/hwmods in that clockdomain are now disabled. No return + * value. + */ +void omap2_dflt_clk_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + u32 v; + + clk = to_clk_hw_omap(hw); + if (!clk->enable_reg) { + /* + * 'independent' here refers to a clock which is not + * controlled by its parent. + */ + pr_err("%s: independent clock %s has no enable_reg\n", + __func__, __clk_get_name(hw->clk)); + return; + } + + v = __raw_readl(clk->enable_reg); + if (clk->flags & INVERT_ENABLE) + v |= (1 << clk->enable_bit); + else + v &= ~(1 << clk->enable_bit); + __raw_writel(v, clk->enable_reg); + /* No OCP barrier needed here since it is a disable operation */ + + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); +} + +/** + * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being enabled + * + * Increment the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 1, the clockdomain will be "enabled." + * Only needed for clocks that don't use omap2_dflt_clk_enable() as + * their enable function pointer. Passes along the return value of + * clkdm_clk_enable(), -EINVAL if @hw is not associated with a + * clockdomain, or 0 if clock framework-based clockdomain control is + * not implemented. + */ +int omap2_clkops_enable_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + int ret = 0; + + clk = to_clk_hw_omap(hw); + + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return -EINVAL; + } + + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return 0; + } + + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); + + return ret; +} + +/** + * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being disabled + * + * Decrement the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 0, the clockdomain will be "disabled." + * Only needed for clocks that don't use omap2_dflt_clk_disable() as their + * disable function pointer. No return value. + */ +void omap2_clkops_disable_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + + clk = to_clk_hw_omap(hw); + + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return; + } + + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return; + } + + clkdm_clk_disable(clk->clkdm, hw->clk); +} + +/** + * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? + * @hw: struct clk_hw * to check + * + * Return 1 if the clock represented by @hw is enabled in the + * hardware, or 0 otherwise. Intended for use in the struct + * clk_ops.is_enabled function pointer. + */ +int omap2_dflt_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 v; + + v = __raw_readl(clk->enable_reg); + + if (clk->flags & INVERT_ENABLE) + v ^= BIT(clk->enable_bit); + + v &= BIT(clk->enable_bit); + + return v ? 1 : 0; +} + +static int __initdata mpurate; + +/* + * By default we use the rate set by the bootloader. + * You can override this with mpurate= cmdline option. + */ +static int __init omap_clk_setup(char *str) +{ + get_option(&str, &mpurate); + + if (!mpurate) + return 1; + + if (mpurate < 1000) + mpurate *= 1000000; + + return 1; +} +__setup("mpurate=", omap_clk_setup); + +const struct clk_hw_omap_ops clkhwops_wait = { + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else int omap2_dflt_clk_enable(struct clk *clk) { u32 v; @@ -482,6 +756,8 @@ void omap2_clk_disable_unused(struct clk *clk) } #endif +#endif /* CONFIG_COMMON_CLK */ + /** * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument * @mpurate_ck_name: clk name of the clock to change rate @@ -512,13 +788,15 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) r = clk_set_rate(mpurate_ck, mpurate); if (IS_ERR_VALUE(r)) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", - mpurate_ck->name, mpurate, r); + mpurate_ck_name, mpurate, r); clk_put(mpurate_ck); return -EINVAL; } calibrate_delay(); +#ifndef CONFIG_COMMON_CLK recalculate_root_clocks(); +#endif clk_put(mpurate_ck); @@ -564,8 +842,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(mpu_ck) / 1000000)); } +#ifndef CONFIG_COMMON_CLK /* Common data */ - int clk_enable(struct clk *clk) { unsigned long flags; @@ -1072,4 +1350,4 @@ err_out: late_initcall(clk_debugfs_init); #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ - +#endif /* CONFIG_COMMON_CLK */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 697e044..5a4f4fe 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -397,6 +397,7 @@ extern const struct clkops clkops_null; extern struct clk dummy_ck; +#endif /* CONFIG_COMMON_CLK */ /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 @@ -427,11 +428,36 @@ extern struct clk dummy_ck; /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 +#ifndef CONFIG_COMMON_CLK int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); +#endif /* CONFIG_COMMON_CLK */ + +#ifdef CONFIG_COMMON_CLK +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); +int omap3_noncore_dpll_enable(struct clk_hw *hw); +void omap3_noncore_dpll_disable(struct clk_hw *hw); +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); +void omap3_dpll_allow_idle(struct clk_hw_omap *clk); +void omap3_dpll_deny_idle(struct clk_hw_omap *clk); +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate); +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate); +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate); +#else long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); unsigned long omap3_dpll_recalc(struct clk *clk); unsigned long omap3_clkoutx2_recalc(struct clk *clk); @@ -446,17 +472,33 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk); void omap4_dpllmx_deny_gatectrl(struct clk *clk); long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); +#endif #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk); #else #define omap2_clk_disable_unused NULL #endif - +#ifdef CONFIG_COMMON_CLK +void omap2_init_clk_clkdm(struct clk_hw *clk); +#else void omap2_init_clk_clkdm(struct clk *clk); +#endif void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ +#ifdef CONFIG_COMMON_CLK +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, + unsigned long target_rate, + u32 *new_div); +u8 omap2_clksel_find_parent_index(struct clk_hw *hw); +unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); +long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); +#else u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 *new_div); void omap2_init_clksel_parent(struct clk *clk); @@ -464,20 +506,38 @@ unsigned long omap2_clksel_recalc(struct clk *clk); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); +#endif /* clkt_iclk.c public functions */ extern void omap2_clkt_iclk_allow_idle(struct clk *clk); extern void omap2_clkt_iclk_deny_idle(struct clk *clk); +#ifdef CONFIG_COMMON_CLK +u8 omap2_init_dpll_parent(struct clk_hw *hw); +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); +#else u32 omap2_get_dpll_rate(struct clk *clk); void omap2_init_dpll_parent(struct clk *clk); +#endif +#ifdef CONFIG_COMMON_CLK +int omap2_dflt_clk_enable(struct clk_hw *hw); +void omap2_dflt_clk_disable(struct clk_hw *hw); +int omap2_dflt_clk_is_enabled(struct clk_hw *hw); +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, + u8 *other_bit); +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, u8 *idlest_val); +#else int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, u8 *other_bit); void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); +#endif int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -496,6 +556,13 @@ extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; +#ifdef CONFIG_COMMON_CLK +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; +extern const struct clk_hw_omap_ops clkhwops_iclk_wait; +extern const struct clk_hw_omap_ops clkhwops_wait; +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; +#endif + extern const struct clkops clkops_omap2_iclk_dflt_wait; extern const struct clkops clkops_omap2_iclk_dflt; extern const struct clkops clkops_omap2_iclk_idle_only; @@ -513,11 +580,17 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; +#ifndef CONFIG_COMMON_CLK /* clocks shared between various OMAP SoCs */ extern struct clk virt_19200000_ck; extern struct clk virt_26000000_ck; +#endif extern int am33xx_clk_init(void); -#endif /* CONFIG_COMMON_CLK */ +#ifdef CONFIG_COMMON_CLK +extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); +extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); +#endif + #endif diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index eacf51f..721588f 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -42,7 +42,11 @@ /* Private functions */ /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ +#ifdef CONFIG_COMMON_CLK +static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) +#else static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) +#endif { const struct dpll_data *dd; u32 v; @@ -56,7 +60,11 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) } /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) +#else static int _omap3_wait_dpll_status(struct clk *clk, u8 state) +#endif { const struct dpll_data *dd; int i = 0; @@ -64,7 +72,11 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) const char *clk_name; dd = clk->dpll_data; +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(clk->hw.clk); +#else clk_name = __clk_get_name(clk); +#endif state <<= __ffs(dd->idlest_mask); @@ -88,7 +100,11 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) } /* From 3430 TRM ES2 4.7.6.2 */ +#ifdef CONFIG_COMMON_CLK +static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) +#else static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) +#endif { unsigned long fint; u16 f = 0; @@ -133,14 +149,22 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) * locked successfully, return 0; if the DPLL did not lock in the time * allotted, or DPLL3 was passed in, return -EINVAL. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_lock(struct clk *clk) +#endif { const struct dpll_data *dd; u8 ai; u8 state = 1; int r = 0; +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); +#else pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); +#endif dd = clk->dpll_data; state <<= __ffs(dd->idlest_mask); @@ -178,7 +202,11 @@ done: * DPLL3 was passed in, or the DPLL does not support low-power bypass, * return -EINVAL. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_bypass(struct clk *clk) +#endif { int r; u8 ai; @@ -187,7 +215,11 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) return -EINVAL; pr_debug("clock: configuring DPLL %s for low-power bypass\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk)); +#else __clk_get_name(clk)); +#endif ai = omap3_dpll_autoidle_read(clk); @@ -210,14 +242,22 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) * code. If DPLL3 was passed in, or the DPLL does not support * low-power stop, return -EINVAL; otherwise, return 0. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_stop(struct clk *clk) +#endif { u8 ai; if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) return -EINVAL; +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); +#else pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); +#endif ai = omap3_dpll_autoidle_read(clk); @@ -241,11 +281,19 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ +#ifdef CONFIG_COMMON_CLK +static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) +#else static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) +#endif { unsigned long fint, clkinp; /* watch out for overflow */ +#ifdef CONFIG_COMMON_CLK + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); +#else clkinp = __clk_get_rate(__clk_get_parent(clk)); +#endif fint = (clkinp / n) * m; if (fint < 1000000000) @@ -266,12 +314,20 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ +#ifdef CONFIG_COMMON_CLK +static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) +#else static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) +#endif { unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2; +#ifdef CONFIG_COMMON_CLK + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); +#else clkinp = __clk_get_rate(__clk_get_parent(clk)); +#endif /* * target sigma-delta to near 250MHz @@ -298,7 +354,12 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) * Program the DPLL with the supplied M, N values, and wait for the DPLL to * lock.. Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n, + u16 freqsel) +#else static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) +#endif { struct dpll_data *dd = clk->dpll_data; u8 dco, sd_div; @@ -355,8 +416,14 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * * Recalculate and propagate the DPLL rate. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else unsigned long omap3_dpll_recalc(struct clk *clk) { +#endif return omap2_get_dpll_rate(clk); } @@ -376,8 +443,14 @@ unsigned long omap3_dpll_recalc(struct clk *clk) * support low-power stop, or if the DPLL took too long to enter * bypass or lock, return -EINVAL; otherwise, return 0. */ +#ifdef CONFIG_COMMON_CLK +int omap3_noncore_dpll_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap3_noncore_dpll_enable(struct clk *clk) { +#endif int r; struct dpll_data *dd; struct clk *parent; @@ -386,15 +459,23 @@ int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(hw->clk); + + if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { +#else parent = __clk_get_parent(clk); if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { +#endif WARN_ON(parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); } else { WARN_ON(parent != dd->clk_ref); r = _omap3_noncore_dpll_lock(clk); } + +#ifndef CONFIG_COMMON_CLK /* *FIXME: this is dubious - if clk->rate has changed, what about * propagating? @@ -402,6 +483,7 @@ int omap3_noncore_dpll_enable(struct clk *clk) if (!r) clk->rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); +#endif return r; } @@ -413,8 +495,14 @@ int omap3_noncore_dpll_enable(struct clk *clk) * Instructs a non-CORE DPLL to enter low-power stop. This function is * intended for use in struct clkops. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_noncore_dpll_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else void omap3_noncore_dpll_disable(struct clk *clk) { +#endif _omap3_noncore_dpll_stop(clk); } @@ -432,6 +520,77 @@ void omap3_noncore_dpll_disable(struct clk *clk) * target rate if it hasn't been done already, then program and lock * the DPLL. Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct clk *new_parent = NULL; + u16 freqsel = 0; + struct dpll_data *dd; + int ret; + + if (!hw || !rate) + return -EINVAL; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref); + + if (__clk_get_rate(dd->clk_bypass) == rate && + (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + pr_debug("%s: %s: set rate: entering bypass.\n", + __func__, __clk_get_name(hw->clk)); + + ret = _omap3_noncore_dpll_bypass(clk); + if (!ret) + new_parent = dd->clk_bypass; + } else { + if (dd->last_rounded_rate != rate) + rate = __clk_round_rate(hw->clk, rate); + + if (dd->last_rounded_rate == 0) + return -EINVAL; + + /* No freqsel on OMAP4 and OMAP3630 */ + if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { + freqsel = _omap3_dpll_compute_freqsel(clk, + dd->last_rounded_n); + if (!freqsel) + WARN_ON(1); + } + + pr_debug("%s: %s: set rate: locking rate to %lu.\n", + __func__, __clk_get_name(hw->clk), rate); + + ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, + dd->last_rounded_n, freqsel); + if (!ret) + new_parent = dd->clk_ref; + } + /* + * FIXME - this is all wrong. common code handles reparenting and + * migrating prepare/enable counts. dplls should be a multiplexer + * clock and this should be a set_parent operation so that all of that + * stuff is inherited for free + */ + + if (!ret) + __clk_reparent(hw->clk, new_parent); + + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass); + + return 0; +} +#else int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { struct clk *new_parent = NULL; @@ -509,6 +668,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) return 0; } +#endif /* DPLL autoidle read/set code */ @@ -520,7 +680,11 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) * -EINVAL if passed a null pointer or if the struct clk does not * appear to refer to a DPLL. */ +#ifdef CONFIG_COMMON_CLK +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) +#else u32 omap3_dpll_autoidle_read(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -549,7 +713,11 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) * OMAP3430. The DPLL will enter low-power stop when its downstream * clocks are gated. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_dpll_allow_idle(struct clk_hw_omap *clk) +#else void omap3_dpll_allow_idle(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -560,8 +728,10 @@ void omap3_dpll_allow_idle(struct clk *clk) dd = clk->dpll_data; if (!dd->autoidle_reg) { +#ifndef CONFIG_COMMON_CLK pr_debug("clock: DPLL %s: autoidle not supported\n", __clk_get_name(clk)); +#endif return; } @@ -583,7 +753,11 @@ void omap3_dpll_allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_dpll_deny_idle(struct clk_hw_omap *clk) +#else void omap3_dpll_deny_idle(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -594,8 +768,10 @@ void omap3_dpll_deny_idle(struct clk *clk) dd = clk->dpll_data; if (!dd->autoidle_reg) { +#ifndef CONFIG_COMMON_CLK pr_debug("clock: DPLL %s: autoidle not supported\n", __clk_get_name(clk)); +#endif return; } @@ -615,6 +791,27 @@ void omap3_dpll_deny_idle(struct clk *clk) * Using parent clock DPLL data, look up DPLL state. If locked, set our * rate to the dpll_clk * 2; otherwise, just use dpll_clk. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + const struct dpll_data *dd; + unsigned long rate; + u32 v; + struct clk_hw_omap *pclk = NULL; + struct clk *parent; + + /* Walk up the parents of clk, looking for a DPLL */ + do { + do { + parent = __clk_get_parent(hw->clk); + hw = __clk_get_hw(parent); + } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); + if (!hw) + break; + pclk = to_clk_hw_omap(hw); + } while (pclk && !pclk->dpll_data); +#else unsigned long omap3_clkoutx2_recalc(struct clk *clk) { const struct dpll_data *dd; @@ -628,6 +825,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) while (pclk && !pclk->dpll_data) pclk = __clk_get_parent(pclk); + parent_rate = __clk_get_rate(__clk_get_parent(clk)); +#endif /* clk does not have a DPLL as a parent? error in the clock data */ if (!pclk) { WARN_ON(1); @@ -638,7 +837,6 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) WARN_ON(!dd->enable_mask); - parent_rate = __clk_get_rate(__clk_get_parent(clk)); v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) @@ -649,7 +847,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) } /* OMAP3/4 non-CORE DPLL clkops */ - +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap3_dpll = { + .allow_idle = omap3_dpll_allow_idle, + .deny_idle = omap3_dpll_deny_idle, +}; +#else const struct clkops clkops_omap3_noncore_dpll_ops = { .enable = omap3_noncore_dpll_enable, .disable = omap3_noncore_dpll_disable, @@ -661,3 +864,4 @@ const struct clkops clkops_omap3_core_dpll_ops = { .allow_idle = omap3_dpll_allow_idle, .deny_idle = omap3_dpll_deny_idle, }; +#endif diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 5854da1..aa75a3c 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -21,7 +21,11 @@ #include "cm-regbits-44xx.h" /* Supported only on OMAP4 */ +#ifdef CONFIG_COMMON_CLK +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) +#else int omap4_dpllmx_gatectrl_read(struct clk *clk) +#endif { u32 v; u32 mask; @@ -40,7 +44,11 @@ int omap4_dpllmx_gatectrl_read(struct clk *clk) return v; } +#ifdef CONFIG_COMMON_CLK +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) +#else void omap4_dpllmx_allow_gatectrl(struct clk *clk) +#endif { u32 v; u32 mask; @@ -58,7 +66,11 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } +#ifdef CONFIG_COMMON_CLK +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) +#else void omap4_dpllmx_deny_gatectrl(struct clk *clk) +#endif { u32 v; u32 mask; @@ -76,10 +88,17 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { + .allow_idle = omap4_dpllmx_allow_gatectrl, + .deny_idle = omap4_dpllmx_deny_gatectrl, +}; +#else const struct clkops clkops_omap4_dpllmx_ops = { .allow_idle = omap4_dpllmx_allow_gatectrl, .deny_idle = omap4_dpllmx_deny_gatectrl, }; +#endif /** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit @@ -90,8 +109,15 @@ const struct clkops clkops_omap4_dpllmx_ops = { * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) * upon success, or 0 upon error. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) { +#endif u32 v; unsigned long rate; struct dpll_data *dd; @@ -123,8 +149,16 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or * ~0 if an error occurred in omap2_dpll_round_rate(). */ +#ifdef CONFIG_COMMON_CLK +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) { +#endif u32 v; struct dpll_data *dd; long r; @@ -140,7 +174,11 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) if (v) target_rate = target_rate / OMAP4430_REGM4XEN_MULT; +#ifdef CONFIG_COMMON_CLK + r = omap2_dpll_round_rate(hw, target_rate, NULL); +#else r = omap2_dpll_round_rate(clk, target_rate); +#endif if (r == ~0) return r; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 03/26] ARM: OMAP4: clock: Convert to common clk 2012-11-08 1:12 ` [PATCH 03/26] ARM: OMAP4: clock: Convert to common clk Mike Turquette 2012-11-12 22:52 ` Paul Walmsley @ 2012-11-13 2:17 ` Paul Walmsley 1 sibling, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-13 2:17 UTC (permalink / raw) To: Mike Turquette Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette Here's an updated version of this one with the dpll3xxx.c changes rolled in. - Paul From: Mike Turquette <mturquette@linaro.org> Date: Sat, 10 Nov 2012 16:58:41 -0700 Subject: [PATCH] ARM: OMAP4: clock: Convert to common clk Convert all OMAP4 specific platform files to use COMMON clk and keep all the changes under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. This converts all apis which will be called directly from COMMON clk to take a struct clk_hw parameter, and all the internal platform apis to take a struct clk_hw_omap parameter. Changes are based off the original patch from Mike Turquette. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: created new omap2_clksel_find_parent_index() rather than modifying omap2_init_clksel_parent(); moved clkhwops_iclk_wait to clkt_iclk.c to fix OMAP4-only builds; added clk-provider.h include to clock.h to try to fix some 3430-builds] [mturquette@ti.com: squash patch for omap2_clkops_{en,dis}able_clkdm; omap2_dflt_clk_is_enabled should not enable clocks] Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: fix compiler warning; update to apply; added kerneldoc on non-trivial new functions; added the dpll3xxx clockdomain modifications] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/clkt_clksel.c | 184 ++++++++++++++++++++++- arch/arm/mach-omap2/clkt_dpll.c | 54 ++++++- arch/arm/mach-omap2/clkt_iclk.c | 14 +- arch/arm/mach-omap2/clock.c | 294 ++++++++++++++++++++++++++++++++++++- arch/arm/mach-omap2/clock.h | 77 +++++++++- arch/arm/mach-omap2/dpll3xxx.c | 226 +++++++++++++++++++++++++++- arch/arm/mach-omap2/dpll44xx.c | 38 +++++ 7 files changed, 868 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 53646fa..03ceb2e 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -41,7 +41,11 @@ #include <linux/kernel.h> #include <linux/errno.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <linux/bug.h> @@ -58,11 +62,18 @@ * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ +#ifdef CONFIG_COMMON_CLK +static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, +#else static const struct clksel *_get_clksel_by_parent(struct clk *clk, +#endif struct clk *src_clk) { const struct clksel *clks; + if (!src_clk) + return NULL; + for (clks = clk->clksel; clks->parent; clks++) if (clks->parent == src_clk) break; /* Found the requested parent */ @@ -70,7 +81,11 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); +#else __clk_get_name(clk), __clk_get_name(src_clk)); +#endif return NULL; } @@ -92,6 +107,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, * success (in this latter case, the corresponding register bitfield * value is passed back in the variable pointed to by @field_val) */ +#ifndef CONFIG_COMMON_CLK static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, u32 *field_val) { @@ -134,6 +150,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, return max_div; } +#endif /** * _write_clksel_reg() - program a clock's clksel register in hardware @@ -148,7 +165,11 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, * take into account any time the hardware might take to switch the * clock source. */ +#ifdef CONFIG_COMMON_CLK +static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) +#else static void _write_clksel_reg(struct clk *clk, u32 field_val) +#endif { u32 v; @@ -171,13 +192,22 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val) * before calling. Returns 0 on error or returns the actual integer divisor * upon success. */ +#ifdef CONFIG_COMMON_CLK +static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) +#else static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) +#endif { const struct clksel *clks; const struct clksel_rate *clkr; struct clk *parent; +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); +#else parent = __clk_get_parent(clk); +#endif + clks = _get_clksel_by_parent(clk, parent); if (!clks) return 0; @@ -193,7 +223,12 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), field_val, + __clk_get_name(parent)); +#else __clk_get_name(clk), field_val, __clk_get_name(parent)); +#endif return 0; } @@ -210,7 +245,11 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. */ +#ifdef CONFIG_COMMON_CLK +static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) +#else static u32 _divisor_to_clksel(struct clk *clk, u32 div) +#endif { const struct clksel *clks; const struct clksel_rate *clkr; @@ -219,7 +258,11 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) /* should never happen */ WARN_ON(div == 0); +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); +#else parent = __clk_get_parent(clk); +#endif clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -234,7 +277,12 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) if (!clkr->div) { pr_err("clock: %s: could not find divisor %d for parent %s\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk), div, + __clk_get_name(parent)); +#else __clk_get_name(clk), div, __clk_get_name(parent)); +#endif return ~0; } @@ -249,7 +297,11 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ +#ifdef CONFIG_COMMON_CLK +static u32 _read_divisor(struct clk_hw_omap *clk) +#else static u32 _read_divisor(struct clk *clk) +#endif { u32 v; @@ -277,7 +329,12 @@ static u32 _read_divisor(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ +#ifdef CONFIG_COMMON_CLK +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, + unsigned long target_rate, +#else u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, +#endif u32 *new_div) { unsigned long test_rate; @@ -288,9 +345,14 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, unsigned long parent_rate; const char *clk_name; +#ifdef CONFIG_COMMON_CLK + parent = __clk_get_parent(clk->hw.clk); + clk_name = __clk_get_name(clk->hw.clk); +#else parent = __clk_get_parent(clk); - parent_rate = __clk_get_rate(parent); clk_name = __clk_get_name(clk); +#endif + parent_rate = __clk_get_rate(parent); if (!clk->clksel || !clk->clksel_mask) return ~0; @@ -340,6 +402,63 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, * (i.e., those used in struct clk field function pointers, etc.) */ +#ifdef CONFIG_COMMON_CLK +/** + * omap2_clksel_find_parent_index() - return the array index of the current + * hardware parent of @hw + * @hw: struct clk_hw * to find the current hardware parent of + * + * Given a struct clk_hw pointer @hw to the 'hw' member of a struct + * clk_hw_omap record representing a source-selectable hardware clock, + * read the hardware register and determine what its parent is + * currently set to. Intended to be called only by the common clock + * framework struct clk_hw_ops.get_parent function pointer. Return + * the array index of this parent clock upon success -- there is no + * way to return an error, so if we encounter an error, just WARN() + * and pretend that we know that we're doing. + */ +u8 omap2_clksel_find_parent_index(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + const struct clksel *clks; + const struct clksel_rate *clkr; + u32 r, found = 0; + struct clk *parent; + const char *clk_name; + int ret = 0, f = 0; + + parent = __clk_get_parent(hw->clk); + clk_name = __clk_get_name(hw->clk); + + /* XXX should be able to return an error */ + WARN((!clk->clksel || !clk->clksel_mask), + "clock: %s: attempt to call on a non-clksel clock", clk_name); + + r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + r >>= __ffs(clk->clksel_mask); + + for (clks = clk->clksel; clks->parent && !found; clks++) { + for (clkr = clks->rates; clkr->div && !found; clkr++) { + if (!(clkr->flags & cpu_mask)) + continue; + + if (clkr->val == r) { + found = 1; + ret = f; + } + } + f++; + } + + /* This indicates a data error */ + WARN(!found, "clock: %s: init parent: could not find regval %0x\n", + clk_name, r); + + return ret; +} + +#else + /** * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr * @clk: OMAP clock struct ptr to use @@ -393,6 +512,8 @@ void omap2_init_clksel_parent(struct clk *clk) return; } +#endif + /** * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field * @clk: struct clk * @@ -402,6 +523,28 @@ void omap2_init_clksel_parent(struct clk *clk) * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) +{ + unsigned long rate; + u32 div = 0; + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + if (!parent_rate) + return 0; + + div = _read_divisor(clk); + if (!div) + rate = parent_rate; + else + rate = parent_rate / div; + + pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__, + __clk_get_name(hw->clk), rate, div); + + return rate; +} +#else unsigned long omap2_clksel_recalc(struct clk *clk) { unsigned long rate; @@ -420,6 +563,7 @@ unsigned long omap2_clksel_recalc(struct clk *clk) return rate; } +#endif /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate @@ -432,8 +576,15 @@ unsigned long omap2_clksel_recalc(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ +#ifdef CONFIG_COMMON_CLK +long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) { +#endif u32 new_div; return omap2_clksel_round_rate_div(clk, target_rate, &new_div); @@ -454,8 +605,15 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) * is changed, they will all be affected without any notification. * Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) { +#endif u32 field_val, validrate, new_div = 0; if (!clk->clksel || !clk->clksel_mask) @@ -471,11 +629,16 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) _write_clksel_reg(clk, field_val); - clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; - +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), + __clk_get_rate(hw->clk)); +#else pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), __clk_get_rate(clk)); + clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; +#endif + return 0; } @@ -499,6 +662,18 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) * affected without any notification. Returns -EINVAL upon error, or * 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + if (!clk->clksel || !clk->clksel_mask) + return -EINVAL; + + _write_clksel_reg(clk, field_val); + return 0; +} +#else int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) { u32 field_val = 0; @@ -510,7 +685,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) parent_div = _get_div_and_fieldval(new_parent, clk, &field_val); if (!parent_div) return -EINVAL; - _write_clksel_reg(clk, field_val); clk_reparent(clk, new_parent); @@ -520,7 +694,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) if (parent_div > 0) __clk_get_rate(clk) /= parent_div; - pr_debug("clock: %s: set parent to %s (new rate %ld)\n", __clk_get_name(clk), __clk_get_name(__clk_get_parent(clk)), @@ -528,3 +701,4 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) return 0; } +#endif diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 8463cc3..f343389 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -16,7 +16,11 @@ #include <linux/kernel.h> #include <linux/errno.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <asm/div64.h> @@ -76,7 +80,11 @@ * (assuming that it is counting N upwards), or -2 if the enclosing loop * should skip to the next iteration (again assuming N is increasing). */ +#ifdef CONFIG_COMMON_CLK +static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) +#else static int _dpll_test_fint(struct clk *clk, u8 n) +#endif { struct dpll_data *dd; long fint, fint_min, fint_max; @@ -85,7 +93,11 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data; /* DPLL divider must result in a valid jitter correction val */ +#ifdef CONFIG_COMMON_CLK + fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; +#else fint = __clk_get_rate(__clk_get_parent(clk)) / n; +#endif if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -186,15 +198,24 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, } /* Public functions */ - +#ifdef CONFIG_COMMON_CLK +u8 omap2_init_dpll_parent(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else void omap2_init_dpll_parent(struct clk *clk) { +#endif u32 v; struct dpll_data *dd; dd = clk->dpll_data; if (!dd) +#ifdef CONFIG_COMMON_CLK + return -EINVAL; +#else return; +#endif v = __raw_readl(dd->control_reg); v &= dd->enable_mask; @@ -204,18 +225,34 @@ void omap2_init_dpll_parent(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) +#ifdef CONFIG_COMMON_CLK + return 1; +#else clk_reparent(clk, dd->clk_bypass); +#endif } +#ifdef CONFIG_COMMON_CLK + return 0; +#else return; +#endif } /** @@ -232,7 +269,11 @@ void omap2_init_dpll_parent(struct clk *clk) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * if the clock @clk is not a DPLL. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) +#else u32 omap2_get_dpll_rate(struct clk *clk) +#endif { long long dpll_clk; u32 dpll_mult, dpll_div, v; @@ -288,8 +329,15 @@ u32 omap2_get_dpll_rate(struct clk *clk) * (expensive) function again. Returns ~0 if the target rate cannot * be rounded, or the rounded rate upon success. */ +#ifdef CONFIG_COMMON_CLK +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) { +#endif int m, n, r, scaled_max_m; unsigned long scaled_rt_rp; unsigned long new_rate = 0; @@ -303,7 +351,11 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd = clk->dpll_data; ref_rate = __clk_get_rate(dd->clk_ref); +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(hw->clk); +#else clk_name = __clk_get_name(clk); +#endif pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", clk_name, target_rate); diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index fe774a0..3b661ba 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -11,7 +11,11 @@ #undef DEBUG #include <linux/kernel.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> @@ -48,6 +52,14 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk) /* Public data */ +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_iclk_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_omap2_iclk_dflt_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, @@ -77,4 +89,4 @@ const struct clkops clkops_omap2_mdmclk_dflt_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, }; - +#endif diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e381d991..72d7105 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -20,7 +20,11 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/delay.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/io.h> #include <linux/bitops.h> @@ -57,7 +61,33 @@ static bool clkdm_control = true; static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); +#ifndef CONFIG_COMMON_CLK static DEFINE_SPINLOCK(clockfw_lock); +#endif + +#ifdef CONFIG_COMMON_CLK + +/* + * Used for clocks that have the same value as the parent clock, + * divided by some factor + */ +unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *oclk; + + if (!hw) { + pr_warn("%s: hw is NULL\n", __func__); + return -EINVAL; + } + + oclk = to_clk_hw_omap(hw); + + WARN_ON(!oclk->fixed_div); + + return parent_rate / oclk->fixed_div; +} +#endif /* * OMAP2+ specific clock functions @@ -109,7 +139,11 @@ static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest, * belong in the clock code and will be moved in the medium term to * module-dependent code. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void _omap2_module_wait_ready(struct clk_hw_omap *clk) +#else static void _omap2_module_wait_ready(struct clk *clk) +#endif { void __iomem *companion_reg, *idlest_reg; u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; @@ -124,12 +158,15 @@ static void _omap2_module_wait_ready(struct clk *clk) } clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); - r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); if (r) { /* IDLEST register not in the CM module */ _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk)); +#else clk->name); +#endif } else { cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); }; @@ -145,15 +182,25 @@ static void _omap2_module_wait_ready(struct clk *clk) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap2_init_clk_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else void omap2_init_clk_clkdm(struct clk *clk) { +#endif struct clockdomain *clkdm; const char *clk_name; if (!clk->clkdm_name) return; +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(hw->clk); +#else clk_name = __clk_get_name(clk); +#endif clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { @@ -200,8 +247,12 @@ void __init omap2_clk_disable_clkdm_control(void) * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit) +#ifdef CONFIG_COMMON_CLK +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, +#else +void omap2_clk_dflt_find_companion(struct clk *clk, +#endif + void __iomem **other_reg, u8 *other_bit) { u32 r; @@ -229,8 +280,12 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * register address ID (e.g., that CM_FCLKEN2 corresponds to * CM_IDLEST2). This is not true for all modules. No return value. */ -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val) +#ifdef CONFIG_COMMON_CLK +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, +#else +void omap2_clk_dflt_find_idlest(struct clk *clk, +#endif + void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) { u32 r; @@ -252,6 +307,225 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, } +#ifdef CONFIG_COMMON_CLK +/** + * omap2_dflt_clk_enable - enable a clock in the hardware + * @hw: struct clk_hw * of the clock to enable + * + * Enable the clock @hw in the hardware. We first call into the OMAP + * clockdomain code to "enable" the corresponding clockdomain if this + * is the first enabled user of the clockdomain. Then program the + * hardware to enable the clock. Then wait for the IP block that uses + * this clock to leave idle (if applicable). Returns the error value + * from clkdm_clk_enable() if it terminated with an error, or -EINVAL + * if @hw has a null clock enable_reg, or zero upon success. + */ +int omap2_dflt_clk_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + u32 v; + int ret = 0; + + clk = to_clk_hw_omap(hw); + + if (clkdm_control && clk->clkdm) { + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, ret); + return ret; + } + } + + if (unlikely(clk->enable_reg == NULL)) { + pr_err("%s: %s missing enable_reg\n", __func__, + __clk_get_name(hw->clk)); + ret = -EINVAL; + goto err; + } + + /* FIXME should not have INVERT_ENABLE bit here */ + v = __raw_readl(clk->enable_reg); + if (clk->flags & INVERT_ENABLE) + v &= ~(1 << clk->enable_bit); + else + v |= (1 << clk->enable_bit); + __raw_writel(v, clk->enable_reg); + v = __raw_readl(clk->enable_reg); /* OCP barrier */ + + if (clk->ops && clk->ops->find_idlest) + _omap2_module_wait_ready(clk); + + return 0; + +err: + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); + return ret; +} + +/** + * omap2_dflt_clk_disable - disable a clock in the hardware + * @hw: struct clk_hw * of the clock to disable + * + * Disable the clock @hw in the hardware, and call into the OMAP + * clockdomain code to "disable" the corresponding clockdomain if all + * clocks/hwmods in that clockdomain are now disabled. No return + * value. + */ +void omap2_dflt_clk_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + u32 v; + + clk = to_clk_hw_omap(hw); + if (!clk->enable_reg) { + /* + * 'independent' here refers to a clock which is not + * controlled by its parent. + */ + pr_err("%s: independent clock %s has no enable_reg\n", + __func__, __clk_get_name(hw->clk)); + return; + } + + v = __raw_readl(clk->enable_reg); + if (clk->flags & INVERT_ENABLE) + v |= (1 << clk->enable_bit); + else + v &= ~(1 << clk->enable_bit); + __raw_writel(v, clk->enable_reg); + /* No OCP barrier needed here since it is a disable operation */ + + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); +} + +/** + * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being enabled + * + * Increment the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 1, the clockdomain will be "enabled." + * Only needed for clocks that don't use omap2_dflt_clk_enable() as + * their enable function pointer. Passes along the return value of + * clkdm_clk_enable(), -EINVAL if @hw is not associated with a + * clockdomain, or 0 if clock framework-based clockdomain control is + * not implemented. + */ +int omap2_clkops_enable_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + int ret = 0; + + clk = to_clk_hw_omap(hw); + + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return -EINVAL; + } + + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return 0; + } + + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); + + return ret; +} + +/** + * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being disabled + * + * Decrement the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 0, the clockdomain will be "disabled." + * Only needed for clocks that don't use omap2_dflt_clk_disable() as their + * disable function pointer. No return value. + */ +void omap2_clkops_disable_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + + clk = to_clk_hw_omap(hw); + + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return; + } + + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return; + } + + clkdm_clk_disable(clk->clkdm, hw->clk); +} + +/** + * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? + * @hw: struct clk_hw * to check + * + * Return 1 if the clock represented by @hw is enabled in the + * hardware, or 0 otherwise. Intended for use in the struct + * clk_ops.is_enabled function pointer. + */ +int omap2_dflt_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 v; + + v = __raw_readl(clk->enable_reg); + + if (clk->flags & INVERT_ENABLE) + v ^= BIT(clk->enable_bit); + + v &= BIT(clk->enable_bit); + + return v ? 1 : 0; +} + +static int __initdata mpurate; + +/* + * By default we use the rate set by the bootloader. + * You can override this with mpurate= cmdline option. + */ +static int __init omap_clk_setup(char *str) +{ + get_option(&str, &mpurate); + + if (!mpurate) + return 1; + + if (mpurate < 1000) + mpurate *= 1000000; + + return 1; +} +__setup("mpurate=", omap_clk_setup); + +const struct clk_hw_omap_ops clkhwops_wait = { + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else int omap2_dflt_clk_enable(struct clk *clk) { u32 v; @@ -482,6 +756,8 @@ void omap2_clk_disable_unused(struct clk *clk) } #endif +#endif /* CONFIG_COMMON_CLK */ + /** * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument * @mpurate_ck_name: clk name of the clock to change rate @@ -512,13 +788,15 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) r = clk_set_rate(mpurate_ck, mpurate); if (IS_ERR_VALUE(r)) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", - mpurate_ck->name, mpurate, r); + mpurate_ck_name, mpurate, r); clk_put(mpurate_ck); return -EINVAL; } calibrate_delay(); +#ifndef CONFIG_COMMON_CLK recalculate_root_clocks(); +#endif clk_put(mpurate_ck); @@ -564,8 +842,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(mpu_ck) / 1000000)); } +#ifndef CONFIG_COMMON_CLK /* Common data */ - int clk_enable(struct clk *clk) { unsigned long flags; @@ -1072,4 +1350,4 @@ err_out: late_initcall(clk_debugfs_init); #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ - +#endif /* CONFIG_COMMON_CLK */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 697e044..5a4f4fe 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -397,6 +397,7 @@ extern const struct clkops clkops_null; extern struct clk dummy_ck; +#endif /* CONFIG_COMMON_CLK */ /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 @@ -427,11 +428,36 @@ extern struct clk dummy_ck; /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 +#ifndef CONFIG_COMMON_CLK int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); +#endif /* CONFIG_COMMON_CLK */ + +#ifdef CONFIG_COMMON_CLK +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); +int omap3_noncore_dpll_enable(struct clk_hw *hw); +void omap3_noncore_dpll_disable(struct clk_hw *hw); +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); +void omap3_dpll_allow_idle(struct clk_hw_omap *clk); +void omap3_dpll_deny_idle(struct clk_hw_omap *clk); +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate); +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate); +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate); +#else long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); unsigned long omap3_dpll_recalc(struct clk *clk); unsigned long omap3_clkoutx2_recalc(struct clk *clk); @@ -446,17 +472,33 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk); void omap4_dpllmx_deny_gatectrl(struct clk *clk); long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); +#endif #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk); #else #define omap2_clk_disable_unused NULL #endif - +#ifdef CONFIG_COMMON_CLK +void omap2_init_clk_clkdm(struct clk_hw *clk); +#else void omap2_init_clk_clkdm(struct clk *clk); +#endif void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ +#ifdef CONFIG_COMMON_CLK +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, + unsigned long target_rate, + u32 *new_div); +u8 omap2_clksel_find_parent_index(struct clk_hw *hw); +unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); +long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); +#else u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 *new_div); void omap2_init_clksel_parent(struct clk *clk); @@ -464,20 +506,38 @@ unsigned long omap2_clksel_recalc(struct clk *clk); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); +#endif /* clkt_iclk.c public functions */ extern void omap2_clkt_iclk_allow_idle(struct clk *clk); extern void omap2_clkt_iclk_deny_idle(struct clk *clk); +#ifdef CONFIG_COMMON_CLK +u8 omap2_init_dpll_parent(struct clk_hw *hw); +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); +#else u32 omap2_get_dpll_rate(struct clk *clk); void omap2_init_dpll_parent(struct clk *clk); +#endif +#ifdef CONFIG_COMMON_CLK +int omap2_dflt_clk_enable(struct clk_hw *hw); +void omap2_dflt_clk_disable(struct clk_hw *hw); +int omap2_dflt_clk_is_enabled(struct clk_hw *hw); +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, + u8 *other_bit); +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, u8 *idlest_val); +#else int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, u8 *other_bit); void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); +#endif int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -496,6 +556,13 @@ extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; +#ifdef CONFIG_COMMON_CLK +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; +extern const struct clk_hw_omap_ops clkhwops_iclk_wait; +extern const struct clk_hw_omap_ops clkhwops_wait; +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; +#endif + extern const struct clkops clkops_omap2_iclk_dflt_wait; extern const struct clkops clkops_omap2_iclk_dflt; extern const struct clkops clkops_omap2_iclk_idle_only; @@ -513,11 +580,17 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; +#ifndef CONFIG_COMMON_CLK /* clocks shared between various OMAP SoCs */ extern struct clk virt_19200000_ck; extern struct clk virt_26000000_ck; +#endif extern int am33xx_clk_init(void); -#endif /* CONFIG_COMMON_CLK */ +#ifdef CONFIG_COMMON_CLK +extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); +extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); +#endif + #endif diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index eacf51f..f72dedb 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -29,6 +29,7 @@ #include <linux/clkdev.h> #include "soc.h" +#include "clockdomain.h" #include "clock.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" @@ -42,7 +43,11 @@ /* Private functions */ /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ +#ifdef CONFIG_COMMON_CLK +static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) +#else static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) +#endif { const struct dpll_data *dd; u32 v; @@ -56,7 +61,11 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) } /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) +#else static int _omap3_wait_dpll_status(struct clk *clk, u8 state) +#endif { const struct dpll_data *dd; int i = 0; @@ -64,7 +73,11 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) const char *clk_name; dd = clk->dpll_data; +#ifdef CONFIG_COMMON_CLK + clk_name = __clk_get_name(clk->hw.clk); +#else clk_name = __clk_get_name(clk); +#endif state <<= __ffs(dd->idlest_mask); @@ -88,7 +101,11 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) } /* From 3430 TRM ES2 4.7.6.2 */ +#ifdef CONFIG_COMMON_CLK +static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) +#else static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) +#endif { unsigned long fint; u16 f = 0; @@ -133,14 +150,22 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) * locked successfully, return 0; if the DPLL did not lock in the time * allotted, or DPLL3 was passed in, return -EINVAL. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_lock(struct clk *clk) +#endif { const struct dpll_data *dd; u8 ai; u8 state = 1; int r = 0; +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); +#else pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); +#endif dd = clk->dpll_data; state <<= __ffs(dd->idlest_mask); @@ -178,7 +203,11 @@ done: * DPLL3 was passed in, or the DPLL does not support low-power bypass, * return -EINVAL. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_bypass(struct clk *clk) +#endif { int r; u8 ai; @@ -187,7 +216,11 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) return -EINVAL; pr_debug("clock: configuring DPLL %s for low-power bypass\n", +#ifdef CONFIG_COMMON_CLK + __clk_get_name(clk->hw.clk)); +#else __clk_get_name(clk)); +#endif ai = omap3_dpll_autoidle_read(clk); @@ -210,14 +243,22 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) * code. If DPLL3 was passed in, or the DPLL does not support * low-power stop, return -EINVAL; otherwise, return 0. */ +#ifdef CONFIG_COMMON_CLK +static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) +#else static int _omap3_noncore_dpll_stop(struct clk *clk) +#endif { u8 ai; if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) return -EINVAL; +#ifdef CONFIG_COMMON_CLK + pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); +#else pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); +#endif ai = omap3_dpll_autoidle_read(clk); @@ -241,11 +282,19 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ +#ifdef CONFIG_COMMON_CLK +static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) +#else static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) +#endif { unsigned long fint, clkinp; /* watch out for overflow */ +#ifdef CONFIG_COMMON_CLK + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); +#else clkinp = __clk_get_rate(__clk_get_parent(clk)); +#endif fint = (clkinp / n) * m; if (fint < 1000000000) @@ -266,12 +315,20 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ +#ifdef CONFIG_COMMON_CLK +static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) +#else static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) +#endif { unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2; +#ifdef CONFIG_COMMON_CLK + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); +#else clkinp = __clk_get_rate(__clk_get_parent(clk)); +#endif /* * target sigma-delta to near 250MHz @@ -298,7 +355,12 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) * Program the DPLL with the supplied M, N values, and wait for the DPLL to * lock.. Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n, + u16 freqsel) +#else static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) +#endif { struct dpll_data *dd = clk->dpll_data; u8 dco, sd_div; @@ -355,8 +417,14 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * * Recalculate and propagate the DPLL rate. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else unsigned long omap3_dpll_recalc(struct clk *clk) { +#endif return omap2_get_dpll_rate(clk); } @@ -376,8 +444,14 @@ unsigned long omap3_dpll_recalc(struct clk *clk) * support low-power stop, or if the DPLL took too long to enter * bypass or lock, return -EINVAL; otherwise, return 0. */ +#ifdef CONFIG_COMMON_CLK +int omap3_noncore_dpll_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap3_noncore_dpll_enable(struct clk *clk) { +#endif int r; struct dpll_data *dd; struct clk *parent; @@ -386,15 +460,34 @@ int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; +#ifdef CONFIG_COMMON_CLK + if (clk->clkdm) { + r = clkdm_clk_enable(clk->clkdm, hw->clk); + if (r) { + WARN(1, + "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, r); + return r; + } + } + + parent = __clk_get_parent(hw->clk); + + if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { +#else parent = __clk_get_parent(clk); if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { +#endif WARN_ON(parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); } else { WARN_ON(parent != dd->clk_ref); r = _omap3_noncore_dpll_lock(clk); } + +#ifndef CONFIG_COMMON_CLK /* *FIXME: this is dubious - if clk->rate has changed, what about * propagating? @@ -402,6 +495,7 @@ int omap3_noncore_dpll_enable(struct clk *clk) if (!r) clk->rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); +#endif return r; } @@ -413,9 +507,21 @@ int omap3_noncore_dpll_enable(struct clk *clk) * Instructs a non-CORE DPLL to enter low-power stop. This function is * intended for use in struct clkops. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_noncore_dpll_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + _omap3_noncore_dpll_stop(clk); + if (clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); +#else void omap3_noncore_dpll_disable(struct clk *clk) { _omap3_noncore_dpll_stop(clk); + if (clk->clkdm) + clkdm_clk_disable(clk->clkdm, clk); +#endif } @@ -432,6 +538,77 @@ void omap3_noncore_dpll_disable(struct clk *clk) * target rate if it hasn't been done already, then program and lock * the DPLL. Returns -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct clk *new_parent = NULL; + u16 freqsel = 0; + struct dpll_data *dd; + int ret; + + if (!hw || !rate) + return -EINVAL; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref); + + if (__clk_get_rate(dd->clk_bypass) == rate && + (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + pr_debug("%s: %s: set rate: entering bypass.\n", + __func__, __clk_get_name(hw->clk)); + + ret = _omap3_noncore_dpll_bypass(clk); + if (!ret) + new_parent = dd->clk_bypass; + } else { + if (dd->last_rounded_rate != rate) + rate = __clk_round_rate(hw->clk, rate); + + if (dd->last_rounded_rate == 0) + return -EINVAL; + + /* No freqsel on OMAP4 and OMAP3630 */ + if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { + freqsel = _omap3_dpll_compute_freqsel(clk, + dd->last_rounded_n); + if (!freqsel) + WARN_ON(1); + } + + pr_debug("%s: %s: set rate: locking rate to %lu.\n", + __func__, __clk_get_name(hw->clk), rate); + + ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, + dd->last_rounded_n, freqsel); + if (!ret) + new_parent = dd->clk_ref; + } + /* + * FIXME - this is all wrong. common code handles reparenting and + * migrating prepare/enable counts. dplls should be a multiplexer + * clock and this should be a set_parent operation so that all of that + * stuff is inherited for free + */ + + if (!ret) + __clk_reparent(hw->clk, new_parent); + + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass); + + return 0; +} +#else int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { struct clk *new_parent = NULL; @@ -509,6 +686,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) return 0; } +#endif /* DPLL autoidle read/set code */ @@ -520,7 +698,11 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) * -EINVAL if passed a null pointer or if the struct clk does not * appear to refer to a DPLL. */ +#ifdef CONFIG_COMMON_CLK +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) +#else u32 omap3_dpll_autoidle_read(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -549,7 +731,11 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) * OMAP3430. The DPLL will enter low-power stop when its downstream * clocks are gated. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_dpll_allow_idle(struct clk_hw_omap *clk) +#else void omap3_dpll_allow_idle(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -560,8 +746,10 @@ void omap3_dpll_allow_idle(struct clk *clk) dd = clk->dpll_data; if (!dd->autoidle_reg) { +#ifndef CONFIG_COMMON_CLK pr_debug("clock: DPLL %s: autoidle not supported\n", __clk_get_name(clk)); +#endif return; } @@ -583,7 +771,11 @@ void omap3_dpll_allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ +#ifdef CONFIG_COMMON_CLK +void omap3_dpll_deny_idle(struct clk_hw_omap *clk) +#else void omap3_dpll_deny_idle(struct clk *clk) +#endif { const struct dpll_data *dd; u32 v; @@ -594,8 +786,10 @@ void omap3_dpll_deny_idle(struct clk *clk) dd = clk->dpll_data; if (!dd->autoidle_reg) { +#ifndef CONFIG_COMMON_CLK pr_debug("clock: DPLL %s: autoidle not supported\n", __clk_get_name(clk)); +#endif return; } @@ -615,6 +809,27 @@ void omap3_dpll_deny_idle(struct clk *clk) * Using parent clock DPLL data, look up DPLL state. If locked, set our * rate to the dpll_clk * 2; otherwise, just use dpll_clk. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + const struct dpll_data *dd; + unsigned long rate; + u32 v; + struct clk_hw_omap *pclk = NULL; + struct clk *parent; + + /* Walk up the parents of clk, looking for a DPLL */ + do { + do { + parent = __clk_get_parent(hw->clk); + hw = __clk_get_hw(parent); + } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); + if (!hw) + break; + pclk = to_clk_hw_omap(hw); + } while (pclk && !pclk->dpll_data); +#else unsigned long omap3_clkoutx2_recalc(struct clk *clk) { const struct dpll_data *dd; @@ -628,6 +843,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) while (pclk && !pclk->dpll_data) pclk = __clk_get_parent(pclk); + parent_rate = __clk_get_rate(__clk_get_parent(clk)); +#endif /* clk does not have a DPLL as a parent? error in the clock data */ if (!pclk) { WARN_ON(1); @@ -638,7 +855,6 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) WARN_ON(!dd->enable_mask); - parent_rate = __clk_get_rate(__clk_get_parent(clk)); v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) @@ -649,7 +865,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) } /* OMAP3/4 non-CORE DPLL clkops */ - +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap3_dpll = { + .allow_idle = omap3_dpll_allow_idle, + .deny_idle = omap3_dpll_deny_idle, +}; +#else const struct clkops clkops_omap3_noncore_dpll_ops = { .enable = omap3_noncore_dpll_enable, .disable = omap3_noncore_dpll_disable, @@ -661,3 +882,4 @@ const struct clkops clkops_omap3_core_dpll_ops = { .allow_idle = omap3_dpll_allow_idle, .deny_idle = omap3_dpll_deny_idle, }; +#endif diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 5854da1..aa75a3c 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -21,7 +21,11 @@ #include "cm-regbits-44xx.h" /* Supported only on OMAP4 */ +#ifdef CONFIG_COMMON_CLK +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) +#else int omap4_dpllmx_gatectrl_read(struct clk *clk) +#endif { u32 v; u32 mask; @@ -40,7 +44,11 @@ int omap4_dpllmx_gatectrl_read(struct clk *clk) return v; } +#ifdef CONFIG_COMMON_CLK +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) +#else void omap4_dpllmx_allow_gatectrl(struct clk *clk) +#endif { u32 v; u32 mask; @@ -58,7 +66,11 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } +#ifdef CONFIG_COMMON_CLK +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) +#else void omap4_dpllmx_deny_gatectrl(struct clk *clk) +#endif { u32 v; u32 mask; @@ -76,10 +88,17 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { + .allow_idle = omap4_dpllmx_allow_gatectrl, + .deny_idle = omap4_dpllmx_deny_gatectrl, +}; +#else const struct clkops clkops_omap4_dpllmx_ops = { .allow_idle = omap4_dpllmx_allow_gatectrl, .deny_idle = omap4_dpllmx_deny_gatectrl, }; +#endif /** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit @@ -90,8 +109,15 @@ const struct clkops clkops_omap4_dpllmx_ops = { * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) * upon success, or 0 upon error. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) { +#endif u32 v; unsigned long rate; struct dpll_data *dd; @@ -123,8 +149,16 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or * ~0 if an error occurred in omap2_dpll_round_rate(). */ +#ifdef CONFIG_COMMON_CLK +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) { +#endif u32 v; struct dpll_data *dd; long r; @@ -140,7 +174,11 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) if (v) target_rate = target_rate / OMAP4430_REGM4XEN_MULT; +#ifdef CONFIG_COMMON_CLK + r = omap2_dpll_round_rate(hw, target_rate, NULL); +#else r = omap2_dpll_round_rate(clk, target_rate); +#endif if (r == ~0) return r; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 04/26] ARM: OMAP3: clock: Convert to common clk 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (2 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 03/26] ARM: OMAP4: clock: Convert to common clk Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 05/26] ARM: OMAP2: " Mike Turquette ` (24 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Convert all OMAP3 specific platform files to use COMMON clk and keep all the chnages under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 13 ++++++++ arch/arm/mach-omap2/clkt_iclk.c | 13 ++++++++ arch/arm/mach-omap2/clock.h | 22 ++++++++++++-- arch/arm/mach-omap2/clock34xx.c | 51 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock3517.c | 37 +++++++++++++++++++---- arch/arm/mach-omap2/clock36xx.c | 25 +++++++++++++--- arch/arm/mach-omap2/clock36xx.h | 4 +++ arch/arm/mach-omap2/clock3xxx.c | 10 ++++++- arch/arm/mach-omap2/clock3xxx.h | 7 +++++ 9 files changed, 170 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 5510d92..aeaaa87 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -45,8 +45,15 @@ * Program the DPLL M2 divider with the rounded target rate. Returns * -EINVAL upon error, or 0 upon success. */ +#ifdef CONFIG_COMMON_CLK +int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) { +#endif u32 new_div = 0; u32 unlock_dll = 0; u32 c; @@ -64,7 +71,11 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; sdrcrate = __clk_get_rate(sdrc_ick_p); +#ifdef CONFIG_COMMON_CLK + clkrate = __clk_get_rate(hw->clk); +#else clkrate = __clk_get_rate(clk); +#endif if (rate > clkrate) sdrcrate <<= ((rate / clkrate) >> 1); else @@ -113,7 +124,9 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); +#ifndef CONFIG_COMMON_CLK clk->rate = rate; +#endif return 0; } diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index d9852c9..13dadf4 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -28,7 +28,11 @@ /* Private functions */ /* XXX */ +#ifdef CONFIG_COMMON_CLK +void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) +#else void omap2_clkt_iclk_allow_idle(struct clk *clk) +#endif { u32 v, r; @@ -40,7 +44,11 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk) } /* XXX */ +#ifdef CONFIG_COMMON_CLK +void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) +#else void omap2_clkt_iclk_deny_idle(struct clk *clk) +#endif { u32 v, r; @@ -54,6 +62,11 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk) /* Public data */ #ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_iclk = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; + const struct clk_hw_omap_ops clkhwops_iclk_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 003520c..d78f90e 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -509,8 +509,13 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); #endif /* clkt_iclk.c public functions */ +#ifdef CONFIG_COMMON_CLK +extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); +extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); +#else extern void omap2_clkt_iclk_allow_idle(struct clk *clk); extern void omap2_clkt_iclk_deny_idle(struct clk *clk); +#endif #ifdef CONFIG_COMMON_CLK u8 omap2_init_dpll_parent(struct clk_hw *hw); @@ -589,8 +594,20 @@ extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; -#endif - +extern const struct clk_hw_omap_ops clkhwops_iclk; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; +extern const struct clk_hw_omap_ops clkhwops_apll54; +extern const struct clk_hw_omap_ops clkhwops_apll96; +extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; +extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; +#else extern const struct clkops clkops_omap2_iclk_dflt_wait; extern const struct clkops clkops_omap2_iclk_dflt; extern const struct clkops clkops_omap2_iclk_idle_only; @@ -599,6 +616,7 @@ extern const struct clkops clkops_omap2xxx_dpll_ops; extern const struct clkops clkops_omap3_noncore_dpll_ops; extern const struct clkops clkops_omap3_core_dpll_ops; extern const struct clkops clkops_omap4_dpllmx_ops; +#endif /* CONFIG_COMMON_CLK */ /* clksel_rate blocks shared between OMAP44xx and AM33xx */ extern const struct clksel_rate div_1_0_rates[]; diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index e41819b..b398a46 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -37,7 +37,11 @@ * from the CM_{I,F}CLKEN bit. Pass back the correct info via * @idlest_reg and @idlest_bit. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, +#else static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, +#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -49,7 +53,19 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait = { + .find_idlest = omap3430es2_clk_ssi_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap3430es2_clk_ssi_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_omap3430es2_ssi_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, @@ -65,6 +81,7 @@ const struct clkops clkops_omap3430es2_iclk_ssi_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, }; +#endif /** * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST @@ -80,7 +97,11 @@ const struct clkops clkops_omap3430es2_iclk_ssi_wait = { * default find_idlest code assumes that they are at the same * position.) No return value. */ +#ifdef CONFIG_COMMON_CLK +static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, +#else static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, +#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -93,7 +114,19 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = { + .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_omap3430es2_dss_usbhost_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, @@ -109,6 +142,7 @@ const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, }; +#endif /** * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB @@ -121,7 +155,11 @@ const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = { * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via * @idlest_reg and @idlest_bit. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, +#else static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, +#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -133,7 +171,19 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = { + .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_omap3430es2_hsotgusb_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, @@ -149,3 +199,4 @@ const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, }; +#endif diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c index 622ea05..467d8bc 100644 --- a/arch/arm/mach-omap2/clock3517.c +++ b/arch/arm/mach-omap2/clock3517.c @@ -47,7 +47,11 @@ * in the enable register itsel at a bit offset of 4 from the enable * bit. A value of 1 indicates that clock is enabled. */ +#ifdef CONFIG_COMMON_CLK +static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, +#else static void am35xx_clk_find_idlest(struct clk *clk, +#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -71,8 +75,14 @@ static void am35xx_clk_find_idlest(struct clk *clk, * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit) +#ifdef CONFIG_COMMON_CLK +static void am35xx_clk_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, +#else +static void am35xx_clk_find_companion(struct clk *clk, + void __iomem **other_reg, +#endif + u8 *other_bit) { *other_reg = (__force void __iomem *)(clk->enable_reg); if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) @@ -80,13 +90,19 @@ static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg, else *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; } - +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { + .find_idlest = am35xx_clk_find_idlest, + .find_companion = am35xx_clk_find_companion, +}; +#else const struct clkops clkops_am35xx_ipss_module_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, .find_idlest = am35xx_clk_find_idlest, .find_companion = am35xx_clk_find_companion, }; +#endif /** * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS @@ -99,7 +115,11 @@ const struct clkops clkops_am35xx_ipss_module_wait = { * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg * and @idlest_bit. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, +#else static void am35xx_clk_ipss_find_idlest(struct clk *clk, +#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -111,7 +131,14 @@ static void am35xx_clk_ipss_find_idlest(struct clk *clk, *idlest_bit = AM35XX_ST_IPSS_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } - +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = am35xx_clk_ipss_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_am35xx_ipss_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, @@ -120,5 +147,5 @@ const struct clkops clkops_am35xx_ipss_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, }; - +#endif diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index 0e1e9e4..9f50e97 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -37,34 +37,51 @@ * (Any other value different from the Read value) to the * corresponding CM_CLKSEL register will refresh the dividers. */ +#ifdef CONFIG_COMMON_CLK +int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) +{ + struct clk_hw_omap *parent; + struct clk_hw *parent_hw; +#else static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) { + struct clk *parent; +#endif u32 dummy_v, orig_v, clksel_shift; int ret; /* Clear PWRDN bit of HSDIVIDER */ ret = omap2_dflt_clk_enable(clk); +#ifdef CONFIG_COMMON_CLK + parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); + parent = to_clk_hw_omap(parent_hw); +#else + parent = clk->parent; +#endif + /* Restore the dividers */ if (!ret) { - clksel_shift = __ffs(clk->parent->clksel_mask); - orig_v = __raw_readl(clk->parent->clksel_reg); + clksel_shift = __ffs(parent->clksel_mask); + orig_v = __raw_readl(parent->clksel_reg); dummy_v = orig_v; /* Write any other value different from the Read value */ dummy_v ^= (1 << clksel_shift); - __raw_writel(dummy_v, clk->parent->clksel_reg); + __raw_writel(dummy_v, parent->clksel_reg); /* Write the original divider */ - __raw_writel(orig_v, clk->parent->clksel_reg); + __raw_writel(orig_v, parent->clksel_reg); } return ret; } +#ifndef CONFIG_COMMON_CLK const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = { .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore, .disable = omap2_dflt_clk_disable, .find_companion = omap2_clk_dflt_find_companion, .find_idlest = omap2_clk_dflt_find_idlest, }; +#endif diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h index a7dee5b..e6a748e 100644 --- a/arch/arm/mach-omap2/clock36xx.h +++ b/arch/arm/mach-omap2/clock36xx.h @@ -8,6 +8,10 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H +#ifdef CONFIG_COMMON_CLK +extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw); +#else extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; +#endif #endif diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 3e8aca2..a6f75cd 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -38,8 +38,12 @@ /* needed by omap3_core_dpll_m2_set_rate() */ struct clk *sdrc_ick_p, *arm_fck_p; - +#ifdef CONFIG_COMMON_CLK +int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +#else int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) +#endif { /* * According to the 12-5 CDP code from TI, "Limitation 2.5" @@ -51,7 +55,11 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; } +#ifdef CONFIG_COMMON_CLK + return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); +#else return omap3_noncore_dpll_set_rate(clk, rate); +#endif } void __init omap3_clk_lock_dpll5(void) diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 8bbeeaf..87f098d 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -9,8 +9,15 @@ #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H int omap3xxx_clk_init(void); +#ifdef CONFIG_COMMON_CLK +int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); +int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); +#else int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); +#endif void omap3_clk_lock_dpll5(void); extern struct clk *sdrc_ick_p; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 05/26] ARM: OMAP2: clock: Convert to common clk 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (3 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 04/26] ARM: OMAP3: " Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-12 22:16 ` Paul Walmsley 2012-11-08 1:12 ` [PATCH 06/26] ARM: OMAP2xxx: clock: add APLL rate recalculation functions Mike Turquette ` (23 subsequent siblings) 28 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Convert all OMAP2 specific platform files to use COMMON clk and keep all the chnages under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clkt2xxx_apll.c | 51 ++++++++++++++++++++++++++ arch/arm/mach-omap2/clkt2xxx_dpll.c | 16 +++++++- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 22 +++++++++++ arch/arm/mach-omap2/clkt2xxx_osc.c | 15 ++++++++ arch/arm/mach-omap2/clkt2xxx_sys.c | 9 ++++- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 19 ++++++++++ arch/arm/mach-omap2/clock2430.c | 11 ++++++ arch/arm/mach-omap2/clock2xxx.c | 1 + arch/arm/mach-omap2/clock2xxx.h | 36 ++++++++++++++++++ arch/arm/mach-omap2/pm24xx.c | 8 ++++ 10 files changed, 186 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index e3f0c1e..83088c4 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -42,8 +42,14 @@ void __iomem *cm_idlest_pll; /* Private functions */ /* Enable an APLL if off */ +#ifdef CONFIG_COMMON_CLK +static int omap2_clk_apll_enable(struct clk_hw *hw, u32 status_mask) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) { +#endif u32 cval, apll_mask; apll_mask = EN_APLL_LOCKED << clk->enable_bit; @@ -58,7 +64,11 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_wait_idlest(cm_idlest_pll, status_mask, +#ifdef CONFIG_COMMON_CLK + OMAP24XX_CM_IDLEST_VAL, __clk_get_name(hw->clk)); +#else OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk)); +#endif /* * REVISIT: Should we return an error code if omap2_wait_clock_ready() @@ -67,39 +77,69 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) return 0; } +#ifdef CONFIG_COMMON_CLK +int omap2_clk_apll96_enable(struct clk_hw *clk) +#else static int omap2_clk_apll96_enable(struct clk *clk) +#endif { return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK); } +#ifdef CONFIG_COMMON_CLK +int omap2_clk_apll54_enable(struct clk_hw *clk) +#else static int omap2_clk_apll54_enable(struct clk *clk) +#endif { return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK); } +#ifdef CONFIG_COMMON_CLK +void _apll96_allow_idle(struct clk_hw_omap *clk) +#else static void _apll96_allow_idle(struct clk *clk) +#endif { omap2xxx_cm_set_apll96_auto_low_power_stop(); } +#ifdef CONFIG_COMMON_CLK +void _apll96_deny_idle(struct clk_hw_omap *clk) +#else static void _apll96_deny_idle(struct clk *clk) +#endif { omap2xxx_cm_set_apll96_disable_autoidle(); } +#ifdef CONFIG_COMMON_CLK +void _apll54_allow_idle(struct clk_hw_omap *clk) +#else static void _apll54_allow_idle(struct clk *clk) +#endif { omap2xxx_cm_set_apll54_auto_low_power_stop(); } +#ifdef CONFIG_COMMON_CLK +void _apll54_deny_idle(struct clk_hw_omap *clk) +#else static void _apll54_deny_idle(struct clk *clk) +#endif { omap2xxx_cm_set_apll54_disable_autoidle(); } /* Stop APLL */ +#ifdef CONFIG_COMMON_CLK +void omap2_clk_apll_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else static void omap2_clk_apll_disable(struct clk *clk) { +#endif u32 cval; cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); @@ -108,7 +148,17 @@ static void omap2_clk_apll_disable(struct clk *clk) } /* Public data */ +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_apll54 = { + .allow_idle = _apll54_allow_idle, + .deny_idle = _apll54_deny_idle, +}; +const struct clk_hw_omap_ops clkhwops_apll96 = { + .allow_idle = _apll96_allow_idle, + .deny_idle = _apll96_deny_idle, +}; +#else const struct clkops clkops_apll96 = { .enable = omap2_clk_apll96_enable, .disable = omap2_clk_apll_disable, @@ -122,6 +172,7 @@ const struct clkops clkops_apll54 = { .allow_idle = _apll54_allow_idle, .deny_idle = _apll54_deny_idle, }; +#endif /* Public functions */ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index 399534c..bbbf032 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -29,7 +29,11 @@ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 * instead. Add some mechanism to optionally enter this mode. */ +#ifdef CONFIG_COMMON_CLK +void _allow_idle(struct clk_hw_omap *clk) +#else static void _allow_idle(struct clk *clk) +#endif { if (!clk || !clk->dpll_data) return; @@ -43,7 +47,11 @@ static void _allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ +#ifdef CONFIG_COMMON_CLK +void _deny_idle(struct clk_hw_omap *clk) +#else static void _deny_idle(struct clk *clk) +#endif { if (!clk || !clk->dpll_data) return; @@ -53,9 +61,15 @@ static void _deny_idle(struct clk *clk) /* Public data */ - +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = { + .allow_idle = _allow_idle, + .deny_idle = _deny_idle, +}; +#else const struct clkops clkops_omap2xxx_dpll_ops = { .allow_idle = _allow_idle, .deny_idle = _deny_idle, }; +#endif diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 3432f91..fb26e2f 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -46,7 +46,11 @@ * struct clk *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2xxx_clk_get_core_rate(struct clk_hw_omap *clk) +#else unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) +#endif { long long core_clk; u32 v; @@ -97,19 +101,37 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else unsigned long omap2_dpllcore_recalc(struct clk *clk) { +#endif return omap2xxx_clk_get_core_rate(clk); } +#ifdef CONFIG_COMMON_CLK +int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) { +#endif u32 cur_rate, low, mult, div, valid_rate, done_rate; u32 bypass = 0; struct prcm_config tmpset; const struct dpll_data *dd; +#ifdef CONFIG_COMMON_CLK + cur_rate = omap2xxx_clk_get_core_rate(to_clk_hw_omap(dclk_hw)); +#else cur_rate = omap2xxx_clk_get_core_rate(dclk); +#endif mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult &= OMAP24XX_CORE_CLK_SRC_MASK; diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index e177737..395e0c1 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -35,7 +35,11 @@ * clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ +#ifdef CONFIG_COMMON_CLK +int omap2_enable_osc_ck(struct clk_hw *clk) +#else static int omap2_enable_osc_ck(struct clk *clk) +#endif { u32 pcc; @@ -53,7 +57,11 @@ static int omap2_enable_osc_ck(struct clk *clk) * clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ +#ifdef CONFIG_COMMON_CLK +void omap2_disable_osc_ck(struct clk_hw *clk) +#else static void omap2_disable_osc_ck(struct clk *clk) +#endif { u32 pcc; @@ -62,12 +70,19 @@ static void omap2_disable_osc_ck(struct clk *clk) __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); } +#ifndef CONFIG_COMMON_CLK const struct clkops clkops_oscck = { .enable = omap2_enable_osc_ck, .disable = omap2_disable_osc_ck, }; +#endif +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate) +#else unsigned long omap2_osc_clk_recalc(struct clk *clk) +#endif { return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); } diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c index 46683b3..e6e73cf 100644 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c @@ -40,9 +40,16 @@ u32 omap2xxx_get_sysclkdiv(void) return div; } +#ifdef CONFIG_COMMON_CLK +unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate) +{ + return parent_rate / omap2xxx_get_sysclkdiv(); +} +#else unsigned long omap2xxx_sys_clk_recalc(struct clk *clk) { return clk->parent->rate / omap2xxx_get_sysclkdiv(); } - +#endif diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index c66276b..23456a8 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -52,7 +52,12 @@ const struct prcm_config *rate_table; * * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, + unsigned long parent_rate) +#else unsigned long omap2_table_mpu_recalc(struct clk *clk) +#endif { return curr_prcm_set->mpu_speed; } @@ -64,7 +69,12 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk) * Some might argue L3-DDR, others ARM, others IVA. This code is simple and * just uses the ARM rates. */ +#ifdef CONFIG_COMMON_CLK +long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +#else long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) +#endif { const struct prcm_config *ptr; long highest_rate, sys_clk_rate; @@ -88,7 +98,12 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) } /* Sets basic clocks based on the specified rate */ +#ifdef CONFIG_COMMON_CLK +int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +#else int omap2_select_table_rate(struct clk *clk, unsigned long rate) +#endif { u32 cur_rate, done_rate, bypass = 0, tmp; const struct prcm_config *prcm; @@ -118,7 +133,11 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) } curr_prcm_set = prcm; +#ifdef CONFIG_COMMON_CLK + cur_rate = omap2xxx_clk_get_core_rate(to_clk_hw_omap(dclk_hw)); +#else cur_rate = omap2xxx_clk_get_core_rate(dclk); +#endif if (prcm->dpll_speed == cur_rate / 2) { omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index e37df53..7a61d78 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c @@ -40,7 +40,11 @@ * passes back the correct CM_IDLEST register address for I2CHS * modules. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, +#else static void omap2430_clk_i2chs_find_idlest(struct clk *clk, +#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -51,9 +55,16 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk, } /* 2430 I2CHS has non-standard IDLEST register */ +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = { + .find_idlest = omap2430_clk_i2chs_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_omap2430_i2chs_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, .find_idlest = omap2430_clk_i2chs_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; +#endif diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 5feee16..d4d82df 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c @@ -29,6 +29,7 @@ #include "cm-regbits-24xx.h" struct clk *vclk, *sclk, *dclk; +struct clk_hw *dclk_hw; /* * Omap24xx specific clock functions diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index cb6df8c..1ce94b6 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -8,6 +8,26 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#include "clock.h" + +unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, + unsigned long parent_rate); +int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate); +unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate); +unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate); +unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, + unsigned long parent_rate); +int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); +unsigned long omap2xxx_clk_get_core_rate(struct clk_hw_omap *clk); +#else unsigned long omap2_table_mpu_recalc(struct clk *clk); int omap2_select_table_rate(struct clk *clk, unsigned long rate); long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); @@ -16,6 +36,7 @@ unsigned long omap2_osc_clk_recalc(struct clk *clk); unsigned long omap2_dpllcore_recalc(struct clk *clk); int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); +#endif u32 omap2xxx_get_apll_clkin(void); u32 omap2xxx_get_sysclkdiv(void); void omap2xxx_clk_prepare_for_reboot(void); @@ -36,9 +57,24 @@ extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; extern struct clk *dclk; +#ifdef CONFIG_COMMON_CLK +extern struct clk_hw *dclk_hw; +int omap2_enable_osc_ck(struct clk_hw *hw); +void omap2_disable_osc_ck(struct clk_hw *hw); +int omap2_clk_apll96_enable(struct clk_hw *hw); +int omap2_clk_apll54_enable(struct clk_hw *hw); +void _apll96_allow_idle(struct clk_hw_omap *hw); +void _apll96_deny_idle(struct clk_hw_omap *hw); +void _apll54_allow_idle(struct clk_hw_omap *hw); +void _apll54_deny_idle(struct clk_hw_omap *hw); +void omap2_clk_apll_disable(struct clk_hw *hw); +void _allow_idle(struct clk_hw_omap *hw); +void _deny_idle(struct clk_hw_omap *hw); +#else extern const struct clkops clkops_omap2430_i2chs_wait; extern const struct clkops clkops_oscck; extern const struct clkops clkops_apll96; extern const struct clkops clkops_apll54; +#endif #endif diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 83815dd..87ae36c 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -25,7 +25,11 @@ #include <linux/sysfs.h> #include <linux/module.h> #include <linux/delay.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/irq.h> #include <linux/time.h> #include <linux/gpio.h> @@ -202,7 +206,11 @@ static int omap2_can_sleep(void) { if (omap2_fclks_active()) return 0; +#ifdef CONFIG_COMMON_CLK + if (__clk_is_enabled(osc_ck)) +#else if (osc_ck->usecount > 1) +#endif return 0; if (omap_dma_running()) return 0; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 05/26] ARM: OMAP2: clock: Convert to common clk 2012-11-08 1:12 ` [PATCH 05/26] ARM: OMAP2: " Mike Turquette @ 2012-11-12 22:16 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-12 22:16 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches This patch needed some significant modifications to deal with the APLL changes in its new base; updated patch follows. - Paul ARM: OMAP2: clock: Convert to common clk From: Rajendra Nayak <rnayak@ti.com> Convert all OMAP2 specific platform files to use COMMON clk and keep all the changes under the CONFIG_COMMON_CLK macro check so it does not break any existing code. At a later point switch to COMMON clk and get rid of all old/legacy code. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/clkt2xxx_apll.c | 43 ++++++++++++++++++++++++++ arch/arm/mach-omap2/clkt2xxx_dpll.c | 16 +++++++++- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 24 +++++++++++++++ arch/arm/mach-omap2/clkt2xxx_osc.c | 15 +++++++++ arch/arm/mach-omap2/clkt2xxx_sys.c | 9 +++++ arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 15 +++++++++ arch/arm/mach-omap2/clock2430.c | 11 +++++++ arch/arm/mach-omap2/clock2xxx.c | 1 + arch/arm/mach-omap2/clock2xxx.h | 33 +++++++++++++++++++- arch/arm/mach-omap2/pm24xx.c | 8 +++++ 10 files changed, 172 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 8c5b13e7..1bd1527 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -38,48 +38,90 @@ /* Private functions */ +#ifdef CONFIG_COMMON_CLK +int omap2_clk_apll96_enable(struct clk_hw *hw) +#else static int _apll96_enable(struct clk *clk) +#endif { return omap2xxx_cm_apll96_enable(); } +#ifdef CONFIG_COMMON_CLK +int omap2_clk_apll54_enable(struct clk_hw *hw) +#else static int _apll54_enable(struct clk *clk) +#endif { return omap2xxx_cm_apll54_enable(); } +#ifdef CONFIG_COMMON_CLK +static void _apll96_allow_idle(struct clk_hw_omap *clk) +#else static void _apll96_allow_idle(struct clk *clk) +#endif { omap2xxx_cm_set_apll96_auto_low_power_stop(); } +#ifdef CONFIG_COMMON_CLK +static void _apll96_deny_idle(struct clk_hw_omap *clk) +#else static void _apll96_deny_idle(struct clk *clk) +#endif { omap2xxx_cm_set_apll96_disable_autoidle(); } +#ifdef CONFIG_COMMON_CLK +static void _apll54_allow_idle(struct clk_hw_omap *clk) +#else static void _apll54_allow_idle(struct clk *clk) +#endif { omap2xxx_cm_set_apll54_auto_low_power_stop(); } +#ifdef CONFIG_COMMON_CLK +static void _apll54_deny_idle(struct clk_hw_omap *clk) +#else static void _apll54_deny_idle(struct clk *clk) +#endif { omap2xxx_cm_set_apll54_disable_autoidle(); } +#ifdef CONFIG_COMMON_CLK +void omap2_clk_apll96_disable(struct clk_hw *hw) +#else static void _apll96_disable(struct clk *clk) +#endif { omap2xxx_cm_apll96_disable(); } +#ifdef CONFIG_COMMON_CLK +void omap2_clk_apll54_disable(struct clk_hw *hw) +#else static void _apll54_disable(struct clk *clk) +#endif { omap2xxx_cm_apll54_disable(); } /* Public data */ +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_apll54 = { + .allow_idle = _apll54_allow_idle, + .deny_idle = _apll54_deny_idle, +}; +const struct clk_hw_omap_ops clkhwops_apll96 = { + .allow_idle = _apll96_allow_idle, + .deny_idle = _apll96_deny_idle, +}; +#else const struct clkops clkops_apll96 = { .enable = _apll96_enable, .disable = _apll96_disable, @@ -93,6 +135,7 @@ const struct clkops clkops_apll54 = { .allow_idle = _apll54_allow_idle, .deny_idle = _apll54_deny_idle, }; +#endif /* Public functions */ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index 399534c..d0fd77b 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -29,7 +29,11 @@ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 * instead. Add some mechanism to optionally enter this mode. */ +#ifdef CONFIG_COMMON_CLK +static void _allow_idle(struct clk_hw_omap *clk) +#else static void _allow_idle(struct clk *clk) +#endif { if (!clk || !clk->dpll_data) return; @@ -43,7 +47,11 @@ static void _allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void _deny_idle(struct clk_hw_omap *clk) +#else static void _deny_idle(struct clk *clk) +#endif { if (!clk || !clk->dpll_data) return; @@ -53,9 +61,15 @@ static void _deny_idle(struct clk *clk) /* Public data */ - +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = { + .allow_idle = _allow_idle, + .deny_idle = _deny_idle, +}; +#else const struct clkops clkops_omap2xxx_dpll_ops = { .allow_idle = _allow_idle, .deny_idle = _deny_idle, }; +#endif diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index e687163..9d8388b 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -41,7 +41,11 @@ * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). */ +#ifdef CONFIG_COMMON_CLK +static struct clk_hw_omap *dpll_core_ck; +#else static struct clk *dpll_core_ck; +#endif /** * omap2xxx_clk_get_core_rate - return the CORE_CLK rate @@ -105,13 +109,25 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, + unsigned long parent_rate) +#else unsigned long omap2_dpllcore_recalc(struct clk *clk) +#endif { return omap2xxx_clk_get_core_rate(); } +#ifdef CONFIG_COMMON_CLK +int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); +#else int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) { +#endif u32 cur_rate, low, mult, div, valid_rate, done_rate; u32 bypass = 0; struct prcm_config tmpset; @@ -189,8 +205,16 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) * statically defined, this code may need to change to increment some * kind of use count on dpll_ck. */ +#ifdef CONFIG_COMMON_CLK +void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw) +#else void omap2xxx_clkt_dpllcore_init(struct clk *clk) +#endif { WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); +#ifdef CONFIG_COMMON_CLK + dpll_core_ck = to_clk_hw_omap(hw); +#else dpll_core_ck = clk; +#endif } diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index e177737..395e0c1 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -35,7 +35,11 @@ * clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ +#ifdef CONFIG_COMMON_CLK +int omap2_enable_osc_ck(struct clk_hw *clk) +#else static int omap2_enable_osc_ck(struct clk *clk) +#endif { u32 pcc; @@ -53,7 +57,11 @@ static int omap2_enable_osc_ck(struct clk *clk) * clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ +#ifdef CONFIG_COMMON_CLK +void omap2_disable_osc_ck(struct clk_hw *clk) +#else static void omap2_disable_osc_ck(struct clk *clk) +#endif { u32 pcc; @@ -62,12 +70,19 @@ static void omap2_disable_osc_ck(struct clk *clk) __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); } +#ifndef CONFIG_COMMON_CLK const struct clkops clkops_oscck = { .enable = omap2_enable_osc_ck, .disable = omap2_disable_osc_ck, }; +#endif +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate) +#else unsigned long omap2_osc_clk_recalc(struct clk *clk) +#endif { return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); } diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c index 46683b3..e6e73cf6 100644 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c @@ -40,9 +40,16 @@ u32 omap2xxx_get_sysclkdiv(void) return div; } +#ifdef CONFIG_COMMON_CLK +unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate) +{ + return parent_rate / omap2xxx_get_sysclkdiv(); +} +#else unsigned long omap2xxx_sys_clk_recalc(struct clk *clk) { return clk->parent->rate / omap2xxx_get_sysclkdiv(); } - +#endif diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index b9b981b..9a79ffa 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -59,7 +59,12 @@ static unsigned long sys_ck_rate; * * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. */ +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, + unsigned long parent_rate) +#else unsigned long omap2_table_mpu_recalc(struct clk *clk) +#endif { return curr_prcm_set->mpu_speed; } @@ -71,7 +76,12 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk) * Some might argue L3-DDR, others ARM, others IVA. This code is simple and * just uses the ARM rates. */ +#ifdef CONFIG_COMMON_CLK +long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +#else long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) +#endif { const struct prcm_config *ptr; long highest_rate; @@ -94,7 +104,12 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) } /* Sets basic clocks based on the specified rate */ +#ifdef CONFIG_COMMON_CLK +int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +#else int omap2_select_table_rate(struct clk *clk, unsigned long rate) +#endif { u32 cur_rate, done_rate, bypass = 0, tmp; const struct prcm_config *prcm; diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index e37df53..7a61d78 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c @@ -40,7 +40,11 @@ * passes back the correct CM_IDLEST register address for I2CHS * modules. No return value. */ +#ifdef CONFIG_COMMON_CLK +static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, +#else static void omap2430_clk_i2chs_find_idlest(struct clk *clk, +#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -51,9 +55,16 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk, } /* 2430 I2CHS has non-standard IDLEST register */ +#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = { + .find_idlest = omap2430_clk_i2chs_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; +#else const struct clkops clkops_omap2430_i2chs_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, .find_idlest = omap2430_clk_i2chs_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; +#endif diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 5f7faeb..1ff6469 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c @@ -28,6 +28,7 @@ #include "cm.h" #include "cm-regbits-24xx.h" +struct clk_hw *dclk_hw; /* * Omap24xx specific clock functions */ diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index ce809c9..5858151 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -8,6 +8,26 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#include "clock.h" + +unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, + unsigned long parent_rate); +int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate); +unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate); +unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate); +unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, + unsigned long parent_rate); +int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); +void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); +#else unsigned long omap2_table_mpu_recalc(struct clk *clk); int omap2_select_table_rate(struct clk *clk, unsigned long rate); long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); @@ -15,11 +35,12 @@ unsigned long omap2xxx_sys_clk_recalc(struct clk *clk); unsigned long omap2_osc_clk_recalc(struct clk *clk); unsigned long omap2_dpllcore_recalc(struct clk *clk); int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); +void omap2xxx_clkt_dpllcore_init(struct clk *clk); +#endif unsigned long omap2xxx_clk_get_core_rate(void); u32 omap2xxx_get_apll_clkin(void); u32 omap2xxx_get_sysclkdiv(void); void omap2xxx_clk_prepare_for_reboot(void); -void omap2xxx_clkt_dpllcore_init(struct clk *clk); void omap2xxx_clkt_vps_check_bootloader_rates(void); void omap2xxx_clkt_vps_late_init(void); @@ -37,9 +58,19 @@ int omap2430_clk_init(void); extern void __iomem *prcm_clksrc_ctrl; +#ifdef CONFIG_COMMON_CLK +extern struct clk_hw *dclk_hw; +int omap2_enable_osc_ck(struct clk_hw *hw); +void omap2_disable_osc_ck(struct clk_hw *hw); +int omap2_clk_apll96_enable(struct clk_hw *hw); +int omap2_clk_apll54_enable(struct clk_hw *hw); +void omap2_clk_apll96_disable(struct clk_hw *hw); +void omap2_clk_apll54_disable(struct clk_hw *hw); +#else extern const struct clkops clkops_omap2430_i2chs_wait; extern const struct clkops clkops_oscck; extern const struct clkops clkops_apll96; extern const struct clkops clkops_apll54; +#endif #endif diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 83815dd..87ae36c 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -25,7 +25,11 @@ #include <linux/sysfs.h> #include <linux/module.h> #include <linux/delay.h> +#ifdef CONFIG_COMMON_CLK +#include <linux/clk-provider.h> +#else #include <linux/clk.h> +#endif #include <linux/irq.h> #include <linux/time.h> #include <linux/gpio.h> @@ -202,7 +206,11 @@ static int omap2_can_sleep(void) { if (omap2_fclks_active()) return 0; +#ifdef CONFIG_COMMON_CLK + if (__clk_is_enabled(osc_ck)) +#else if (osc_ck->usecount > 1) +#endif return 0; if (omap_dma_running()) return 0; ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 06/26] ARM: OMAP2xxx: clock: add APLL rate recalculation functions 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (4 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 05/26] ARM: OMAP2: " Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 07/26] ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle Mike Turquette ` (22 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Paul Walmsley <paul@pwsan.com> OMAP2420 and OMAP2430 chips each have two on-chip APLLs. When locked, one APLL generates a 96 MHz rate; the other, a 54 MHz rate. Previously we treated these clocks as fixed-rate clocks at the locked rates, but this isn't quite right. The locked rate should be returned when the APLL is locked, and a zero rate should be returned when the APLL is stopped. This patch adds the infrastructure that will be used by the CCF changes. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> --- arch/arm/mach-omap2/clkt2xxx_apll.c | 35 +++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock2xxx.h | 4 ++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 83088c4..d8a850b 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -41,6 +41,27 @@ void __iomem *cm_idlest_pll; /* Private functions */ +#ifdef CONFIG_COMMON_CLK +/** + * omap2xxx_clk_apll_locked - is the APLL locked? + * @hw: struct clk_hw * of the APLL to check + * + * If the APLL IP block referred to by @hw indicates that it's locked, + * return true; otherwise, return false. + */ +static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 r, apll_mask; + + apll_mask = EN_APLL_LOCKED << clk->enable_bit; + + r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + + return ((r & apll_mask) == apll_mask) ? true : false; +} +#endif + /* Enable an APLL if off */ #ifdef CONFIG_COMMON_CLK static int omap2_clk_apll_enable(struct clk_hw *hw, u32 status_mask) @@ -147,6 +168,20 @@ static void omap2_clk_apll_disable(struct clk *clk) omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); } +#ifdef CONFIG_COMMON_CLK +unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0; +} + +unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0; +} +#endif + /* Public data */ #ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_apll54 = { diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 1ce94b6..f2b93e3 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -27,6 +27,10 @@ unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); unsigned long omap2xxx_clk_get_core_rate(struct clk_hw_omap *clk); +unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, + unsigned long parent_rate); +unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, + unsigned long parent_rate); #else unsigned long omap2_table_mpu_recalc(struct clk *clk); int omap2_select_table_rate(struct clk *clk, unsigned long rate); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 07/26] ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (5 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 06/26] ARM: OMAP2xxx: clock: add APLL rate recalculation functions Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-12 23:00 ` Paul Walmsley 2012-11-08 1:12 ` [PATCH 08/26] ARM: OMAP: clock: Define a function to enable clocks at init Mike Turquette ` (21 subsequent siblings) 28 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Platforms can call omap2_init_clk_hw_omap_clocks() to register a clock using clk_hw_omap. omap2_clk_enable_autoidle_all() and omap2_clk_disable_autoidle_all() can then be used to run through all the clocks which support autoidle to enable/disable them. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clock.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 3 +++ arch/arm/mach-omap2/io.c | 27 +++++++++++++++++++++++++++ arch/arm/mach-omap2/omap_hwmod.c | 4 ++-- 4 files changed, 64 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 3a4c1c5..2b4cfae 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -57,6 +57,7 @@ static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clockfw_lock); #ifdef CONFIG_COMMON_CLK +LIST_HEAD(clk_hw_omap_clocks); /* * Used for clocks that have the same value as the parent clock, @@ -426,6 +427,37 @@ static int __init omap_clk_setup(char *str) } __setup("mpurate=", omap_clk_setup); +void omap2_init_clk_hw_omap_clocks(struct clk *clk) +{ + struct clk_hw_omap *c; + + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return; + + c = to_clk_hw_omap(__clk_get_hw(clk)); + list_add(&c->node, &clk_hw_omap_clocks); +} + +int omap2_clk_enable_autoidle_all(void) +{ + struct clk_hw_omap *c; + + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->allow_idle) + c->ops->allow_idle(c); + return 0; +} + +int omap2_clk_disable_autoidle_all(void) +{ + struct clk_hw_omap *c; + + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->deny_idle) + c->ops->deny_idle(c); + return 0; +} + const struct clk_hw_omap_ops clkhwops_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index d78f90e..b075831 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -562,6 +562,9 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); +void omap2_init_clk_hw_omap_clocks(struct clk *clk); +int omap2_clk_enable_autoidle_all(void); +int omap2_clk_disable_autoidle_all(void); #else int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4fadc78..a62010e 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -393,6 +393,9 @@ void __init omap2420_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap2_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } #endif @@ -415,6 +418,9 @@ void __init omap2430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap2_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } #endif @@ -476,6 +482,9 @@ void __init omap3_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init omap3430_init_late(void) @@ -483,6 +492,9 @@ void __init omap3430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init omap35xx_init_late(void) @@ -490,6 +502,9 @@ void __init omap35xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init omap3630_init_late(void) @@ -497,6 +512,9 @@ void __init omap3630_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init am35xx_init_late(void) @@ -504,6 +522,9 @@ void __init am35xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init ti81xx_init_late(void) @@ -511,6 +532,9 @@ void __init ti81xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } #endif @@ -550,6 +574,9 @@ void __init omap4430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap4_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } #endif diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 1754d7e..ce93ec0 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -623,12 +623,12 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) struct clockdomain *_get_clkdm(struct omap_hwmod *oh) { - struct clk_hw_omap *clk; - if (oh->clkdm) { return oh->clkdm; } else if (oh->_clk) { #ifdef CONFIG_COMMON_CLK + struct clk_hw_omap *clk; + clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); return clk->clkdm; #else -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 07/26] ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle 2012-11-08 1:12 ` [PATCH 07/26] ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle Mike Turquette @ 2012-11-12 23:00 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-12 23:00 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches Added kerneldoc to the non-trivial new functions added by this patch, as is local policy. Updated patch below. - Paul From: Rajendra Nayak <rnayak@ti.com> Date: Fri, 1 Jun 2012 14:02:49 +0530 Subject: [PATCH] ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle Platforms can call omap2_init_clk_hw_omap_clocks() to register a clock using clk_hw_omap. omap2_clk_enable_autoidle_all() and omap2_clk_disable_autoidle_all() can then be used to run through all the clocks which support autoidle to enable/disable them. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: added kerneldoc on non-trivial new functions] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/clock.c | 59 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 3 +++ arch/arm/mach-omap2/io.c | 27 ++++++++++++++++++++ 3 files changed, 89 insertions(+) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 72d7105..c64203e 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -66,6 +66,7 @@ static DEFINE_SPINLOCK(clockfw_lock); #endif #ifdef CONFIG_COMMON_CLK +static LIST_HEAD(clk_hw_omap_clocks); /* * Used for clocks that have the same value as the parent clock, @@ -521,6 +522,64 @@ static int __init omap_clk_setup(char *str) } __setup("mpurate=", omap_clk_setup); +/** + * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock + * @clk: struct clk * to initialize + * + * Add an OMAP clock @clk to the internal list of OMAP clocks. Used + * temporarily for autoidle handling, until this support can be + * integrated into the common clock framework code in some way. No + * return value. + */ +void omap2_init_clk_hw_omap_clocks(struct clk *clk) +{ + struct clk_hw_omap *c; + + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return; + + c = to_clk_hw_omap(__clk_get_hw(clk)); + list_add(&c->node, &clk_hw_omap_clocks); +} + +/** + * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that + * support it + * + * Enable clock autoidle on all OMAP clocks that have allow_idle + * function pointers associated with them. This function is intended + * to be temporary until support for this is added to the common clock + * code. Returns 0. + */ +int omap2_clk_enable_autoidle_all(void) +{ + struct clk_hw_omap *c; + + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->allow_idle) + c->ops->allow_idle(c); + return 0; +} + +/** + * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that + * support it + * + * Disable clock autoidle on all OMAP clocks that have allow_idle + * function pointers associated with them. This function is intended + * to be temporary until support for this is added to the common clock + * code. Returns 0. + */ +int omap2_clk_disable_autoidle_all(void) +{ + struct clk_hw_omap *c; + + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->deny_idle) + c->ops->deny_idle(c); + return 0; +} + const struct clk_hw_omap_ops clkhwops_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 6800d5f..20a3be7 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -535,6 +535,9 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); +void omap2_init_clk_hw_omap_clocks(struct clk *clk); +int omap2_clk_enable_autoidle_all(void); +int omap2_clk_disable_autoidle_all(void); #else int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index c3472bd..41c6013 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -407,6 +407,9 @@ void __init omap2420_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap2_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } #endif @@ -436,6 +439,9 @@ void __init omap2430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap2_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } #endif @@ -509,6 +515,9 @@ void __init omap3_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init omap3430_init_late(void) @@ -516,6 +525,9 @@ void __init omap3430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init omap35xx_init_late(void) @@ -523,6 +535,9 @@ void __init omap35xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init omap3630_init_late(void) @@ -530,6 +545,9 @@ void __init omap3630_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init am35xx_init_late(void) @@ -537,6 +555,9 @@ void __init am35xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } void __init ti81xx_init_late(void) @@ -544,6 +565,9 @@ void __init ti81xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } #endif @@ -597,6 +621,9 @@ void __init omap4430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap4_pm_init(); +#ifdef CONFIG_COMMON_CLK + omap2_clk_enable_autoidle_all(); +#endif } #endif -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 08/26] ARM: OMAP: clock: Define a function to enable clocks at init 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (6 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 07/26] ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-12 23:01 ` Paul Walmsley 2012-11-08 1:12 ` [PATCH 09/26] ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions Mike Turquette ` (20 subsequent siblings) 28 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Platform code can use omap2_clk_enable_init_clocks() to enable a list of clocks that are needed to be enabled at init. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clock.c | 11 +++++++++++ arch/arm/mach-omap2/clock.h | 1 + 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 2b4cfae..99fb246 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -458,6 +458,17 @@ int omap2_clk_disable_autoidle_all(void) return 0; } +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) +{ + struct clk *init_clk; + int i; + + for (i = 0; i < num_clocks; i++) { + init_clk = clk_get(NULL, clk_names[i]); + clk_prepare_enable(init_clk); + } +} + const struct clk_hw_omap_ops clkhwops_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b075831..22555fd 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -565,6 +565,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); int omap2_clk_disable_autoidle_all(void); +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); #else int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 08/26] ARM: OMAP: clock: Define a function to enable clocks at init 2012-11-08 1:12 ` [PATCH 08/26] ARM: OMAP: clock: Define a function to enable clocks at init Mike Turquette @ 2012-11-12 23:01 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-12 23:01 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches Added kerneldoc on the new non-trivial function in this patch, as is local policy. Updated patch follows. - Paul From: Rajendra Nayak <rnayak@ti.com> Date: Fri, 1 Jun 2012 14:02:49 +0530 Subject: [PATCH] ARM: OMAP: clock: Define a function to enable clocks at init Platform code can use omap2_clk_enable_init_clocks() to enable a list of clocks that are needed to be enabled at init. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: added kerneldoc to non-trivial new function] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/clock.c | 21 +++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 1 + 2 files changed, 22 insertions(+) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index c64203e..744e6eb 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -580,6 +580,27 @@ int omap2_clk_disable_autoidle_all(void) return 0; } +/** + * omap2_clk_enable_init_clocks - prepare & enable a list of clocks + * @clk_names: ptr to an array of strings of clock names to enable + * @num_clocks: number of clock names in @clk_names + * + * Prepare and enable a list of clocks, named by @clk_names. No + * return value. XXX Deprecated; only needed until these clocks are + * properly claimed and enabled by the drivers or core code that uses + * them. XXX What code disables & calls clk_put on these clocks? + */ +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) +{ + struct clk *init_clk; + int i; + + for (i = 0; i < num_clocks; i++) { + init_clk = clk_get(NULL, clk_names[i]); + clk_prepare_enable(init_clk); + } +} + const struct clk_hw_omap_ops clkhwops_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 20a3be7..e669fc8 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -538,6 +538,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); int omap2_clk_disable_autoidle_all(void); +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); #else int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 09/26] ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (7 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 08/26] ARM: OMAP: clock: Define a function to enable clocks at init Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 10/26] ARM: OMAP: clock: Get rid of some clkdm assocations within clks Mike Turquette ` (19 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul Cc: rnayak, linux-omap, linux-arm-kernel, patches, Vaibhav Hiremath, Mike Turquette From: Vaibhav Hiremath <hvaibhav@ti.com> Without this kernel would crash, since clkdm inside omap_hwmod is accessed in some of the init funtion like, _init_main_clk. So call init_clkdm before _init_main_clk(). Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/omap_hwmod.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index ce93ec0..22a41f6 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1522,11 +1522,12 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); + if (soc_ops.init_clkdm) + ret |= soc_ops.init_clkdm(oh); + ret |= _init_main_clk(oh); ret |= _init_interface_clks(oh); ret |= _init_opt_clks(oh); - if (soc_ops.init_clkdm) - ret |= soc_ops.init_clkdm(oh); if (!ret) oh->_state = _HWMOD_STATE_CLKS_INITED; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 10/26] ARM: OMAP: clock: Get rid of some clkdm assocations within clks 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (8 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 09/26] ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 11/26] ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h Mike Turquette ` (18 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> It's suspected that some of the clockdomain associations with clocks can be removed from the clock data. Drop several of these associations to save diffstat and improve performance. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: removed most of the changes in this patch; modified patch description] Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clock2420_data.c | 10 ---------- arch/arm/mach-omap2/clock2430_data.c | 10 ---------- arch/arm/mach-omap2/clock3xxx_data.c | 22 ---------------------- 3 files changed, 42 deletions(-) diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index da1e388..3534f88 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -54,14 +54,12 @@ static struct clk func_32k_ck = { .name = "func_32k_ck", .ops = &clkops_null, .rate = 32768, - .clkdm_name = "wkup_clkdm", }; static struct clk secure_32k_ck = { .name = "secure_32k_ck", .ops = &clkops_null, .rate = 32768, - .clkdm_name = "wkup_clkdm", }; /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ @@ -85,7 +83,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .name = "alt_ck", .ops = &clkops_null, .rate = 54000000, - .clkdm_name = "wkup_clkdm", }; /* Optional external clock input for McBSP CLKS */ @@ -178,7 +175,6 @@ static struct clk func_54m_ck = { .name = "func_54m_ck", .ops = &clkops_null, .parent = &apll54_ck, /* can also be alt_clk */ - .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_54M_SOURCE_MASK, @@ -239,7 +235,6 @@ static struct clk func_12m_ck = { .ops = &clkops_null, .parent = &func_48m_ck, .fixed_div = 4, - .clkdm_name = "wkup_clkdm", .recalc = &omap_fixed_divisor_recalc, }; @@ -321,7 +316,6 @@ static struct clk sys_clkout = { .name = "sys_clkout", .ops = &clkops_null, .parent = &sys_clkout_src, - .clkdm_name = "wkup_clkdm", .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, .clksel = sys_clkout_clksel, @@ -357,7 +351,6 @@ static struct clk sys_clkout2 = { .name = "sys_clkout2", .ops = &clkops_null, .parent = &sys_clkout2_src, - .clkdm_name = "wkup_clkdm", .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, @@ -405,7 +398,6 @@ static struct clk mpu_ck = { /* Control cpu */ .name = "mpu_ck", .ops = &clkops_null, .parent = &core_ck, - .clkdm_name = "mpu_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, @@ -539,7 +531,6 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ .name = "core_l3_ck", .ops = &clkops_null, .parent = &core_ck, - .clkdm_name = "core_l3_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, .clksel = core_l3_clksel, @@ -595,7 +586,6 @@ static struct clk l4_ck = { /* used both as an ick and fck */ .name = "l4_ck", .ops = &clkops_null, .parent = &core_l3_ck, - .clkdm_name = "core_l4_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, .clksel = l4_clksel, diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index c97dafe..adda9ac 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -53,14 +53,12 @@ static struct clk func_32k_ck = { .name = "func_32k_ck", .ops = &clkops_null, .rate = 32768, - .clkdm_name = "wkup_clkdm", }; static struct clk secure_32k_ck = { .name = "secure_32k_ck", .ops = &clkops_null, .rate = 32768, - .clkdm_name = "wkup_clkdm", }; /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ @@ -84,7 +82,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .name = "alt_ck", .ops = &clkops_null, .rate = 54000000, - .clkdm_name = "wkup_clkdm", }; /* Optional external clock input for McBSP CLKS */ @@ -177,7 +174,6 @@ static struct clk func_54m_ck = { .name = "func_54m_ck", .ops = &clkops_null, .parent = &apll54_ck, /* can also be alt_clk */ - .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_54M_SOURCE_MASK, @@ -214,7 +210,6 @@ static struct clk func_96m_ck = { .name = "func_96m_ck", .ops = &clkops_null, .parent = &apll96_ck, - .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP2430_96M_SOURCE_MASK, @@ -259,7 +254,6 @@ static struct clk func_12m_ck = { .ops = &clkops_null, .parent = &func_48m_ck, .fixed_div = 4, - .clkdm_name = "wkup_clkdm", .recalc = &omap_fixed_divisor_recalc, }; @@ -341,7 +335,6 @@ static struct clk sys_clkout = { .name = "sys_clkout", .ops = &clkops_null, .parent = &sys_clkout_src, - .clkdm_name = "wkup_clkdm", .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, .clksel = sys_clkout_clksel, @@ -386,7 +379,6 @@ static struct clk mpu_ck = { /* Control cpu */ .name = "mpu_ck", .ops = &clkops_null, .parent = &core_ck, - .clkdm_name = "mpu_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, @@ -484,7 +476,6 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ .name = "core_l3_ck", .ops = &clkops_null, .parent = &core_ck, - .clkdm_name = "core_l3_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, .clksel = core_l3_clksel, @@ -540,7 +531,6 @@ static struct clk l4_ck = { /* used both as an ick and fck */ .name = "l4_ck", .ops = &clkops_null, .parent = &core_l3_ck, - .clkdm_name = "core_l4_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, .clksel = l4_clksel, diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 6cca199..eaa7f2f 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -300,7 +300,6 @@ static struct clk dpll1_x2_ck = { .name = "dpll1_x2_ck", .ops = &clkops_null, .parent = &dpll1_ck, - .clkdm_name = "dpll1_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -322,7 +321,6 @@ static struct clk dpll1_x2m2_ck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll1_x2m2_clksel, - .clkdm_name = "dpll1_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -382,7 +380,6 @@ static struct clk dpll2_m2_ck = { OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll2_m2x2_clksel, - .clkdm_name = "dpll2_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -430,7 +427,6 @@ static struct clk dpll3_x2_ck = { .name = "dpll3_x2_ck", .ops = &clkops_null, .parent = &dpll3_ck, - .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -483,7 +479,6 @@ static struct clk dpll3_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, .clksel = div31_dpll3m2_clksel, - .clkdm_name = "dpll3_clkdm", .round_rate = &omap2_clksel_round_rate, .set_rate = &omap3_core_dpll_m2_set_rate, .recalc = &omap2_clksel_recalc, @@ -500,7 +495,6 @@ static struct clk dpll3_m2x2_ck = { .name = "dpll3_m2x2_ck", .ops = &clkops_null, .parent = &dpll3_m2_ck, - .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -519,7 +513,6 @@ static struct clk dpll3_m3_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, .clksel = div16_dpll3_clksel, - .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -614,7 +607,6 @@ static struct clk dpll4_x2_ck = { .name = "dpll4_x2_ck", .ops = &clkops_null, .parent = &dpll4_ck, - .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -632,7 +624,6 @@ static struct clk dpll4_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3630_DIV_96M_MASK, .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -735,7 +726,6 @@ static struct clk dpll4_m3_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_TV_MASK, .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -820,7 +810,6 @@ static struct clk dpll4_m4_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, .set_rate = &omap2_clksel_set_rate, .round_rate = &omap2_clksel_round_rate, @@ -847,7 +836,6 @@ static struct clk dpll4_m5_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", .set_rate = &omap2_clksel_set_rate, .round_rate = &omap2_clksel_round_rate, .recalc = &omap2_clksel_recalc, @@ -874,7 +862,6 @@ static struct clk dpll4_m6_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3630_DIV_DPLL4_MASK, .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -948,7 +935,6 @@ static struct clk dpll5_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), .clksel_mask = OMAP3430ES2_DIV_120M_MASK, .clksel = div16_dpll5_clksel, - .clkdm_name = "dpll5_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1087,7 +1073,6 @@ static struct clk arm_fck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = arm_fck_clksel, - .clkdm_name = "mpu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1140,7 +1125,6 @@ static struct clk l3_ick = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L3_MASK, .clksel = div2_core_clksel, - .clkdm_name = "core_l3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1157,7 +1141,6 @@ static struct clk l4_ick = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L4_MASK, .clksel = div2_l3_clksel, - .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2968,7 +2951,6 @@ static struct clk pclk_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel = pclk_emu_clksel, - .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2991,7 +2973,6 @@ static struct clk pclkx2_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel = pclkx2_emu_clksel, - .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3007,7 +2988,6 @@ static struct clk atclk_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel = atclk_emu_clksel, - .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3018,7 +2998,6 @@ static struct clk traceclk_src_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3041,7 +3020,6 @@ static struct clk traceclk_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, .clksel = traceclk_clksel, - .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 11/26] ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (9 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 10/26] ARM: OMAP: clock: Get rid of some clkdm assocations within clks Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 12/26] ARM: OMAP4: clock: Add 44xx data using common struct clk Mike Turquette ` (17 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Paul Walmsley <paul@pwsan.com> Define four convenience macros to be used in the upcoming OMAP2+ common clock framework port. Although the use of these macros will make the data somewhat more difficult to read, they significantly reduce the number of lines in the output patch data. Most of these were created by Rajendra Nayak and Mike Turquette, as far as I know. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com> [mturquette@ti.com: added DEFINE_CLK_OMAP_HSDIVIDER macro] Cc: Rajendra Nayak <rnayak@ti.com> --- arch/arm/mach-omap2/clock.h | 77 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 22555fd..1599f7b 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -58,6 +58,83 @@ struct omap_clk { struct clockdomain; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) +#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ + static struct clk _name = { \ + .name = #_name, \ + .hw = &_name##_hw.hw, \ + .parent_names = _parent_array_name, \ + .num_parents = ARRAY_SIZE(_parent_array_name), \ + .ops = &_clkops_name, \ + }; + +#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ + static struct clk_hw_omap _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .clkdm_name = _clkdm_name, \ + }; + +#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ + _clksel_reg, _clksel_mask, \ + _parent_names, _ops) \ + static struct clk _name; \ + static struct clk_hw_omap _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .clksel = _clksel, \ + .clksel_reg = _clksel_reg, \ + .clksel_mask = _clksel_mask, \ + .clkdm_name = _clkdm_name, \ + }; \ + DEFINE_STRUCT_CLK(_name, _parent_names, _ops); + +#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ + _clksel_reg, _clksel_mask, \ + _enable_reg, _enable_bit, \ + _hwops, _parent_names, _ops) \ + static struct clk _name; \ + static struct clk_hw_omap _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .ops = _hwops, \ + .enable_reg = _enable_reg, \ + .enable_bit = _enable_bit, \ + .clksel = _clksel, \ + .clksel_reg = _clksel_reg, \ + .clksel_mask = _clksel_mask, \ + .clkdm_name = _clkdm_name, \ + }; \ + DEFINE_STRUCT_CLK(_name, _parent_names, _ops); + +#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask) \ + static const struct clksel _name##_div[] = { \ + { \ + .parent = _parent_ptr, \ + .rates = div31_1to31_rates \ + }, \ + { .parent = NULL }, \ + }; \ + static struct clk _name; \ + static const char *_name##_parent_names[] = { \ + _parent_name, \ + }; \ + static struct clk_hw_omap _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .clksel = _name##_div, \ + .clksel_reg = _clksel_reg, \ + .clksel_mask = _clksel_mask, \ + .ops = &clkhwops_omap4_dpllmx, \ + }; \ + DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); + + #else struct module; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 12/26] ARM: OMAP4: clock: Add 44xx data using common struct clk 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (10 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 11/26] ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-13 1:37 ` Paul Walmsley 2012-11-08 1:12 ` [PATCH 13/26] ARM: AM33XX: clock: add clock data in common clock format Mike Turquette ` (16 subsequent siblings) 28 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> This patch is output from updated omap hw data autogeneration scripts mostly contributed by Mike Turquette, with some later fixes from me. All data is added into a new cclock44xx_data.c file which will be switched with clock44xx_data.c file in a later patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflowed macros; updated DEFINE_STRUCT_CLK_HW_OMAP macro to include clkdm_name; use macros for clksel mux+gate clocks; many other fixes] Signed-off-by: Mike Turquette <mturquette@ti.com> [mturquette@ti.com: converted DPLL outputs to HSDIVIDER macro] [mturquette@ti.com: trace_clk_div_ck has clkdm ops] --- arch/arm/mach-omap2/cclock44xx_data.c | 1991 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 2 + arch/arm/mach-omap2/clock44xx_data.c | 8 - arch/arm/mach-omap2/clock_common_data.c | 22 + arch/arm/mach-omap2/dpll3xxx.c | 20 +- arch/arm/mach-omap2/scrm44xx.h | 2 + 6 files changed, 2036 insertions(+), 9 deletions(-) create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c new file mode 100644 index 0000000..18dcf78 --- /dev/null +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -0,0 +1,1991 @@ +/* + * OMAP4 Clock data + * + * Copyright (C) 2009-2012 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Mike Turquette (mturquette@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX Some of the ES1 clocks have been removed/changed; once support + * is added for discriminating clocks by ES level, these should be added back + * in. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-private.h> +#include <linux/clkdev.h> +#include <linux/io.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock44xx.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" +#include "cm-regbits-44xx.h" +#include "prm44xx.h" +#include "prm-regbits-44xx.h" +#include "control.h" +#include "scrm44xx.h" + +/* OMAP4 modulemode control */ +#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 +#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 + +/* Root clocks */ + +DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); + +DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT, + 0x0, NULL); + +DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT, + 0x0, NULL); + +DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); + +static const char *sys_clkin_ck_parents[] = { + "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck", + "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", + "virt_38400000_ck", +}; + +DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, + OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT, + OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); + +DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0); + +DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0); + +/* Module clocks and DPLL outputs */ + +static const char *abe_dpll_bypass_clk_mux_ck_parents[] = { + "sys_clkin_ck", "sys_32k_ck", +}; + +DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, + NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT, + OMAP4430_CLKSEL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +/* DPLL_ABE */ +static struct dpll_data dpll_abe_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, + .clk_bypass = &abe_dpll_bypass_clk_mux_ck, + .clk_ref = &abe_dpll_refclk_mux_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static const char *dpll_abe_ck_parents[] = { + "abe_dpll_refclk_mux_ck", +}; + +static struct clk dpll_abe_ck; + +static const struct clk_ops dpll_abe_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap4_dpll_regm4xen_recalc, + .round_rate = &omap4_dpll_regm4xen_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_abe_ck_hw = { + .hw = { + .clk = &dpll_abe_ck, + }, + .dpll_data = &dpll_abe_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_abe_x2_ck_parents[] = { + "dpll_abe_ck", +}; + +static struct clk dpll_abe_x2_ck; + +static const struct clk_ops dpll_abe_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll_abe_x2_ck_hw = { + .hw = { + .clk = &dpll_abe_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); + +static const struct clk_ops omap_hsdivider_ops = { + .set_rate = &omap2_clksel_set_rate, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, + 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, + 0x0, 1, 8); + +DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT, + OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, + OMAP4430_CLKSEL_AESS_FCLK_SHIFT, + OMAP4430_CLKSEL_AESS_FCLK_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, 0x0, + OMAP4430_CM_DIV_M3_DPLL_ABE, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK); + +static const char *core_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "dpll_abe_m3x2_ck", +}; + +DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE, + OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH, + 0x0, NULL); + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, + .clk_bypass = &core_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static const char *dpll_core_ck_parents[] = { + "sys_clkin_ck", +}; + +static struct clk dpll_core_ck; + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .hw = { + .clk = &dpll_core_ck, + }, + .dpll_data = &dpll_core_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); + +static const char *dpll_core_x2_ck_parents[] = { + "dpll_core_ck", +}; + +static struct clk dpll_core_x2_ck; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .hw = { + .clk = &dpll_core_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, + OMAP4430_CM_DIV_M6_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_CORE, OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1, + 2); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, + OMAP4430_CM_DIV_M5_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, + OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, + OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_MASK); + +DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, + 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, + OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, + OMAP4430_CM_DIV_M4_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, + 0x0, 1, 2); + +DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, + OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static const struct clk_ops dmic_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, + .init = &omap2_init_clk_clkdm, +}; + +static const char *dpll_core_m3x2_ck_parents[] = { + "dpll_core_x2_ck", +}; + +static const struct clksel dpll_core_m3x2_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +/* XXX Missing round_rate, set_rate in ops */ +DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, + OMAP4430_CM_DIV_M3_DPLL_CORE, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, + OMAP4430_CM_DIV_M3_DPLL_CORE, + OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, + dpll_core_m3x2_ck_parents, dmic_fck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, + OMAP4430_CM_DIV_M7_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); + +static const char *iva_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "div_iva_hs_clk", +}; + +DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, + OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); + +/* DPLL_IVA */ +static struct dpll_data dpll_iva_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, + .clk_bypass = &iva_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static struct clk dpll_iva_ck; + +static struct clk_hw_omap dpll_iva_ck_hw = { + .hw = { + .clk = &dpll_iva_ck, + }, + .dpll_data = &dpll_iva_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_iva_x2_ck_parents[] = { + "dpll_iva_ck", +}; + +static struct clk dpll_iva_x2_ck; + +static struct clk_hw_omap dpll_iva_x2_ck_hw = { + .hw = { + .clk = &dpll_iva_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, 0x0, + OMAP4430_CM_DIV_M4_DPLL_IVA, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, 0x0, + OMAP4430_CM_DIV_M5_DPLL_IVA, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, + .clk_bypass = &div_mpu_hs_clk, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static struct clk dpll_mpu_ck; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .hw = { + .clk = &dpll_mpu_ck, + }, + .dpll_data = &dpll_mpu_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_MPU, OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck", + &dpll_abe_m3x2_ck, 0x0, 1, 2); + +static const char *per_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "per_hs_clk_div_ck", +}; + +DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, + OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, + .clk_bypass = &per_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static struct clk dpll_per_ck; + +static struct clk_hw_omap dpll_per_ck_hw = { + .hw = { + .clk = &dpll_per_ck, + }, + .dpll_data = &dpll_per_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, + OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static const char *dpll_per_x2_ck_parents[] = { + "dpll_per_ck", +}; + +static struct clk dpll_per_x2_ck; + +static struct clk_hw_omap dpll_per_x2_ck_hw = { + .hw = { + .clk = &dpll_per_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_MASK); + +static const char *dpll_per_m3x2_ck_parents[] = { + "dpll_per_x2_ck", +}; + +static const struct clksel dpll_per_m3x2_div[] = { + { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +/* XXX Missing round_rate, set_rate in ops */ +DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, + OMAP4430_CM_DIV_M3_DPLL_PER, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, + OMAP4430_CM_DIV_M3_DPLL_PER, + OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, + dpll_per_m3x2_ck_parents, dmic_fck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M4_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M5_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M6_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M7_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck", + &dpll_abe_m3x2_ck, 0x0, 1, 3); + +/* DPLL_USB */ +static struct dpll_data dpll_usb_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, + .clk_bypass = &usb_hs_clk_div_ck, + .flags = DPLL_J_TYPE, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, + .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, + .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, + .max_multiplier = 4095, + .max_divider = 256, + .min_divider = 1, +}; + + +static struct clk dpll_usb_ck; + +static struct clk_hw_omap dpll_usb_ck_hw = { + .hw = { + .clk = &dpll_usb_ck, + }, + .dpll_data = &dpll_usb_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_usb_clkdcoldo_ck_parents[] = { + "dpll_usb_ck", +}; + +static struct clk dpll_usb_clkdcoldo_ck; + +static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = { +}; + +static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { + .hw = { + .clk = &dpll_usb_clkdcoldo_ck, + }, + .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents, + dpll_usb_clkdcoldo_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_USB, + OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK); + +static const char *ducati_clk_mux_ck_parents[] = { + "div_core_ck", "dpll_per_m6x2_ck", +}; + +DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 16); + +DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, + 1, 4); + +DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 8); + +static const struct clk_div_table func_48m_fclk_rates[] = { + { .div = 4, .val = 0 }, + { .div = 8, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates, + NULL); + +DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 4); + +static const struct clk_div_table func_64m_fclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 4, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates, + NULL); + +static const struct clk_div_table func_96m_fclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 4, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates, + NULL); + +static const struct clk_div_table init_60m_fclk_rates[] = { + { .div = 1, .val = 0 }, + { .div = 8, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, + 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ, + OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH, + 0x0, init_60m_fclk_rates, NULL); + +DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT, + OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT, + OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL); + +DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, + 0x0, 1, 16); + +static const char *l4_wkup_clk_mux_ck_parents[] = { + "sys_clkin_ck", "lp_clk_div_ck", +}; + +DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +static const struct clk_div_table ocp_abe_iclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 1, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, + OMAP4430_CLKSEL_AESS_FCLK_SHIFT, + OMAP4430_CLKSEL_AESS_FCLK_WIDTH, + 0x0, ocp_abe_iclk_rates, NULL); + +DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, + 0x0, 1, 4); + +DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, + OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +static struct clk dbgclk_mux_ck; +DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); +DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents, + dpll_usb_clkdcoldo_ck_ops); + +/* Leaf clocks controlled by modules */ + +DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_AES1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_AES2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); + +static const struct clk_div_table div_ts_ck_rates[] = { + { .div = 8, .val = 0 }, + { .div = 16, .val = 1 }, + { .div = 32, .val = 2 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4430_CLKSEL_24_25_SHIFT, + OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates, + NULL); + +DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, + OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +static const char *dmic_sync_mux_ck_parents[] = { + "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", +}; + +DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, + 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_dmic_abe_gfclk_sel[] = { + { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *dmic_fck_parents[] = { + "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_dmic_abe_gfclk into dmic */ +static struct clk dmic_fck; + +DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + dmic_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0, + OMAP4430_CM_TESLA_TESLA_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, + OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, + OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0, + OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0, + OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, + OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, + OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0, + OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO2_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO4_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO5_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO6_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +static const struct clksel sgx_clk_mux_sel[] = { + { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *gpu_fck_parents[] = { + "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", +}; + +/* Merged sgx_clk_mux into gpu */ +DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel, + OMAP4430_CM_GFX_GFX_CLKCTRL, + OMAP4430_CLKSEL_SGX_FCLK_MASK, + OMAP4430_CM_GFX_GFX_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + gpu_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0, + OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, + OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, + OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, + OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, + OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, + OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static struct clk l3_instr_ick; + +static const char *l3_instr_ick_parent_names[] = { + "l3_div_ck", +}; + +static const struct clk_ops l3_instr_ick_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap l3_instr_ick_hw = { + .hw = { + .clk = &l3_instr_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +static struct clk l3_main_3_ick; +static struct clk_hw_omap l3_main_3_ick_hw = { + .hw = { + .clk = &l3_main_3_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +#if 0 +DEFINE_CLK_GATE(l3_main_3_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); +#endif + +DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcasp_abe_gfclk_sel[] = { + { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcasp_fck_parents[] = { + "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcasp_abe_gfclk into mcasp */ +DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcasp_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp1_gfclk_sel[] = { + { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parents[] = { + "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp1_gfclk into mcbsp1 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp1_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp2_gfclk_sel[] = { + { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp2_fck_parents[] = { + "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp2_gfclk into mcbsp2 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp2_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp3_gfclk_sel[] = { + { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp3_fck_parents[] = { + "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp3_gfclk into mcbsp3 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp3_fck_parents, dmic_fck_ops); + +static const char *mcbsp4_sync_mux_ck_parents[] = { + "func_96m_fclk", "per_abe_nc_fclk", +}; + +DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel per_mcbsp4_gfclk_sel[] = { + { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp4_fck_parents[] = { + "mcbsp4_sync_mux_ck", "pad_clks_ck", +}; + +/* Merged per_mcbsp4_gfclk into mcbsp4 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_24_24_MASK, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp4_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0, + OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const struct clksel hsmmc1_fclk_sel[] = { + { .parent = &func_64m_fclk, .rates = div_1_0_rates }, + { .parent = &func_96m_fclk, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *mmc1_fck_parents[] = { + "func_64m_fclk", "func_96m_fclk", +}; + +/* Merged hsmmc1_fclk into mmc1 */ +DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mmc1_fck_parents, dmic_fck_ops); + +/* Merged hsmmc2_fclk into mmc2 */ +DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mmc1_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +static struct clk ocp_wp_noc_ick; + +static struct clk_hw_omap ocp_wp_noc_ick_hw = { + .hw = { + .clk = &ocp_wp_noc_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, + OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", + &pad_slimbus_core_clks_ck, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const struct clksel dmt1_clk_mux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +/* Merged dmt1_clk_mux into timer1 */ +DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm10_mux into timer10 */ +DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm11_mux into timer11 */ +DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm2_mux into timer2 */ +DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm3_mux into timer3 */ +DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm4_mux into timer4 */ +DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +static const struct clksel timer5_sync_mux_sel[] = { + { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *timer5_fck_parents[] = { + "syc_clk_div_ck", "sys_32k_ck", +}; + +/* Merged timer5_sync_mux into timer5 */ +DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer6_sync_mux into timer6 */ +DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer7_sync_mux into timer7 */ +DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer8_sync_mux into timer8 */ +DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged cm2_dm9_mux into timer9 */ +DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static struct clk usb_host_fs_fck; + +static const char *usb_host_fs_fck_parent_names[] = { + "func_48mc_fclk", +}; + +static const struct clk_ops usb_host_fs_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap usb_host_fs_fck_hw = { + .hw = { + .clk = &usb_host_fs_fck, + }, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, + .clkdm_name = "l3_init_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names, + usb_host_fs_fck_ops); + +static const char *utmi_p1_gfclk_parents[] = { + "init_60m_fclk", "xclk60mhsp1_ck", +}; + +DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH, + 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL); + +static const char *utmi_p2_gfclk_parents[] = { + "init_60m_fclk", "xclk60mhsp2_ck", +}; + +DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH, + 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", + &dpll_usb_m2_ck, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk", + &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk", + &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", + &dpll_usb_m2_ck, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const char *otg_60m_gfclk_parents[] = { + "utmi_phy_clkout_ck", "xclk60motg_ck", +}; + +DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT, + OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL); + +DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_ALWON_USBPHY_CLKCTRL, + OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +static const struct clk_div_table usim_ck_rates[] = { + { .div = 14, .val = 0 }, + { .div = 18, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, + OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH, + 0x0, usim_ck_rates, NULL); + +DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +/* Remaining optional clocks */ +static const char *pmd_stm_clock_mux_ck_parents[] = { + "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", +}; + +DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT, + OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT, + OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck", + &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT, + OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +static const char *trace_clk_div_ck_parents[] = { + "pmd_trace_clk_mux_ck", +}; + +static const struct clksel trace_clk_div_div[] = { + { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, +}; + +static struct clk trace_clk_div_ck; + +static const struct clk_ops trace_clk_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clkops_enable_clkdm, + .disable = &omap2_clkops_disable_clkdm, +}; + +static struct clk_hw_omap trace_clk_div_ck_hw = { + .hw = { + .clk = &trace_clk_div_ck, + }, + .clkdm_name = "emu_sys_clkdm", + .clksel = trace_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, +}; + +DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents, trace_clk_div_ck_ops); + +/* SCRM aux clk nodes */ + +static const struct clksel auxclk_src_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *auxclk_src_ck_parents[] = { + "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck", +}; + +static const struct clk_ops auxclk_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, +}; + +DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0, + OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0, + OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0, + OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0, + OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0, + OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0, + OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +static const char *auxclkreq_ck_parents[] = { + "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck", + "auxclk5_ck", +}; + +DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +/* + * clkdev + */ + +static struct omap_clk omap44xx_clks[] = { + CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), + CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), + CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), + CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), + CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), + CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), + CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), + CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), + CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), + CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), + CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), + CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), + CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), + CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), + CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), + CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), + CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), + CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), + CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), + CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), + CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), + CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), + CLK(NULL, "abe_clk", &abe_clk, CK_443X), + CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), + CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), + CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), + CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), + CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), + CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), + CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), + CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), + CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), + CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), + CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), + CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), + CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), + CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), + CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), + CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), + CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), + CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), + CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), + CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), + CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), + CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), + CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), + CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), + CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), + CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), + CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), + CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), + CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), + CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), + CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), + CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), + CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), + CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), + CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), + CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), + CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), + CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), + CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), + CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), + CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), + CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), + CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), + CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), + CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), + CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), + CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), + CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), + CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), + CLK(NULL, "aess_fck", &aess_fck, CK_443X), + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), + CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), + CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), + CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), + CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), + CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), + CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), + CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), + CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), + CLK(NULL, "dss_fck", &dss_fck, CK_443X), + CLK("omapdss_dss", "ick", &dss_fck, CK_443X), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), + CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), + CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), + CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), + CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), + CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), + CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), + CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), + CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), + CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), + CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), + CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), + CLK(NULL, "iss_fck", &iss_fck, CK_443X), + CLK(NULL, "iva_fck", &iva_fck, CK_443X), + CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), + CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), + CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), + CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), + CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), + CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), + CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), + CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), + CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), + CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), + CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), + CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), + CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), + CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), + CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), + CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), + CLK(NULL, "rng_ick", &rng_ick, CK_443X), + CLK("omap_rng", "ick", &rng_ick, CK_443X), + CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), + CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), + CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), + CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), + CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), + CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), + CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), + CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), + CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), + CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), + CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), + CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), + CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), + CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), + CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), + CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), + CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), + CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), + CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), + CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), + CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK(NULL, "usim_ck", &usim_ck, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), + CLK(NULL, "usim_fck", &usim_fck, CK_443X), + CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), + CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), + CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), + CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), + CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), + CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), + CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), + CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), + CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), + CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), + CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), + CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), + CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), + CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), + CLK("omap_wdt", "ick", &dummy_ck, CK_443X), + CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), + /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ + CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), +}; + +static const char *enable_init_clks[] = { + "emif1_fck", + "emif2_fck", + "gpmc_ick", + "l3_instr_ick", + "l3_main_3_ick", + "ocp_wp_noc_ick", +}; + +int __init omap4xxx_clk_init(void) +{ + u32 cpu_clkflg; + struct omap_clk *c; + + if (cpu_is_omap443x()) { + cpu_mask = RATE_IN_4430; + cpu_clkflg = CK_443X; + } else if (cpu_is_omap446x() || cpu_is_omap447x()) { + cpu_mask = RATE_IN_4460 | RATE_IN_4430; + cpu_clkflg = CK_446X | CK_443X; + + if (cpu_is_omap447x()) + pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); + } else { + return 0; + } + + for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); + c++) { + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + return 0; +} diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 1599f7b..6a72ab2 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -669,6 +669,7 @@ extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; +extern struct clk dummy_ck; #ifdef CONFIG_COMMON_CLK extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; @@ -701,6 +702,7 @@ extern const struct clkops clkops_omap4_dpllmx_ops; /* clksel_rate blocks shared between OMAP44xx and AM33xx */ extern const struct clksel_rate div_1_0_rates[]; +extern const struct clksel_rate div3_1to4_rates[]; extern const struct clksel_rate div_1_1_rates[]; extern const struct clksel_rate div_1_2_rates[]; extern const struct clksel_rate div_1_3_rates[]; diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 2a450c9..ef6d09e 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -275,13 +275,6 @@ static struct clk abe_24m_fclk = { .recalc = &omap_fixed_divisor_recalc, }; -static const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - static const struct clksel abe_clk_div[] = { { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, { .parent = NULL }, @@ -677,7 +670,6 @@ static struct dpll_data dpll_mpu_dd = { .min_divider = 1, }; - static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", .parent = &sys_clkin_ck, diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index b9f3ba6..c0d02a9 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -52,6 +52,13 @@ const struct clksel_rate div_1_0_rates[] = { { .div = 0 }, }; +const struct clksel_rate div3_1to4_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 4, .val = 2, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + const struct clksel_rate div_1_1_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, { .div = 0 }, @@ -108,6 +115,19 @@ const struct clksel_rate div31_1to31_rates[] = { }; /* Clocks shared between various OMAP SoCs */ +#ifdef CONFIG_COMMON_CLK + +#include <linux/clk-private.h> + +static struct clk_ops dummy_ck_ops = {}; + +struct clk dummy_ck = { + .name = "dummy_clk", + .ops = &dummy_ck_ops, + .flags = CLK_IS_BASIC, +}; + +#else struct clk virt_19200000_ck = { .name = "virt_19200000_ck", @@ -120,3 +140,5 @@ struct clk virt_26000000_ck = { .ops = &clkops_null, .rate = 26000000, }; + +#endif diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 721588f..f72dedb 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -29,6 +29,7 @@ #include <linux/clkdev.h> #include "soc.h" +#include "clockdomain.h" #include "clock.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" @@ -460,6 +461,17 @@ int omap3_noncore_dpll_enable(struct clk *clk) return -EINVAL; #ifdef CONFIG_COMMON_CLK + if (clk->clkdm) { + r = clkdm_clk_enable(clk->clkdm, hw->clk); + if (r) { + WARN(1, + "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, r); + return r; + } + } + parent = __clk_get_parent(hw->clk); if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { @@ -499,11 +511,17 @@ int omap3_noncore_dpll_enable(struct clk *clk) void omap3_noncore_dpll_disable(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + _omap3_noncore_dpll_stop(clk); + if (clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); #else void omap3_noncore_dpll_disable(struct clk *clk) { -#endif _omap3_noncore_dpll_stop(clk); + if (clk->clkdm) + clkdm_clk_disable(clk->clkdm, clk); +#endif } diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h index 701bf2d..e897ac8 100644 --- a/arch/arm/mach-omap2/scrm44xx.h +++ b/arch/arm/mach-omap2/scrm44xx.h @@ -127,12 +127,14 @@ /* AUXCLKREQ0 */ #define OMAP4_MAPPING_SHIFT 2 #define OMAP4_MAPPING_MASK (0x7 << 2) +#define OMAP4_MAPPING_WIDTH 3 #define OMAP4_ACCURACY_SHIFT 1 #define OMAP4_ACCURACY_MASK (1 << 1) /* AUXCLK0 */ #define OMAP4_CLKDIV_SHIFT 16 #define OMAP4_CLKDIV_MASK (0xf << 16) +#define OMAP4_CLKDIV_WIDTH 4 #define OMAP4_DISABLECLK_SHIFT 9 #define OMAP4_DISABLECLK_MASK (1 << 9) #define OMAP4_ENABLE_SHIFT 8 -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 12/26] ARM: OMAP4: clock: Add 44xx data using common struct clk 2012-11-08 1:12 ` [PATCH 12/26] ARM: OMAP4: clock: Add 44xx data using common struct clk Mike Turquette @ 2012-11-13 1:37 ` Paul Walmsley 2012-11-13 2:16 ` Paul Walmsley 0 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-13 1:37 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches This one missed the new omap-gpmc.fck alias added by commit a2e5b90b0879e42eee4bef49bd217661abc35ee6; updated patch follows. commit a2e5b90b0879e42eee4bef49bd217661abc35ee6 Author: Benoit Cousson <b-cousson@ti.com> Date: Tue Oct 16 11:19:17 2012 -0700 ARM: OMAP2+: clock data: Add dev-id for the omap-gpmc dummy fck - Paul From: Rajendra Nayak <rnayak@ti.com> Date: Tue, 6 Nov 2012 15:41:08 -0700 Subject: [PATCH] ARM: OMAP4: clock: Add 44xx data using common struct clk This patch is output from updated omap hw data autogeneration scripts mostly contributed by Mike Turquette, with some later fixes from me. All data is added into a new cclock44xx_data.c file which will be switched with clock44xx_data.c file in a later patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflowed macros; updated DEFINE_STRUCT_CLK_HW_OMAP macro to include clkdm_name; use macros for clksel mux+gate clocks; many other fixes] [mturquette@ti.com: converted DPLL outputs to HSDIVIDER macro; trace_clk_div_ck has clkdm ops] Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: fixed the omap-gpmc.fck alias per commit a2e5b90b] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/cclock44xx_data.c | 1991 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 2 + arch/arm/mach-omap2/clock44xx_data.c | 8 - arch/arm/mach-omap2/clock_common_data.c | 22 + arch/arm/mach-omap2/dpll3xxx.c | 20 +- arch/arm/mach-omap2/scrm44xx.h | 2 + 6 files changed, 2036 insertions(+), 9 deletions(-) create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c new file mode 100644 index 0000000..ff0424e --- /dev/null +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -0,0 +1,1991 @@ +/* + * OMAP4 Clock data + * + * Copyright (C) 2009-2012 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Mike Turquette (mturquette@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX Some of the ES1 clocks have been removed/changed; once support + * is added for discriminating clocks by ES level, these should be added back + * in. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-private.h> +#include <linux/clkdev.h> +#include <linux/io.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock44xx.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" +#include "cm-regbits-44xx.h" +#include "prm44xx.h" +#include "prm-regbits-44xx.h" +#include "control.h" +#include "scrm44xx.h" + +/* OMAP4 modulemode control */ +#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 +#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 + +/* Root clocks */ + +DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); + +DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT, + 0x0, NULL); + +DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT, + 0x0, NULL); + +DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); + +static const char *sys_clkin_ck_parents[] = { + "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck", + "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", + "virt_38400000_ck", +}; + +DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, + OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT, + OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); + +DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0); + +DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0); + +/* Module clocks and DPLL outputs */ + +static const char *abe_dpll_bypass_clk_mux_ck_parents[] = { + "sys_clkin_ck", "sys_32k_ck", +}; + +DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, + NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT, + OMAP4430_CLKSEL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +/* DPLL_ABE */ +static struct dpll_data dpll_abe_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, + .clk_bypass = &abe_dpll_bypass_clk_mux_ck, + .clk_ref = &abe_dpll_refclk_mux_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static const char *dpll_abe_ck_parents[] = { + "abe_dpll_refclk_mux_ck", +}; + +static struct clk dpll_abe_ck; + +static const struct clk_ops dpll_abe_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap4_dpll_regm4xen_recalc, + .round_rate = &omap4_dpll_regm4xen_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_abe_ck_hw = { + .hw = { + .clk = &dpll_abe_ck, + }, + .dpll_data = &dpll_abe_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_abe_x2_ck_parents[] = { + "dpll_abe_ck", +}; + +static struct clk dpll_abe_x2_ck; + +static const struct clk_ops dpll_abe_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll_abe_x2_ck_hw = { + .hw = { + .clk = &dpll_abe_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); + +static const struct clk_ops omap_hsdivider_ops = { + .set_rate = &omap2_clksel_set_rate, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, + 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, + 0x0, 1, 8); + +DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT, + OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, + OMAP4430_CLKSEL_AESS_FCLK_SHIFT, + OMAP4430_CLKSEL_AESS_FCLK_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, 0x0, + OMAP4430_CM_DIV_M3_DPLL_ABE, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK); + +static const char *core_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "dpll_abe_m3x2_ck", +}; + +DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE, + OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH, + 0x0, NULL); + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, + .clk_bypass = &core_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static const char *dpll_core_ck_parents[] = { + "sys_clkin_ck", +}; + +static struct clk dpll_core_ck; + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .hw = { + .clk = &dpll_core_ck, + }, + .dpll_data = &dpll_core_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); + +static const char *dpll_core_x2_ck_parents[] = { + "dpll_core_ck", +}; + +static struct clk dpll_core_x2_ck; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .hw = { + .clk = &dpll_core_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, + OMAP4430_CM_DIV_M6_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_CORE, OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1, + 2); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, + OMAP4430_CM_DIV_M5_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, + OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, + OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_MASK); + +DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, + 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, + OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, + OMAP4430_CM_DIV_M4_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, + 0x0, 1, 2); + +DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, + OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static const struct clk_ops dmic_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, + .init = &omap2_init_clk_clkdm, +}; + +static const char *dpll_core_m3x2_ck_parents[] = { + "dpll_core_x2_ck", +}; + +static const struct clksel dpll_core_m3x2_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +/* XXX Missing round_rate, set_rate in ops */ +DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, + OMAP4430_CM_DIV_M3_DPLL_CORE, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, + OMAP4430_CM_DIV_M3_DPLL_CORE, + OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, + dpll_core_m3x2_ck_parents, dmic_fck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, + OMAP4430_CM_DIV_M7_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); + +static const char *iva_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "div_iva_hs_clk", +}; + +DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, + OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); + +/* DPLL_IVA */ +static struct dpll_data dpll_iva_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, + .clk_bypass = &iva_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static struct clk dpll_iva_ck; + +static struct clk_hw_omap dpll_iva_ck_hw = { + .hw = { + .clk = &dpll_iva_ck, + }, + .dpll_data = &dpll_iva_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_iva_x2_ck_parents[] = { + "dpll_iva_ck", +}; + +static struct clk dpll_iva_x2_ck; + +static struct clk_hw_omap dpll_iva_x2_ck_hw = { + .hw = { + .clk = &dpll_iva_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, 0x0, + OMAP4430_CM_DIV_M4_DPLL_IVA, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, 0x0, + OMAP4430_CM_DIV_M5_DPLL_IVA, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, + .clk_bypass = &div_mpu_hs_clk, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static struct clk dpll_mpu_ck; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .hw = { + .clk = &dpll_mpu_ck, + }, + .dpll_data = &dpll_mpu_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_MPU, OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck", + &dpll_abe_m3x2_ck, 0x0, 1, 2); + +static const char *per_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "per_hs_clk_div_ck", +}; + +DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, + OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, + .clk_bypass = &per_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static struct clk dpll_per_ck; + +static struct clk_hw_omap dpll_per_ck_hw = { + .hw = { + .clk = &dpll_per_ck, + }, + .dpll_data = &dpll_per_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, + OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static const char *dpll_per_x2_ck_parents[] = { + "dpll_per_ck", +}; + +static struct clk dpll_per_x2_ck; + +static struct clk_hw_omap dpll_per_x2_ck_hw = { + .hw = { + .clk = &dpll_per_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_MASK); + +static const char *dpll_per_m3x2_ck_parents[] = { + "dpll_per_x2_ck", +}; + +static const struct clksel dpll_per_m3x2_div[] = { + { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +/* XXX Missing round_rate, set_rate in ops */ +DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, + OMAP4430_CM_DIV_M3_DPLL_PER, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, + OMAP4430_CM_DIV_M3_DPLL_PER, + OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, + dpll_per_m3x2_ck_parents, dmic_fck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M4_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M5_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M6_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, + OMAP4430_CM_DIV_M7_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck", + &dpll_abe_m3x2_ck, 0x0, 1, 3); + +/* DPLL_USB */ +static struct dpll_data dpll_usb_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, + .clk_bypass = &usb_hs_clk_div_ck, + .flags = DPLL_J_TYPE, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, + .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, + .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, + .max_multiplier = 4095, + .max_divider = 256, + .min_divider = 1, +}; + + +static struct clk dpll_usb_ck; + +static struct clk_hw_omap dpll_usb_ck_hw = { + .hw = { + .clk = &dpll_usb_ck, + }, + .dpll_data = &dpll_usb_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_usb_clkdcoldo_ck_parents[] = { + "dpll_usb_ck", +}; + +static struct clk dpll_usb_clkdcoldo_ck; + +static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = { +}; + +static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { + .hw = { + .clk = &dpll_usb_clkdcoldo_ck, + }, + .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents, + dpll_usb_clkdcoldo_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_USB, + OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK); + +static const char *ducati_clk_mux_ck_parents[] = { + "div_core_ck", "dpll_per_m6x2_ck", +}; + +DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 16); + +DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, + 1, 4); + +DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 8); + +static const struct clk_div_table func_48m_fclk_rates[] = { + { .div = 4, .val = 0 }, + { .div = 8, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates, + NULL); + +DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 4); + +static const struct clk_div_table func_64m_fclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 4, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates, + NULL); + +static const struct clk_div_table func_96m_fclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 4, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates, + NULL); + +static const struct clk_div_table init_60m_fclk_rates[] = { + { .div = 1, .val = 0 }, + { .div = 8, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, + 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ, + OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH, + 0x0, init_60m_fclk_rates, NULL); + +DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT, + OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT, + OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL); + +DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, + 0x0, 1, 16); + +static const char *l4_wkup_clk_mux_ck_parents[] = { + "sys_clkin_ck", "lp_clk_div_ck", +}; + +DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +static const struct clk_div_table ocp_abe_iclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 1, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, + OMAP4430_CLKSEL_AESS_FCLK_SHIFT, + OMAP4430_CLKSEL_AESS_FCLK_WIDTH, + 0x0, ocp_abe_iclk_rates, NULL); + +DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, + 0x0, 1, 4); + +DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, + OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +static struct clk dbgclk_mux_ck; +DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); +DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents, + dpll_usb_clkdcoldo_ck_ops); + +/* Leaf clocks controlled by modules */ + +DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_AES1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_AES2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); + +static const struct clk_div_table div_ts_ck_rates[] = { + { .div = 8, .val = 0 }, + { .div = 16, .val = 1 }, + { .div = 32, .val = 2 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4430_CLKSEL_24_25_SHIFT, + OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates, + NULL); + +DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, + OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +static const char *dmic_sync_mux_ck_parents[] = { + "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", +}; + +DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, + 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_dmic_abe_gfclk_sel[] = { + { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *dmic_fck_parents[] = { + "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_dmic_abe_gfclk into dmic */ +static struct clk dmic_fck; + +DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + dmic_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0, + OMAP4430_CM_TESLA_TESLA_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, + OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, + OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0, + OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0, + OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, + OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, + OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0, + OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO2_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO4_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO5_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO6_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +static const struct clksel sgx_clk_mux_sel[] = { + { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *gpu_fck_parents[] = { + "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", +}; + +/* Merged sgx_clk_mux into gpu */ +DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel, + OMAP4430_CM_GFX_GFX_CLKCTRL, + OMAP4430_CLKSEL_SGX_FCLK_MASK, + OMAP4430_CM_GFX_GFX_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + gpu_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0, + OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, + OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, + OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, + OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, + OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, + OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static struct clk l3_instr_ick; + +static const char *l3_instr_ick_parent_names[] = { + "l3_div_ck", +}; + +static const struct clk_ops l3_instr_ick_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap l3_instr_ick_hw = { + .hw = { + .clk = &l3_instr_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +static struct clk l3_main_3_ick; +static struct clk_hw_omap l3_main_3_ick_hw = { + .hw = { + .clk = &l3_main_3_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +#if 0 +DEFINE_CLK_GATE(l3_main_3_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); +#endif + +DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcasp_abe_gfclk_sel[] = { + { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcasp_fck_parents[] = { + "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcasp_abe_gfclk into mcasp */ +DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcasp_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp1_gfclk_sel[] = { + { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parents[] = { + "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp1_gfclk into mcbsp1 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp1_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp2_gfclk_sel[] = { + { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp2_fck_parents[] = { + "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp2_gfclk into mcbsp2 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp2_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp3_gfclk_sel[] = { + { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp3_fck_parents[] = { + "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp3_gfclk into mcbsp3 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp3_fck_parents, dmic_fck_ops); + +static const char *mcbsp4_sync_mux_ck_parents[] = { + "func_96m_fclk", "per_abe_nc_fclk", +}; + +DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel per_mcbsp4_gfclk_sel[] = { + { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp4_fck_parents[] = { + "mcbsp4_sync_mux_ck", "pad_clks_ck", +}; + +/* Merged per_mcbsp4_gfclk into mcbsp4 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_24_24_MASK, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp4_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0, + OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const struct clksel hsmmc1_fclk_sel[] = { + { .parent = &func_64m_fclk, .rates = div_1_0_rates }, + { .parent = &func_96m_fclk, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *mmc1_fck_parents[] = { + "func_64m_fclk", "func_96m_fclk", +}; + +/* Merged hsmmc1_fclk into mmc1 */ +DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mmc1_fck_parents, dmic_fck_ops); + +/* Merged hsmmc2_fclk into mmc2 */ +DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mmc1_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +static struct clk ocp_wp_noc_ick; + +static struct clk_hw_omap ocp_wp_noc_ick_hw = { + .hw = { + .clk = &ocp_wp_noc_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, + OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", + &pad_slimbus_core_clks_ck, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const struct clksel dmt1_clk_mux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +/* Merged dmt1_clk_mux into timer1 */ +DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm10_mux into timer10 */ +DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm11_mux into timer11 */ +DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm2_mux into timer2 */ +DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm3_mux into timer3 */ +DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm4_mux into timer4 */ +DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +static const struct clksel timer5_sync_mux_sel[] = { + { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *timer5_fck_parents[] = { + "syc_clk_div_ck", "sys_32k_ck", +}; + +/* Merged timer5_sync_mux into timer5 */ +DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer6_sync_mux into timer6 */ +DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer7_sync_mux into timer7 */ +DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer8_sync_mux into timer8 */ +DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged cm2_dm9_mux into timer9 */ +DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static struct clk usb_host_fs_fck; + +static const char *usb_host_fs_fck_parent_names[] = { + "func_48mc_fclk", +}; + +static const struct clk_ops usb_host_fs_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap usb_host_fs_fck_hw = { + .hw = { + .clk = &usb_host_fs_fck, + }, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, + .clkdm_name = "l3_init_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names, + usb_host_fs_fck_ops); + +static const char *utmi_p1_gfclk_parents[] = { + "init_60m_fclk", "xclk60mhsp1_ck", +}; + +DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH, + 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL); + +static const char *utmi_p2_gfclk_parents[] = { + "init_60m_fclk", "xclk60mhsp2_ck", +}; + +DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH, + 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", + &dpll_usb_m2_ck, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk", + &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk", + &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", + &dpll_usb_m2_ck, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const char *otg_60m_gfclk_parents[] = { + "utmi_phy_clkout_ck", "xclk60motg_ck", +}; + +DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT, + OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL); + +DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_ALWON_USBPHY_CLKCTRL, + OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +static const struct clk_div_table usim_ck_rates[] = { + { .div = 14, .val = 0 }, + { .div = 18, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, + OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH, + 0x0, usim_ck_rates, NULL); + +DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +/* Remaining optional clocks */ +static const char *pmd_stm_clock_mux_ck_parents[] = { + "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", +}; + +DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT, + OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT, + OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck", + &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT, + OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +static const char *trace_clk_div_ck_parents[] = { + "pmd_trace_clk_mux_ck", +}; + +static const struct clksel trace_clk_div_div[] = { + { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, +}; + +static struct clk trace_clk_div_ck; + +static const struct clk_ops trace_clk_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clkops_enable_clkdm, + .disable = &omap2_clkops_disable_clkdm, +}; + +static struct clk_hw_omap trace_clk_div_ck_hw = { + .hw = { + .clk = &trace_clk_div_ck, + }, + .clkdm_name = "emu_sys_clkdm", + .clksel = trace_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, +}; + +DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents, trace_clk_div_ck_ops); + +/* SCRM aux clk nodes */ + +static const struct clksel auxclk_src_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *auxclk_src_ck_parents[] = { + "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck", +}; + +static const struct clk_ops auxclk_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, +}; + +DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0, + OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0, + OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0, + OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0, + OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0, + OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0, + OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +static const char *auxclkreq_ck_parents[] = { + "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck", + "auxclk5_ck", +}; + +DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +/* + * clkdev + */ + +static struct omap_clk omap44xx_clks[] = { + CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), + CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), + CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), + CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), + CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), + CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), + CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), + CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), + CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), + CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), + CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), + CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), + CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), + CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), + CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), + CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), + CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), + CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), + CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), + CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), + CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), + CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), + CLK(NULL, "abe_clk", &abe_clk, CK_443X), + CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), + CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), + CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), + CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), + CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), + CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), + CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), + CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), + CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), + CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), + CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), + CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), + CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), + CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), + CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), + CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), + CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), + CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), + CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), + CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), + CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), + CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), + CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), + CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), + CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), + CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), + CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), + CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), + CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), + CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), + CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), + CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), + CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), + CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), + CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), + CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), + CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), + CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), + CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), + CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), + CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), + CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), + CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), + CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), + CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), + CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), + CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), + CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), + CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), + CLK(NULL, "aess_fck", &aess_fck, CK_443X), + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), + CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), + CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), + CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), + CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), + CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), + CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), + CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), + CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), + CLK(NULL, "dss_fck", &dss_fck, CK_443X), + CLK("omapdss_dss", "ick", &dss_fck, CK_443X), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), + CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), + CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), + CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), + CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), + CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), + CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), + CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), + CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), + CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), + CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), + CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), + CLK(NULL, "iss_fck", &iss_fck, CK_443X), + CLK(NULL, "iva_fck", &iva_fck, CK_443X), + CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), + CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), + CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), + CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), + CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), + CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), + CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), + CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), + CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), + CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), + CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), + CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), + CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), + CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), + CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), + CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), + CLK(NULL, "rng_ick", &rng_ick, CK_443X), + CLK("omap_rng", "ick", &rng_ick, CK_443X), + CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), + CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), + CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), + CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), + CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), + CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), + CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), + CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), + CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), + CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), + CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), + CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), + CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), + CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), + CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), + CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), + CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), + CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), + CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), + CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), + CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK(NULL, "usim_ck", &usim_ck, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), + CLK(NULL, "usim_fck", &usim_fck, CK_443X), + CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), + CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), + CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), + CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), + CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), + CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), + CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), + CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), + CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), + CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), + CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), + CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), + CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), + CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), + CLK("omap_wdt", "ick", &dummy_ck, CK_443X), + CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), + /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ + CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), +}; + +static const char *enable_init_clks[] = { + "emif1_fck", + "emif2_fck", + "gpmc_ick", + "l3_instr_ick", + "l3_main_3_ick", + "ocp_wp_noc_ick", +}; + +int __init omap4xxx_clk_init(void) +{ + u32 cpu_clkflg; + struct omap_clk *c; + + if (cpu_is_omap443x()) { + cpu_mask = RATE_IN_4430; + cpu_clkflg = CK_443X; + } else if (cpu_is_omap446x() || cpu_is_omap447x()) { + cpu_mask = RATE_IN_4460 | RATE_IN_4430; + cpu_clkflg = CK_446X | CK_443X; + + if (cpu_is_omap447x()) + pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); + } else { + return 0; + } + + for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); + c++) { + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + return 0; +} diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index ec63f01..e1aa9c5 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -641,6 +641,7 @@ extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; +extern struct clk dummy_ck; #ifdef CONFIG_COMMON_CLK extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; @@ -673,6 +674,7 @@ extern const struct clkops clkops_omap4_dpllmx_ops; /* clksel_rate blocks shared between OMAP44xx and AM33xx */ extern const struct clksel_rate div_1_0_rates[]; +extern const struct clksel_rate div3_1to4_rates[]; extern const struct clksel_rate div_1_1_rates[]; extern const struct clksel_rate div_1_2_rates[]; extern const struct clksel_rate div_1_3_rates[]; diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 2a450c9..ef6d09e 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -275,13 +275,6 @@ static struct clk abe_24m_fclk = { .recalc = &omap_fixed_divisor_recalc, }; -static const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - static const struct clksel abe_clk_div[] = { { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, { .parent = NULL }, @@ -677,7 +670,6 @@ static struct dpll_data dpll_mpu_dd = { .min_divider = 1, }; - static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", .parent = &sys_clkin_ck, diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index b9f3ba6..c0d02a9 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -52,6 +52,13 @@ const struct clksel_rate div_1_0_rates[] = { { .div = 0 }, }; +const struct clksel_rate div3_1to4_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 4, .val = 2, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + const struct clksel_rate div_1_1_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, { .div = 0 }, @@ -108,6 +115,19 @@ const struct clksel_rate div31_1to31_rates[] = { }; /* Clocks shared between various OMAP SoCs */ +#ifdef CONFIG_COMMON_CLK + +#include <linux/clk-private.h> + +static struct clk_ops dummy_ck_ops = {}; + +struct clk dummy_ck = { + .name = "dummy_clk", + .ops = &dummy_ck_ops, + .flags = CLK_IS_BASIC, +}; + +#else struct clk virt_19200000_ck = { .name = "virt_19200000_ck", @@ -120,3 +140,5 @@ struct clk virt_26000000_ck = { .ops = &clkops_null, .rate = 26000000, }; + +#endif diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 721588f..f72dedb 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -29,6 +29,7 @@ #include <linux/clkdev.h> #include "soc.h" +#include "clockdomain.h" #include "clock.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" @@ -460,6 +461,17 @@ int omap3_noncore_dpll_enable(struct clk *clk) return -EINVAL; #ifdef CONFIG_COMMON_CLK + if (clk->clkdm) { + r = clkdm_clk_enable(clk->clkdm, hw->clk); + if (r) { + WARN(1, + "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, r); + return r; + } + } + parent = __clk_get_parent(hw->clk); if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { @@ -499,11 +511,17 @@ int omap3_noncore_dpll_enable(struct clk *clk) void omap3_noncore_dpll_disable(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + _omap3_noncore_dpll_stop(clk); + if (clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); #else void omap3_noncore_dpll_disable(struct clk *clk) { -#endif _omap3_noncore_dpll_stop(clk); + if (clk->clkdm) + clkdm_clk_disable(clk->clkdm, clk); +#endif } diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h index 701bf2d..e897ac8 100644 --- a/arch/arm/mach-omap2/scrm44xx.h +++ b/arch/arm/mach-omap2/scrm44xx.h @@ -127,12 +127,14 @@ /* AUXCLKREQ0 */ #define OMAP4_MAPPING_SHIFT 2 #define OMAP4_MAPPING_MASK (0x7 << 2) +#define OMAP4_MAPPING_WIDTH 3 #define OMAP4_ACCURACY_SHIFT 1 #define OMAP4_ACCURACY_MASK (1 << 1) /* AUXCLK0 */ #define OMAP4_CLKDIV_SHIFT 16 #define OMAP4_CLKDIV_MASK (0xf << 16) +#define OMAP4_CLKDIV_WIDTH 4 #define OMAP4_DISABLECLK_SHIFT 9 #define OMAP4_DISABLECLK_MASK (1 << 9) #define OMAP4_ENABLE_SHIFT 8 -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 12/26] ARM: OMAP4: clock: Add 44xx data using common struct clk 2012-11-13 1:37 ` Paul Walmsley @ 2012-11-13 2:16 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-13 2:16 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches This patch included some code modifications to mach-omap2/dpll3xxx.c which belong in a different patch. So they've been moved to the 'ARM: OMAP4: clock: Convert to common clk' patch where the other dpll3xxx.c code modifications are. The patch also had some checkpatch issues that were previously lost in the storm of clkdev 80-column warnings and static const char * array warnings; these have been resolved. Updated patch follows. - Paul From: Rajendra Nayak <rnayak@ti.com> Date: Tue, 6 Nov 2012 15:41:08 -0700 Subject: [PATCH] ARM: OMAP4: clock: Add 44xx data using common struct clk This patch is output from updated omap hw data autogeneration scripts mostly contributed by Mike Turquette, with some later fixes from me. All data is added into a new cclock44xx_data.c file which will be switched with clock44xx_data.c file in a later patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflowed macros; updated DEFINE_STRUCT_CLK_HW_OMAP macro to include clkdm_name; use macros for clksel mux+gate clocks; many other fixes] [mturquette@ti.com: converted DPLL outputs to HSDIVIDER macro; trace_clk_div_ck has clkdm ops] Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: fixed the omap-gpmc.fck alias per commit a2e5b90b; fixed several checkpatch issues; moved the dpll3xxx.c clockdomain modifications to another patch] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/cclock44xx_data.c | 1987 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 2 + arch/arm/mach-omap2/clock44xx_data.c | 8 - arch/arm/mach-omap2/clock_common_data.c | 22 + arch/arm/mach-omap2/scrm44xx.h | 2 + 5 files changed, 2013 insertions(+), 8 deletions(-) create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c new file mode 100644 index 0000000..aa56c3e --- /dev/null +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -0,0 +1,1987 @@ +/* + * OMAP4 Clock data + * + * Copyright (C) 2009-2012 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Mike Turquette (mturquette@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX Some of the ES1 clocks have been removed/changed; once support + * is added for discriminating clocks by ES level, these should be added back + * in. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-private.h> +#include <linux/clkdev.h> +#include <linux/io.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock44xx.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" +#include "cm-regbits-44xx.h" +#include "prm44xx.h" +#include "prm-regbits-44xx.h" +#include "control.h" +#include "scrm44xx.h" + +/* OMAP4 modulemode control */ +#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 +#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 + +/* Root clocks */ + +DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); + +DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT, + 0x0, NULL); + +DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT, + 0x0, NULL); + +DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); + +static const char *sys_clkin_ck_parents[] = { + "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck", + "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", + "virt_38400000_ck", +}; + +DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, + OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT, + OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); + +DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0); + +DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0); + +/* Module clocks and DPLL outputs */ + +static const char *abe_dpll_bypass_clk_mux_ck_parents[] = { + "sys_clkin_ck", "sys_32k_ck", +}; + +DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, + NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT, + OMAP4430_CLKSEL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +/* DPLL_ABE */ +static struct dpll_data dpll_abe_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, + .clk_bypass = &abe_dpll_bypass_clk_mux_ck, + .clk_ref = &abe_dpll_refclk_mux_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static const char *dpll_abe_ck_parents[] = { + "abe_dpll_refclk_mux_ck", +}; + +static struct clk dpll_abe_ck; + +static const struct clk_ops dpll_abe_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap4_dpll_regm4xen_recalc, + .round_rate = &omap4_dpll_regm4xen_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_abe_ck_hw = { + .hw = { + .clk = &dpll_abe_ck, + }, + .dpll_data = &dpll_abe_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_abe_x2_ck_parents[] = { + "dpll_abe_ck", +}; + +static struct clk dpll_abe_x2_ck; + +static const struct clk_ops dpll_abe_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll_abe_x2_ck_hw = { + .hw = { + .clk = &dpll_abe_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); + +static const struct clk_ops omap_hsdivider_ops = { + .set_rate = &omap2_clksel_set_rate, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, + 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, + 0x0, 1, 8); + +DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT, + OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, + OMAP4430_CLKSEL_AESS_FCLK_SHIFT, + OMAP4430_CLKSEL_AESS_FCLK_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, + 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK); + +static const char *core_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "dpll_abe_m3x2_ck", +}; + +DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE, + OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH, + 0x0, NULL); + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, + .clk_bypass = &core_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static const char *dpll_core_ck_parents[] = { + "sys_clkin_ck", +}; + +static struct clk dpll_core_ck; + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .hw = { + .clk = &dpll_core_ck, + }, + .dpll_data = &dpll_core_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); + +static const char *dpll_core_x2_ck_parents[] = { + "dpll_core_ck", +}; + +static struct clk dpll_core_x2_ck; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .hw = { + .clk = &dpll_core_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck", + &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_CORE, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1, + 2); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck", + &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, + OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", + &dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, + OMAP4430_CLKSEL_0_1_MASK); + +DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, + 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, + OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck", + &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, + 0x0, 1, 2); + +DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, + OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static const struct clk_ops dmic_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, + .init = &omap2_init_clk_clkdm, +}; + +static const char *dpll_core_m3x2_ck_parents[] = { + "dpll_core_x2_ck", +}; + +static const struct clksel dpll_core_m3x2_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +/* XXX Missing round_rate, set_rate in ops */ +DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, + OMAP4430_CM_DIV_M3_DPLL_CORE, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, + OMAP4430_CM_DIV_M3_DPLL_CORE, + OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, + dpll_core_m3x2_ck_parents, dmic_fck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", + &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); + +static const char *iva_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "div_iva_hs_clk", +}; + +DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, + OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); + +/* DPLL_IVA */ +static struct dpll_data dpll_iva_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, + .clk_bypass = &iva_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +static struct clk dpll_iva_ck; + +static struct clk_hw_omap dpll_iva_ck_hw = { + .hw = { + .clk = &dpll_iva_ck, + }, + .dpll_data = &dpll_iva_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_iva_x2_ck_parents[] = { + "dpll_iva_ck", +}; + +static struct clk dpll_iva_x2_ck; + +static struct clk_hw_omap dpll_iva_x2_ck_hw = { + .hw = { + .clk = &dpll_iva_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, + 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, + 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, + .clk_bypass = &div_mpu_hs_clk, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +static struct clk dpll_mpu_ck; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .hw = { + .clk = &dpll_mpu_ck, + }, + .dpll_data = &dpll_mpu_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_MPU, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck", + &dpll_abe_m3x2_ck, 0x0, 1, 2); + +static const char *per_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "per_hs_clk_div_ck", +}; + +DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, + OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, + .clk_bypass = &per_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static struct clk dpll_per_ck; + +static struct clk_hw_omap dpll_per_ck_hw = { + .hw = { + .clk = &dpll_per_ck, + }, + .dpll_data = &dpll_per_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, + OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static const char *dpll_per_x2_ck_parents[] = { + "dpll_per_ck", +}; + +static struct clk dpll_per_x2_ck; + +static struct clk_hw_omap dpll_per_x2_ck_hw = { + .hw = { + .clk = &dpll_per_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M2_DPLL_PER, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +static const char *dpll_per_m3x2_ck_parents[] = { + "dpll_per_x2_ck", +}; + +static const struct clksel dpll_per_m3x2_div[] = { + { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +/* XXX Missing round_rate, set_rate in ops */ +DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, + OMAP4430_CM_DIV_M3_DPLL_PER, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, + OMAP4430_CM_DIV_M3_DPLL_PER, + OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, + dpll_per_m3x2_ck_parents, dmic_fck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M5_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M6_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M7_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck", + &dpll_abe_m3x2_ck, 0x0, 1, 3); + +/* DPLL_USB */ +static struct dpll_data dpll_usb_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, + .clk_bypass = &usb_hs_clk_div_ck, + .flags = DPLL_J_TYPE, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, + .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, + .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, + .max_multiplier = 4095, + .max_divider = 256, + .min_divider = 1, +}; + +static struct clk dpll_usb_ck; + +static struct clk_hw_omap dpll_usb_ck_hw = { + .hw = { + .clk = &dpll_usb_ck, + }, + .dpll_data = &dpll_usb_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_usb_clkdcoldo_ck_parents[] = { + "dpll_usb_ck", +}; + +static struct clk dpll_usb_clkdcoldo_ck; + +static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = { +}; + +static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { + .hw = { + .clk = &dpll_usb_clkdcoldo_ck, + }, + .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents, + dpll_usb_clkdcoldo_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_USB, + OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK); + +static const char *ducati_clk_mux_ck_parents[] = { + "div_core_ck", "dpll_per_m6x2_ck", +}; + +DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 16); + +DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, + 1, 4); + +DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 8); + +static const struct clk_div_table func_48m_fclk_rates[] = { + { .div = 4, .val = 0 }, + { .div = 8, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates, + NULL); + +DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 4); + +static const struct clk_div_table func_64m_fclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 4, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates, + NULL); + +static const struct clk_div_table func_96m_fclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 4, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates, + NULL); + +static const struct clk_div_table init_60m_fclk_rates[] = { + { .div = 1, .val = 0 }, + { .div = 8, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, + 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ, + OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH, + 0x0, init_60m_fclk_rates, NULL); + +DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT, + OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT, + OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL); + +DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, + 0x0, 1, 16); + +static const char *l4_wkup_clk_mux_ck_parents[] = { + "sys_clkin_ck", "lp_clk_div_ck", +}; + +DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +static const struct clk_div_table ocp_abe_iclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 1, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, + OMAP4430_CLKSEL_AESS_FCLK_SHIFT, + OMAP4430_CLKSEL_AESS_FCLK_WIDTH, + 0x0, ocp_abe_iclk_rates, NULL); + +DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, + 0x0, 1, 4); + +DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, + OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +static struct clk dbgclk_mux_ck; +DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); +DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents, + dpll_usb_clkdcoldo_ck_ops); + +/* Leaf clocks controlled by modules */ + +DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_AES1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_AES2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); + +static const struct clk_div_table div_ts_ck_rates[] = { + { .div = 8, .val = 0 }, + { .div = 16, .val = 1 }, + { .div = 32, .val = 2 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4430_CLKSEL_24_25_SHIFT, + OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates, + NULL); + +DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, + OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +static const char *dmic_sync_mux_ck_parents[] = { + "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", +}; + +DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, + 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_dmic_abe_gfclk_sel[] = { + { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *dmic_fck_parents[] = { + "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_dmic_abe_gfclk into dmic */ +static struct clk dmic_fck; + +DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + dmic_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0, + OMAP4430_CM_TESLA_TESLA_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, + OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, + OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0, + OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0, + OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, + OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, + OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0, + OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO2_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO4_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO5_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO6_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +static const struct clksel sgx_clk_mux_sel[] = { + { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *gpu_fck_parents[] = { + "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", +}; + +/* Merged sgx_clk_mux into gpu */ +DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel, + OMAP4430_CM_GFX_GFX_CLKCTRL, + OMAP4430_CLKSEL_SGX_FCLK_MASK, + OMAP4430_CM_GFX_GFX_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + gpu_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0, + OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, + OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, + OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, + OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, + OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, + OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static struct clk l3_instr_ick; + +static const char *l3_instr_ick_parent_names[] = { + "l3_div_ck", +}; + +static const struct clk_ops l3_instr_ick_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap l3_instr_ick_hw = { + .hw = { + .clk = &l3_instr_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +static struct clk l3_main_3_ick; +static struct clk_hw_omap l3_main_3_ick_hw = { + .hw = { + .clk = &l3_main_3_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcasp_abe_gfclk_sel[] = { + { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcasp_fck_parents[] = { + "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcasp_abe_gfclk into mcasp */ +DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcasp_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp1_gfclk_sel[] = { + { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parents[] = { + "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp1_gfclk into mcbsp1 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp1_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp2_gfclk_sel[] = { + { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp2_fck_parents[] = { + "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp2_gfclk into mcbsp2 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp2_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp3_gfclk_sel[] = { + { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp3_fck_parents[] = { + "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp3_gfclk into mcbsp3 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp3_fck_parents, dmic_fck_ops); + +static const char *mcbsp4_sync_mux_ck_parents[] = { + "func_96m_fclk", "per_abe_nc_fclk", +}; + +DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel per_mcbsp4_gfclk_sel[] = { + { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp4_fck_parents[] = { + "mcbsp4_sync_mux_ck", "pad_clks_ck", +}; + +/* Merged per_mcbsp4_gfclk into mcbsp4 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_24_24_MASK, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp4_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0, + OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const struct clksel hsmmc1_fclk_sel[] = { + { .parent = &func_64m_fclk, .rates = div_1_0_rates }, + { .parent = &func_96m_fclk, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *mmc1_fck_parents[] = { + "func_64m_fclk", "func_96m_fclk", +}; + +/* Merged hsmmc1_fclk into mmc1 */ +DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mmc1_fck_parents, dmic_fck_ops); + +/* Merged hsmmc2_fclk into mmc2 */ +DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mmc1_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +static struct clk ocp_wp_noc_ick; + +static struct clk_hw_omap ocp_wp_noc_ick_hw = { + .hw = { + .clk = &ocp_wp_noc_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, + OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", + &pad_slimbus_core_clks_ck, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const struct clksel dmt1_clk_mux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +/* Merged dmt1_clk_mux into timer1 */ +DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm10_mux into timer10 */ +DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm11_mux into timer11 */ +DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm2_mux into timer2 */ +DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm3_mux into timer3 */ +DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm4_mux into timer4 */ +DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +static const struct clksel timer5_sync_mux_sel[] = { + { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *timer5_fck_parents[] = { + "syc_clk_div_ck", "sys_32k_ck", +}; + +/* Merged timer5_sync_mux into timer5 */ +DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer6_sync_mux into timer6 */ +DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer7_sync_mux into timer7 */ +DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer8_sync_mux into timer8 */ +DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged cm2_dm9_mux into timer9 */ +DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static struct clk usb_host_fs_fck; + +static const char *usb_host_fs_fck_parent_names[] = { + "func_48mc_fclk", +}; + +static const struct clk_ops usb_host_fs_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap usb_host_fs_fck_hw = { + .hw = { + .clk = &usb_host_fs_fck, + }, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, + .clkdm_name = "l3_init_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names, + usb_host_fs_fck_ops); + +static const char *utmi_p1_gfclk_parents[] = { + "init_60m_fclk", "xclk60mhsp1_ck", +}; + +DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH, + 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL); + +static const char *utmi_p2_gfclk_parents[] = { + "init_60m_fclk", "xclk60mhsp2_ck", +}; + +DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH, + 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", + &dpll_usb_m2_ck, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk", + &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk", + &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", + &dpll_usb_m2_ck, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const char *otg_60m_gfclk_parents[] = { + "utmi_phy_clkout_ck", "xclk60motg_ck", +}; + +DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT, + OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL); + +DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_ALWON_USBPHY_CLKCTRL, + OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +static const struct clk_div_table usim_ck_rates[] = { + { .div = 14, .val = 0 }, + { .div = 18, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, + OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH, + 0x0, usim_ck_rates, NULL); + +DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +/* Remaining optional clocks */ +static const char *pmd_stm_clock_mux_ck_parents[] = { + "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", +}; + +DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT, + OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT, + OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck", + &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT, + OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +static const char *trace_clk_div_ck_parents[] = { + "pmd_trace_clk_mux_ck", +}; + +static const struct clksel trace_clk_div_div[] = { + { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, +}; + +static struct clk trace_clk_div_ck; + +static const struct clk_ops trace_clk_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clkops_enable_clkdm, + .disable = &omap2_clkops_disable_clkdm, +}; + +static struct clk_hw_omap trace_clk_div_ck_hw = { + .hw = { + .clk = &trace_clk_div_ck, + }, + .clkdm_name = "emu_sys_clkdm", + .clksel = trace_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, +}; + +DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents, + trace_clk_div_ck_ops); + +/* SCRM aux clk nodes */ + +static const struct clksel auxclk_src_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *auxclk_src_ck_parents[] = { + "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck", +}; + +static const struct clk_ops auxclk_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, +}; + +DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0, + OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0, + OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0, + OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0, + OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0, + OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0, + OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +static const char *auxclkreq_ck_parents[] = { + "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck", + "auxclk5_ck", +}; + +DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +/* + * clkdev + */ + +static struct omap_clk omap44xx_clks[] = { + CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), + CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), + CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), + CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), + CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), + CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), + CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), + CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), + CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), + CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), + CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), + CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), + CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), + CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), + CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), + CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), + CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), + CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), + CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), + CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), + CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), + CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), + CLK(NULL, "abe_clk", &abe_clk, CK_443X), + CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), + CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), + CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), + CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), + CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), + CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), + CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), + CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), + CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), + CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), + CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), + CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), + CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), + CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), + CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), + CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), + CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), + CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), + CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), + CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), + CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), + CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), + CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), + CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), + CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), + CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), + CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), + CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), + CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), + CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), + CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), + CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), + CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), + CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), + CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), + CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), + CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), + CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), + CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), + CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), + CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), + CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), + CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), + CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), + CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), + CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), + CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), + CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), + CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), + CLK(NULL, "aess_fck", &aess_fck, CK_443X), + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), + CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), + CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), + CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), + CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), + CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), + CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), + CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), + CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), + CLK(NULL, "dss_fck", &dss_fck, CK_443X), + CLK("omapdss_dss", "ick", &dss_fck, CK_443X), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), + CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), + CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), + CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), + CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), + CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), + CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), + CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), + CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), + CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), + CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), + CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), + CLK(NULL, "iss_fck", &iss_fck, CK_443X), + CLK(NULL, "iva_fck", &iva_fck, CK_443X), + CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), + CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), + CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), + CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), + CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), + CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), + CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), + CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), + CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), + CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), + CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), + CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), + CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), + CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), + CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), + CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), + CLK(NULL, "rng_ick", &rng_ick, CK_443X), + CLK("omap_rng", "ick", &rng_ick, CK_443X), + CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), + CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), + CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), + CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), + CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), + CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), + CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), + CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), + CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), + CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), + CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), + CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), + CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), + CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), + CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), + CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), + CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), + CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), + CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), + CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), + CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK(NULL, "usim_ck", &usim_ck, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), + CLK(NULL, "usim_fck", &usim_fck, CK_443X), + CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), + CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), + CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), + CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), + CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), + CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), + CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), + CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), + CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), + CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), + CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), + CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), + CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), + CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), + CLK("omap_wdt", "ick", &dummy_ck, CK_443X), + CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), + /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ + CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), +}; + +static const char *enable_init_clks[] = { + "emif1_fck", + "emif2_fck", + "gpmc_ick", + "l3_instr_ick", + "l3_main_3_ick", + "ocp_wp_noc_ick", +}; + +int __init omap4xxx_clk_init(void) +{ + u32 cpu_clkflg; + struct omap_clk *c; + + if (cpu_is_omap443x()) { + cpu_mask = RATE_IN_4430; + cpu_clkflg = CK_443X; + } else if (cpu_is_omap446x() || cpu_is_omap447x()) { + cpu_mask = RATE_IN_4460 | RATE_IN_4430; + cpu_clkflg = CK_446X | CK_443X; + + if (cpu_is_omap447x()) + pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); + } else { + return 0; + } + + for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); + c++) { + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + return 0; +} diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index ec63f01..e1aa9c5 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -641,6 +641,7 @@ extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; +extern struct clk dummy_ck; #ifdef CONFIG_COMMON_CLK extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; @@ -673,6 +674,7 @@ extern const struct clkops clkops_omap4_dpllmx_ops; /* clksel_rate blocks shared between OMAP44xx and AM33xx */ extern const struct clksel_rate div_1_0_rates[]; +extern const struct clksel_rate div3_1to4_rates[]; extern const struct clksel_rate div_1_1_rates[]; extern const struct clksel_rate div_1_2_rates[]; extern const struct clksel_rate div_1_3_rates[]; diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 2a450c9..ef6d09e 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -275,13 +275,6 @@ static struct clk abe_24m_fclk = { .recalc = &omap_fixed_divisor_recalc, }; -static const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - static const struct clksel abe_clk_div[] = { { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, { .parent = NULL }, @@ -677,7 +670,6 @@ static struct dpll_data dpll_mpu_dd = { .min_divider = 1, }; - static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", .parent = &sys_clkin_ck, diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index b9f3ba6..c0d02a9 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -52,6 +52,13 @@ const struct clksel_rate div_1_0_rates[] = { { .div = 0 }, }; +const struct clksel_rate div3_1to4_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 4, .val = 2, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + const struct clksel_rate div_1_1_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, { .div = 0 }, @@ -108,6 +115,19 @@ const struct clksel_rate div31_1to31_rates[] = { }; /* Clocks shared between various OMAP SoCs */ +#ifdef CONFIG_COMMON_CLK + +#include <linux/clk-private.h> + +static struct clk_ops dummy_ck_ops = {}; + +struct clk dummy_ck = { + .name = "dummy_clk", + .ops = &dummy_ck_ops, + .flags = CLK_IS_BASIC, +}; + +#else struct clk virt_19200000_ck = { .name = "virt_19200000_ck", @@ -120,3 +140,5 @@ struct clk virt_26000000_ck = { .ops = &clkops_null, .rate = 26000000, }; + +#endif diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h index 701bf2d..e897ac8 100644 --- a/arch/arm/mach-omap2/scrm44xx.h +++ b/arch/arm/mach-omap2/scrm44xx.h @@ -127,12 +127,14 @@ /* AUXCLKREQ0 */ #define OMAP4_MAPPING_SHIFT 2 #define OMAP4_MAPPING_MASK (0x7 << 2) +#define OMAP4_MAPPING_WIDTH 3 #define OMAP4_ACCURACY_SHIFT 1 #define OMAP4_ACCURACY_MASK (1 << 1) /* AUXCLK0 */ #define OMAP4_CLKDIV_SHIFT 16 #define OMAP4_CLKDIV_MASK (0xf << 16) +#define OMAP4_CLKDIV_WIDTH 4 #define OMAP4_DISABLECLK_SHIFT 9 #define OMAP4_DISABLECLK_MASK (1 << 9) #define OMAP4_ENABLE_SHIFT 8 -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 13/26] ARM: AM33XX: clock: add clock data in common clock format 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (11 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 12/26] ARM: OMAP4: clock: Add 44xx data using common struct clk Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 16/26] ARM: OMAP: clock: Switch to COMMON clk Mike Turquette ` (15 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul Cc: rnayak, linux-omap, linux-arm-kernel, patches, Vaibhav Hiremath, Benoit Cousson, Mike Turquette From: Paul Walmsley <paul@pwsan.com> OMAP2/3/4 clock-tree data is migrated to common-clock framework, so it is needed to do same for AM33XX device. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); modified to not use the AM33xx common clock data yet; updated patch description; reflowed the macros; updated DEFINE_STRUCT_CLK_HW_OMAP usage to include clkdm_name] Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/cclock33xx_data.c | 961 +++++++++++++++++++++++++++++++++ 1 file changed, 961 insertions(+) create mode 100644 arch/arm/mach-omap2/cclock33xx_data.c diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c new file mode 100644 index 0000000..ea64ad6 --- /dev/null +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -0,0 +1,961 @@ +/* + * AM33XX Clock data + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-private.h> +#include <linux/clkdev.h> +#include <linux/io.h> + +#include "am33xx.h" +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "control.h" +#include "cm.h" +#include "cm33xx.h" +#include "cm-regbits-33xx.h" +#include "prm.h" + +/* Modulemode control */ +#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0 +#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1 + +/*LIST_HEAD(clocks);*/ + +/* Root clocks */ + +/* RTC 32k */ +DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0); + +/* On-Chip 32KHz RC OSC */ +DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0); + +/* Crystal input clks */ +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); + +/* Oscillator clock */ +/* 19.2, 24, 25 or 26 MHz */ +static const char *sys_clkin_ck_parents[] = { + "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck", + "virt_26000000_ck", +}; + +/* + * sys_clk in: input to the dpll and also used as funtional clock for, + * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse + * + */ +DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, + AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), + AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT, + AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH, + 0, NULL); + +/* External clock - 12 MHz */ +DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0); + +/* Module clocks and DPLL outputs */ + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +/* CLKDCOLDO output */ +static const char *dpll_core_ck_parents[] = { + "sys_clkin_ck", +}; + +static struct clk dpll_core_ck; + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .hw = { + .clk = &dpll_core_ck, + }, + .dpll_data = &dpll_core_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); + +static const char *dpll_core_x2_ck_parents[] = { + "dpll_core_ck", +}; + +static struct clk dpll_core_x2_ck; + +static const struct clk_ops dpll_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .hw = { + .clk = &dpll_core_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, +}; + +DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops); + +DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, + 0x0, AM33XX_CM_DIV_M4_DPLL_CORE, + AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT, + AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, + NULL); + +DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, + 0x0, AM33XX_CM_DIV_M5_DPLL_CORE, + AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT, + AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, + 0x0, AM33XX_CM_DIV_M6_DPLL_CORE, + AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT, + AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_mpu_ck; + +static const struct clk_ops dpll_mpu_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .hw = { + .clk = &dpll_mpu_ck, + }, + .dpll_data = &dpll_mpu_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops); + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, + 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT, + AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +/* DPLL_DDR */ +static struct dpll_data dpll_ddr_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_ddr_ck; + +static const struct clk_ops dpll_ddr_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +static struct clk_hw_omap dpll_ddr_ck_hw = { + .hw = { + .clk = &dpll_ddr_ck, + }, + .dpll_data = &dpll_ddr_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, + 0x0, AM33XX_CM_DIV_M2_DPLL_DDR, + AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +/* emif_fck functional clock */ +DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, + 0x0, 1, 2); + +/* DPLL_DISP */ +static struct dpll_data dpll_disp_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_disp_ck; + +static struct clk_hw_omap dpll_disp_ck_hw = { + .hw = { + .clk = &dpll_disp_ck, + }, + .dpll_data = &dpll_disp_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0, + AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT, + AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, + .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, + .div1_mask = AM33XX_DPLL_PER_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .flags = DPLL_J_TYPE, +}; + +/* CLKDCOLDO */ +static struct clk dpll_per_ck; + +static struct clk_hw_omap dpll_per_ck_hw = { + .hw = { + .clk = &dpll_per_ck, + }, + .dpll_data = &dpll_per_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); + +/* CLKOUT: fdpll/M2 */ +DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, + AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT, + AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, + NULL); + +DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck", + &dpll_per_m2_ck, 0x0, 1, 4); + +DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck", + &dpll_per_m2_ck, 0x0, 1, 4); + +DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck", + &dpll_core_m4_ck, 0x0, 1, 2); + +DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, + 1, 2); + +DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, + 8); + +/* + * Below clock nodes describes clockdomains derived out + * of core clock. + */ +static const struct clk_ops clk_ops_null = { +}; + +static const char *l3_gclk_parents[] = { + "dpll_core_m4_ck" +}; + +static struct clk l3_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL); +DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null); + +static struct clk l4hs_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL); +DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null); + +static const char *l3s_gclk_parents[] = { + "dpll_core_m4_div2_ck" +}; + +static struct clk l3s_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL); +DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null); + +static struct clk l4fw_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL); +DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null); + +static struct clk l4ls_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL); +DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null); + +static struct clk sysclk_div_ck; +DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL); +DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null); + +/* + * In order to match the clock domain with hwmod clockdomain entry, + * separate clock nodes is required for the modules which are + * directly getting their funtioncal clock from sys_clkin. + */ +static struct clk adc_tsc_fck; +DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL); +DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk dcan0_fck; +DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL); +DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk dcan1_fck; +DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL); +DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk mcasp0_fck; +DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL); +DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk mcasp1_fck; +DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL); +DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk smartreflex0_fck; +DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL); +DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk smartreflex1_fck; +DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); +DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); + +/* + * Modules clock nodes + * + * The following clock leaf nodes are added for the moment because: + * + * - hwmod data is not present for these modules, either hwmod + * control is not required or its not populated. + * - Driver code is not yet migrated to use hwmod/runtime pm + * - Modules outside kernel access (to disable them by default) + * + * - debugss + * - mmu (gfx domain) + * - cefuse + * - usbotg_fck (its additional clock and not really a modulemode) + * - ieee5000 + */ +DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, + AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, + AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +/* + * clkdiv32 is generated from fixed division of 732.4219 + */ +DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732); + +DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0, + AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +/* "usbotg_fck" is an additional clock and not really a modulemode */ +DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0, + AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, + 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL, + AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +/* Timers */ +static const struct clksel timer1_clkmux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, + { .parent = &tclkin_ck, .rates = div_1_2_rates }, + { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, + { .parent = &clk_32768_ck, .rates = div_1_4_rates }, + { .parent = NULL }, +}; + +static const char *timer1_ck_parents[] = { + "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck", + "clk_32768_ck", +}; + +static struct clk timer1_fck; + +static const struct clk_ops timer1_fck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap timer1_fck_hw = { + .hw = { + .clk = &timer1_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer1_clkmux_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, + .clksel_mask = AM33XX_CLKSEL_0_2_MASK, +}; + +DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops); + +static const struct clksel timer2_to_7_clk_sel[] = { + { .parent = &tclkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *timer2_to_7_ck_parents[] = { + "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick", +}; + +static struct clk timer2_fck; + +static struct clk_hw_omap timer2_fck_hw = { + .hw = { + .clk = &timer2_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer3_fck; + +static struct clk_hw_omap timer3_fck_hw = { + .hw = { + .clk = &timer3_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer4_fck; + +static struct clk_hw_omap timer4_fck_hw = { + .hw = { + .clk = &timer4_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer5_fck; + +static struct clk_hw_omap timer5_fck_hw = { + .hw = { + .clk = &timer5_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer6_fck; + +static struct clk_hw_omap timer6_fck_hw = { + .hw = { + .clk = &timer6_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer7_fck; + +static struct clk_hw_omap timer7_fck_hw = { + .hw = { + .clk = &timer7_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk, + "dpll_core_m5_ck", + &dpll_core_m5_ck, + 0x0, + 1, 2); + +static const struct clk_ops cpsw_fck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { + { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *cpsw_cpts_rft_ck_parents[] = { + "dpll_core_m5_ck", "dpll_core_m4_ck", +}; + +static struct clk cpsw_cpts_rft_clk; + +static struct clk_hw_omap cpsw_cpts_rft_clk_hw = { + .hw = { + .clk = &cpsw_cpts_rft_clk, + }, + .clkdm_name = "cpsw_125mhz_clkdm", + .clksel = cpsw_cpts_rft_clkmux_sel, + .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, +}; + +DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops); + + +/* gpio */ +static const char *gpio0_ck_parents[] = { + "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick", +}; + +static const struct clksel gpio0_dbclk_mux_sel[] = { + { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, + { .parent = &clk_32768_ck, .rates = div_1_1_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const struct clk_ops gpio_fck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk gpio0_dbclk_mux_ck; + +static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = { + .hw = { + .clk = &gpio0_dbclk_mux_ck, + }, + .clkdm_name = "l4_wkup_clkdm", + .clksel = gpio0_dbclk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops); + +DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0, + AM33XX_CM_WKUP_GPIO0_CLKCTRL, + AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, + AM33XX_CM_PER_GPIO1_CLKCTRL, + AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, + AM33XX_CM_PER_GPIO2_CLKCTRL, + AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, + AM33XX_CM_PER_GPIO3_CLKCTRL, + AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL); + + +static const char *pruss_ck_parents[] = { + "l3_gclk", "dpll_disp_m2_ck", +}; + +static const struct clksel pruss_ocp_clk_mux_sel[] = { + { .parent = &l3_gclk, .rates = div_1_0_rates }, + { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk pruss_ocp_gclk; + +static struct clk_hw_omap pruss_ocp_gclk_hw = { + .hw = { + .clk = &pruss_ocp_gclk, + }, + .clkdm_name = "pruss_ocp_clkdm", + .clksel = pruss_ocp_clk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, +}; + +DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops); + +static const char *lcd_ck_parents[] = { + "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck", +}; + +static const struct clksel lcd_clk_mux_sel[] = { + { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk lcd_gclk; + +static struct clk_hw_omap lcd_gclk_hw = { + .hw = { + .clk = &lcd_gclk, + }, + .clkdm_name = "lcdc_clkdm", + .clksel = lcd_clk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops); + +DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2); + +static const char *gfx_ck_parents[] = { + "dpll_core_m4_ck", "dpll_per_m2_ck", +}; + +static const struct clksel gfx_clksel_sel[] = { + { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk gfx_fclk_clksel_ck; + +static struct clk_hw_omap gfx_fclk_clksel_ck_hw = { + .hw = { + .clk = &gfx_fclk_clksel_ck, + }, + .clksel = gfx_clksel_sel, + .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, + .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, +}; + +DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops); + +static const struct clk_div_table div_1_0_2_1_rates[] = { + { .div = 1, .val = 0, }, + { .div = 2, .val = 1, }, + { .div = 0 }, +}; + +DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck", + &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK, + AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH, + 0x0, div_1_0_2_1_rates, NULL); + +static const char *sysclkout_ck_parents[] = { + "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck", + "lcd_gclk", +}; + +static const struct clksel sysclkout_pre_sel[] = { + { .parent = &clk_32768_ck, .rates = div_1_0_rates }, + { .parent = &l3_gclk, .rates = div_1_1_rates }, + { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, + { .parent = &lcd_gclk, .rates = div_1_4_rates }, + { .parent = NULL }, +}; + +static struct clk sysclkout_pre_ck; + +static struct clk_hw_omap sysclkout_pre_ck_hw = { + .hw = { + .clk = &sysclkout_pre_ck, + }, + .clksel = sysclkout_pre_sel, + .clksel_reg = AM33XX_CM_CLKOUT_CTRL, + .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, +}; + +DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops); + +/* Divide by 8 clock rates with default clock is 1/1*/ +static const struct clk_div_table div8_rates[] = { + { .div = 1, .val = 0, }, + { .div = 2, .val = 1, }, + { .div = 3, .val = 2, }, + { .div = 4, .val = 3, }, + { .div = 5, .val = 4, }, + { .div = 6, .val = 5, }, + { .div = 7, .val = 6, }, + { .div = 8, .val = 7, }, + { .div = 0 }, +}; + +DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck, + 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT, + AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL); + +DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0, + AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL); + +static const char *wdt_ck_parents[] = { + "clk_rc32k_ck", "clkdiv32k_ick", +}; + +static const struct clksel wdt_clkmux_sel[] = { + { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk wdt1_fck; + +static struct clk_hw_omap wdt1_fck_hw = { + .hw = { + .clk = &wdt1_fck, + }, + .clkdm_name = "l4_wkup_clkdm", + .clksel = wdt_clkmux_sel, + .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); + +/* + * clkdev + */ +static struct omap_clk am33xx_clks[] = { + CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), + CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), + CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), + CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), + CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), + CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), + CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), + CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), + CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), + CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), + CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX), + CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), + CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), + CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), + CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), + CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), + CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), + CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), + CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), + CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), + CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), + CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), + CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), + CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), + CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), + CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), + CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), + CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), + CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), + CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), + CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), + CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), + CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), + CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), + CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), + CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), + CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), + CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), + CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), + CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), + CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), + CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), + CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), + CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), + CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), + CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), + CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), + CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), + CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), + CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), + CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), + CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), + CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), + CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), +}; + + +static const char *enable_init_clks[] = { + "dpll_ddr_m2_ck", + "dpll_mpu_m2_ck", + "l3_gclk", + "l4hs_gclk", + "l4fw_gclk", + "l4ls_gclk", +}; + +int __init am33xx_clk_init(void) +{ + struct omap_clk *c; + u32 cpu_clkflg; + + if (soc_is_am33xx()) { + cpu_mask = RATE_IN_AM33XX; + cpu_clkflg = CK_AM33XX; + } + + for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always + * physically present, in such a case HWMOD enabling of + * clock would be failure with default parent. And timer + * probe thinks clock is already enabled, this leads to + * crash upon accessing timer 3 & 6 registers in probe. + * Fix by setting parent of both these timers to master + * oscillator clock. + */ + + clk_set_parent(&timer3_fck, &sys_clkin_ck); + clk_set_parent(&timer6_fck, &sys_clkin_ck); + + return 0; +} -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 16/26] ARM: OMAP: clock: Switch to COMMON clk 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (12 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 13/26] ARM: AM33XX: clock: add clock data in common clock format Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 17/26] ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette ` (14 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Select COMMON_CLK for all OMAP2+ SoCs and switch over to using new data files for OMAP2/3/4. The older data files will get removed in subsequent patches. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: move 'select COMMON_CLK' from ARCH_OMAP2PLUS_TYPICAL to the per-SoC and per-"arch" Kconfig sections] Signed-off-by: Mike Turquette <mturquette@ti.com> [mturquette@ti.com: fixed up #ifdef mismatch in clock.h in previous patch which drops that change from this patch] --- arch/arm/mach-omap2/Kconfig | 5 +++++ arch/arm/mach-omap2/Makefile | 10 +++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 2a1a898..98268fa 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -35,6 +35,7 @@ config ARCH_OMAP2 select CPU_V6 select MULTI_IRQ_HANDLER select SOC_HAS_OMAP2_SDRC + select COMMON_CLK config ARCH_OMAP3 bool "TI OMAP3" @@ -48,6 +49,7 @@ config ARCH_OMAP3 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select SOC_HAS_OMAP2_SDRC + select COMMON_CLK select USB_ARCH_HAS_EHCI if USB_SUPPORT config ARCH_OMAP4 @@ -69,6 +71,7 @@ config ARCH_OMAP4 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select USB_ARCH_HAS_EHCI if USB_SUPPORT + select COMMON_CLK config SOC_OMAP5 bool "TI OMAP5" @@ -78,6 +81,7 @@ config SOC_OMAP5 select CPU_V7 select HAVE_SMP select SOC_HAS_REALTIME_COUNTER + select COMMON_CLK comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -112,6 +116,7 @@ config SOC_AM33XX select ARM_CPU_SUSPEND if PM select CPU_V7 select MULTI_IRQ_HANDLER + select COMMON_CLK config OMAP_PACKAGE_ZAF bool diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ae87a3e..f8dbf0c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -153,17 +153,17 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o -obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o -obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o +obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o +obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o -obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o -obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o +obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 17/26] ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (13 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 16/26] ARM: OMAP: clock: Switch to COMMON clk Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 18/26] ARM: OMAP4: clock: " Mike Turquette ` (13 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Clean all #ifdef's added as part of fixing the clkdm accesses from hwmod. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/omap_hwmod.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 22a41f6..25052d6 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -130,11 +130,7 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/io.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/delay.h> #include <linux/err.h> #include <linux/list.h> @@ -623,17 +619,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) struct clockdomain *_get_clkdm(struct omap_hwmod *oh) { + struct clk_hw_omap *clk; + if (oh->clkdm) { return oh->clkdm; } else if (oh->_clk) { -#ifdef CONFIG_COMMON_CLK - struct clk_hw_omap *clk; - clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); return clk->clkdm; -#else - return oh->_clk->clkdm; -#endif } return NULL; } @@ -3590,9 +3582,7 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) struct clk *c; struct omap_hwmod_ocp_if *oi; struct clockdomain *clkdm; -#ifdef CONFIG_COMMON_CLK struct clk_hw_omap *clk; -#endif if (!oh) return NULL; @@ -3609,12 +3599,8 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) c = oi->_clk; } -#ifdef CONFIG_COMMON_CLK clk = to_clk_hw_omap(__clk_get_hw(c)); clkdm = clk->clkdm; -#else - clkdm = c->clkdm; -#endif if (!clkdm) return NULL; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 18/26] ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (14 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 17/26] ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 20/26] ARM: omap3: " Mike Turquette ` (12 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Clean all #ifdef's added to OMAP4 clock code to make it COMMON clk ready, now that CONFIG_COMMON_CLK is enabled. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/dpll44xx.c | 33 --------------------------------- arch/arm/mach-omap2/io.c | 2 -- 2 files changed, 35 deletions(-) diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index aa75a3c..d3326c4 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -21,11 +21,7 @@ #include "cm-regbits-44xx.h" /* Supported only on OMAP4 */ -#ifdef CONFIG_COMMON_CLK int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) -#else -int omap4_dpllmx_gatectrl_read(struct clk *clk) -#endif { u32 v; u32 mask; @@ -44,11 +40,7 @@ int omap4_dpllmx_gatectrl_read(struct clk *clk) return v; } -#ifdef CONFIG_COMMON_CLK void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) -#else -void omap4_dpllmx_allow_gatectrl(struct clk *clk) -#endif { u32 v; u32 mask; @@ -66,11 +58,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } -#ifdef CONFIG_COMMON_CLK void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) -#else -void omap4_dpllmx_deny_gatectrl(struct clk *clk) -#endif { u32 v; u32 mask; @@ -88,17 +76,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { .allow_idle = omap4_dpllmx_allow_gatectrl, .deny_idle = omap4_dpllmx_deny_gatectrl, }; -#else -const struct clkops clkops_omap4_dpllmx_ops = { - .allow_idle = omap4_dpllmx_allow_gatectrl, - .deny_idle = omap4_dpllmx_deny_gatectrl, -}; -#endif /** * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit @@ -109,15 +90,10 @@ const struct clkops clkops_omap4_dpllmx_ops = { * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) * upon success, or 0 upon error. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) -{ -#endif u32 v; unsigned long rate; struct dpll_data *dd; @@ -149,16 +125,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or * ~0 if an error occurred in omap2_dpll_round_rate(). */ -#ifdef CONFIG_COMMON_CLK long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) -{ -#endif u32 v; struct dpll_data *dd; long r; @@ -174,11 +145,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) if (v) target_rate = target_rate / OMAP4430_REGM4XEN_MULT; -#ifdef CONFIG_COMMON_CLK r = omap2_dpll_round_rate(hw, target_rate, NULL); -#else - r = omap2_dpll_round_rate(clk, target_rate); -#endif if (r == ~0) return r; diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a62010e..e6192cb 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -574,9 +574,7 @@ void __init omap4430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap4_pm_init(); -#ifdef CONFIG_COMMON_CLK omap2_clk_enable_autoidle_all(); -#endif } #endif -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 20/26] ARM: omap3: clock: Cleanup !CONFIG_COMMON_CLK parts 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (15 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 18/26] ARM: OMAP4: clock: " Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 22/26] ARM: AM33xx: clock: drop obsolete clock data Mike Turquette ` (11 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Clean all #ifdef's added to OMAP3 clock code to make it COMMON clk ready, not that CONFIG_COMMON_CLK is enabled. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 13 ------ arch/arm/mach-omap2/clock.h | 16 -------- arch/arm/mach-omap2/clock34xx.c | 68 +------------------------------- arch/arm/mach-omap2/clock3517.c | 35 +--------------- arch/arm/mach-omap2/clock36xx.c | 19 --------- arch/arm/mach-omap2/clock36xx.h | 4 -- arch/arm/mach-omap2/clock3xxx.c | 8 ---- arch/arm/mach-omap2/clock3xxx.h | 5 --- 8 files changed, 3 insertions(+), 165 deletions(-) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index aeaaa87..8e48c6d 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -45,15 +45,10 @@ * Program the DPLL M2 divider with the rounded target rate. Returns * -EINVAL upon error, or 0 upon success. */ -#ifdef CONFIG_COMMON_CLK int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) -{ -#endif u32 new_div = 0; u32 unlock_dll = 0; u32 c; @@ -71,11 +66,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; sdrcrate = __clk_get_rate(sdrc_ick_p); -#ifdef CONFIG_COMMON_CLK clkrate = __clk_get_rate(hw->clk); -#else - clkrate = __clk_get_rate(clk); -#endif if (rate > clkrate) sdrcrate <<= ((rate / clkrate) >> 1); else @@ -124,10 +115,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); -#ifndef CONFIG_COMMON_CLK - clk->rate = rate; -#endif - return 0; } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 6a72ab2..a3e9067 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -586,13 +586,8 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); #endif /* clkt_iclk.c public functions */ -#ifdef CONFIG_COMMON_CLK extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -#else -extern void omap2_clkt_iclk_allow_idle(struct clk *clk); -extern void omap2_clkt_iclk_deny_idle(struct clk *clk); -#endif #ifdef CONFIG_COMMON_CLK u8 omap2_init_dpll_parent(struct clk_hw *hw); @@ -671,7 +666,6 @@ extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; extern struct clk dummy_ck; -#ifdef CONFIG_COMMON_CLK extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; @@ -689,16 +683,6 @@ extern const struct clk_hw_omap_ops clkhwops_apll54; extern const struct clk_hw_omap_ops clkhwops_apll96; extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; -#else -extern const struct clkops clkops_omap2_iclk_dflt_wait; -extern const struct clkops clkops_omap2_iclk_dflt; -extern const struct clkops clkops_omap2_iclk_idle_only; -extern const struct clkops clkops_omap2_mdmclk_dflt_wait; -extern const struct clkops clkops_omap2xxx_dpll_ops; -extern const struct clkops clkops_omap3_noncore_dpll_ops; -extern const struct clkops clkops_omap3_core_dpll_ops; -extern const struct clkops clkops_omap4_dpllmx_ops; -#endif /* CONFIG_COMMON_CLK */ /* clksel_rate blocks shared between OMAP44xx and AM33xx */ extern const struct clksel_rate div_1_0_rates[]; diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index b398a46..4596468 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -37,11 +37,7 @@ * from the CM_{I,F}CLKEN bit. Pass back the correct info via * @idlest_reg and @idlest_bit. No return value. */ -#ifdef CONFIG_COMMON_CLK static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, -#else -static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, -#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -53,7 +49,6 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait = { .find_idlest = omap3430es2_clk_ssi_find_idlest, .find_companion = omap2_clk_dflt_find_companion, @@ -65,23 +60,6 @@ const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = { .find_idlest = omap3430es2_clk_ssi_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_omap3430es2_ssi_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clkops clkops_omap3430es2_iclk_ssi_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -#endif /** * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST @@ -97,11 +75,7 @@ const struct clkops clkops_omap3430es2_iclk_ssi_wait = { * default find_idlest code assumes that they are at the same * position.) No return value. */ -#ifdef CONFIG_COMMON_CLK static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, -#else -static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, -#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -114,7 +88,7 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } -#ifdef CONFIG_COMMON_CLK + const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = { .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, .find_companion = omap2_clk_dflt_find_companion, @@ -126,23 +100,6 @@ const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = { .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_omap3430es2_dss_usbhost_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -#endif /** * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB @@ -155,11 +112,7 @@ const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = { * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via * @idlest_reg and @idlest_bit. No return value. */ -#ifdef CONFIG_COMMON_CLK static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, -#else -static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, -#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -171,7 +124,7 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } -#ifdef CONFIG_COMMON_CLK + const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, @@ -183,20 +136,3 @@ const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = { .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_omap3430es2_hsotgusb_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -#endif diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c index 467d8bc..4d79ae2 100644 --- a/arch/arm/mach-omap2/clock3517.c +++ b/arch/arm/mach-omap2/clock3517.c @@ -47,11 +47,7 @@ * in the enable register itsel at a bit offset of 4 from the enable * bit. A value of 1 indicates that clock is enabled. */ -#ifdef CONFIG_COMMON_CLK static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, -#else -static void am35xx_clk_find_idlest(struct clk *clk, -#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -75,13 +71,8 @@ static void am35xx_clk_find_idlest(struct clk *clk, * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -#ifdef CONFIG_COMMON_CLK static void am35xx_clk_find_companion(struct clk_hw_omap *clk, void __iomem **other_reg, -#else -static void am35xx_clk_find_companion(struct clk *clk, - void __iomem **other_reg, -#endif u8 *other_bit) { *other_reg = (__force void __iomem *)(clk->enable_reg); @@ -90,19 +81,10 @@ static void am35xx_clk_find_companion(struct clk *clk, else *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; } -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { .find_idlest = am35xx_clk_find_idlest, .find_companion = am35xx_clk_find_companion, }; -#else -const struct clkops clkops_am35xx_ipss_module_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = am35xx_clk_find_idlest, - .find_companion = am35xx_clk_find_companion, -}; -#endif /** * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS @@ -115,11 +97,7 @@ const struct clkops clkops_am35xx_ipss_module_wait = { * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg * and @idlest_bit. No return value. */ -#ifdef CONFIG_COMMON_CLK static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, -#else -static void am35xx_clk_ipss_find_idlest(struct clk *clk, -#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -131,21 +109,10 @@ static void am35xx_clk_ipss_find_idlest(struct clk *clk, *idlest_bit = AM35XX_ST_IPSS_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } -#ifdef CONFIG_COMMON_CLK + const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, .find_idlest = am35xx_clk_ipss_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_am35xx_ipss_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = am35xx_clk_ipss_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -#endif - diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index 9f50e97..8f3bf4e 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -37,28 +37,18 @@ * (Any other value different from the Read value) to the * corresponding CM_CLKSEL register will refresh the dividers. */ -#ifdef CONFIG_COMMON_CLK int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) { struct clk_hw_omap *parent; struct clk_hw *parent_hw; -#else -static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) -{ - struct clk *parent; -#endif u32 dummy_v, orig_v, clksel_shift; int ret; /* Clear PWRDN bit of HSDIVIDER */ ret = omap2_dflt_clk_enable(clk); -#ifdef CONFIG_COMMON_CLK parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); parent = to_clk_hw_omap(parent_hw); -#else - parent = clk->parent; -#endif /* Restore the dividers */ if (!ret) { @@ -76,12 +66,3 @@ static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) return ret; } - -#ifndef CONFIG_COMMON_CLK -const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = { - .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -}; -#endif diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h index e6a748e..945bb7f 100644 --- a/arch/arm/mach-omap2/clock36xx.h +++ b/arch/arm/mach-omap2/clock36xx.h @@ -8,10 +8,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H -#ifdef CONFIG_COMMON_CLK extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw); -#else -extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; -#endif #endif diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index a6f75cd..4eacab8 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -38,12 +38,8 @@ /* needed by omap3_core_dpll_m2_set_rate() */ struct clk *sdrc_ick_p, *arm_fck_p; -#ifdef CONFIG_COMMON_CLK int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) -#else -int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) -#endif { /* * According to the 12-5 CDP code from TI, "Limitation 2.5" @@ -55,11 +51,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; } -#ifdef CONFIG_COMMON_CLK return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); -#else - return omap3_noncore_dpll_set_rate(clk, rate); -#endif } void __init omap3_clk_lock_dpll5(void) diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 87f098d..8cd4b0a 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -9,15 +9,10 @@ #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H int omap3xxx_clk_init(void); -#ifdef CONFIG_COMMON_CLK int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); -#else -int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); -#endif void omap3_clk_lock_dpll5(void); extern struct clk *sdrc_ick_p; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 22/26] ARM: AM33xx: clock: drop obsolete clock data 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (16 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 20/26] ARM: omap3: " Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:12 ` [PATCH 23/26] ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette ` (10 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Paul Walmsley <paul@pwsan.com> Drop the now-obsolete AM33xx original OMAP clock data. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clock33xx_data.c | 1107 ---------------------------------- 1 file changed, 1107 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock33xx_data.c diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c deleted file mode 100644 index 1cb79cc..0000000 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ /dev/null @@ -1,1107 +0,0 @@ -/* - * AM33XX Clock data - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath <hvaibhav@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/clk.h> - -#include "soc.h" -#include "iomap.h" -#include "control.h" -#include "clock.h" -#include "cm.h" -#include "cm33xx.h" -#include "cm-regbits-33xx.h" -#include "prm.h" - -/* Maximum DPLL multiplier, divider values for AM33XX */ -#define AM33XX_MAX_DPLL_MULT 2047 -#define AM33XX_MAX_DPLL_DIV 128 - -/* Modulemode control */ -#define AM33XX_MODULEMODE_HWCTRL 0 -#define AM33XX_MODULEMODE_SWCTRL 1 - -/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always - * physically present, in such a case HWMOD enabling of - * clock would be failure with default parent. And timer - * probe thinks clock is already enabled, this leads to - * crash upon accessing timer 3 & 6 registers in probe. - * Fix by setting parent of both these timers to master - * oscillator clock. - */ -static inline void am33xx_init_timer_parent(struct clk *clk) -{ - omap2_clksel_set_parent(clk, clk->parent); -} - -/* Root clocks */ - -/* RTC 32k */ -static struct clk clk_32768_ck = { - .name = "clk_32768_ck", - .clkdm_name = "l4_rtc_clkdm", - .rate = 32768, - .ops = &clkops_null, -}; - -/* On-Chip 32KHz RC OSC */ -static struct clk clk_rc32k_ck = { - .name = "clk_rc32k_ck", - .rate = 32000, - .ops = &clkops_null, -}; - -/* Crystal input clks */ -static struct clk virt_24000000_ck = { - .name = "virt_24000000_ck", - .rate = 24000000, - .ops = &clkops_null, -}; - -static struct clk virt_25000000_ck = { - .name = "virt_25000000_ck", - .rate = 25000000, - .ops = &clkops_null, -}; - -/* Oscillator clock */ -/* 19.2, 24, 25 or 26 MHz */ -static const struct clksel sys_clkin_sel[] = { - { .parent = &virt_19200000_ck, .rates = div_1_0_rates }, - { .parent = &virt_24000000_ck, .rates = div_1_1_rates }, - { .parent = &virt_25000000_ck, .rates = div_1_2_rates }, - { .parent = &virt_26000000_ck, .rates = div_1_3_rates }, - { .parent = NULL }, -}; - -/* External clock - 12 MHz */ -static struct clk tclkin_ck = { - .name = "tclkin_ck", - .rate = 12000000, - .ops = &clkops_null, -}; - -/* - * sys_clk in: input to the dpll and also used as funtional clock for, - * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse - * - */ -static struct clk sys_clkin_ck = { - .name = "sys_clkin_ck", - .parent = &virt_24000000_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), - .clksel_mask = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK, - .clksel = sys_clkin_sel, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, -}; - -/* CLKDCOLDO output */ -static struct clk dpll_core_ck = { - .name = "dpll_core_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_core_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_core_dpll_ops, - .recalc = &omap3_dpll_recalc, -}; - -static struct clk dpll_core_x2_ck = { - .name = "dpll_core_x2_ck", - .parent = &dpll_core_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; - - -static const struct clksel dpll_core_m4_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m4_ck = { - .name = "dpll_core_m4_ck", - .parent = &dpll_core_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel = dpll_core_m4_div, - .clksel_reg = AM33XX_CM_DIV_M4_DPLL_CORE, - .clksel_mask = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel dpll_core_m5_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m5_ck = { - .name = "dpll_core_m5_ck", - .parent = &dpll_core_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel = dpll_core_m5_div, - .clksel_reg = AM33XX_CM_DIV_M5_DPLL_CORE, - .clksel_mask = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel dpll_core_m6_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m6_ck = { - .name = "dpll_core_m6_ck", - .parent = &dpll_core_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel = dpll_core_m6_div, - .clksel_reg = AM33XX_CM_DIV_M6_DPLL_CORE, - .clksel_mask = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_mpu_ck = { - .name = "dpll_mpu_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_mpu_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -static const struct clksel dpll_mpu_m2_div[] = { - { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_mpu_m2_ck = { - .name = "dpll_mpu_m2_ck", - .clkdm_name = "mpu_clkdm", - .parent = &dpll_mpu_ck, - .clksel = dpll_mpu_m2_div, - .clksel_reg = AM33XX_CM_DIV_M2_DPLL_MPU, - .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* DPLL_DDR */ -static struct dpll_data dpll_ddr_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_ddr_ck = { - .name = "dpll_ddr_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_ddr_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_null, - .recalc = &omap3_dpll_recalc, -}; - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -static const struct clksel dpll_ddr_m2_div[] = { - { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_ddr_m2_ck = { - .name = "dpll_ddr_m2_ck", - .parent = &dpll_ddr_ck, - .clksel = dpll_ddr_m2_div, - .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DDR, - .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* emif_fck functional clock */ -static struct clk dpll_ddr_m2_div2_ck = { - .name = "dpll_ddr_m2_div2_ck", - .clkdm_name = "l3_clkdm", - .parent = &dpll_ddr_m2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -/* DPLL_DISP */ -static struct dpll_data dpll_disp_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_disp_ck = { - .name = "dpll_disp_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_disp_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_null, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -static const struct clksel dpll_disp_m2_div[] = { - { .parent = &dpll_disp_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_disp_m2_ck = { - .name = "dpll_disp_m2_ck", - .parent = &dpll_disp_ck, - .clksel = dpll_disp_m2_div, - .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DISP, - .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, - .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, - .div1_mask = AM33XX_DPLL_PER_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, - .flags = DPLL_J_TYPE, -}; - -/* CLKDCOLDO */ -static struct clk dpll_per_ck = { - .name = "dpll_per_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_per_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_null, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -/* CLKOUT: fdpll/M2 */ -static const struct clksel dpll_per_m2_div[] = { - { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_per_m2_ck = { - .name = "dpll_per_m2_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = AM33XX_CM_DIV_M2_DPLL_PER, - .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m2_div4_wkupdm_ck = { - .name = "dpll_per_m2_div4_wkupdm_ck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &dpll_per_m2_ck, - .fixed_div = 4, - .ops = &clkops_null, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk dpll_per_m2_div4_ck = { - .name = "dpll_per_m2_div4_ck", - .clkdm_name = "l4ls_clkdm", - .parent = &dpll_per_m2_ck, - .fixed_div = 4, - .ops = &clkops_null, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk l3_gclk = { - .name = "l3_gclk", - .clkdm_name = "l3_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk dpll_core_m4_div2_ck = { - .name = "dpll_core_m4_div2_ck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk l4_rtc_gclk = { - .name = "l4_rtc_gclk", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk clk_24mhz = { - .name = "clk_24mhz", - .parent = &dpll_per_m2_ck, - .fixed_div = 8, - .ops = &clkops_null, - .recalc = &omap_fixed_divisor_recalc, -}; - -/* - * Below clock nodes describes clockdomains derived out - * of core clock. - */ -static struct clk l4hs_gclk = { - .name = "l4hs_gclk", - .clkdm_name = "l4hs_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk l3s_gclk = { - .name = "l3s_gclk", - .clkdm_name = "l3s_clkdm", - .parent = &dpll_core_m4_div2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk l4fw_gclk = { - .name = "l4fw_gclk", - .clkdm_name = "l4fw_clkdm", - .parent = &dpll_core_m4_div2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk l4ls_gclk = { - .name = "l4ls_gclk", - .clkdm_name = "l4ls_clkdm", - .parent = &dpll_core_m4_div2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk sysclk_div_ck = { - .name = "sysclk_div_ck", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -/* - * In order to match the clock domain with hwmod clockdomain entry, - * separate clock nodes is required for the modules which are - * directly getting their funtioncal clock from sys_clkin. - */ -static struct clk adc_tsc_fck = { - .name = "adc_tsc_fck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk dcan0_fck = { - .name = "dcan0_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk dcan1_fck = { - .name = "dcan1_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk mcasp0_fck = { - .name = "mcasp0_fck", - .clkdm_name = "l3s_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk mcasp1_fck = { - .name = "mcasp1_fck", - .clkdm_name = "l3s_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex0_fck = { - .name = "smartreflex0_fck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex1_fck = { - .name = "smartreflex1_fck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -/* - * Modules clock nodes - * - * The following clock leaf nodes are added for the moment because: - * - * - hwmod data is not present for these modules, either hwmod - * control is not required or its not populated. - * - Driver code is not yet migrated to use hwmod/runtime pm - * - Modules outside kernel access (to disable them by default) - * - * - debugss - * - mmu (gfx domain) - * - cefuse - * - usbotg_fck (its additional clock and not really a modulemode) - * - ieee5000 - */ -static struct clk debugss_ick = { - .name = "debugss_ick", - .clkdm_name = "l3_aon_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_omap2_dflt, - .enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .recalc = &followparent_recalc, -}; - -static struct clk mmu_fck = { - .name = "mmu_fck", - .clkdm_name = "gfx_l3_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_omap2_dflt, - .enable_reg = AM33XX_CM_GFX_MMUDATA_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .recalc = &followparent_recalc, -}; - -static struct clk cefuse_fck = { - .name = "cefuse_fck", - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, - .enable_reg = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -/* - * clkdiv32 is generated from fixed division of 732.4219 - */ -static struct clk clkdiv32k_ick = { - .name = "clkdiv32k_ick", - .clkdm_name = "clk_24mhz_clkdm", - .rate = 32768, - .parent = &clk_24mhz, - .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .ops = &clkops_omap2_dflt, -}; - -static struct clk usbotg_fck = { - .name = "usbotg_fck", - .clkdm_name = "l3s_clkdm", - .parent = &dpll_per_ck, - .enable_reg = AM33XX_CM_CLKDCOLDO_DPLL_PER, - .enable_bit = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static struct clk ieee5000_fck = { - .name = "ieee5000_fck", - .clkdm_name = "l3s_clkdm", - .parent = &dpll_core_m4_div2_ck, - .enable_reg = AM33XX_CM_PER_IEEE5000_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -/* Timers */ -static const struct clksel timer1_clkmux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, - { .parent = &tclkin_ck, .rates = div_1_2_rates }, - { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, - { .parent = &clk_32768_ck, .rates = div_1_4_rates }, - { .parent = NULL }, -}; - -static struct clk timer1_fck = { - .name = "timer1_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer1_clkmux_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, - .clksel_mask = AM33XX_CLKSEL_0_2_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel timer2_to_7_clk_sel[] = { - { .parent = &tclkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk timer2_fck = { - .name = "timer2_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer3_fck = { - .name = "timer3_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &am33xx_init_timer_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer4_fck = { - .name = "timer4_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer5_fck = { - .name = "timer5_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer6_fck = { - .name = "timer6_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &am33xx_init_timer_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer7_fck = { - .name = "timer7_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk cpsw_125mhz_gclk = { - .name = "cpsw_125mhz_gclk", - .clkdm_name = "cpsw_125mhz_clkdm", - .parent = &dpll_core_m5_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { - { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk cpsw_cpts_rft_clk = { - .name = "cpsw_cpts_rft_clk", - .clkdm_name = "cpsw_125mhz_clkdm", - .parent = &dpll_core_m5_ck, - .clksel = cpsw_cpts_rft_clkmux_sel, - .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -/* gpio */ -static const struct clksel gpio0_dbclk_mux_sel[] = { - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, - { .parent = &clk_32768_ck, .rates = div_1_1_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk gpio0_dbclk_mux_ck = { - .name = "gpio0_dbclk_mux_ck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &clk_rc32k_ck, - .init = &omap2_init_clksel_parent, - .clksel = gpio0_dbclk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpio0_dbclk = { - .name = "gpio0_dbclk", - .clkdm_name = "l4_wkup_clkdm", - .parent = &gpio0_dbclk_mux_ck, - .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL, - .enable_bit = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_dbclk = { - .name = "gpio1_dbclk", - .clkdm_name = "l4ls_clkdm", - .parent = &clkdiv32k_ick, - .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL, - .enable_bit = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_dbclk = { - .name = "gpio2_dbclk", - .clkdm_name = "l4ls_clkdm", - .parent = &clkdiv32k_ick, - .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL, - .enable_bit = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_dbclk = { - .name = "gpio3_dbclk", - .clkdm_name = "l4ls_clkdm", - .parent = &clkdiv32k_ick, - .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL, - .enable_bit = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static const struct clksel pruss_ocp_clk_mux_sel[] = { - { .parent = &l3_gclk, .rates = div_1_0_rates }, - { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk pruss_ocp_gclk = { - .name = "pruss_ocp_gclk", - .clkdm_name = "pruss_ocp_clkdm", - .parent = &l3_gclk, - .init = &omap2_init_clksel_parent, - .clksel = pruss_ocp_clk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static const struct clksel lcd_clk_mux_sel[] = { - { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk lcd_gclk = { - .name = "lcd_gclk", - .clkdm_name = "lcdc_clkdm", - .parent = &dpll_disp_m2_ck, - .init = &omap2_init_clksel_parent, - .clksel = lcd_clk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk mmc_clk = { - .name = "mmc_clk", - .clkdm_name = "l4ls_clkdm", - .parent = &dpll_per_m2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk mmc2_fck = { - .name = "mmc2_fck", - .clkdm_name = "l3s_clkdm", - .parent = &mmc_clk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static const struct clksel gfx_clksel_sel[] = { - { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk gfx_fclk_clksel_ck = { - .name = "gfx_fclk_clksel_ck", - .parent = &dpll_core_m4_ck, - .clksel = gfx_clksel_sel, - .ops = &clkops_null, - .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, - .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate div_1_0_2_1_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_AM33XX }, - { .div = 2, .val = 1, .flags = RATE_IN_AM33XX }, - { .div = 0 }, -}; - -static const struct clksel gfx_div_sel[] = { - { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates }, - { .parent = NULL }, -}; - -static struct clk gfx_fck_div_ck = { - .name = "gfx_fck_div_ck", - .clkdm_name = "gfx_l3_clkdm", - .parent = &gfx_fclk_clksel_ck, - .init = &omap2_init_clksel_parent, - .clksel = gfx_div_sel, - .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .ops = &clkops_null, -}; - -static const struct clksel sysclkout_pre_sel[] = { - { .parent = &clk_32768_ck, .rates = div_1_0_rates }, - { .parent = &l3_gclk, .rates = div_1_1_rates }, - { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, - { .parent = &lcd_gclk, .rates = div_1_4_rates }, - { .parent = NULL }, -}; - -static struct clk sysclkout_pre_ck = { - .name = "sysclkout_pre_ck", - .parent = &clk_32768_ck, - .init = &omap2_init_clksel_parent, - .clksel = sysclkout_pre_sel, - .clksel_reg = AM33XX_CM_CLKOUT_CTRL, - .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* Divide by 8 clock rates with default clock is 1/1*/ -static const struct clksel_rate div8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_AM33XX }, - { .div = 2, .val = 1, .flags = RATE_IN_AM33XX }, - { .div = 3, .val = 2, .flags = RATE_IN_AM33XX }, - { .div = 4, .val = 3, .flags = RATE_IN_AM33XX }, - { .div = 5, .val = 4, .flags = RATE_IN_AM33XX }, - { .div = 6, .val = 5, .flags = RATE_IN_AM33XX }, - { .div = 7, .val = 6, .flags = RATE_IN_AM33XX }, - { .div = 8, .val = 7, .flags = RATE_IN_AM33XX }, - { .div = 0 }, -}; - -static const struct clksel clkout2_div[] = { - { .parent = &sysclkout_pre_ck, .rates = div8_rates }, - { .parent = NULL }, -}; - -static struct clk clkout2_ck = { - .name = "clkout2_ck", - .parent = &sysclkout_pre_ck, - .ops = &clkops_omap2_dflt, - .clksel = clkout2_div, - .clksel_reg = AM33XX_CM_CLKOUT_CTRL, - .clksel_mask = AM33XX_CLKOUT2DIV_MASK, - .enable_reg = AM33XX_CM_CLKOUT_CTRL, - .enable_bit = AM33XX_CLKOUT2EN_SHIFT, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel wdt_clkmux_sel[] = { - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk wdt1_fck = { - .name = "wdt1_fck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &clk_rc32k_ck, - .init = &omap2_init_clksel_parent, - .clksel = wdt_clkmux_sel, - .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* - * clkdev - */ -static struct omap_clk am33xx_clks[] = { - CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), - CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), - CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), - CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), - CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), - CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), - CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), - CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), - CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), - CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), - CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), - CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), - CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), - CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), - CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), - CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), - CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), - CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), - CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX), - CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX), - CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), - CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), - CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX), - CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), - CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), - CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), - CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), - CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), - CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), - CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), - CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), - CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), - CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), - CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), - CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), - CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), - CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), - CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), - CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), - CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), - CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), - CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), - CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), - CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), - CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), - CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), - CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), - CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), - CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), - CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), - CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), - CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), - CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), - CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), - CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX), -}; - -int __init am33xx_clk_init(void) -{ - struct omap_clk *c; - u32 cpu_clkflg; - - if (soc_is_am33xx()) { - cpu_mask = RATE_IN_AM33XX; - cpu_clkflg = CK_AM33XX; - } - - for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) - clk_preinit(c->lk.clk); - - for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } - } - - recalculate_root_clocks(); - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - return 0; -} -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 23/26] ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (17 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 22/26] ARM: AM33xx: clock: drop obsolete clock data Mike Turquette @ 2012-11-08 1:12 ` Mike Turquette 2012-11-08 1:13 ` [PATCH 25/26] ARM: OMAP2+: clock: remove unnecessary declarations Mike Turquette ` (9 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:12 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette From: Rajendra Nayak <rnayak@ti.com> Clean all #ifdef's added to OMAP2 clock code to make it COMMON clk ready, not that CONFIG_COMMON_CLK is enabled. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: also drop CONFIG_COMMON_CLK tests around APLL recalc_rate functions] Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clkt2xxx_apll.c | 58 -------------------------- arch/arm/mach-omap2/clkt2xxx_dpll.c | 16 ------- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 18 -------- arch/arm/mach-omap2/clkt2xxx_osc.c | 20 --------- arch/arm/mach-omap2/clkt2xxx_sys.c | 8 ---- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 16 ------- arch/arm/mach-omap2/clock2430.c | 13 ------ arch/arm/mach-omap2/clock2xxx.h | 19 --------- arch/arm/mach-omap2/pm24xx.c | 8 ---- 9 files changed, 176 deletions(-) diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index d8a850b..225da8a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -41,7 +41,6 @@ void __iomem *cm_idlest_pll; /* Private functions */ -#ifdef CONFIG_COMMON_CLK /** * omap2xxx_clk_apll_locked - is the APLL locked? * @hw: struct clk_hw * of the APLL to check @@ -60,17 +59,11 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) return ((r & apll_mask) == apll_mask) ? true : false; } -#endif /* Enable an APLL if off */ -#ifdef CONFIG_COMMON_CLK static int omap2_clk_apll_enable(struct clk_hw *hw, u32 status_mask) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) -{ -#endif u32 cval, apll_mask; apll_mask = EN_APLL_LOCKED << clk->enable_bit; @@ -85,11 +78,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_wait_idlest(cm_idlest_pll, status_mask, -#ifdef CONFIG_COMMON_CLK OMAP24XX_CM_IDLEST_VAL, __clk_get_name(hw->clk)); -#else - OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk)); -#endif /* * REVISIT: Should we return an error code if omap2_wait_clock_ready() @@ -98,69 +87,40 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) return 0; } -#ifdef CONFIG_COMMON_CLK int omap2_clk_apll96_enable(struct clk_hw *clk) -#else -static int omap2_clk_apll96_enable(struct clk *clk) -#endif { return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK); } -#ifdef CONFIG_COMMON_CLK int omap2_clk_apll54_enable(struct clk_hw *clk) -#else -static int omap2_clk_apll54_enable(struct clk *clk) -#endif { return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK); } -#ifdef CONFIG_COMMON_CLK void _apll96_allow_idle(struct clk_hw_omap *clk) -#else -static void _apll96_allow_idle(struct clk *clk) -#endif { omap2xxx_cm_set_apll96_auto_low_power_stop(); } -#ifdef CONFIG_COMMON_CLK void _apll96_deny_idle(struct clk_hw_omap *clk) -#else -static void _apll96_deny_idle(struct clk *clk) -#endif { omap2xxx_cm_set_apll96_disable_autoidle(); } -#ifdef CONFIG_COMMON_CLK void _apll54_allow_idle(struct clk_hw_omap *clk) -#else -static void _apll54_allow_idle(struct clk *clk) -#endif { omap2xxx_cm_set_apll54_auto_low_power_stop(); } -#ifdef CONFIG_COMMON_CLK void _apll54_deny_idle(struct clk_hw_omap *clk) -#else -static void _apll54_deny_idle(struct clk *clk) -#endif { omap2xxx_cm_set_apll54_disable_autoidle(); } /* Stop APLL */ -#ifdef CONFIG_COMMON_CLK void omap2_clk_apll_disable(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -static void omap2_clk_apll_disable(struct clk *clk) -{ -#endif u32 cval; cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); @@ -168,7 +128,6 @@ static void omap2_clk_apll_disable(struct clk *clk) omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); } -#ifdef CONFIG_COMMON_CLK unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, unsigned long parent_rate) { @@ -180,10 +139,8 @@ unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, { return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0; } -#endif /* Public data */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_apll54 = { .allow_idle = _apll54_allow_idle, .deny_idle = _apll54_deny_idle, @@ -193,21 +150,6 @@ const struct clk_hw_omap_ops clkhwops_apll96 = { .allow_idle = _apll96_allow_idle, .deny_idle = _apll96_deny_idle, }; -#else -const struct clkops clkops_apll96 = { - .enable = omap2_clk_apll96_enable, - .disable = omap2_clk_apll_disable, - .allow_idle = _apll96_allow_idle, - .deny_idle = _apll96_deny_idle, -}; - -const struct clkops clkops_apll54 = { - .enable = omap2_clk_apll54_enable, - .disable = omap2_clk_apll_disable, - .allow_idle = _apll54_allow_idle, - .deny_idle = _apll54_deny_idle, -}; -#endif /* Public functions */ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index bbbf032..58931c4 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -29,11 +29,7 @@ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 * instead. Add some mechanism to optionally enter this mode. */ -#ifdef CONFIG_COMMON_CLK void _allow_idle(struct clk_hw_omap *clk) -#else -static void _allow_idle(struct clk *clk) -#endif { if (!clk || !clk->dpll_data) return; @@ -47,11 +43,7 @@ static void _allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ -#ifdef CONFIG_COMMON_CLK void _deny_idle(struct clk_hw_omap *clk) -#else -static void _deny_idle(struct clk *clk) -#endif { if (!clk || !clk->dpll_data) return; @@ -61,15 +53,7 @@ static void _deny_idle(struct clk *clk) /* Public data */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = { .allow_idle = _allow_idle, .deny_idle = _deny_idle, }; -#else -const struct clkops clkops_omap2xxx_dpll_ops = { - .allow_idle = _allow_idle, - .deny_idle = _deny_idle, -}; -#endif - diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index fb26e2f..54be803 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -46,11 +46,7 @@ * struct clk *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap2xxx_clk_get_core_rate(struct clk_hw_omap *clk) -#else -unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) -#endif { long long core_clk; u32 v; @@ -101,37 +97,23 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } -#ifdef CONFIG_COMMON_CLK unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -unsigned long omap2_dpllcore_recalc(struct clk *clk) -{ -#endif return omap2xxx_clk_get_core_rate(clk); } -#ifdef CONFIG_COMMON_CLK int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) -{ -#endif u32 cur_rate, low, mult, div, valid_rate, done_rate; u32 bypass = 0; struct prcm_config tmpset; const struct dpll_data *dd; -#ifdef CONFIG_COMMON_CLK cur_rate = omap2xxx_clk_get_core_rate(to_clk_hw_omap(dclk_hw)); -#else - cur_rate = omap2xxx_clk_get_core_rate(dclk); -#endif mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult &= OMAP24XX_CORE_CLK_SRC_MASK; diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index 395e0c1..19f54d4 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -35,11 +35,7 @@ * clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ -#ifdef CONFIG_COMMON_CLK int omap2_enable_osc_ck(struct clk_hw *clk) -#else -static int omap2_enable_osc_ck(struct clk *clk) -#endif { u32 pcc; @@ -57,11 +53,7 @@ static int omap2_enable_osc_ck(struct clk *clk) * clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ -#ifdef CONFIG_COMMON_CLK void omap2_disable_osc_ck(struct clk_hw *clk) -#else -static void omap2_disable_osc_ck(struct clk *clk) -#endif { u32 pcc; @@ -70,20 +62,8 @@ static void omap2_disable_osc_ck(struct clk *clk) __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); } -#ifndef CONFIG_COMMON_CLK -const struct clkops clkops_oscck = { - .enable = omap2_enable_osc_ck, - .disable = omap2_disable_osc_ck, -}; -#endif - -#ifdef CONFIG_COMMON_CLK unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, unsigned long parent_rate) -#else -unsigned long omap2_osc_clk_recalc(struct clk *clk) -#endif { return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); } - diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c index e6e73cf..f467d07 100644 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c @@ -40,16 +40,8 @@ u32 omap2xxx_get_sysclkdiv(void) return div; } -#ifdef CONFIG_COMMON_CLK unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, unsigned long parent_rate) { return parent_rate / omap2xxx_get_sysclkdiv(); } -#else -unsigned long omap2xxx_sys_clk_recalc(struct clk *clk) -{ - return clk->parent->rate / omap2xxx_get_sysclkdiv(); -} -#endif - diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 23456a8..5055e2b 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -52,12 +52,8 @@ const struct prcm_config *rate_table; * * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, unsigned long parent_rate) -#else -unsigned long omap2_table_mpu_recalc(struct clk *clk) -#endif { return curr_prcm_set->mpu_speed; } @@ -69,12 +65,8 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk) * Some might argue L3-DDR, others ARM, others IVA. This code is simple and * just uses the ARM rates. */ -#ifdef CONFIG_COMMON_CLK long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) -#else -long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) -#endif { const struct prcm_config *ptr; long highest_rate, sys_clk_rate; @@ -98,12 +90,8 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) } /* Sets basic clocks based on the specified rate */ -#ifdef CONFIG_COMMON_CLK int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) -#else -int omap2_select_table_rate(struct clk *clk, unsigned long rate) -#endif { u32 cur_rate, done_rate, bypass = 0, tmp; const struct prcm_config *prcm; @@ -133,11 +121,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) } curr_prcm_set = prcm; -#ifdef CONFIG_COMMON_CLK cur_rate = omap2xxx_clk_get_core_rate(to_clk_hw_omap(dclk_hw)); -#else - cur_rate = omap2xxx_clk_get_core_rate(dclk); -#endif if (prcm->dpll_speed == cur_rate / 2) { omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index 7a61d78..cef0c8d 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c @@ -40,11 +40,7 @@ * passes back the correct CM_IDLEST register address for I2CHS * modules. No return value. */ -#ifdef CONFIG_COMMON_CLK static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, -#else -static void omap2430_clk_i2chs_find_idlest(struct clk *clk, -#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -55,16 +51,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk, } /* 2430 I2CHS has non-standard IDLEST register */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = { .find_idlest = omap2430_clk_i2chs_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_omap2430_i2chs_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap2430_clk_i2chs_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; -#endif diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index f2b93e3..7b8ae61 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -8,7 +8,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> #include "clock.h" @@ -31,16 +30,6 @@ unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, unsigned long parent_rate); unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, unsigned long parent_rate); -#else -unsigned long omap2_table_mpu_recalc(struct clk *clk); -int omap2_select_table_rate(struct clk *clk, unsigned long rate); -long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); -unsigned long omap2xxx_sys_clk_recalc(struct clk *clk); -unsigned long omap2_osc_clk_recalc(struct clk *clk); -unsigned long omap2_dpllcore_recalc(struct clk *clk); -int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); -unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); -#endif u32 omap2xxx_get_apll_clkin(void); u32 omap2xxx_get_sysclkdiv(void); void omap2xxx_clk_prepare_for_reboot(void); @@ -60,8 +49,6 @@ int omap2430_clk_init(void); extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; extern struct clk *dclk; - -#ifdef CONFIG_COMMON_CLK extern struct clk_hw *dclk_hw; int omap2_enable_osc_ck(struct clk_hw *hw); void omap2_disable_osc_ck(struct clk_hw *hw); @@ -74,11 +61,5 @@ void _apll54_deny_idle(struct clk_hw_omap *hw); void omap2_clk_apll_disable(struct clk_hw *hw); void _allow_idle(struct clk_hw_omap *hw); void _deny_idle(struct clk_hw_omap *hw); -#else -extern const struct clkops clkops_omap2430_i2chs_wait; -extern const struct clkops clkops_oscck; -extern const struct clkops clkops_apll96; -extern const struct clkops clkops_apll54; -#endif #endif diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 87ae36c..3d35bd6 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -25,11 +25,7 @@ #include <linux/sysfs.h> #include <linux/module.h> #include <linux/delay.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/irq.h> #include <linux/time.h> #include <linux/gpio.h> @@ -206,11 +202,7 @@ static int omap2_can_sleep(void) { if (omap2_fclks_active()) return 0; -#ifdef CONFIG_COMMON_CLK if (__clk_is_enabled(osc_ck)) -#else - if (osc_ck->usecount > 1) -#endif return 0; if (omap_dma_running()) return 0; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 25/26] ARM: OMAP2+: clock: remove unnecessary declarations 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (18 preceding siblings ...) 2012-11-08 1:12 ` [PATCH 23/26] ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette @ 2012-11-08 1:13 ` Mike Turquette 2012-11-08 1:13 ` [PATCH 26/26] ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette ` (8 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:13 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette At some point during the CM/PRM cleanup a few function declarations were added back to clock.h which are unnecessary. This patch removes them. Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clock.h | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index a3e9067..4a095b0 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -597,33 +597,6 @@ u32 omap2_get_dpll_rate(struct clk *clk); void omap2_init_dpll_parent(struct clk *clk); #endif -int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); - - -#ifdef CONFIG_ARCH_OMAP2 -void omap2xxx_clk_prepare_for_reboot(void); -#else -static inline void omap2xxx_clk_prepare_for_reboot(void) -{ -} -#endif - -#ifdef CONFIG_ARCH_OMAP3 -void omap3_clk_prepare_for_reboot(void); -#else -static inline void omap3_clk_prepare_for_reboot(void) -{ -} -#endif - -#ifdef CONFIG_ARCH_OMAP4 -void omap4_clk_prepare_for_reboot(void); -#else -static inline void omap4_clk_prepare_for_reboot(void) -{ -} -#endif - #ifdef CONFIG_COMMON_CLK int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 26/26] ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (19 preceding siblings ...) 2012-11-08 1:13 ` [PATCH 25/26] ARM: OMAP2+: clock: remove unnecessary declarations Mike Turquette @ 2012-11-08 1:13 ` Mike Turquette 2012-11-08 1:31 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (7 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:13 UTC (permalink / raw) To: paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette Clean all #ifdef's added to common clock code. This code is no longer needed due to migration to the common clock framework. Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clkt_clksel.c | 238 ---------- arch/arm/mach-omap2/clkt_dpll.c | 50 -- arch/arm/mach-omap2/clkt_iclk.c | 42 -- arch/arm/mach-omap2/clock.c | 778 ------------------------------- arch/arm/mach-omap2/clock.h | 221 +-------- arch/arm/mach-omap2/clock_common_data.c | 20 +- 6 files changed, 2 insertions(+), 1347 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 03ceb2e..0ec9f6f 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -41,11 +41,7 @@ #include <linux/kernel.h> #include <linux/errno.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/io.h> #include <linux/bug.h> @@ -62,11 +58,7 @@ * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ -#ifdef CONFIG_COMMON_CLK static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, -#else -static const struct clksel *_get_clksel_by_parent(struct clk *clk, -#endif struct clk *src_clk) { const struct clksel *clks; @@ -81,11 +73,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", -#ifdef CONFIG_COMMON_CLK __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); -#else - __clk_get_name(clk), __clk_get_name(src_clk)); -#endif return NULL; } @@ -93,66 +81,6 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, } /** - * _get_div_and_fieldval() - find the new clksel divisor and field value to use - * @src_clk: planned new parent struct clk * - * @clk: struct clk * that is being reparented - * @field_val: pointer to a u32 to contain the register data for the divisor - * - * Given an intended new parent struct clk * @src_clk, and the struct - * clk * @clk to the clock that is being reparented, find the - * appropriate rate divisor for the new clock (returned as the return - * value), and the corresponding register bitfield data to program to - * reach that divisor (returned in the u32 pointed to by @field_val). - * Returns 0 on error, or returns the newly-selected divisor upon - * success (in this latter case, the corresponding register bitfield - * value is passed back in the variable pointed to by @field_val) - */ -#ifndef CONFIG_COMMON_CLK -static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, - u32 *field_val) -{ - const struct clksel *clks; - const struct clksel_rate *clkr, *max_clkr = NULL; - u8 max_div = 0; - - clks = _get_clksel_by_parent(clk, src_clk); - if (!clks) - return 0; - - /* - * Find the highest divisor (e.g., the one resulting in the - * lowest rate) to use as the default. This should avoid - * clock rates that are too high for the device. XXX A better - * solution here would be to try to determine if there is a - * divisor matching the original clock rate before the parent - * switch, and if it cannot be found, to fall back to the - * highest divisor. - */ - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->div > max_div) { - max_div = clkr->div; - max_clkr = clkr; - } - } - - if (max_div == 0) { - /* This indicates an error in the clksel data */ - WARN(1, "clock: %s: could not find divisor for parent %s\n", - __clk_get_name(clk), - __clk_get_name(__clk_get_parent(src_clk))); - return 0; - } - - *field_val = max_clkr->val; - - return max_div; -} -#endif - -/** * _write_clksel_reg() - program a clock's clksel register in hardware * @clk: struct clk * to program * @v: clksel bitfield value to program (with LSB at bit 0) @@ -165,11 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, * take into account any time the hardware might take to switch the * clock source. */ -#ifdef CONFIG_COMMON_CLK static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) -#else -static void _write_clksel_reg(struct clk *clk, u32 field_val) -#endif { u32 v; @@ -192,21 +116,13 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val) * before calling. Returns 0 on error or returns the actual integer divisor * upon success. */ -#ifdef CONFIG_COMMON_CLK static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) -#else -static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) -#endif { const struct clksel *clks; const struct clksel_rate *clkr; struct clk *parent; -#ifdef CONFIG_COMMON_CLK parent = __clk_get_parent(clk->hw.clk); -#else - parent = __clk_get_parent(clk); -#endif clks = _get_clksel_by_parent(clk, parent); if (!clks) @@ -223,12 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", -#ifdef CONFIG_COMMON_CLK __clk_get_name(clk->hw.clk), field_val, __clk_get_name(parent)); -#else - __clk_get_name(clk), field_val, __clk_get_name(parent)); -#endif return 0; } @@ -245,11 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. */ -#ifdef CONFIG_COMMON_CLK static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) -#else -static u32 _divisor_to_clksel(struct clk *clk, u32 div) -#endif { const struct clksel *clks; const struct clksel_rate *clkr; @@ -258,11 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) /* should never happen */ WARN_ON(div == 0); -#ifdef CONFIG_COMMON_CLK parent = __clk_get_parent(clk->hw.clk); -#else - parent = __clk_get_parent(clk); -#endif clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -277,12 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) if (!clkr->div) { pr_err("clock: %s: could not find divisor %d for parent %s\n", -#ifdef CONFIG_COMMON_CLK __clk_get_name(clk->hw.clk), div, __clk_get_name(parent)); -#else - __clk_get_name(clk), div, __clk_get_name(parent)); -#endif return ~0; } @@ -297,11 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ -#ifdef CONFIG_COMMON_CLK static u32 _read_divisor(struct clk_hw_omap *clk) -#else -static u32 _read_divisor(struct clk *clk) -#endif { u32 v; @@ -329,12 +225,8 @@ static u32 _read_divisor(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ -#ifdef CONFIG_COMMON_CLK u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, unsigned long target_rate, -#else -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, -#endif u32 *new_div) { unsigned long test_rate; @@ -345,13 +237,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, unsigned long parent_rate; const char *clk_name; -#ifdef CONFIG_COMMON_CLK parent = __clk_get_parent(clk->hw.clk); clk_name = __clk_get_name(clk->hw.clk); -#else - parent = __clk_get_parent(clk); - clk_name = __clk_get_name(clk); -#endif parent_rate = __clk_get_rate(parent); if (!clk->clksel || !clk->clksel_mask) @@ -402,7 +289,6 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, * (i.e., those used in struct clk field function pointers, etc.) */ -#ifdef CONFIG_COMMON_CLK /** * omap2_clksel_find_parent_index() - return the array index of the current * hardware parent of @hw @@ -457,62 +343,6 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) return ret; } -#else - -/** - * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr - * @clk: OMAP clock struct ptr to use - * - * Given a pointer @clk to a source-selectable struct clk, read the - * hardware register and determine what its parent is currently set - * to. Update @clk's .parent field with the appropriate clk ptr. No - * return value. - */ -void omap2_init_clksel_parent(struct clk *clk) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 r, found = 0; - struct clk *parent; - const char *clk_name; - - if (!clk->clksel || !clk->clksel_mask) - return; - - parent = __clk_get_parent(clk); - clk_name = __clk_get_name(clk); - - r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - r >>= __ffs(clk->clksel_mask); - - for (clks = clk->clksel; clks->parent && !found; clks++) { - for (clkr = clks->rates; clkr->div && !found; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->val == r) { - if (parent != clks->parent) { - pr_debug("clock: %s: inited parent to %s (was %s)\n", - clk_name, - __clk_get_name(clks->parent), - ((parent) ? - __clk_get_name(parent) : - "NULL")); - clk_reparent(clk, clks->parent); - } - found = 1; - } - } - } - - /* This indicates a data error */ - WARN(!found, "clock: %s: init parent: could not find regval %0x\n", - clk_name, r); - - return; -} - -#endif /** * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field @@ -523,7 +353,6 @@ void omap2_init_clksel_parent(struct clk *clk) * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) { unsigned long rate; @@ -544,26 +373,6 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) return rate; } -#else -unsigned long omap2_clksel_recalc(struct clk *clk) -{ - unsigned long rate; - u32 div = 0; - struct clk *parent; - - div = _read_divisor(clk); - if (div == 0) - return __clk_get_rate(clk); - - parent = __clk_get_parent(clk); - rate = __clk_get_rate(parent) / div; - - pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", - __clk_get_name(clk), rate, div); - - return rate; -} -#endif /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate @@ -576,15 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ -#ifdef CONFIG_COMMON_CLK long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) -{ -#endif u32 new_div; return omap2_clksel_round_rate_div(clk, target_rate, &new_div); @@ -605,15 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) * is changed, they will all be affected without any notification. * Returns -EINVAL upon error, or 0 upon success. */ -#ifdef CONFIG_COMMON_CLK int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) -{ -#endif u32 field_val, validrate, new_div = 0; if (!clk->clksel || !clk->clksel_mask) @@ -629,15 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) _write_clksel_reg(clk, field_val); -#ifdef CONFIG_COMMON_CLK pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), __clk_get_rate(hw->clk)); -#else - pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), - __clk_get_rate(clk)); - - clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; -#endif return 0; } @@ -662,7 +454,6 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) * affected without any notification. Returns -EINVAL upon error, or * 0 upon success. */ -#ifdef CONFIG_COMMON_CLK int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); @@ -673,32 +464,3 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) _write_clksel_reg(clk, field_val); return 0; } -#else -int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) -{ - u32 field_val = 0; - u32 parent_div; - - if (!clk->clksel || !clk->clksel_mask) - return -EINVAL; - - parent_div = _get_div_and_fieldval(new_parent, clk, &field_val); - if (!parent_div) - return -EINVAL; - _write_clksel_reg(clk, field_val); - - clk_reparent(clk, new_parent); - - /* CLKSEL clocks follow their parents' rates, divided by a divisor */ - clk->rate = __clk_get_rate(new_parent); - - if (parent_div > 0) - __clk_get_rate(clk) /= parent_div; - pr_debug("clock: %s: set parent to %s (new rate %ld)\n", - __clk_get_name(clk), - __clk_get_name(__clk_get_parent(clk)), - __clk_get_rate(clk)); - - return 0; -} -#endif diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index f343389..924c230 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -16,11 +16,7 @@ #include <linux/kernel.h> #include <linux/errno.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/io.h> #include <asm/div64.h> @@ -80,11 +76,7 @@ * (assuming that it is counting N upwards), or -2 if the enclosing loop * should skip to the next iteration (again assuming N is increasing). */ -#ifdef CONFIG_COMMON_CLK static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) -#else -static int _dpll_test_fint(struct clk *clk, u8 n) -#endif { struct dpll_data *dd; long fint, fint_min, fint_max; @@ -93,11 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data; /* DPLL divider must result in a valid jitter correction val */ -#ifdef CONFIG_COMMON_CLK fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; -#else - fint = __clk_get_rate(__clk_get_parent(clk)) / n; -#endif if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -198,24 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, } /* Public functions */ -#ifdef CONFIG_COMMON_CLK u8 omap2_init_dpll_parent(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -void omap2_init_dpll_parent(struct clk *clk) -{ -#endif u32 v; struct dpll_data *dd; dd = clk->dpll_data; if (!dd) -#ifdef CONFIG_COMMON_CLK return -EINVAL; -#else - return; -#endif v = __raw_readl(dd->control_reg); v &= dd->enable_mask; @@ -225,34 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) -#ifdef CONFIG_COMMON_CLK return 1; -#else - clk_reparent(clk, dd->clk_bypass); -#endif } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) -#ifdef CONFIG_COMMON_CLK return 1; -#else - clk_reparent(clk, dd->clk_bypass); -#endif } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) -#ifdef CONFIG_COMMON_CLK return 1; -#else - clk_reparent(clk, dd->clk_bypass); -#endif } -#ifdef CONFIG_COMMON_CLK return 0; -#else - return; -#endif } /** @@ -269,11 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * if the clock @clk is not a DPLL. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) -#else -u32 omap2_get_dpll_rate(struct clk *clk) -#endif { long long dpll_clk; u32 dpll_mult, dpll_div, v; @@ -329,15 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk) * (expensive) function again. Returns ~0 if the target rate cannot * be rounded, or the rounded rate upon success. */ -#ifdef CONFIG_COMMON_CLK long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) -{ -#endif int m, n, r, scaled_max_m; unsigned long scaled_rt_rp; unsigned long new_rate = 0; @@ -351,11 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd = clk->dpll_data; ref_rate = __clk_get_rate(dd->clk_ref); -#ifdef CONFIG_COMMON_CLK clk_name = __clk_get_name(hw->clk); -#else - clk_name = __clk_get_name(clk); -#endif pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", clk_name, target_rate); diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index 13dadf4..f10eb03 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -11,14 +11,9 @@ #undef DEBUG #include <linux/kernel.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/io.h> -#include <plat/prcm.h> #include "clock.h" #include "clock2xxx.h" @@ -28,11 +23,7 @@ /* Private functions */ /* XXX */ -#ifdef CONFIG_COMMON_CLK void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) -#else -void omap2_clkt_iclk_allow_idle(struct clk *clk) -#endif { u32 v, r; @@ -44,11 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk) } /* XXX */ -#ifdef CONFIG_COMMON_CLK void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) -#else -void omap2_clkt_iclk_deny_idle(struct clk *clk) -#endif { u32 v, r; @@ -61,7 +48,6 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk) /* Public data */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_iclk = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, @@ -73,34 +59,6 @@ const struct clk_hw_omap_ops clkhwops_iclk_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_omap2_iclk_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -const struct clkops clkops_omap2_iclk_dflt = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -const struct clkops clkops_omap2_iclk_idle_only = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -const struct clkops clkops_omap2_mdmclk_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -#endif diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 99fb246..25f35d6 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -20,11 +20,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/delay.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/io.h> #include <linux/bitops.h> @@ -52,11 +48,6 @@ u16 cpu_mask; */ static bool clkdm_control = true; -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -static DEFINE_SPINLOCK(clockfw_lock); - -#ifdef CONFIG_COMMON_CLK LIST_HEAD(clk_hw_omap_clocks); /* @@ -79,7 +70,6 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, return parent_rate / oclk->fixed_div; } -#endif /* * OMAP2+ specific clock functions @@ -97,11 +87,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, * belong in the clock code and will be moved in the medium term to * module-dependent code. No return value. */ -#ifdef CONFIG_COMMON_CLK static void _omap2_module_wait_ready(struct clk_hw_omap *clk) -#else -static void _omap2_module_wait_ready(struct clk *clk) -#endif { void __iomem *companion_reg, *idlest_reg; u8 other_bit, idlest_bit, idlest_val; @@ -132,25 +118,16 @@ static void _omap2_module_wait_ready(struct clk *clk) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ -#ifdef CONFIG_COMMON_CLK void omap2_init_clk_clkdm(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -void omap2_init_clk_clkdm(struct clk *clk) -{ -#endif struct clockdomain *clkdm; const char *clk_name; if (!clk->clkdm_name) return; -#ifdef CONFIG_COMMON_CLK clk_name = __clk_get_name(hw->clk); -#else - clk_name = __clk_get_name(clk); -#endif clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { @@ -197,11 +174,7 @@ void __init omap2_clk_disable_clkdm_control(void) * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -#ifdef CONFIG_COMMON_CLK void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, -#else -void omap2_clk_dflt_find_companion(struct clk *clk, -#endif void __iomem **other_reg, u8 *other_bit) { u32 r; @@ -230,11 +203,7 @@ void omap2_clk_dflt_find_companion(struct clk *clk, * register address ID (e.g., that CM_FCLKEN2 corresponds to * CM_IDLEST2). This is not true for all modules. No return value. */ -#ifdef CONFIG_COMMON_CLK void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, -#else -void omap2_clk_dflt_find_idlest(struct clk *clk, -#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) { u32 r; @@ -257,7 +226,6 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, } -#ifdef CONFIG_COMMON_CLK int omap2_dflt_clk_enable(struct clk_hw *hw) { struct clk_hw_omap *clk; @@ -473,238 +441,6 @@ const struct clk_hw_omap_ops clkhwops_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -int omap2_dflt_clk_enable(struct clk *clk) -{ - u32 v; - - if (unlikely(clk->enable_reg == NULL)) { - pr_err("clock.c: Enable for %s without enable code\n", - clk->name); - return 0; /* REVISIT: -EINVAL */ - } - - v = __raw_readl(clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v &= ~(1 << clk->enable_bit); - else - v |= (1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); - v = __raw_readl(clk->enable_reg); /* OCP barrier */ - - if (clk->ops->find_idlest) - _omap2_module_wait_ready(clk); - - return 0; -} - -void omap2_dflt_clk_disable(struct clk *clk) -{ - u32 v; - - if (!clk->enable_reg) { - /* - * 'Independent' here refers to a clock which is not - * controlled by its parent. - */ - pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name); - return; - } - - v = __raw_readl(clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v |= (1 << clk->enable_bit); - else - v &= ~(1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); - /* No OCP barrier needed here since it is a disable operation */ -} - -const struct clkops clkops_omap2_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -}; - -const struct clkops clkops_omap2_dflt = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, -}; - -/** - * omap2_clk_disable - disable a clock, if the system is not using it - * @clk: struct clk * to disable - * - * Decrements the usecount on struct clk @clk. If there are no users - * left, call the clkops-specific clock disable function to disable it - * in hardware. If the clock is part of a clockdomain (which they all - * should be), request that the clockdomain be disabled. (It too has - * a usecount, and so will not be disabled in the hardware until it no - * longer has any users.) If the clock has a parent clock (most of - * them do), then call ourselves, recursing on the parent clock. This - * can cause an entire branch of the clock tree to be powered off by - * simply disabling one clock. Intended to be called with the clockfw_lock - * spinlock held. No return value. - */ -void omap2_clk_disable(struct clk *clk) -{ - if (clk->usecount == 0) { - WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name); - return; - } - - pr_debug("clock: %s: decrementing usecount\n", clk->name); - - clk->usecount--; - - if (clk->usecount > 0) - return; - - pr_debug("clock: %s: disabling in hardware\n", clk->name); - - if (clk->ops && clk->ops->disable) { - trace_clock_disable(clk->name, 0, smp_processor_id()); - clk->ops->disable(clk); - } - - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); - - if (clk->parent) - omap2_clk_disable(clk->parent); -} - -/** - * omap2_clk_enable - request that the system enable a clock - * @clk: struct clk * to enable - * - * Increments the usecount on struct clk @clk. If there were no users - * previously, then recurse up the clock tree, enabling all of the - * clock's parents and all of the parent clockdomains, and finally, - * enabling @clk's clockdomain, and @clk itself. Intended to be - * called with the clockfw_lock spinlock held. Returns 0 upon success - * or a negative error code upon failure. - */ -int omap2_clk_enable(struct clk *clk) -{ - int ret; - - pr_debug("clock: %s: incrementing usecount\n", clk->name); - - clk->usecount++; - - if (clk->usecount > 1) - return 0; - - pr_debug("clock: %s: enabling in hardware\n", clk->name); - - if (clk->parent) { - ret = omap2_clk_enable(clk->parent); - if (ret) { - WARN(1, "clock: %s: could not enable parent %s: %d\n", - clk->name, clk->parent->name, ret); - goto oce_err1; - } - } - - if (clkdm_control && clk->clkdm) { - ret = clkdm_clk_enable(clk->clkdm, clk); - if (ret) { - WARN(1, "clock: %s: could not enable clockdomain %s: %d\n", - clk->name, clk->clkdm->name, ret); - goto oce_err2; - } - } - - if (clk->ops && clk->ops->enable) { - trace_clock_enable(clk->name, 1, smp_processor_id()); - ret = clk->ops->enable(clk); - if (ret) { - WARN(1, "clock: %s: could not enable: %d\n", - clk->name, ret); - goto oce_err3; - } - } - - return 0; - -oce_err3: - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); -oce_err2: - if (clk->parent) - omap2_clk_disable(clk->parent); -oce_err1: - clk->usecount--; - - return ret; -} - -/* Given a clock and a rate apply a clock specific rounding function */ -long omap2_clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk->round_rate) - return clk->round_rate(clk, rate); - - return clk->rate; -} - -/* Set the clock rate for a clock source */ -int omap2_clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); - - /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ - if (clk->set_rate) { - trace_clock_set_rate(clk->name, rate, smp_processor_id()); - ret = clk->set_rate(clk, rate); - } - - return ret; -} - -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) -{ - if (!clk->clksel) - return -EINVAL; - - if (clk->parent == new_parent) - return 0; - - return omap2_clksel_set_parent(clk, new_parent); -} - -/* - * OMAP2+ clock reset and init functions - */ - -#ifdef CONFIG_OMAP_RESET_CLOCKS -void omap2_clk_disable_unused(struct clk *clk) -{ - u32 regval32, v; - - v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; - - regval32 = __raw_readl(clk->enable_reg); - if ((regval32 & (1 << clk->enable_bit)) == v) - return; - - pr_debug("Disabling unused clock \"%s\"\n", clk->name); - if (cpu_is_omap34xx()) { - omap2_clk_enable(clk); - omap2_clk_disable(clk); - } else { - clk->ops->disable(clk); - } - if (clk->clkdm != NULL) - pwrdm_state_switch(clk->clkdm->pwrdm.ptr); -} -#endif - -#endif /* CONFIG_COMMON_CLK */ /** * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument @@ -742,10 +478,6 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) } calibrate_delay(); -#ifndef CONFIG_COMMON_CLK - recalculate_root_clocks(); -#endif - clk_put(mpurate_ck); return 0; @@ -789,513 +521,3 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(core_ck) / 1000000), (clk_get_rate(mpu_ck) / 1000000)); } - -#ifndef CONFIG_COMMON_CLK -/* Common data */ -int clk_enable(struct clk *clk) -{ - unsigned long flags; - int ret; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap2_clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - pr_err("Trying disable clock %s with 0 usecount\n", - clk->name); - WARN_ON(1); - goto out; - } - - omap2_clk_disable(clk); - -out: - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long flags; - unsigned long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = clk->rate; - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_get_rate); - -/* - * Optional clock functions defined in include/linux/clk.h - */ - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap2_clk_round_rate(clk, rate); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap2_clk_set_rate(clk, rate); - if (ret == 0) - propagate_rate(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - ret = omap2_clk_set_parent(clk, parent); - if (ret == 0) - propagate_rate(clk); - } else { - ret = -EBUSY; - } - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -/* - * OMAP specific clock functions shared between omap1 and omap2 - */ - -int __initdata mpurate; - -/* - * By default we use the rate set by the bootloader. - * You can override this with mpurate= cmdline option. - */ -static int __init omap_clk_setup(char *str) -{ - get_option(&str, &mpurate); - - if (!mpurate) - return 1; - - if (mpurate < 1000) - mpurate *= 1000000; - - return 1; -} -__setup("mpurate=", omap_clk_setup); - -/* Used for clocks that always have same value as the parent clock */ -unsigned long followparent_recalc(struct clk *clk) -{ - return clk->parent->rate; -} - -/* - * Used for clocks that have the same value as the parent clock, - * divided by some factor - */ -unsigned long omap_fixed_divisor_recalc(struct clk *clk) -{ - WARN_ON(!clk->fixed_div); - - return clk->parent->rate / clk->fixed_div; -} - -void clk_reparent(struct clk *child, struct clk *parent) -{ - list_del_init(&child->sibling); - if (parent) - list_add(&child->sibling, &parent->children); - child->parent = parent; - - /* now do the debugfs renaming to reattach the child - to the proper parent */ -} - -/* Propagate rate to children */ -void propagate_rate(struct clk *tclk) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &tclk->children, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -static LIST_HEAD(root_clks); - -/** - * recalculate_root_clocks - recalculate and propagate all root clocks - * - * Recalculates all root clocks (clocks with no parent), which if the - * clock's .recalc is set correctly, should also propagate their rates. - * Called at init. - */ -void recalculate_root_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &root_clks, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -/** - * clk_preinit - initialize any fields in the struct clk before clk init - * @clk: struct clk * to initialize - * - * Initialize any struct clk fields needed before normal clk initialization - * can run. No return value. - */ -void clk_preinit(struct clk *clk) -{ - INIT_LIST_HEAD(&clk->children); -} - -int clk_register(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - /* - * trap out already registered clocks - */ - if (clk->node.next || clk->node.prev) - return 0; - - mutex_lock(&clocks_mutex); - if (clk->parent) - list_add(&clk->sibling, &clk->parent->children); - else - list_add(&clk->sibling, &root_clks); - - list_add(&clk->node, &clocks); - if (clk->init) - clk->init(clk); - mutex_unlock(&clocks_mutex); - - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - - mutex_lock(&clocks_mutex); - list_del(&clk->sibling); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -void clk_enable_init_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &clocks, node) - if (clkp->flags & ENABLE_ON_INIT) - clk_enable(clkp); -} - -/** - * omap_clk_get_by_name - locate OMAP struct clk by its name - * @name: name of the struct clk to locate - * - * Locate an OMAP struct clk by its name. Assumes that struct clk - * names are unique. Returns NULL if not found or a pointer to the - * struct clk if found. - */ -struct clk *omap_clk_get_by_name(const char *name) -{ - struct clk *c; - struct clk *ret = NULL; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(c, &clocks, node) { - if (!strcmp(c->name, name)) { - ret = c; - break; - } - } - - mutex_unlock(&clocks_mutex); - - return ret; -} - -int omap_clk_enable_autoidle_all(void) -{ - struct clk *c; - unsigned long flags; - - spin_lock_irqsave(&clockfw_lock, flags); - - list_for_each_entry(c, &clocks, node) - if (c->ops->allow_idle) - c->ops->allow_idle(c); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} - -int omap_clk_disable_autoidle_all(void) -{ - struct clk *c; - unsigned long flags; - - spin_lock_irqsave(&clockfw_lock, flags); - - list_for_each_entry(c, &clocks, node) - if (c->ops->deny_idle) - c->ops->deny_idle(c); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} - -/* - * Low level helpers - */ -static int clkll_enable_null(struct clk *clk) -{ - return 0; -} - -static void clkll_disable_null(struct clk *clk) -{ -} - -const struct clkops clkops_null = { - .enable = clkll_enable_null, - .disable = clkll_disable_null, -}; - -/* - * Dummy clock - * - * Used for clock aliases that are needed on some OMAPs, but not others - */ -struct clk dummy_ck = { - .name = "dummy", - .ops = &clkops_null, -}; - -/* - * - */ - -#ifdef CONFIG_OMAP_RESET_CLOCKS -/* - * Disable any unused clocks left on by the bootloader - */ -static int __init clk_disable_unused(void) -{ - struct clk *ck; - unsigned long flags; - - pr_info("clock: disabling unused clocks to save power\n"); - - spin_lock_irqsave(&clockfw_lock, flags); - list_for_each_entry(ck, &clocks, node) { - if (ck->ops == &clkops_null) - continue; - - if (ck->usecount > 0 || !ck->enable_reg) - continue; - - omap2_clk_disable_unused(ck); - } - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -late_initcall(clk_disable_unused); -late_initcall(omap_clk_enable_autoidle_all); -#endif - -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) -/* - * debugfs support to trace clock tree hierarchy and attributes - */ - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -static struct dentry *clk_debugfs_root; - -static int clk_dbg_show_summary(struct seq_file *s, void *unused) -{ - struct clk *c; - struct clk *pa; - - mutex_lock(&clocks_mutex); - seq_printf(s, "%-30s %-30s %-10s %s\n", - "clock-name", "parent-name", "rate", "use-count"); - - list_for_each_entry(c, &clocks, node) { - pa = c->parent; - seq_printf(s, "%-30s %-30s %-10lu %d\n", - c->name, pa ? pa->name : "none", c->rate, - c->usecount); - } - mutex_unlock(&clocks_mutex); - - return 0; -} - -static int clk_dbg_open(struct inode *inode, struct file *file) -{ - return single_open(file, clk_dbg_show_summary, inode->i_private); -} - -static const struct file_operations debug_clock_fops = { - .open = clk_dbg_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int clk_debugfs_register_one(struct clk *c) -{ - int err; - struct dentry *d; - struct clk *pa = c->parent; - - d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root); - if (!d) - return -ENOMEM; - c->dent = d; - - d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount); - if (!d) { - err = -ENOMEM; - goto err_out; - } - d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); - if (!d) { - err = -ENOMEM; - goto err_out; - } - d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); - if (!d) { - err = -ENOMEM; - goto err_out; - } - return 0; - -err_out: - debugfs_remove_recursive(c->dent); - return err; -} - -static int clk_debugfs_register(struct clk *c) -{ - int err; - struct clk *pa = c->parent; - - if (pa && !pa->dent) { - err = clk_debugfs_register(pa); - if (err) - return err; - } - - if (!c->dent) { - err = clk_debugfs_register_one(c); - if (err) - return err; - } - return 0; -} - -static int __init clk_debugfs_init(void) -{ - struct clk *c; - struct dentry *d; - int err; - - d = debugfs_create_dir("clock", NULL); - if (!d) - return -ENOMEM; - clk_debugfs_root = d; - - list_for_each_entry(c, &clocks, node) { - err = clk_debugfs_register(c); - if (err) - goto err_out; - } - - d = debugfs_create_file("summary", S_IRUGO, - d, NULL, &debug_clock_fops); - if (!d) - return -ENOMEM; - - return 0; -err_out: - debugfs_remove_recursive(clk_debugfs_root); - return err; -} -late_initcall(clk_debugfs_init); - -#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ -#endif /* CONFIG_COMMON_CLK */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 4a095b0..6cfb798 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -20,6 +20,7 @@ #include <linux/list.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> struct omap_clk { u16 cpu; @@ -52,9 +53,6 @@ struct omap_clk { #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) -#ifdef CONFIG_COMMON_CLK -#include <linux/clk-provider.h> - struct clockdomain; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) @@ -134,48 +132,6 @@ struct clockdomain; }; \ DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); - -#else - -struct module; -struct clk; -struct clockdomain; - -/* Temporary, needed during the common clock framework conversion */ -#define __clk_get_name(clk) (clk->name) -#define __clk_get_parent(clk) (clk->parent) -#define __clk_get_rate(clk) (clk->rate) - -/** - * struct clkops - some clock function pointers - * @enable: fn ptr that enables the current clock in hardware - * @disable: fn ptr that enables the current clock in hardware - * @find_idlest: function returning the IDLEST register for the clock's IP blk - * @find_companion: function returning the "companion" clk reg for the clock - * @allow_idle: fn ptr that enables autoidle for the current clock in hardware - * @deny_idle: fn ptr that disables autoidle for the current clock in hardware - * - * A "companion" clk is an accompanying clock to the one being queried - * that must be enabled for the IP module connected to the clock to - * become accessible by the hardware. Neither @find_idlest nor - * @find_companion should be needed; that information is IP - * block-specific; the hwmod code has been created to handle this, but - * until hwmod data is ready and drivers have been converted to use PM - * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and - * @find_companion must, unfortunately, remain. - */ -struct clkops { - int (*enable)(struct clk *); - void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, - u8 *, u8 *); - void (*find_companion)(struct clk *, void __iomem **, - u8 *); - void (*allow_idle)(struct clk *); - void (*deny_idle)(struct clk *); -}; -#endif - /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) @@ -314,7 +270,6 @@ struct dpll_data { #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ #define CLOCK_CLKOUTX2 (1 << 5) -#ifdef CONFIG_COMMON_CLK /** * struct clk_hw_omap - OMAP struct clk * @node: list_head connecting this clock into the full clock list @@ -367,114 +322,6 @@ struct clk_hw_omap_ops { unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, unsigned long parent_rate); -#else -/** - * struct clk - OMAP struct clk - * @node: list_head connecting this clock into the full clock list - * @ops: struct clkops * for this clock - * @name: the name of the clock in the hardware (used in hwmod data and debug) - * @parent: pointer to this clock's parent struct clk - * @children: list_head connecting to the child clks' @sibling list_heads - * @sibling: list_head connecting this clk to its parent clk's @children - * @rate: current clock rate - * @enable_reg: register to write to enable the clock (see @enable_bit) - * @recalc: fn ptr that returns the clock's current rate - * @set_rate: fn ptr that can change the clock's current rate - * @round_rate: fn ptr that can round the clock's current rate - * @init: fn ptr to do clock-specific initialization - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) - * @usecount: number of users that have requested this clock to be enabled - * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div - * @flags: see "struct clk.flags possibilities" above - * @clksel_reg: for clksel clks, register va containing src/divisor select - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector - * @clksel: for clksel clks, pointer to struct clksel for this clock - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock - * @clkdm_name: clockdomain name that this clock is contained in - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) - * @src_offset: bitshift for source selection bitfield (OMAP1 only) - * - * XXX @rate_offset, @src_offset should probably be removed and OMAP1 - * clock code converted to use clksel. - * - * XXX @usecount is poorly named. It should be "enable_count" or - * something similar. "users" in the description refers to kernel - * code (core code or drivers) that have called clk_enable() and not - * yet called clk_disable(); the usecount of parent clocks is also - * incremented by the clock code when clk_enable() is called on child - * clocks and decremented by the clock code when clk_disable() is - * called on child clocks. - * - * XXX @clkdm, @usecount, @children, @sibling should be marked for - * internal use only. - * - * @children and @sibling are used to optimize parent-to-child clock - * tree traversals. (child-to-parent traversals use @parent.) - * - * XXX The notion of the clock's current rate probably needs to be - * separated from the clock's target rate. - */ -struct clk { - struct list_head node; - const struct clkops *ops; - const char *name; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ - unsigned long rate; - void __iomem *enable_reg; - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - void (*init)(struct clk *); - u8 enable_bit; - s8 usecount; - u8 fixed_div; - u8 flags; - void __iomem *clksel_reg; - u32 clksel_mask; - const struct clksel *clksel; - struct dpll_data *dpll_data; - const char *clkdm_name; - struct clockdomain *clkdm; -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ -#endif -}; - -struct clk_functions { - int (*clk_enable)(struct clk *clk); - void (*clk_disable)(struct clk *clk); - long (*clk_round_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_parent)(struct clk *clk, struct clk *parent); - void (*clk_allow_idle)(struct clk *clk); - void (*clk_deny_idle)(struct clk *clk); - void (*clk_disable_unused)(struct clk *clk); -}; - -extern int mpurate; - -extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_preinit(struct clk *clk); -extern int clk_register(struct clk *clk); -extern void clk_reparent(struct clk *child, struct clk *parent); -extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk); -extern void recalculate_root_clocks(void); -extern unsigned long followparent_recalc(struct clk *clk); -extern void clk_enable_init_clocks(void); -unsigned long omap_fixed_divisor_recalc(struct clk *clk); -extern struct clk *omap_clk_get_by_name(const char *name); -extern int omap_clk_enable_autoidle_all(void); -extern int omap_clk_disable_autoidle_all(void); - -extern const struct clkops clkops_null; - -extern struct clk dummy_ck; - -#endif /* CONFIG_COMMON_CLK */ /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 @@ -505,15 +352,6 @@ extern struct clk dummy_ck; /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 -#ifndef CONFIG_COMMON_CLK -int omap2_clk_enable(struct clk *clk); -void omap2_clk_disable(struct clk *clk); -long omap2_clk_round_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); -#endif /* CONFIG_COMMON_CLK */ - -#ifdef CONFIG_COMMON_CLK long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); @@ -534,37 +372,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); -#else -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap3_dpll_recalc(struct clk *clk); -unsigned long omap3_clkoutx2_recalc(struct clk *clk); -void omap3_dpll_allow_idle(struct clk *clk); -void omap3_dpll_deny_idle(struct clk *clk); -u32 omap3_dpll_autoidle_read(struct clk *clk); -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); -int omap3_noncore_dpll_enable(struct clk *clk); -void omap3_noncore_dpll_disable(struct clk *clk); -int omap4_dpllmx_gatectrl_read(struct clk *clk); -void omap4_dpllmx_allow_gatectrl(struct clk *clk); -void omap4_dpllmx_deny_gatectrl(struct clk *clk); -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); -#endif -#ifdef CONFIG_OMAP_RESET_CLOCKS -void omap2_clk_disable_unused(struct clk *clk); -#else -#define omap2_clk_disable_unused NULL -#endif -#ifdef CONFIG_COMMON_CLK void omap2_init_clk_clkdm(struct clk_hw *clk); -#else -void omap2_init_clk_clkdm(struct clk *clk); -#endif void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ -#ifdef CONFIG_COMMON_CLK u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, unsigned long target_rate, u32 *new_div); @@ -575,29 +387,14 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); -#else -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, - u32 *new_div); -void omap2_init_clksel_parent(struct clk *clk); -unsigned long omap2_clksel_recalc(struct clk *clk); -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); -int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); -#endif /* clkt_iclk.c public functions */ extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -#ifdef CONFIG_COMMON_CLK u8 omap2_init_dpll_parent(struct clk_hw *hw); unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); -#else -u32 omap2_get_dpll_rate(struct clk *clk); -void omap2_init_dpll_parent(struct clk *clk); -#endif -#ifdef CONFIG_COMMON_CLK int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); @@ -611,14 +408,6 @@ void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); int omap2_clk_disable_autoidle_all(void); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); -#else -int omap2_dflt_clk_enable(struct clk *clk); -void omap2_dflt_clk_disable(struct clk *clk); -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit); -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val); -#endif int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -666,17 +455,9 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; -#ifndef CONFIG_COMMON_CLK -/* clocks shared between various OMAP SoCs */ -extern struct clk virt_19200000_ck; -extern struct clk virt_26000000_ck; -#endif - extern int am33xx_clk_init(void); -#ifdef CONFIG_COMMON_CLK extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); -#endif #endif diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index c0d02a9..ef4d21b 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -16,6 +16,7 @@ * OMAP3xxx clock definition files. */ +#include <linux/clk-private.h> #include "clock.h" /* clksel_rate data common to 24xx/343x */ @@ -115,9 +116,6 @@ const struct clksel_rate div31_1to31_rates[] = { }; /* Clocks shared between various OMAP SoCs */ -#ifdef CONFIG_COMMON_CLK - -#include <linux/clk-private.h> static struct clk_ops dummy_ck_ops = {}; @@ -126,19 +124,3 @@ struct clk dummy_ck = { .ops = &dummy_ck_ops, .flags = CLK_IS_BASIC, }; - -#else - -struct clk virt_19200000_ck = { - .name = "virt_19200000_ck", - .ops = &clkops_null, - .rate = 19200000, -}; - -struct clk virt_26000000_ck = { - .name = "virt_26000000_ck", - .ops = &clkops_null, - .rate = 26000000, -}; - -#endif -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (20 preceding siblings ...) 2012-11-08 1:13 ` [PATCH 26/26] ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette @ 2012-11-08 1:31 ` Mike Turquette 2012-11-08 1:42 ` Tony Lindgren 2012-11-08 5:02 ` Rajendra Nayak ` (6 subsequent siblings) 28 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:31 UTC (permalink / raw) To: Mike Turquette, paul; +Cc: rnayak, linux-omap, linux-arm-kernel, patches Doh, I got the LAKML address wrong... Thankfully it's already up on some archives: http://article.gmane.org/gmane.linux.ports.arm.omap/88824 For anyone interested in testing: git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 Regards, Mike Quoting Mike Turquette (2012-11-07 17:12:35) > From: Mike Turquette <mturquette@linaro.org> > > Hi all, > > This series is based on top of Paul's PRM/CM clean-up work. It is a > refresh of the patches Rajendra sent out a while back[1], with the > addition of several fixes for PM regressions[2] across several > platforms. > > I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF > patches (delta is zero) and also suspend/resume. > > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > appears sane. However Panda-ES never comes back from suspend/resume. > This problem exists on the PRM/CM branch I based on and was not > introduced by this series. I am investigating that independently of > this series. > > Anyone wanting to pull the work can find it at: > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771 > [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015 > > Mike Turquette (3): > ARM: OMAP4: clock: Convert to common clk > ARM: OMAP2+: clock: remove unnecessary declarations > ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts > > Paul Walmsley (7): > ARM: OMAP2xxx: clock: add APLL rate recalculation functions > ARM: OMAP2+: clock: add OMAP CCF convenience macros to > mach-omap2/clock.h > ARM: AM33XX: clock: add clock data in common clock format > ARM: OMAP44xx: clock: drop obsolete clock data > ARM: OMAP3xxx: clk: drop obsolete clock data > ARM: AM33xx: clock: drop obsolete clock data > ARM: OMAP2xxx: clock: drop obsolete clock data > > Rajendra Nayak (15): > ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap > ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses > ARM: OMAP3: clock: Convert to common clk > ARM: OMAP2: clock: Convert to common clk > ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable > autoidle > ARM: OMAP: clock: Define a function to enable clocks at init > ARM: OMAP: clock: Get rid of some clkdm assocations within clks > ARM: OMAP4: clock: Add 44xx data using common struct clk > ARM: OMAP3: clock: Add 3xxx data using common struct clk > ARM: omap2: clock: Add 24xx data using common struct clk > ARM: OMAP: clock: Switch to COMMON clk > ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts > ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts > ARM: omap3: clock: Cleanup !CONFIG_COMMON_CLK parts > ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts > > Vaibhav Hiremath (1): > ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions > > arch/arm/mach-omap2/Kconfig | 5 + > arch/arm/mach-omap2/Makefile | 10 +- > arch/arm/mach-omap2/cclock2420_data.c | 1959 ++++++++++++++ > arch/arm/mach-omap2/cclock2430_data.c | 2073 +++++++++++++++ > arch/arm/mach-omap2/cclock33xx_data.c | 961 +++++++ > arch/arm/mach-omap2/cclock3xxx_data.c | 3595 +++++++++++++++++++++++++ > arch/arm/mach-omap2/cclock44xx_data.c | 1991 ++++++++++++++ > arch/arm/mach-omap2/clkt2xxx_apll.c | 66 +- > arch/arm/mach-omap2/clkt2xxx_dpll.c | 8 +- > arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 12 +- > arch/arm/mach-omap2/clkt2xxx_osc.c | 13 +- > arch/arm/mach-omap2/clkt2xxx_sys.c | 7 +- > arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 11 +- > arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 8 +- > arch/arm/mach-omap2/clkt_clksel.c | 194 +- > arch/arm/mach-omap2/clkt_dpll.c | 28 +- > arch/arm/mach-omap2/clkt_iclk.c | 31 +- > arch/arm/mach-omap2/clock.c | 845 ++---- > arch/arm/mach-omap2/clock.h | 356 ++- > arch/arm/mach-omap2/clock2420_data.c | 1986 -------------- > arch/arm/mach-omap2/clock2430.c | 8 +- > arch/arm/mach-omap2/clock2430_data.c | 2085 --------------- > arch/arm/mach-omap2/clock2xxx.c | 1 + > arch/arm/mach-omap2/clock2xxx.h | 47 +- > arch/arm/mach-omap2/clock33xx_data.c | 1107 -------- > arch/arm/mach-omap2/clock34xx.c | 51 +- > arch/arm/mach-omap2/clock3517.c | 24 +- > arch/arm/mach-omap2/clock36xx.c | 22 +- > arch/arm/mach-omap2/clock36xx.h | 2 +- > arch/arm/mach-omap2/clock3xxx.c | 6 +- > arch/arm/mach-omap2/clock3xxx.h | 6 +- > arch/arm/mach-omap2/clock3xxx_data.c | 3613 -------------------------- > arch/arm/mach-omap2/clock44xx_data.c | 3398 ------------------------ > arch/arm/mach-omap2/clock_common_data.c | 22 +- > arch/arm/mach-omap2/cm-regbits-24xx.h | 5 + > arch/arm/mach-omap2/cm-regbits-34xx.h | 31 + > arch/arm/mach-omap2/cm2xxx_3xxx.h | 1 + > arch/arm/mach-omap2/dpll3xxx.c | 226 +- > arch/arm/mach-omap2/dpll44xx.c | 21 +- > arch/arm/mach-omap2/io.c | 25 + > arch/arm/mach-omap2/omap_hwmod.c | 63 +- > arch/arm/mach-omap2/pm24xx.c | 4 +- > arch/arm/mach-omap2/prm-regbits-24xx.h | 2 + > arch/arm/mach-omap2/prm-regbits-34xx.h | 1 + > arch/arm/mach-omap2/prm2xxx_3xxx.h | 1 + > arch/arm/mach-omap2/scrm44xx.h | 2 + > 46 files changed, 11539 insertions(+), 13394 deletions(-) > create mode 100644 arch/arm/mach-omap2/cclock2420_data.c > create mode 100644 arch/arm/mach-omap2/cclock2430_data.c > create mode 100644 arch/arm/mach-omap2/cclock33xx_data.c > create mode 100644 arch/arm/mach-omap2/cclock3xxx_data.c > create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c > delete mode 100644 arch/arm/mach-omap2/clock2420_data.c > delete mode 100644 arch/arm/mach-omap2/clock2430_data.c > delete mode 100644 arch/arm/mach-omap2/clock33xx_data.c > delete mode 100644 arch/arm/mach-omap2/clock3xxx_data.c > delete mode 100644 arch/arm/mach-omap2/clock44xx_data.c > > -- > 1.7.9.5 ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 1:31 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette @ 2012-11-08 1:42 ` Tony Lindgren 2012-11-08 1:54 ` Mike Turquette 0 siblings, 1 reply; 67+ messages in thread From: Tony Lindgren @ 2012-11-08 1:42 UTC (permalink / raw) To: Mike Turquette Cc: Mike Turquette, paul, rnayak, linux-omap, linux-arm-kernel, patches Hi, * Mike Turquette <mturquette@linaro.org> [121107 17:33]: > Doh, I got the LAKML address wrong... > > Thankfully it's already up on some archives: > http://article.gmane.org/gmane.linux.ports.arm.omap/88824 > > For anyone interested in testing: > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > Regards, > Mike > > Quoting Mike Turquette (2012-11-07 17:12:35) > > From: Mike Turquette <mturquette@linaro.org> > > > > Hi all, > > > > This series is based on top of Paul's PRM/CM clean-up work. It is a > > refresh of the patches Rajendra sent out a while back[1], with the > > addition of several fixes for PM regressions[2] across several > > platforms. > > > > I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF > > patches (delta is zero) and also suspend/resume. > > > > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > > appears sane. However Panda-ES never comes back from suspend/resume. > > This problem exists on the PRM/CM branch I based on and was not > > introduced by this series. I am investigating that independently of > > this series. Cool! Do we still have some omaps that have issues booting with these? Regards, Tony > > Anyone wanting to pull the work can find it at: > > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771 > > [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015 ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 1:42 ` Tony Lindgren @ 2012-11-08 1:54 ` Mike Turquette 2012-11-08 2:50 ` Paul Walmsley 0 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 1:54 UTC (permalink / raw) To: Tony Lindgren; +Cc: paul, rnayak, linux-omap, linux-arm-kernel, patches Quoting Tony Lindgren (2012-11-07 17:42:18) > Hi, > > * Mike Turquette <mturquette@linaro.org> [121107 17:33]: > > Doh, I got the LAKML address wrong... > > > > Thankfully it's already up on some archives: > > http://article.gmane.org/gmane.linux.ports.arm.omap/88824 > > > > For anyone interested in testing: > > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > > > Regards, > > Mike > > > > Quoting Mike Turquette (2012-11-07 17:12:35) > > > From: Mike Turquette <mturquette@linaro.org> > > > > > > Hi all, > > > > > > This series is based on top of Paul's PRM/CM clean-up work. It is a > > > refresh of the patches Rajendra sent out a while back[1], with the > > > addition of several fixes for PM regressions[2] across several > > > platforms. > > > > > > I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF > > > patches (delta is zero) and also suspend/resume. > > > > > > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > > > appears sane. However Panda-ES never comes back from suspend/resume. > > > This problem exists on the PRM/CM branch I based on and was not > > > introduced by this series. I am investigating that independently of > > > this series. > > Cool! Do we still have some omaps that have issues booting with > these? > We shouldn't (fingers crossed). I've just now stolen a Beagle and a Bone to test, but I'm going to have to get bootloaders and a userspace all set up for them which will take some time. I believe Paul is planning on putting this series through his automated test rig. Regards, Mike > Regards, > > Tony > > > > > Anyone wanting to pull the work can find it at: > > > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > > > > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771 > > > [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015 ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 1:54 ` Mike Turquette @ 2012-11-08 2:50 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-08 2:50 UTC (permalink / raw) To: Mike Turquette Cc: Tony Lindgren, rnayak, linux-omap, linux-arm-kernel, patches On Wed, 7 Nov 2012, Mike Turquette wrote: > I believe Paul is planning on putting this series through his automated > test rig. Indeed and this is underway now. - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (21 preceding siblings ...) 2012-11-08 1:31 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette @ 2012-11-08 5:02 ` Rajendra Nayak 2012-11-08 5:19 ` Mike Turquette [not found] ` <1352337181-29427-15-git-send-email-mturquette@ti.com> ` (5 subsequent siblings) 28 siblings, 1 reply; 67+ messages in thread From: Rajendra Nayak @ 2012-11-08 5:02 UTC (permalink / raw) To: Mike Turquette Cc: paul, linux-omap, linux-arm-kernel, patches, Mike Turquette On Thursday 08 November 2012 06:42 AM, Mike Turquette wrote: > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > appears sane. However Panda-ES never comes back from suspend/resume. > This problem exists on the PRM/CM branch I based on and was not > introduced by this series. I am investigating that independently of > this series. Don't bother. Its been a know issue for a long time now. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg72056.html ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 5:02 ` Rajendra Nayak @ 2012-11-08 5:19 ` Mike Turquette 2012-11-08 19:20 ` Kevin Hilman 0 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 5:19 UTC (permalink / raw) To: Rajendra Nayak; +Cc: paul, linux-omap, linux-arm-kernel, patches Quoting Rajendra Nayak (2012-11-07 21:02:59) > On Thursday 08 November 2012 06:42 AM, Mike Turquette wrote: > > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > > appears sane. However Panda-ES never comes back from suspend/resume. > > This problem exists on the PRM/CM branch I based on and was not > > introduced by this series. I am investigating that independently of > > this series. > > Don't bother. Its been a know issue for a long time now. > http://www.mail-archive.com/linux-omap@vger.kernel.org/msg72056.html Thanks. I realized that after posting! I think there are fixes posted to the list so I will re-test with those fixes tomorrow. Regards, Mike ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 5:19 ` Mike Turquette @ 2012-11-08 19:20 ` Kevin Hilman 0 siblings, 0 replies; 67+ messages in thread From: Kevin Hilman @ 2012-11-08 19:20 UTC (permalink / raw) To: Mike Turquette Cc: Rajendra Nayak, paul, linux-omap, linux-arm-kernel, patches Mike Turquette <mturquette@ti.com> writes: > Quoting Rajendra Nayak (2012-11-07 21:02:59) >> On Thursday 08 November 2012 06:42 AM, Mike Turquette wrote: >> > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming >> > appears sane. However Panda-ES never comes back from suspend/resume. >> > This problem exists on the PRM/CM branch I based on and was not >> > introduced by this series. I am investigating that independently of >> > this series. >> >> Don't bother. Its been a know issue for a long time now. >> http://www.mail-archive.com/linux-omap@vger.kernel.org/msg72056.html > > Thanks. I realized that after posting! I think there are fixes posted > to the list so I will re-test with those fixes tomorrow. I recently sent a pull request for these: http://marc.info/?l=linux-omap&m=135224963505956&w=2 With that, suspend/resume is working fine on 4460/Panda-ES. Kevin ^ permalink raw reply [flat|nested] 67+ messages in thread
[parent not found: <1352337181-29427-15-git-send-email-mturquette@ti.com>]
* Re: [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk [not found] ` <1352337181-29427-15-git-send-email-mturquette@ti.com> @ 2012-11-08 18:08 ` Paul Walmsley 2012-11-08 21:52 ` Mike Turquette ` (2 more replies) 0 siblings, 3 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-08 18:08 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches On Wed, 7 Nov 2012, Mike Turquette wrote: > From: Rajendra Nayak <rnayak@ti.com> > > The patch is the output from a python script which converts > from the old OMAP clk format to COMMON clk format using a > JSON parser in between which was developed by Paul Walmsley. > > Signed-off-by: Rajendra Nayak <rnayak@ti.com> > [paul@pwsan.com: AM3517/05: dropped bogus hsotgusb "ick" and "fck" > clkdev aliases; added hsotgusb_fck alias; added emac_ick and emac_fck > aliases; replace omap2_init_clksel_parent() with > omap2_clksel_find_parent_index(); reflow macros and parent name > lists; add clkdm_name argument to DEFINE_STRUCT_CLK_HW_OMAP macros] > Signed-off-by: Mike Turquette <mturquette@ti.com> Am seeing warnings during the disable-unused-clocks phase of the boot on the OMAP3 test boards here. Log is included at the bottom of this E-mail, with some debugging added for extra context. The problem appears to be that the clock code is disabling clocks that are active in the hardware, but for which the clockdomain use count is 0, since they've never been enabled. Ideally there would be some way for the core CCF code to indicate to the underlying clock hardware implementation that the disable-unused-clock process is a 'force disable'. The OMAP clock hardware implementation code could then also put the clockdomain to sleep (and skip the warning) in such a circumstance. - Paul [ 2.685943] disabling sys_clkout1: ec = 0 [ 2.690277] disabling wdt1_ick: ec = 0 [ 2.694366] disabling cam_mclk: ec = 0 [ 2.698333] ------------[ cut here ]------------ [ 2.703216] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8() [ 2.712646] Modules linked in: [ 2.715911] [<c001c38c>] (unwind_backtrace+0x0/0xf0) from [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) [ 2.725799] [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) from [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) [ 2.735961] [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) from [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) [ 2.746520] [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) [ 2.757781] [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) from [<c0437b40>] (clk_disable_unused_subtree+0x20/0xbc) [ 2.769226] ---[ end trace ebefd5468131571a ]--- [ 2.774261] disabling mspro_fck: ec = 0 [ 2.778320] disabling ssi_ssr_fck_3430es2: ec = 0 [ 2.783355] disabling pka_ick: ec = 0 [ 2.787231] disabling sad2d_ick: ec = 0 [ 2.791259] ------------[ cut here ]------------ [ 2.796142] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8() [ 2.805572] Modules linked in: [ 2.808807] [<c001c38c>] (unwind_backtrace+0x0/0xf0) from [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) [ 2.818695] [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) from [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) [ 2.828857] [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) from [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) [ 2.839416] [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) [ 2.850677] [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) from [<c0437b40>] (clk_disable_unused_subtree+0x20/0xbc) [ 2.862121] ---[ end trace ebefd5468131571b ]--- [ 2.867065] disabling wdt3_ick: ec = 0 [ 2.871032] disabling des1_ick: ec = 0 [ 2.875030] disabling sha11_ick: ec = 0 [ 2.879089] disabling rng_ick: ec = 0 [ 2.882995] disabling aes1_ick: ec = 0 [ 2.886932] disabling ssi_ick_3430es2: ec = 0 [ 2.891601] disabling mspro_ick: ec = 0 [ 2.895660] disabling des2_ick: ec = 0 [ 2.899658] disabling sha12_ick: ec = 0 [ 2.903686] disabling aes2_ick: ec = 0 [ 2.907684] disabling icr_ick: ec = 0 [ 2.911621] disabling wdt3_fck: ec = 0 ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk 2012-11-08 18:08 ` [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk Paul Walmsley @ 2012-11-08 21:52 ` Mike Turquette 2012-11-08 22:01 ` Paul Walmsley 2012-11-08 23:31 ` [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks Mike Turquette 2 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-08 21:52 UTC (permalink / raw) To: Paul Walmsley; +Cc: rnayak, linux-omap, linux-arm-kernel, patches Quoting Paul Walmsley (2012-11-08 10:08:16) > On Wed, 7 Nov 2012, Mike Turquette wrote: > > > From: Rajendra Nayak <rnayak@ti.com> > > > > The patch is the output from a python script which converts > > from the old OMAP clk format to COMMON clk format using a > > JSON parser in between which was developed by Paul Walmsley. > > > > Signed-off-by: Rajendra Nayak <rnayak@ti.com> > > [paul@pwsan.com: AM3517/05: dropped bogus hsotgusb "ick" and "fck" > > clkdev aliases; added hsotgusb_fck alias; added emac_ick and emac_fck > > aliases; replace omap2_init_clksel_parent() with > > omap2_clksel_find_parent_index(); reflow macros and parent name > > lists; add clkdm_name argument to DEFINE_STRUCT_CLK_HW_OMAP macros] > > Signed-off-by: Mike Turquette <mturquette@ti.com> > > Am seeing warnings during the disable-unused-clocks phase of the boot > on the OMAP3 test boards here. Log is included at the bottom of this > E-mail, with some debugging added for extra context. The problem > appears to be that the clock code is disabling clocks that are active > in the hardware, but for which the clockdomain use count is 0, since > they've never been enabled. > Right. The old omap2_disabled_unused_clocks code used to call omap2_clk_enable before calling omap2_clk_disable. That approach is sort of "cooking the books" and the generic implementation in drivers/clk/clk.c simply disables the clocks (without first enabling), which is why these WARNs are new. > Ideally there would be some way for the core CCF code to indicate to the > underlying clock hardware implementation that the disable-unused-clock > process is a 'force disable'. The OMAP clock hardware implementation code > could then also put the clockdomain to sleep (and skip the warning) in > such a circumstance. > I'm looking at a few different ways to do that now. Regards, Mike > > - Paul > > [ 2.685943] disabling sys_clkout1: ec = 0 > [ 2.690277] disabling wdt1_ick: ec = 0 > [ 2.694366] disabling cam_mclk: ec = 0 > [ 2.698333] ------------[ cut here ]------------ > [ 2.703216] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8() > [ 2.712646] Modules linked in: > [ 2.715911] [<c001c38c>] (unwind_backtrace+0x0/0xf0) from [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) > [ 2.725799] [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) from [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) > [ 2.735961] [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) from [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) > [ 2.746520] [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) > [ 2.757781] [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) from [<c0437b40>] (clk_disable_unused_subtree+0x20/0xbc) > [ 2.769226] ---[ end trace ebefd5468131571a ]--- > [ 2.774261] disabling mspro_fck: ec = 0 > [ 2.778320] disabling ssi_ssr_fck_3430es2: ec = 0 > [ 2.783355] disabling pka_ick: ec = 0 > [ 2.787231] disabling sad2d_ick: ec = 0 > [ 2.791259] ------------[ cut here ]------------ > [ 2.796142] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8() > [ 2.805572] Modules linked in: > [ 2.808807] [<c001c38c>] (unwind_backtrace+0x0/0xf0) from [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) > [ 2.818695] [<c0043cd8>] (warn_slowpath_common+0x4c/0x64) from [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) > [ 2.828857] [<c0043d0c>] (warn_slowpath_null+0x1c/0x24) from [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) > [ 2.839416] [<c003705c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) > [ 2.850677] [<c0437bd0>] (clk_disable_unused_subtree+0xb0/0xbc) from [<c0437b40>] (clk_disable_unused_subtree+0x20/0xbc) > [ 2.862121] ---[ end trace ebefd5468131571b ]--- > [ 2.867065] disabling wdt3_ick: ec = 0 > [ 2.871032] disabling des1_ick: ec = 0 > [ 2.875030] disabling sha11_ick: ec = 0 > [ 2.879089] disabling rng_ick: ec = 0 > [ 2.882995] disabling aes1_ick: ec = 0 > [ 2.886932] disabling ssi_ick_3430es2: ec = 0 > [ 2.891601] disabling mspro_ick: ec = 0 > [ 2.895660] disabling des2_ick: ec = 0 > [ 2.899658] disabling sha12_ick: ec = 0 > [ 2.903686] disabling aes2_ick: ec = 0 > [ 2.907684] disabling icr_ick: ec = 0 > [ 2.911621] disabling wdt3_fck: ec = 0 ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk 2012-11-08 18:08 ` [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk Paul Walmsley 2012-11-08 21:52 ` Mike Turquette @ 2012-11-08 22:01 ` Paul Walmsley 2012-11-09 0:11 ` Paul Walmsley 2012-11-08 23:31 ` [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks Mike Turquette 2 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-08 22:01 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches On Thu, 8 Nov 2012, Paul Walmsley wrote: > Am seeing warnings during the disable-unused-clocks phase of the boot on > the OMAP3 test boards here. Similar problems during system suspend on 3530ES3 Beagle. Not sure what's causing these yet. At this point the clockdomain usecounts should be accurate. - Paul root@beagleboard:~# echo mem > /sys/power/state [ 36.488800] PM: Syncing filesystems ... done. [ 37.037841] Freezing user space processes ... (elapsed 0.01 seconds) done. [ 37.059600] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. [ 37.082885] Suspending console(s) (use no_console_suspend to debug) [ 37.222747] PM: suspend of devices complete after 129.791 msecs [ 37.228057] PM: late suspend of devices complete after 5.310 msecs [ 37.235412] ------------[ cut here ]------------ [ 37.235473] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8() [ 37.235504] Modules linked in: [ 37.235565] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c00435f8>] (warn_slowpath_common+0x4c/0x64) [ 37.235565] [<c00435f8>] (warn_slowpath_common+0x4c/0x64) from [<c004362c>] (warn_slowpath_null+0x1c/0x24) [ 37.235595] [<c004362c>] (warn_slowpath_null+0x1c/0x24) from [<c003697c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) [ 37.235626] [<c003697c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437d1c>] (__clk_disable+0x70/0xa8) [ 37.235656] [<c0437d1c>] (__clk_disable+0x70/0xa8) from [<c0437d74>] (clk_disable+0x20/0x34) [ 37.235687] [<c0437d74>] (clk_disable+0x20/0x34) from [<c002a330>] (_disable_clocks+0x18/0x68) [ 37.235717] [<c002a330>] (_disable_clocks+0x18/0x68) from [<c002b09c>] (_idle+0xf8/0x1b4) [ 37.235717] [<c002b09c>] (_idle+0xf8/0x1b4) from [<c002bf08>] (omap_hwmod_idle+0x24/0x40) [ 37.235748] [<c002bf08>] (omap_hwmod_idle+0x24/0x40) from [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) [ 37.235778] [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) from [<c002d024>] (_omap_device_deactivate+0x9c/0x138) [ 37.235778] [<c002d024>] (_omap_device_deactivate+0x9c/0x138) from [<c002d984>] (omap_device_idle+0x28/0x54) [ 37.235809] [<c002d984>] (omap_device_idle+0x28/0x54) from [<c002da48>] (_od_suspend_noirq+0x74/0x7c) [ 37.235839] [<c002da48>] (_od_suspend_noirq+0x74/0x7c) from [<c034cbec>] (dpm_run_callback.clone.9+0x30/0xb4) [ 37.235870] [<c034cbec>] (dpm_run_callback.clone.9+0x30/0xb4) from [<c034d440>] (dpm_suspend_end+0x364/0x554) [ 37.235870] [<c034d440>] (dpm_suspend_end+0x364/0x554) from [<c0084ec0>] (suspend_devices_and_enter+0xbc/0x2d0) [ 37.235900] [<c0084ec0>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c0085260>] (pm_suspend+0x18c/0x208) [ 37.235931] [<c0085260>] (pm_suspend+0x18c/0x208) from [<c00844f4>] (state_store+0x120/0x134) [ 37.235961] [<c00844f4>] (state_store+0x120/0x134) from [<c02d29b8>] (kobj_attr_store+0x14/0x20) [ 37.235992] [<c02d29b8>] (kobj_attr_store+0x14/0x20) from [<c017a630>] (sysfs_write_file+0x100/0x184) [ 37.236022] [<c017a630>] (sysfs_write_file+0x100/0x184) from [<c0116630>] (vfs_write+0xb4/0x148) [ 37.236022] [<c0116630>] (vfs_write+0xb4/0x148) from [<c01168b4>] (sys_write+0x40/0x6c) [ 37.236053] [<c01168b4>] (sys_write+0x40/0x6c) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c) [ 37.236083] ---[ end trace 86835b3ee8ec9dde ]--- [ 37.236083] ------------[ cut here ]------------ [ 37.236114] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 _clkdm_clk_hwmod_disable+0xc4/0xd8() [ 37.236145] Modules linked in: [ 37.236175] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c00435f8>] (warn_slowpath_common+0x4c/0x64) [ 37.236175] [<c00435f8>] (warn_slowpath_common+0x4c/0x64) from [<c004362c>] (warn_slowpath_null+0x1c/0x24) [ 37.236206] [<c004362c>] (warn_slowpath_null+0x1c/0x24) from [<c003697c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) [ 37.236236] [<c003697c>] (_clkdm_clk_hwmod_disable+0xc4/0xd8) from [<c0437d1c>] (__clk_disable+0x70/0xa8) [ 37.236267] [<c0437d1c>] (__clk_disable+0x70/0xa8) from [<c0437d74>] (clk_disable+0x20/0x34) [ 37.236267] [<c0437d74>] (clk_disable+0x20/0x34) from [<c002a330>] (_disable_clocks+0x18/0x68) [ 37.236297] [<c002a330>] (_disable_clocks+0x18/0x68) from [<c002b09c>] (_idle+0xf8/0x1b4) [ 37.236328] [<c002b09c>] (_idle+0xf8/0x1b4) from [<c002bf08>] (omap_hwmod_idle+0x24/0x40) [ 37.236328] [<c002bf08>] (omap_hwmod_idle+0x24/0x40) from [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) [ 37.236358] [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) from [<c002d024>] (_omap_device_deactivate+0x9c/0x138) [ 37.236389] [<c002d024>] (_omap_device_deactivate+0x9c/0x138) from [<c002d984>] (omap_device_idle+0x28/0x54) [ 37.236389] [<c002d984>] (omap_device_idle+0x28/0x54) from [<c002da48>] (_od_suspend_noirq+0x74/0x7c) [ 37.236419] [<c002da48>] (_od_suspend_noirq+0x74/0x7c) from [<c034cbec>] (dpm_run_callback.clone.9+0x30/0xb4) [ 37.236450] [<c034cbec>] (dpm_run_callback.clone.9+0x30/0xb4) from [<c034d440>] (dpm_suspend_end+0x364/0x554) [ 37.236450] [<c034d440>] (dpm_suspend_end+0x364/0x554) from [<c0084ec0>] (suspend_devices_and_enter+0xbc/0x2d0) [ 37.236480] [<c0084ec0>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c0085260>] (pm_suspend+0x18c/0x208) [ 37.236511] [<c0085260>] (pm_suspend+0x18c/0x208) from [<c00844f4>] (state_store+0x120/0x134) [ 37.236541] [<c00844f4>] (state_store+0x120/0x134) from [<c02d29b8>] (kobj_attr_store+0x14/0x20) [ 37.236541] [<c02d29b8>] (kobj_attr_store+0x14/0x20) from [<c017a630>] (sysfs_write_file+0x100/0x184) [ 37.236572] [<c017a630>] (sysfs_write_file+0x100/0x184) from [<c0116630>] (vfs_write+0xb4/0x148) [ 37.236602] [<c0116630>] (vfs_write+0xb4/0x148) from [<c01168b4>] (sys_write+0x40/0x6c) [ 37.236602] [<c01168b4>] (sys_write+0x40/0x6c) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c) [ 37.236633] ---[ end trace 86835b3ee8ec9ddf ]--- [ 37.237213] PM: noirq suspend of devices complete after 9.124 msecs [ 37.237304] Disabling non-boot CPUs ... [ 37.237792] Successfully put all powerdomains to target state [ 37.242034] PM: noirq resume of devices complete after 3.967 msecs [ 37.247161] PM: early resume of devices complete after 3.570 msecs [ 37.536956] PM: resume of devices complete after 289.550 msecs [ 37.815185] Restarting tasks ... done. root@beagleboard:~# ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk 2012-11-08 22:01 ` Paul Walmsley @ 2012-11-09 0:11 ` Paul Walmsley 2012-11-09 0:33 ` Paul Walmsley 2012-11-09 0:57 ` Mike Turquette 0 siblings, 2 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 0:11 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches On Thu, 8 Nov 2012, Paul Walmsley wrote: > On Thu, 8 Nov 2012, Paul Walmsley wrote: > > > Am seeing warnings during the disable-unused-clocks phase of the boot on > > the OMAP3 test boards here. > > Similar problems during system suspend on 3530ES3 Beagle. Not sure > what's causing these yet. At this point the clockdomain usecounts > should be accurate. Here's a redacted debugging log for these cases. The suspend events start around the 30 second mark. One observation is that dpll4_m5x2_ck and dpll4_m6x2_ck are never enabled. The tracebacks occur when something in the suspend path tries to disable those clocks. - Paul [ 0.135528] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck [ 0.135559] clockdomain: dpll4_clkdm: enabled [ 0.135589] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck [ 0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck [ 0.135711] clockdomain: dpll4_clkdm: disabled [ 0.135772] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck [ 0.135803] clockdomain: dpll4_clkdm: enabled [ 0.135833] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 0.135894] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck [ 0.135925] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck [ 0.135955] clockdomain: dpll4_clkdm: disabled [ 0.135986] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck [ 0.136016] clockdomain: dpll4_clkdm: enabled [ 0.136047] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 0.136138] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck [ 0.136169] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck [ 0.136169] clockdomain: dpll4_clkdm: disabled [ 0.136260] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck [ 0.136291] clockdomain: dpll4_clkdm: enabled [ 0.136322] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 0.140594] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck [ 0.140686] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck [ 0.140838] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck [ 0.140930] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck [ 0.141479] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck [ 0.141571] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck [ 0.141601] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck [ 0.141662] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck [ 0.141693] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck [ 0.141784] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck [ 0.141815] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck [ 0.141876] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck [ 3.399200] disabling clkdm dpll4_clkdm during disable of clk dpll4_m6x2_ck [ 3.417694] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) [ 3.445251] ---[ end trace 72e2d7bdcf98ea8b ]--- [ 3.450134] disabling clkdm dpll4_clkdm during disable of clk dpll4_m5x2_ck [ 3.453918] clockdomain: dpll4_clkdm: disabled [ 3.477569] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) [ 3.505096] ---[ end trace 72e2d7bdcf98ea8c ]--- [ 3.531280] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) [ 3.558807] ---[ end trace 72e2d7bdcf98ea8d ]--- [ 38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck [ 38.999267] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) [ 38.999816] ---[ end trace 72e2d7bdcf98ea8e ]--- [ 38.999816] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck [ 38.999908] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) [ 39.000366] ---[ end trace 72e2d7bdcf98ea8f ]--- [ 42.169647] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck [ 42.169647] clockdomain: dpll4_clkdm: enabled [ 42.169677] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 45.730346] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) [ 45.795654] ---[ end trace 72e2d7bdcf98ea90 ]--- ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk 2012-11-09 0:11 ` Paul Walmsley @ 2012-11-09 0:33 ` Paul Walmsley 2012-11-09 0:49 ` Paul Walmsley 2012-11-09 0:57 ` Mike Turquette 1 sibling, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 0:33 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches On Fri, 9 Nov 2012, Paul Walmsley wrote: > One observation is that dpll4_m5x2_ck and dpll4_m6x2_ck are never enabled. > The tracebacks occur when something in the suspend path tries to disable > those clocks. Sorry, this part is inaccurate - I misread the trace. The suspend path errors are coming from a disable of dpll4_m2x2_ck which is probably caused by the disable of i2c1_fck. Here's the unredacted trace of this section. The enables and disables of dpll4_m2x2_ck from the entire log appear to be balanced: [ 0.135589] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck [ 0.135833] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 0.135894] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck [ 0.136047] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 0.136138] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck [ 0.136322] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck [ 38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck - Paul [ 38.986267] PM: suspend of devices complete after 129.760 msecs [ 38.991668] PM: late suspend of devices complete after 5.340 msecs [ 38.996459] disabling clkdm core_l4_clkdm during disable of clk mmchs1_fck [ 38.998718] disabling clkdm per_clkdm during disable of clk uart3_fck [ 38.998840] disabling clkdm core_l4_clkdm during disable of clk uart2_fck [ 38.998931] disabling clkdm core_l4_clkdm during disable of clk uart1_fck [ 38.999114] disabling clkdm core_l4_clkdm during disable of clk i2c1_fck [ 38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck [ 38.999145] ------------[ cut here ]------------ [ 38.999206] WARNING: at arch/arm/mach-omap2/clockdomain.c:962 _clkdm_clk_hwmod_disable+0xa4/0xf8() [ 38.999206] Modules linked in: [ 38.999267] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) [ 38.999298] [<c0043680>] (warn_slowpath_common+0x4c/0x64) from [<c00436b4>] (warn_slowpath_null+0x1c/0x24) [ 38.999328] [<c00436b4>] (warn_slowpath_null+0x1c/0x24) from [<c003695c>] (_clkdm_clk_hwmod_disable+0xa4/0xf8) [ 38.999359] [<c003695c>] (_clkdm_clk_hwmod_disable+0xa4/0xf8) from [<c0437d38>] (__clk_disable+0x70/0xac) [ 38.999389] [<c0437d38>] (__clk_disable+0x70/0xac) from [<c0437d94>] (clk_disable+0x20/0x34) [ 38.999420] [<c0437d94>] (clk_disable+0x20/0x34) from [<c002a330>] (_disable_clocks+0x18/0x68) [ 38.999420] [<c002a330>] (_disable_clocks+0x18/0x68) from [<c002b09c>] (_idle+0xf8/0x1b4) [ 38.999450] [<c002b09c>] (_idle+0xf8/0x1b4) from [<c002bf08>] (omap_hwmod_idle+0x24/0x40) [ 38.999481] [<c002bf08>] (omap_hwmod_idle+0x24/0x40) from [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) [ 38.999511] [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) from [<c002d024>] (_omap_device_deactivate+0x9c/0x138) [ 38.999511] [<c002d024>] (_omap_device_deactivate+0x9c/0x138) from [<c002d984>] (omap_device_idle+0x28/0x54) [ 38.999542] [<c002d984>] (omap_device_idle+0x28/0x54) from [<c002da48>] (_od_suspend_noirq+0x74/0x7c) [ 38.999572] [<c002da48>] (_od_suspend_noirq+0x74/0x7c) from [<c034cc6c>] (dpm_run_callback.clone.9+0x30/0xb4) [ 38.999603] [<c034cc6c>] (dpm_run_callback.clone.9+0x30/0xb4) from [<c034d4c0>] (dpm_suspend_end+0x364/0x554) [ 38.999603] [<c034d4c0>] (dpm_suspend_end+0x364/0x554) from [<c0084f48>] (suspend_devices_and_enter+0xbc/0x2d0) [ 38.999633] [<c0084f48>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c00852e8>] (pm_suspend+0x18c/0x208) [ 38.999664] [<c00852e8>] (pm_suspend+0x18c/0x208) from [<c008457c>] (state_store+0x120/0x134) [ 38.999694] [<c008457c>] (state_store+0x120/0x134) from [<c02d2a38>] (kobj_attr_store+0x14/0x20) [ 38.999725] [<c02d2a38>] (kobj_attr_store+0x14/0x20) from [<c017a6b8>] (sysfs_write_file+0x100/0x184) [ 38.999755] [<c017a6b8>] (sysfs_write_file+0x100/0x184) from [<c01166b8>] (vfs_write+0xb4/0x148) [ 38.999755] [<c01166b8>] (vfs_write+0xb4/0x148) from [<c011693c>] (sys_write+0x40/0x6c) [ 38.999786] [<c011693c>] (sys_write+0x40/0x6c) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c) [ 38.999816] ---[ end trace 72e2d7bdcf98ea8e ]--- [ 38.999816] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck [ 38.999847] ------------[ cut here ]------------ [ 38.999847] WARNING: at arch/arm/mach-omap2/clockdomain.c:962 _clkdm_clk_hwmod_disable+0xa4/0xf8() [ 38.999877] Modules linked in: [ 38.999908] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) [ 38.999938] [<c0043680>] (warn_slowpath_common+0x4c/0x64) from [<c00436b4>] (warn_slowpath_null+0x1c/0x24) [ 38.999938] [<c00436b4>] (warn_slowpath_null+0x1c/0x24) from [<c003695c>] (_clkdm_clk_hwmod_disable+0xa4/0xf8) [ 38.999969] [<c003695c>] (_clkdm_clk_hwmod_disable+0xa4/0xf8) from [<c0437d38>] (__clk_disable+0x70/0xac) [ 38.999999] [<c0437d38>] (__clk_disable+0x70/0xac) from [<c0437d94>] (clk_disable+0x20/0x34) [ 38.999999] [<c0437d94>] (clk_disable+0x20/0x34) from [<c002a330>] (_disable_clocks+0x18/0x68) [ 39.000030] [<c002a330>] (_disable_clocks+0x18/0x68) from [<c002b09c>] (_idle+0xf8/0x1b4) [ 39.000061] [<c002b09c>] (_idle+0xf8/0x1b4) from [<c002bf08>] (omap_hwmod_idle+0x24/0x40) [ 39.000061] [<c002bf08>] (omap_hwmod_idle+0x24/0x40) from [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) [ 39.000091] [<c002ce34>] (omap_device_idle_hwmods+0x24/0x3c) from [<c002d024>] (_omap_device_deactivate+0x9c/0x138) [ 39.000122] [<c002d024>] (_omap_device_deactivate+0x9c/0x138) from [<c002d984>] (omap_device_idle+0x28/0x54) [ 39.000152] [<c002d984>] (omap_device_idle+0x28/0x54) from [<c002da48>] (_od_suspend_noirq+0x74/0x7c) [ 39.000152] [<c002da48>] (_od_suspend_noirq+0x74/0x7c) from [<c034cc6c>] (dpm_run_callback.clone.9+0x30/0xb4) [ 39.000183] [<c034cc6c>] (dpm_run_callback.clone.9+0x30/0xb4) from [<c034d4c0>] (dpm_suspend_end+0x364/0x554) [ 39.000213] [<c034d4c0>] (dpm_suspend_end+0x364/0x554) from [<c0084f48>] (suspend_devices_and_enter+0xbc/0x2d0) [ 39.000213] [<c0084f48>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c00852e8>] (pm_suspend+0x18c/0x208) [ 39.000244] [<c00852e8>] (pm_suspend+0x18c/0x208) from [<c008457c>] (state_store+0x120/0x134) [ 39.000274] [<c008457c>] (state_store+0x120/0x134) from [<c02d2a38>] (kobj_attr_store+0x14/0x20) [ 39.000274] [<c02d2a38>] (kobj_attr_store+0x14/0x20) from [<c017a6b8>] (sysfs_write_file+0x100/0x184) [ 39.000305] [<c017a6b8>] (sysfs_write_file+0x100/0x184) from [<c01166b8>] (vfs_write+0xb4/0x148) [ 39.000335] [<c01166b8>] (vfs_write+0xb4/0x148) from [<c011693c>] (sys_write+0x40/0x6c) [ 39.000366] [<c011693c>] (sys_write+0x40/0x6c) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c) [ 39.000366] ---[ end trace 72e2d7bdcf98ea8f ]--- [ 39.000823] disabling clkdm wkup_clkdm during disable of clk gpio1_ick [ 39.000976] PM: noirq suspend of devices complete after 9.307 msecs [ 39.001068] Disabling non-boot CPUs ... ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk 2012-11-09 0:33 ` Paul Walmsley @ 2012-11-09 0:49 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 0:49 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches On Fri, 9 Nov 2012, Paul Walmsley wrote: > The enables and disables of dpll4_m2x2_ck from the entire log appear to be balanced: Looks like this is an artifact of the disable-unused-clocks problem. The disable of dpll4_m6x2_ck during that phase removes the usecount that was previously added by the enable of dpll4_m2x2_ck. So fixing that problem should clean this one up. - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk 2012-11-09 0:11 ` Paul Walmsley 2012-11-09 0:33 ` Paul Walmsley @ 2012-11-09 0:57 ` Mike Turquette 1 sibling, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-09 0:57 UTC (permalink / raw) To: Paul Walmsley; +Cc: rnayak, linux-omap, linux-arm-kernel, patches Quoting Paul Walmsley (2012-11-08 16:11:12) > On Thu, 8 Nov 2012, Paul Walmsley wrote: > > > On Thu, 8 Nov 2012, Paul Walmsley wrote: > > > > > Am seeing warnings during the disable-unused-clocks phase of the boot on > > > the OMAP3 test boards here. > > > > Similar problems during system suspend on 3530ES3 Beagle. Not sure > > what's causing these yet. At this point the clockdomain usecounts > > should be accurate. > > Here's a redacted debugging log for these cases. The suspend events start > around the 30 second mark. > > One observation is that dpll4_m5x2_ck and dpll4_m6x2_ck are never enabled. > The tracebacks occur when something in the suspend path tries to disable > those clocks. Hi Paul, My instrumentation shows that dpll4_ck & dpll4_m2x2_ck are triggering the WARNs: [ 25.214599] _clkdm_clk_hwmod_disable: dpll4_m2x2_ck [ 25.214599] ------------[ cut here ]------------ [ 25.214660] WARNING: at arch/arm/mach-omap2/clockdomain.c:967 _clkdm_clk_hwmod_disable+0xd0/0x118() ... [ 25.215209] _clkdm_clk_hwmod_disable: dpll4_ck [ 25.215209] ------------[ cut here ]------------ [ 25.215240] WARNING: at arch/arm/mach-omap2/clockdomain.c:967 _clkdm_clk_hwmod_disable+0xd0/0x118() Patch that give that information: diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 64e5046..a9d5965 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -947,7 +947,8 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) return 0; } -static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) +static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm, + struct clk *clk) { unsigned long flags; @@ -957,6 +958,9 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) spin_lock_irqsave(&clkdm->lock, flags); if (atomic_read(&clkdm->usecount) == 0) { + if (clk) + pr_err("%s: %s\n", __func__, __clk_get_name(clk)); + spin_unlock_irqrestore(&clkdm->lock, flags); WARN_ON(1); /* underflow */ return -ERANGE; @@ -1026,7 +1030,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) if (!clk) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + return _clkdm_clk_hwmod_disable(clkdm, clk); } /** @@ -1089,6 +1093,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) if (!oh) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + return _clkdm_clk_hwmod_disable(clkdm, NULL); } Regards, Mike > > > - Paul > > [ 0.135528] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 0.135559] clockdomain: dpll4_clkdm: enabled > [ 0.135589] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck > [ 0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck > [ 0.135711] clockdomain: dpll4_clkdm: disabled > [ 0.135772] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 0.135803] clockdomain: dpll4_clkdm: enabled > [ 0.135833] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 0.135894] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck > [ 0.135925] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck > [ 0.135955] clockdomain: dpll4_clkdm: disabled > [ 0.135986] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 0.136016] clockdomain: dpll4_clkdm: enabled > [ 0.136047] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 0.136138] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck > [ 0.136169] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck > [ 0.136169] clockdomain: dpll4_clkdm: disabled > [ 0.136260] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 0.136291] clockdomain: dpll4_clkdm: enabled > [ 0.136322] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 0.140594] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck > [ 0.140686] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck > [ 0.140838] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck > [ 0.140930] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck > [ 0.141479] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck > [ 0.141571] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck > [ 0.141601] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck > [ 0.141662] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck > [ 0.141693] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck > [ 0.141784] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck > [ 0.141815] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck > [ 0.141876] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck > [ 3.399200] disabling clkdm dpll4_clkdm during disable of clk dpll4_m6x2_ck > [ 3.417694] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) > [ 3.445251] ---[ end trace 72e2d7bdcf98ea8b ]--- > [ 3.450134] disabling clkdm dpll4_clkdm during disable of clk dpll4_m5x2_ck > [ 3.453918] clockdomain: dpll4_clkdm: disabled > [ 3.477569] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) > [ 3.505096] ---[ end trace 72e2d7bdcf98ea8c ]--- > [ 3.531280] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) > [ 3.558807] ---[ end trace 72e2d7bdcf98ea8d ]--- > [ 38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck > [ 38.999267] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) > [ 38.999816] ---[ end trace 72e2d7bdcf98ea8e ]--- > [ 38.999816] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck > [ 38.999908] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) > [ 39.000366] ---[ end trace 72e2d7bdcf98ea8f ]--- > [ 42.169647] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 42.169647] clockdomain: dpll4_clkdm: enabled > [ 42.169677] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 45.730346] [<c001c1cc>] (unwind_backtrace+0x0/0xf0) from [<c0043680>] (warn_slowpath_common+0x4c/0x64) > [ 45.795654] ---[ end trace 72e2d7bdcf98ea90 ]--- ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks 2012-11-08 18:08 ` [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk Paul Walmsley 2012-11-08 21:52 ` Mike Turquette 2012-11-08 22:01 ` Paul Walmsley @ 2012-11-08 23:31 ` Mike Turquette 2012-11-09 0:58 ` Paul Walmsley 2 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-08 23:31 UTC (permalink / raw) To: paul; +Cc: linux-omap, linux-arm-kernel, Mike Turquette The OMAP port to the common clk framework[1] resulted in spurious WARNs while disable unused clocks. This is due to _clkdm_clk_hwmod_disable catching clkdm->usecount's with a value of zero. Even less desirable it would not allow the clkdm_clk_disable function pointer to get called due to an early return of -ERANGE. This patch adds a check for such a corner case by skipping the WARN and early return in the event that clkdm->usecount and clk->enable_usecount are both zero. Presumably this could only happen during the check for unused clocks at boot-time. [1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824 Signed-off-by: Mike Turquette <mturquette@ti.com> --- arch/arm/mach-omap2/clockdomain.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 64e5046..b0c0ce6 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -947,16 +947,22 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) return 0; } -static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) +static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm, + struct clk *clk) { unsigned long flags; + int clk_enable_count = 1; if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; spin_lock_irqsave(&clkdm->lock, flags); - if (atomic_read(&clkdm->usecount) == 0) { + /* corner case: disabling unused clocks */ + if (clk) + clk_enable_count = __clk_get_enable_count(clk); + + if (atomic_read(&clkdm->usecount) == 0 && clk_enable_count) { spin_unlock_irqrestore(&clkdm->lock, flags); WARN_ON(1); /* underflow */ return -ERANGE; @@ -1026,7 +1032,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) if (!clk) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + return _clkdm_clk_hwmod_disable(clkdm, clk); } /** @@ -1089,6 +1095,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) if (!oh) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + return _clkdm_clk_hwmod_disable(clkdm, NULL); } -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks 2012-11-08 23:31 ` [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks Mike Turquette @ 2012-11-09 0:58 ` Paul Walmsley 2012-11-09 1:17 ` Mike Turquette 0 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 0:58 UTC (permalink / raw) To: Mike Turquette; +Cc: linux-omap, linux-arm-kernel On Thu, 8 Nov 2012, Mike Turquette wrote: > The OMAP port to the common clk framework[1] resulted in spurious WARNs > while disable unused clocks. This is due to _clkdm_clk_hwmod_disable > catching clkdm->usecount's with a value of zero. Even less desirable it > would not allow the clkdm_clk_disable function pointer to get called due > to an early return of -ERANGE. > > This patch adds a check for such a corner case by skipping the WARN and > early return in the event that clkdm->usecount and clk->enable_usecount > are both zero. Presumably this could only happen during the check for > unused clocks at boot-time. > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824 > > Signed-off-by: Mike Turquette <mturquette@ti.com> I don't think this is going to work, as it currently stands. The code will just bypass the warning and the error return. The clockdomain usecount still will be decremented, which is going to cause problems since the usecount will be inaccurate. - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks 2012-11-09 0:58 ` Paul Walmsley @ 2012-11-09 1:17 ` Mike Turquette 2012-11-09 19:06 ` Paul Walmsley 0 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-09 1:17 UTC (permalink / raw) To: Paul Walmsley; +Cc: linux-omap, linux-arm-kernel Quoting Paul Walmsley (2012-11-08 16:58:21) > On Thu, 8 Nov 2012, Mike Turquette wrote: > > > The OMAP port to the common clk framework[1] resulted in spurious WARNs > > while disable unused clocks. This is due to _clkdm_clk_hwmod_disable > > catching clkdm->usecount's with a value of zero. Even less desirable it > > would not allow the clkdm_clk_disable function pointer to get called due > > to an early return of -ERANGE. > > > > This patch adds a check for such a corner case by skipping the WARN and > > early return in the event that clkdm->usecount and clk->enable_usecount > > are both zero. Presumably this could only happen during the check for > > unused clocks at boot-time. > > > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824 > > > > Signed-off-by: Mike Turquette <mturquette@ti.com> > > I don't think this is going to work, as it currently stands. The code > will just bypass the warning and the error return. The clockdomain > usecount still will be decremented, which is going to cause problems since > the usecount will be inaccurate. > You're right. In my rush I glossed over the clkdm decrement part. In light of the suspend/resume issues I'm not sure this approach is really valid. I think getting to the bottom of those issues will give the final word. Regards, Mike > > - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks 2012-11-09 1:17 ` Mike Turquette @ 2012-11-09 19:06 ` Paul Walmsley 2012-11-09 19:08 ` Paul Walmsley 0 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 19:06 UTC (permalink / raw) To: Mike Turquette; +Cc: linux-omap, linux-arm-kernel On Thu, 8 Nov 2012, Mike Turquette wrote: > You're right. In my rush I glossed over the clkdm decrement part. In > light of the suspend/resume issues I'm not sure this approach is really > valid. I think getting to the bottom of those issues will give the > final word. What do you think about something like this? It's still under test and review here, but seems to avoid the warnings on 3530ES3 Beagle at least. The usage of __clk_get_enable_count() in this code still seems like a hack to me. It would be better for the CCF to call a different clk_hw_ops function pointer for the disable-unused-clocks case. But if you agree, and plan to fix this, or have some other cleaner fix in mind for the near future, then something like this seems reasonable for the short term to me. What do you think? - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks 2012-11-09 19:06 ` Paul Walmsley @ 2012-11-09 19:08 ` Paul Walmsley 2012-11-09 19:40 ` Mike Turquette 0 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 19:08 UTC (permalink / raw) To: Mike Turquette; +Cc: linux-omap, linux-arm-kernel On Fri, 9 Nov 2012, Paul Walmsley wrote: > On Thu, 8 Nov 2012, Mike Turquette wrote: > > > You're right. In my rush I glossed over the clkdm decrement part. In > > light of the suspend/resume issues I'm not sure this approach is really > > valid. I think getting to the bottom of those issues will give the > > final word. > > What do you think about something like this? It's still under test and > review here, but seems to avoid the warnings on 3530ES3 Beagle at least. > > The usage of __clk_get_enable_count() in this code still seems like a hack > to me. It would be better for the CCF to call a different clk_hw_ops > function pointer for the disable-unused-clocks case. But if you agree, > and plan to fix this, or have some other cleaner fix in mind for the near > future, then something like this seems reasonable for the short term to > me. What do you think? Here's the patch. The changes to clkdm_clk_disable() are the important ones, the rest can be ignored for the purposes of this review. - Paul From: Mike Turquette <mturquette@ti.com> Date: Fri, 9 Nov 2012 11:28:42 -0700 Subject: [PATCH] ARM: OMAP2+: clockdomain: bypass clockdomain handling when disabling unused clks The OMAP port to the common clk framework[1] resulted in spurious WARNs while disable unused clocks. This is due to _clkdm_clk_hwmod_disable catching clkdm->usecount's with a value of zero. Even less desirable it would not allow the clkdm_clk_disable function pointer to get called due to an early return of -ERANGE. This patch adds a check for such a corner case by skipping the WARN and early return in the event that clkdm->usecount and clk->enable_usecount are both zero. Presumably this could only happen during the check for unused clocks at boot-time. [1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824 Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: split the hwmod and clock disable cases; modified the code to skip the clockdomain handling during the disable-unused-clocks phase] --- arch/arm/mach-omap2/clockdomain.c | 91 ++++++++++++++++++++++--------------- 1 file changed, 54 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 64e5046..1bd0ff0 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -22,6 +22,7 @@ #include <linux/clk.h> #include <linux/limits.h> #include <linux/err.h> +#include <linux/clk-private.h> #include <linux/io.h> @@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) return 0; } -static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) -{ - unsigned long flags; - - if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) - return -EINVAL; - - spin_lock_irqsave(&clkdm->lock, flags); - - if (atomic_read(&clkdm->usecount) == 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); - WARN_ON(1); /* underflow */ - return -ERANGE; - } - - if (atomic_dec_return(&clkdm->usecount) > 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); - return 0; - } - - arch_clkdm->clkdm_clk_disable(clkdm); - pwrdm_state_switch(clkdm->pwrdm.ptr); - spin_unlock_irqrestore(&clkdm->lock, flags); - - pr_debug("clockdomain: %s: disabled\n", clkdm->name); - - return 0; -} - /** * clkdm_clk_enable - add an enabled downstream clock to this clkdm * @clkdm: struct clockdomain * @@ -1018,15 +990,39 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) */ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) { - /* - * XXX Rewrite this code to maintain a list of enabled - * downstream clocks for debugging purposes? - */ + unsigned long flags; + int force_disable = 0; - if (!clk) + if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + spin_lock_irqsave(&clkdm->lock, flags); + + /* corner case: disabling unused clocks */ + force_disable = (__clk_get_enable_count(clk) == 0) ? 1 : 0; + if (force_disable) + goto ccd_exit; + + if (atomic_read(&clkdm->usecount) == 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + WARN_ON(1); /* underflow */ + return -ERANGE; + } + + if (atomic_dec_return(&clkdm->usecount) > 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + return 0; + } + + arch_clkdm->clkdm_clk_disable(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); + + pr_debug("clockdomain: %s: disabled\n", clkdm->name); + +ccd_exit: + spin_unlock_irqrestore(&clkdm->lock, flags); + + return 0; } /** @@ -1077,6 +1073,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh) */ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) { + unsigned long flags; + /* The clkdm attribute does not exist yet prior OMAP4 */ if (cpu_is_omap24xx() || cpu_is_omap34xx()) return 0; @@ -1086,9 +1084,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) * downstream hwmods for debugging purposes? */ - if (!oh) + if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + spin_lock_irqsave(&clkdm->lock, flags); + + if (atomic_read(&clkdm->usecount) == 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + WARN_ON(1); /* underflow */ + return -ERANGE; + } + + if (atomic_dec_return(&clkdm->usecount) > 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + return 0; + } + + arch_clkdm->clkdm_clk_disable(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); + spin_unlock_irqrestore(&clkdm->lock, flags); + + pr_debug("clockdomain: %s: disabled\n", clkdm->name); + + return 0; } -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks 2012-11-09 19:08 ` Paul Walmsley @ 2012-11-09 19:40 ` Mike Turquette 2012-11-09 19:52 ` Paul Walmsley 0 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-09 19:40 UTC (permalink / raw) To: Paul Walmsley; +Cc: linux-omap, linux-arm-kernel Quoting Paul Walmsley (2012-11-09 11:08:00) > On Fri, 9 Nov 2012, Paul Walmsley wrote: > > > On Thu, 8 Nov 2012, Mike Turquette wrote: > > > > > You're right. In my rush I glossed over the clkdm decrement part. In > > > light of the suspend/resume issues I'm not sure this approach is really > > > valid. I think getting to the bottom of those issues will give the > > > final word. > > > > What do you think about something like this? It's still under test and > > review here, but seems to avoid the warnings on 3530ES3 Beagle at least. > > > > The usage of __clk_get_enable_count() in this code still seems like a hack > > to me. It would be better for the CCF to call a different clk_hw_ops > > function pointer for the disable-unused-clocks case. But if you agree, > > and plan to fix this, or have some other cleaner fix in mind for the near > > future, then something like this seems reasonable for the short term to > > me. What do you think? > For avoiding the WARNs, this seems fine to me. And I agree that a new clk_ops function pointer is needed. Maybe something like, void (*unused_disable)(struct clk_hw *hw); But I'm OK with the below patch in the short term. I just have one question: did you observe any PM regressions by skipping the clkdm programming? Thanks, Mike > Here's the patch. The changes to clkdm_clk_disable() are the important > ones, the rest can be ignored for the purposes of this review. > > > - Paul > > From: Mike Turquette <mturquette@ti.com> > Date: Fri, 9 Nov 2012 11:28:42 -0700 > Subject: [PATCH] ARM: OMAP2+: clockdomain: bypass clockdomain handling when > disabling unused clks > > The OMAP port to the common clk framework[1] resulted in spurious WARNs > while disable unused clocks. This is due to _clkdm_clk_hwmod_disable > catching clkdm->usecount's with a value of zero. Even less desirable it > would not allow the clkdm_clk_disable function pointer to get called due > to an early return of -ERANGE. > > This patch adds a check for such a corner case by skipping the WARN and > early return in the event that clkdm->usecount and clk->enable_usecount > are both zero. Presumably this could only happen during the check for > unused clocks at boot-time. > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824 > > Signed-off-by: Mike Turquette <mturquette@ti.com> > [paul@pwsan.com: split the hwmod and clock disable cases; modified the > code to skip the clockdomain handling during the disable-unused-clocks phase] > --- > arch/arm/mach-omap2/clockdomain.c | 91 ++++++++++++++++++++++--------------- > 1 file changed, 54 insertions(+), 37 deletions(-) > > diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c > index 64e5046..1bd0ff0 100644 > --- a/arch/arm/mach-omap2/clockdomain.c > +++ b/arch/arm/mach-omap2/clockdomain.c > @@ -22,6 +22,7 @@ > #include <linux/clk.h> > #include <linux/limits.h> > #include <linux/err.h> > +#include <linux/clk-private.h> > > #include <linux/io.h> > > @@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) > return 0; > } > > -static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) > -{ > - unsigned long flags; > - > - if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) > - return -EINVAL; > - > - spin_lock_irqsave(&clkdm->lock, flags); > - > - if (atomic_read(&clkdm->usecount) == 0) { > - spin_unlock_irqrestore(&clkdm->lock, flags); > - WARN_ON(1); /* underflow */ > - return -ERANGE; > - } > - > - if (atomic_dec_return(&clkdm->usecount) > 0) { > - spin_unlock_irqrestore(&clkdm->lock, flags); > - return 0; > - } > - > - arch_clkdm->clkdm_clk_disable(clkdm); > - pwrdm_state_switch(clkdm->pwrdm.ptr); > - spin_unlock_irqrestore(&clkdm->lock, flags); > - > - pr_debug("clockdomain: %s: disabled\n", clkdm->name); > - > - return 0; > -} > - > /** > * clkdm_clk_enable - add an enabled downstream clock to this clkdm > * @clkdm: struct clockdomain * > @@ -1018,15 +990,39 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) > */ > int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) > { > - /* > - * XXX Rewrite this code to maintain a list of enabled > - * downstream clocks for debugging purposes? > - */ > + unsigned long flags; > + int force_disable = 0; > > - if (!clk) > + if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) > return -EINVAL; > > - return _clkdm_clk_hwmod_disable(clkdm); > + spin_lock_irqsave(&clkdm->lock, flags); > + > + /* corner case: disabling unused clocks */ > + force_disable = (__clk_get_enable_count(clk) == 0) ? 1 : 0; > + if (force_disable) > + goto ccd_exit; > + > + if (atomic_read(&clkdm->usecount) == 0) { > + spin_unlock_irqrestore(&clkdm->lock, flags); > + WARN_ON(1); /* underflow */ > + return -ERANGE; > + } > + > + if (atomic_dec_return(&clkdm->usecount) > 0) { > + spin_unlock_irqrestore(&clkdm->lock, flags); > + return 0; > + } > + > + arch_clkdm->clkdm_clk_disable(clkdm); > + pwrdm_state_switch(clkdm->pwrdm.ptr); > + > + pr_debug("clockdomain: %s: disabled\n", clkdm->name); > + > +ccd_exit: > + spin_unlock_irqrestore(&clkdm->lock, flags); > + > + return 0; > } > > /** > @@ -1077,6 +1073,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh) > */ > int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) > { > + unsigned long flags; > + > /* The clkdm attribute does not exist yet prior OMAP4 */ > if (cpu_is_omap24xx() || cpu_is_omap34xx()) > return 0; > @@ -1086,9 +1084,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) > * downstream hwmods for debugging purposes? > */ > > - if (!oh) > + if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) > return -EINVAL; > > - return _clkdm_clk_hwmod_disable(clkdm); > + spin_lock_irqsave(&clkdm->lock, flags); > + > + if (atomic_read(&clkdm->usecount) == 0) { > + spin_unlock_irqrestore(&clkdm->lock, flags); > + WARN_ON(1); /* underflow */ > + return -ERANGE; > + } > + > + if (atomic_dec_return(&clkdm->usecount) > 0) { > + spin_unlock_irqrestore(&clkdm->lock, flags); > + return 0; > + } > + > + arch_clkdm->clkdm_clk_disable(clkdm); > + pwrdm_state_switch(clkdm->pwrdm.ptr); > + spin_unlock_irqrestore(&clkdm->lock, flags); > + > + pr_debug("clockdomain: %s: disabled\n", clkdm->name); > + > + return 0; > } > > -- > 1.7.10.4 ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks 2012-11-09 19:40 ` Mike Turquette @ 2012-11-09 19:52 ` Paul Walmsley 2012-11-09 20:53 ` Paul Walmsley 0 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 19:52 UTC (permalink / raw) To: Mike Turquette; +Cc: linux-omap, linux-arm-kernel On Fri, 9 Nov 2012, Mike Turquette wrote: > But I'm OK with the below patch in the short term. I just have one > question: did you observe any PM regressions by skipping the clkdm > programming? It's still under test here but 3530ES3 Beagle passed the PM tests with it, with no obvious warnings. - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks 2012-11-09 19:52 ` Paul Walmsley @ 2012-11-09 20:53 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 20:53 UTC (permalink / raw) To: Mike Turquette; +Cc: linux-omap, linux-arm-kernel On Fri, 9 Nov 2012, Paul Walmsley wrote: > On Fri, 9 Nov 2012, Mike Turquette wrote: > > > But I'm OK with the below patch in the short term. I just have one > > question: did you observe any PM regressions by skipping the clkdm > > programming? > > It's still under test here but 3530ES3 Beagle passed the PM tests with it, > with no obvious warnings. OK I'm satisfied with this general fix. Will have to break it up into pieces and move it earlier in the patch stack to ensure that PM doesn't break in the middle of the series, but the idea seems reasonably sound for short-term use. A clock should only be disabled during the disable-unused-clocks phase if its usecount is zero and it's enabled in the hardware. As far as I can tell, this can only happen when the clock is enabled by the bootloader/ROM code/PPA, and never touched by the kernel before the disable-unused-clocks phase. The only regression cases that come to mind at the moment are: 1. CONFIG_PM=n and a clockdomain only contains unused clocks; or 2. CONFIG_PM=y and a clockdomain only contains unused clocks and that same clockdomain does not support hardware-supervised autoidle or force-idle In those cases, I'd assume the clockdomain would effectively get stuck on. #1 we don't really care about since CONFIG_PM=n anyway. #2 is more of a concern but it should disappear completely once hwmods are present for all of the IP blocks on the device. (The presence of the hwmods will ensure that every clock that matters from an idle-management perspective is enabled at least once when the IP block is reset.) For this reason, it's important to note that when the hwmod reset code is moved to run late in the boot process, it will have to run before the unused clocks are disabled. One nice side-effect of this bug is that it highlighted that we're still missing OMAP3 hwmods for the camera subsystem, and that the reset code for the SAD2D module needs to be moved out of arch/arm/mach-omap2/pm34xx.c:omap3_d2d_idle() and into something that can be called from the hwmod reset code. - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (23 preceding siblings ...) [not found] ` <1352337181-29427-15-git-send-email-mturquette@ti.com> @ 2012-11-08 19:04 ` Vaibhav Hiremath 2012-11-09 21:12 ` Paul Walmsley ` (3 subsequent siblings) 28 siblings, 0 replies; 67+ messages in thread From: Vaibhav Hiremath @ 2012-11-08 19:04 UTC (permalink / raw) To: Mike Turquette Cc: paul, rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette On 11/8/2012 6:42 AM, Mike Turquette wrote: > From: Mike Turquette <mturquette@linaro.org> > > Hi all, > > This series is based on top of Paul's PRM/CM clean-up work. It is a > refresh of the patches Rajendra sent out a while back[1], with the > addition of several fixes for PM regressions[2] across several > platforms. > > I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF > patches (delta is zero) and also suspend/resume. > > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > appears sane. However Panda-ES never comes back from suspend/resume. > This problem exists on the PRM/CM branch I based on and was not > introduced by this series. I am investigating that independently of > this series. > > Anyone wanting to pull the work can find it at: > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771 > [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015 > > Mike Turquette (3): > ARM: OMAP4: clock: Convert to common clk > ARM: OMAP2+: clock: remove unnecessary declarations > ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts > > Paul Walmsley (7): > ARM: OMAP2xxx: clock: add APLL rate recalculation functions > ARM: OMAP2+: clock: add OMAP CCF convenience macros to > mach-omap2/clock.h > ARM: AM33XX: clock: add clock data in common clock format > ARM: OMAP44xx: clock: drop obsolete clock data > ARM: OMAP3xxx: clk: drop obsolete clock data > ARM: AM33xx: clock: drop obsolete clock data > ARM: OMAP2xxx: clock: drop obsolete clock data > > Rajendra Nayak (15): > ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap > ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses > ARM: OMAP3: clock: Convert to common clk > ARM: OMAP2: clock: Convert to common clk > ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable > autoidle > ARM: OMAP: clock: Define a function to enable clocks at init > ARM: OMAP: clock: Get rid of some clkdm assocations within clks > ARM: OMAP4: clock: Add 44xx data using common struct clk > ARM: OMAP3: clock: Add 3xxx data using common struct clk > ARM: omap2: clock: Add 24xx data using common struct clk > ARM: OMAP: clock: Switch to COMMON clk > ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts > ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts > ARM: omap3: clock: Cleanup !CONFIG_COMMON_CLK parts > ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts > > Vaibhav Hiremath (1): > ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions > > arch/arm/mach-omap2/Kconfig | 5 + > arch/arm/mach-omap2/Makefile | 10 +- > arch/arm/mach-omap2/cclock2420_data.c | 1959 ++++++++++++++ > arch/arm/mach-omap2/cclock2430_data.c | 2073 +++++++++++++++ > arch/arm/mach-omap2/cclock33xx_data.c | 961 +++++++ > arch/arm/mach-omap2/cclock3xxx_data.c | 3595 +++++++++++++++++++++++++ > arch/arm/mach-omap2/cclock44xx_data.c | 1991 ++++++++++++++ > arch/arm/mach-omap2/clkt2xxx_apll.c | 66 +- > arch/arm/mach-omap2/clkt2xxx_dpll.c | 8 +- > arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 12 +- > arch/arm/mach-omap2/clkt2xxx_osc.c | 13 +- > arch/arm/mach-omap2/clkt2xxx_sys.c | 7 +- > arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 11 +- > arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 8 +- > arch/arm/mach-omap2/clkt_clksel.c | 194 +- > arch/arm/mach-omap2/clkt_dpll.c | 28 +- > arch/arm/mach-omap2/clkt_iclk.c | 31 +- > arch/arm/mach-omap2/clock.c | 845 ++---- > arch/arm/mach-omap2/clock.h | 356 ++- > arch/arm/mach-omap2/clock2420_data.c | 1986 -------------- > arch/arm/mach-omap2/clock2430.c | 8 +- > arch/arm/mach-omap2/clock2430_data.c | 2085 --------------- > arch/arm/mach-omap2/clock2xxx.c | 1 + > arch/arm/mach-omap2/clock2xxx.h | 47 +- > arch/arm/mach-omap2/clock33xx_data.c | 1107 -------- > arch/arm/mach-omap2/clock34xx.c | 51 +- > arch/arm/mach-omap2/clock3517.c | 24 +- > arch/arm/mach-omap2/clock36xx.c | 22 +- > arch/arm/mach-omap2/clock36xx.h | 2 +- > arch/arm/mach-omap2/clock3xxx.c | 6 +- > arch/arm/mach-omap2/clock3xxx.h | 6 +- > arch/arm/mach-omap2/clock3xxx_data.c | 3613 -------------------------- > arch/arm/mach-omap2/clock44xx_data.c | 3398 ------------------------ > arch/arm/mach-omap2/clock_common_data.c | 22 +- > arch/arm/mach-omap2/cm-regbits-24xx.h | 5 + > arch/arm/mach-omap2/cm-regbits-34xx.h | 31 + > arch/arm/mach-omap2/cm2xxx_3xxx.h | 1 + > arch/arm/mach-omap2/dpll3xxx.c | 226 +- > arch/arm/mach-omap2/dpll44xx.c | 21 +- > arch/arm/mach-omap2/io.c | 25 + > arch/arm/mach-omap2/omap_hwmod.c | 63 +- > arch/arm/mach-omap2/pm24xx.c | 4 +- > arch/arm/mach-omap2/prm-regbits-24xx.h | 2 + > arch/arm/mach-omap2/prm-regbits-34xx.h | 1 + > arch/arm/mach-omap2/prm2xxx_3xxx.h | 1 + > arch/arm/mach-omap2/scrm44xx.h | 2 + > 46 files changed, 11539 insertions(+), 13394 deletions(-) > create mode 100644 arch/arm/mach-omap2/cclock2420_data.c > create mode 100644 arch/arm/mach-omap2/cclock2430_data.c > create mode 100644 arch/arm/mach-omap2/cclock33xx_data.c > create mode 100644 arch/arm/mach-omap2/cclock3xxx_data.c > create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c > delete mode 100644 arch/arm/mach-omap2/clock2420_data.c > delete mode 100644 arch/arm/mach-omap2/clock2430_data.c > delete mode 100644 arch/arm/mach-omap2/clock33xx_data.c > delete mode 100644 arch/arm/mach-omap2/clock3xxx_data.c > delete mode 100644 arch/arm/mach-omap2/clock44xx_data.c > Thanks Mike for the patches. Just boot tested it on BeagleBone Platform, and it is booting up fine for me without any issues. Also I did some basic clk_rate check, and it came out well. Anyway, I will try to review it tomorrow (if time permits). Thanks, Vaibhav ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (24 preceding siblings ...) 2012-11-08 19:04 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Vaibhav Hiremath @ 2012-11-09 21:12 ` Paul Walmsley 2012-11-09 22:09 ` Tony Lindgren 2012-11-09 22:18 ` Mike Turquette 2012-11-12 21:50 ` [PATCH] ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections Paul Walmsley ` (2 subsequent siblings) 28 siblings, 2 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 21:12 UTC (permalink / raw) To: Mike Turquette, rnayak Cc: linux-omap, linux-arm-kernel, patches, Mike Turquette Hi With the fixes that have been posted, this is testing clean here. Mike and Rajendra have put in months of work on these patches under often-difficult conditions, and it's really great that we've arrived at this point with zero obvious remaining regressions from the current code. The branch has been posted for the time being at git://git.pwsan.com/linux-2.6 in the branch 'common_clk_devel_3.8', with the head at commit 376676b429cb6dc95c39cdac82b2be816ea22893, in case anyone else wants to try it. Anyway, barring any further regressions that haven't reared their ugly heads yet, and barring anything truly horrible in the code or data that I've missed so far, will take this branch from here. It still needs some more work before it's ready to merge. The clockdomain usecounting fix patch needs to be split and moved earlier in the patch stack so 'git bisect' doesn't result in warnings and broken PM on OMAP3. And it all is going to be rebased on the second set of PRCM cleanup patches at commit b99db36cdf37decb1b5575c5f293d170cbbc53d6, which I'm assuming Tony is planning to pull. Then will plan to send that pull request to Tony. Then after that, if there's still time to merge some of the clock changes that have showed up on the lists for 3.8, those will get stacked onto a topic branch based on the branch that's sent to Tony. - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-09 21:12 ` Paul Walmsley @ 2012-11-09 22:09 ` Tony Lindgren 2012-11-09 22:18 ` Mike Turquette 1 sibling, 0 replies; 67+ messages in thread From: Tony Lindgren @ 2012-11-09 22:09 UTC (permalink / raw) To: Paul Walmsley Cc: Mike Turquette, rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette * Paul Walmsley <paul@pwsan.com> [121109 13:14]: > > Hi > > With the fixes that have been posted, this is testing clean here. Mike > and Rajendra have put in months of work on these patches under > often-difficult conditions, and it's really great that we've arrived at > this point with zero obvious remaining regressions from the current code. That's excellent news :) > The branch has been posted for the time being at > git://git.pwsan.com/linux-2.6 in the branch 'common_clk_devel_3.8', with > the head at commit 376676b429cb6dc95c39cdac82b2be816ea22893, in case > anyone else wants to try it. > > Anyway, barring any further regressions that haven't reared their ugly > heads yet, and barring anything truly horrible in the code or data that > I've missed so far, will take this branch from here. It still needs some > more work before it's ready to merge. The clockdomain usecounting fix > patch needs to be split and moved earlier in the patch stack so 'git > bisect' doesn't result in warnings and broken PM on OMAP3. And it all is > going to be rebased on the second set of PRCM cleanup patches at commit > b99db36cdf37decb1b5575c5f293d170cbbc53d6, which I'm assuming Tony is > planning to pull. Then will plan to send that pull request to Tony. > > Then after that, if there's still time to merge some of the clock changes > that have showed up on the lists for 3.8, those will get stacked onto a > topic branch based on the branch that's sent to Tony. Sounds good to me. Thanks, Tony ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-09 21:12 ` Paul Walmsley 2012-11-09 22:09 ` Tony Lindgren @ 2012-11-09 22:18 ` Mike Turquette 2012-11-09 23:47 ` Paul Walmsley 1 sibling, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-09 22:18 UTC (permalink / raw) To: Paul Walmsley, rnayak; +Cc: linux-omap, linux-arm-kernel, patches Quoting Paul Walmsley (2012-11-09 13:12:24) > Hi > > With the fixes that have been posted, this is testing clean here. Mike > and Rajendra have put in months of work on these patches under > often-difficult conditions, and it's really great that we've arrived at > this point with zero obvious remaining regressions from the current code. > > The branch has been posted for the time being at > git://git.pwsan.com/linux-2.6 in the branch 'common_clk_devel_3.8', with > the head at commit 376676b429cb6dc95c39cdac82b2be816ea22893, in case > anyone else wants to try it. > Thanks a lot Paul. You put in a lot of work on this series as well and that should not go unnoticed. I'm truly happy to see this series come together. > Anyway, barring any further regressions that haven't reared their ugly > heads yet, and barring anything truly horrible in the code or data that > I've missed so far, will take this branch from here. It still needs some > more work before it's ready to merge. The clockdomain usecounting fix > patch needs to be split and moved earlier in the patch stack so 'git > bisect' doesn't result in warnings and broken PM on OMAP3. And it all is > going to be rebased on the second set of PRCM cleanup patches at commit > b99db36cdf37decb1b5575c5f293d170cbbc53d6, which I'm assuming Tony is > planning to pull. Then will plan to send that pull request to Tony. > I just did some more testing on your branch and everything looks great. The only thing that caught my eye was using the clk-private.h header in the top-most patch. The following patch will help me sleep better at night: diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index ba4d14c..3848735 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -22,7 +22,7 @@ #include <linux/clk.h> #include <linux/limits.h> #include <linux/err.h> -#include <linux/clk-private.h> +#include <linux/clk-provider.h> #include <linux/io.h> Tested on 3530 ES3.0 Beagleboard, boot + suspend/resume. Regards, Mike > Then after that, if there's still time to merge some of the clock changes > that have showed up on the lists for 3.8, those will get stacked onto a > topic branch based on the branch that's sent to Tony. > > > - Paul ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-09 22:18 ` Mike Turquette @ 2012-11-09 23:47 ` Paul Walmsley 0 siblings, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 23:47 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches On Fri, 9 Nov 2012, Mike Turquette wrote: > I just did some more testing on your branch and everything looks great. > The only thing that caught my eye was using the clk-private.h header in > the top-most patch. The following patch will help me sleep better at > night: > > diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c > index ba4d14c..3848735 100644 > --- a/arch/arm/mach-omap2/clockdomain.c > +++ b/arch/arm/mach-omap2/clockdomain.c > @@ -22,7 +22,7 @@ > #include <linux/clk.h> > #include <linux/limits.h> > #include <linux/err.h> > -#include <linux/clk-private.h> > +#include <linux/clk-provider.h> > > #include <linux/io.h> Just folded this one in, the updated patch follows. > Tested on 3530 ES3.0 Beagleboard, boot + suspend/resume. Great! - Paul From: Mike Turquette <mturquette@ti.com> Date: Fri, 9 Nov 2012 11:28:42 -0700 Subject: [PATCH] ARM: OMAP2+: clockdomain: bypass clockdomain handling when disabling unused clks The OMAP port to the common clk framework[1] resulted in spurious WARNs while disable unused clocks. This is due to _clkdm_clk_hwmod_disable catching clkdm->usecount's with a value of zero. Even less desirable it would not allow the clkdm_clk_disable function pointer to get called due to an early return of -ERANGE. This patch adds a check for such a corner case by skipping the WARN and early return in the event that clkdm->usecount and clk->enable_usecount are both zero. Presumably this could only happen during the check for unused clocks at boot-time. [1] http://article.gmane.org/gmane.linux.ports.arm.omap/88824 Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: split the hwmod and clock disable cases; modified the code to skip the clockdomain handling during the disable-unused-clocks phase; added COMMON_CLK ifdef; removed include of clk-private.h at Mike's request] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/clockdomain.c | 91 ++++++++++++++++++++++--------------- 1 file changed, 54 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 64e5046..4424f3d 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -22,6 +22,7 @@ #include <linux/clk.h> #include <linux/limits.h> #include <linux/err.h> +#include <linux/clk-provider.h> #include <linux/io.h> @@ -947,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) return 0; } -static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) -{ - unsigned long flags; - - if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) - return -EINVAL; - - spin_lock_irqsave(&clkdm->lock, flags); - - if (atomic_read(&clkdm->usecount) == 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); - WARN_ON(1); /* underflow */ - return -ERANGE; - } - - if (atomic_dec_return(&clkdm->usecount) > 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); - return 0; - } - - arch_clkdm->clkdm_clk_disable(clkdm); - pwrdm_state_switch(clkdm->pwrdm.ptr); - spin_unlock_irqrestore(&clkdm->lock, flags); - - pr_debug("clockdomain: %s: disabled\n", clkdm->name); - - return 0; -} - /** * clkdm_clk_enable - add an enabled downstream clock to this clkdm * @clkdm: struct clockdomain * @@ -1018,15 +990,39 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) */ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) { - /* - * XXX Rewrite this code to maintain a list of enabled - * downstream clocks for debugging purposes? - */ + unsigned long flags; - if (!clk) + if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + spin_lock_irqsave(&clkdm->lock, flags); + +#ifdef CONFIG_COMMON_CLK + /* corner case: disabling unused clocks */ + if (__clk_get_enable_count(clk) == 0) + goto ccd_exit; +#endif + + if (atomic_read(&clkdm->usecount) == 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + WARN_ON(1); /* underflow */ + return -ERANGE; + } + + if (atomic_dec_return(&clkdm->usecount) > 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + return 0; + } + + arch_clkdm->clkdm_clk_disable(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); + + pr_debug("clockdomain: %s: disabled\n", clkdm->name); + +ccd_exit: + spin_unlock_irqrestore(&clkdm->lock, flags); + + return 0; } /** @@ -1077,6 +1073,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh) */ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) { + unsigned long flags; + /* The clkdm attribute does not exist yet prior OMAP4 */ if (cpu_is_omap24xx() || cpu_is_omap34xx()) return 0; @@ -1086,9 +1084,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) * downstream hwmods for debugging purposes? */ - if (!oh) + if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + spin_lock_irqsave(&clkdm->lock, flags); + + if (atomic_read(&clkdm->usecount) == 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + WARN_ON(1); /* underflow */ + return -ERANGE; + } + + if (atomic_dec_return(&clkdm->usecount) > 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + return 0; + } + + arch_clkdm->clkdm_clk_disable(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); + spin_unlock_irqrestore(&clkdm->lock, flags); + + pr_debug("clockdomain: %s: disabled\n", clkdm->name); + + return 0; } -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH] ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (25 preceding siblings ...) 2012-11-09 21:12 ` Paul Walmsley @ 2012-11-12 21:50 ` Paul Walmsley 2012-11-12 22:30 ` Mike Turquette [not found] ` <1352337181-29427-16-git-send-email-mturquette@ti.com> 2012-11-13 13:42 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Laurent Pinchart 28 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-12 21:50 UTC (permalink / raw) To: Mike Turquette Cc: rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette Remove all of the code that is compiled when CONFIG_COMMON_CLK=n in the OMAP3+ DPLL handling code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Mike Turquette <mturquette@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> --- This will be merged as part of the OMAP CCF conversion set. arch/arm/mach-omap2/dpll3xxx.c | 231 +--------------------------------------- 1 file changed, 3 insertions(+), 228 deletions(-) diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index f72dedb..fafb28c 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -43,11 +43,7 @@ /* Private functions */ /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ -#ifdef CONFIG_COMMON_CLK static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) -#else -static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) -#endif { const struct dpll_data *dd; u32 v; @@ -61,11 +57,7 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) } /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ -#ifdef CONFIG_COMMON_CLK static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) -#else -static int _omap3_wait_dpll_status(struct clk *clk, u8 state) -#endif { const struct dpll_data *dd; int i = 0; @@ -73,11 +65,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) const char *clk_name; dd = clk->dpll_data; -#ifdef CONFIG_COMMON_CLK clk_name = __clk_get_name(clk->hw.clk); -#else - clk_name = __clk_get_name(clk); -#endif state <<= __ffs(dd->idlest_mask); @@ -101,11 +89,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) } /* From 3430 TRM ES2 4.7.6.2 */ -#ifdef CONFIG_COMMON_CLK static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) -#else -static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) -#endif { unsigned long fint; u16 f = 0; @@ -150,22 +134,14 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) * locked successfully, return 0; if the DPLL did not lock in the time * allotted, or DPLL3 was passed in, return -EINVAL. */ -#ifdef CONFIG_COMMON_CLK static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) -#else -static int _omap3_noncore_dpll_lock(struct clk *clk) -#endif { const struct dpll_data *dd; u8 ai; u8 state = 1; int r = 0; -#ifdef CONFIG_COMMON_CLK pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); -#else - pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); -#endif dd = clk->dpll_data; state <<= __ffs(dd->idlest_mask); @@ -203,11 +179,7 @@ done: * DPLL3 was passed in, or the DPLL does not support low-power bypass, * return -EINVAL. */ -#ifdef CONFIG_COMMON_CLK static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) -#else -static int _omap3_noncore_dpll_bypass(struct clk *clk) -#endif { int r; u8 ai; @@ -216,11 +188,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) return -EINVAL; pr_debug("clock: configuring DPLL %s for low-power bypass\n", -#ifdef CONFIG_COMMON_CLK __clk_get_name(clk->hw.clk)); -#else - __clk_get_name(clk)); -#endif ai = omap3_dpll_autoidle_read(clk); @@ -243,22 +211,14 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) * code. If DPLL3 was passed in, or the DPLL does not support * low-power stop, return -EINVAL; otherwise, return 0. */ -#ifdef CONFIG_COMMON_CLK static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) -#else -static int _omap3_noncore_dpll_stop(struct clk *clk) -#endif { u8 ai; if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) return -EINVAL; -#ifdef CONFIG_COMMON_CLK pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); -#else - pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); -#endif ai = omap3_dpll_autoidle_read(clk); @@ -282,19 +242,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ -#ifdef CONFIG_COMMON_CLK static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) -#else -static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) -#endif { unsigned long fint, clkinp; /* watch out for overflow */ -#ifdef CONFIG_COMMON_CLK clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); -#else - clkinp = __clk_get_rate(__clk_get_parent(clk)); -#endif fint = (clkinp / n) * m; if (fint < 1000000000) @@ -315,20 +267,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ -#ifdef CONFIG_COMMON_CLK static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) -#else -static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) -#endif { unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2; -#ifdef CONFIG_COMMON_CLK clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); -#else - clkinp = __clk_get_rate(__clk_get_parent(clk)); -#endif /* * target sigma-delta to near 250MHz @@ -355,12 +299,8 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) * Program the DPLL with the supplied M, N values, and wait for the DPLL to * lock.. Returns -EINVAL upon error, or 0 upon success. */ -#ifdef CONFIG_COMMON_CLK static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n, u16 freqsel) -#else -static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) -#endif { struct dpll_data *dd = clk->dpll_data; u8 dco, sd_div; @@ -417,14 +357,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * * Recalculate and propagate the DPLL rate. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -unsigned long omap3_dpll_recalc(struct clk *clk) -{ -#endif + return omap2_get_dpll_rate(clk); } @@ -444,14 +380,9 @@ unsigned long omap3_dpll_recalc(struct clk *clk) * support low-power stop, or if the DPLL took too long to enter * bypass or lock, return -EINVAL; otherwise, return 0. */ -#ifdef CONFIG_COMMON_CLK int omap3_noncore_dpll_enable(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -int omap3_noncore_dpll_enable(struct clk *clk) -{ -#endif int r; struct dpll_data *dd; struct clk *parent; @@ -460,7 +391,6 @@ int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; -#ifdef CONFIG_COMMON_CLK if (clk->clkdm) { r = clkdm_clk_enable(clk->clkdm, hw->clk); if (r) { @@ -475,11 +405,6 @@ int omap3_noncore_dpll_enable(struct clk *clk) parent = __clk_get_parent(hw->clk); if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { -#else - parent = __clk_get_parent(clk); - - if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { -#endif WARN_ON(parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); } else { @@ -487,16 +412,6 @@ int omap3_noncore_dpll_enable(struct clk *clk) r = _omap3_noncore_dpll_lock(clk); } -#ifndef CONFIG_COMMON_CLK - /* - *FIXME: this is dubious - if clk->rate has changed, what about - * propagating? - */ - if (!r) - clk->rate = (clk->recalc) ? clk->recalc(clk) : - omap2_get_dpll_rate(clk); -#endif - return r; } @@ -507,7 +422,6 @@ int omap3_noncore_dpll_enable(struct clk *clk) * Instructs a non-CORE DPLL to enter low-power stop. This function is * intended for use in struct clkops. No return value. */ -#ifdef CONFIG_COMMON_CLK void omap3_noncore_dpll_disable(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); @@ -515,13 +429,6 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw) _omap3_noncore_dpll_stop(clk); if (clk->clkdm) clkdm_clk_disable(clk->clkdm, hw->clk); -#else -void omap3_noncore_dpll_disable(struct clk *clk) -{ - _omap3_noncore_dpll_stop(clk); - if (clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); -#endif } @@ -538,7 +445,6 @@ void omap3_noncore_dpll_disable(struct clk *clk) * target rate if it hasn't been done already, then program and lock * the DPLL. Returns -EINVAL upon error, or 0 upon success. */ -#ifdef CONFIG_COMMON_CLK int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -608,85 +514,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } -#else -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *new_parent = NULL; - unsigned long hw_rate, bypass_rate; - u16 freqsel = 0; - struct dpll_data *dd; - int ret; - - if (!clk || !rate) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); - if (rate == hw_rate) - return 0; - - /* - * Ensure both the bypass and ref clocks are enabled prior to - * doing anything; we need the bypass clock running to reprogram - * the DPLL. - */ - omap2_clk_enable(dd->clk_bypass); - omap2_clk_enable(dd->clk_ref); - - bypass_rate = __clk_get_rate(dd->clk_bypass); - if (bypass_rate == rate && - (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); - - ret = _omap3_noncore_dpll_bypass(clk); - if (!ret) - new_parent = dd->clk_bypass; - } else { - if (dd->last_rounded_rate != rate) - rate = clk->round_rate(clk, rate); - - if (dd->last_rounded_rate == 0) - return -EINVAL; - - /* No freqsel on OMAP4 and OMAP3630 */ - if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { - freqsel = _omap3_dpll_compute_freqsel(clk, - dd->last_rounded_n); - if (!freqsel) - WARN_ON(1); - } - - pr_debug("clock: %s: set rate: locking rate to %lu.\n", - __clk_get_name(clk), rate); - - ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, - dd->last_rounded_n, freqsel); - if (!ret) - new_parent = dd->clk_ref; - } - if (!ret) { - /* - * Switch the parent clock in the hierarchy, and make sure - * that the new parent's usecount is correct. Note: we - * enable the new parent before disabling the old to avoid - * any unnecessary hardware disable->enable transitions. - */ - if (clk->usecount) { - omap2_clk_enable(new_parent); - omap2_clk_disable(clk->parent); - } - clk_reparent(clk, new_parent); - clk->rate = rate; - } - omap2_clk_disable(dd->clk_ref); - omap2_clk_disable(dd->clk_bypass); - - return 0; -} -#endif /* DPLL autoidle read/set code */ @@ -698,11 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) * -EINVAL if passed a null pointer or if the struct clk does not * appear to refer to a DPLL. */ -#ifdef CONFIG_COMMON_CLK u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) -#else -u32 omap3_dpll_autoidle_read(struct clk *clk) -#endif { const struct dpll_data *dd; u32 v; @@ -731,11 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) * OMAP3430. The DPLL will enter low-power stop when its downstream * clocks are gated. No return value. */ -#ifdef CONFIG_COMMON_CLK void omap3_dpll_allow_idle(struct clk_hw_omap *clk) -#else -void omap3_dpll_allow_idle(struct clk *clk) -#endif { const struct dpll_data *dd; u32 v; @@ -745,13 +564,8 @@ void omap3_dpll_allow_idle(struct clk *clk) dd = clk->dpll_data; - if (!dd->autoidle_reg) { -#ifndef CONFIG_COMMON_CLK - pr_debug("clock: DPLL %s: autoidle not supported\n", - __clk_get_name(clk)); -#endif + if (!dd->autoidle_reg) return; - } /* * REVISIT: CORE DPLL can optionally enter low-power bypass @@ -771,11 +585,7 @@ void omap3_dpll_allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ -#ifdef CONFIG_COMMON_CLK void omap3_dpll_deny_idle(struct clk_hw_omap *clk) -#else -void omap3_dpll_deny_idle(struct clk *clk) -#endif { const struct dpll_data *dd; u32 v; @@ -785,13 +595,8 @@ void omap3_dpll_deny_idle(struct clk *clk) dd = clk->dpll_data; - if (!dd->autoidle_reg) { -#ifndef CONFIG_COMMON_CLK - pr_debug("clock: DPLL %s: autoidle not supported\n", - __clk_get_name(clk)); -#endif + if (!dd->autoidle_reg) return; - } v = __raw_readl(dd->autoidle_reg); v &= ~dd->autoidle_mask; @@ -809,7 +614,6 @@ void omap3_dpll_deny_idle(struct clk *clk) * Using parent clock DPLL data, look up DPLL state. If locked, set our * rate to the dpll_clk * 2; otherwise, just use dpll_clk. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, unsigned long parent_rate) { @@ -829,22 +633,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, break; pclk = to_clk_hw_omap(hw); } while (pclk && !pclk->dpll_data); -#else -unsigned long omap3_clkoutx2_recalc(struct clk *clk) -{ - const struct dpll_data *dd; - unsigned long rate; - u32 v; - struct clk *pclk; - unsigned long parent_rate; - /* Walk up the parents of clk, looking for a DPLL */ - pclk = __clk_get_parent(clk); - while (pclk && !pclk->dpll_data) - pclk = __clk_get_parent(pclk); - - parent_rate = __clk_get_rate(__clk_get_parent(clk)); -#endif /* clk does not have a DPLL as a parent? error in the clock data */ if (!pclk) { WARN_ON(1); @@ -865,21 +654,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) } /* OMAP3/4 non-CORE DPLL clkops */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_omap3_dpll = { .allow_idle = omap3_dpll_allow_idle, .deny_idle = omap3_dpll_deny_idle, }; -#else -const struct clkops clkops_omap3_noncore_dpll_ops = { - .enable = omap3_noncore_dpll_enable, - .disable = omap3_noncore_dpll_disable, - .allow_idle = omap3_dpll_allow_idle, - .deny_idle = omap3_dpll_deny_idle, -}; - -const struct clkops clkops_omap3_core_dpll_ops = { - .allow_idle = omap3_dpll_allow_idle, - .deny_idle = omap3_dpll_deny_idle, -}; -#endif -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH] ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections 2012-11-12 21:50 ` [PATCH] ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections Paul Walmsley @ 2012-11-12 22:30 ` Mike Turquette 0 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-12 22:30 UTC (permalink / raw) To: Paul Walmsley; +Cc: rnayak, linux-omap, linux-arm-kernel, patches Quoting Paul Walmsley (2012-11-12 13:50:53) > Remove all of the code that is compiled when CONFIG_COMMON_CLK=n in the > OMAP3+ DPLL handling code. > > Signed-off-by: Paul Walmsley <paul@pwsan.com> > Cc: Mike Turquette <mturquette@ti.com> > Cc: Rajendra Nayak <rnayak@ti.com> Hmm, dpll3xxx.c fell through the cracks during #ifdef cleanup. Patch looks good to me. Regards, Mike > --- > > This will be merged as part of the OMAP CCF conversion set. > > arch/arm/mach-omap2/dpll3xxx.c | 231 +--------------------------------------- > 1 file changed, 3 insertions(+), 228 deletions(-) > > diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c > index f72dedb..fafb28c 100644 > --- a/arch/arm/mach-omap2/dpll3xxx.c > +++ b/arch/arm/mach-omap2/dpll3xxx.c > @@ -43,11 +43,7 @@ > /* Private functions */ > > /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ > -#ifdef CONFIG_COMMON_CLK > static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) > -#else > -static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) > -#endif > { > const struct dpll_data *dd; > u32 v; > @@ -61,11 +57,7 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) > } > > /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ > -#ifdef CONFIG_COMMON_CLK > static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) > -#else > -static int _omap3_wait_dpll_status(struct clk *clk, u8 state) > -#endif > { > const struct dpll_data *dd; > int i = 0; > @@ -73,11 +65,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) > const char *clk_name; > > dd = clk->dpll_data; > -#ifdef CONFIG_COMMON_CLK > clk_name = __clk_get_name(clk->hw.clk); > -#else > - clk_name = __clk_get_name(clk); > -#endif > > state <<= __ffs(dd->idlest_mask); > > @@ -101,11 +89,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) > } > > /* From 3430 TRM ES2 4.7.6.2 */ > -#ifdef CONFIG_COMMON_CLK > static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) > -#else > -static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) > -#endif > { > unsigned long fint; > u16 f = 0; > @@ -150,22 +134,14 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) > * locked successfully, return 0; if the DPLL did not lock in the time > * allotted, or DPLL3 was passed in, return -EINVAL. > */ > -#ifdef CONFIG_COMMON_CLK > static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) > -#else > -static int _omap3_noncore_dpll_lock(struct clk *clk) > -#endif > { > const struct dpll_data *dd; > u8 ai; > u8 state = 1; > int r = 0; > > -#ifdef CONFIG_COMMON_CLK > pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); > -#else > - pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); > -#endif > > dd = clk->dpll_data; > state <<= __ffs(dd->idlest_mask); > @@ -203,11 +179,7 @@ done: > * DPLL3 was passed in, or the DPLL does not support low-power bypass, > * return -EINVAL. > */ > -#ifdef CONFIG_COMMON_CLK > static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) > -#else > -static int _omap3_noncore_dpll_bypass(struct clk *clk) > -#endif > { > int r; > u8 ai; > @@ -216,11 +188,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) > return -EINVAL; > > pr_debug("clock: configuring DPLL %s for low-power bypass\n", > -#ifdef CONFIG_COMMON_CLK > __clk_get_name(clk->hw.clk)); > -#else > - __clk_get_name(clk)); > -#endif > > ai = omap3_dpll_autoidle_read(clk); > > @@ -243,22 +211,14 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) > * code. If DPLL3 was passed in, or the DPLL does not support > * low-power stop, return -EINVAL; otherwise, return 0. > */ > -#ifdef CONFIG_COMMON_CLK > static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) > -#else > -static int _omap3_noncore_dpll_stop(struct clk *clk) > -#endif > { > u8 ai; > > if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) > return -EINVAL; > > -#ifdef CONFIG_COMMON_CLK > pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); > -#else > - pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); > -#endif > > ai = omap3_dpll_autoidle_read(clk); > > @@ -282,19 +242,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) > * XXX This code is not needed for 3430/AM35xx; can it be optimized > * out in non-multi-OMAP builds for those chips? > */ > -#ifdef CONFIG_COMMON_CLK > static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) > -#else > -static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) > -#endif > { > unsigned long fint, clkinp; /* watch out for overflow */ > > -#ifdef CONFIG_COMMON_CLK > clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); > -#else > - clkinp = __clk_get_rate(__clk_get_parent(clk)); > -#endif > fint = (clkinp / n) * m; > > if (fint < 1000000000) > @@ -315,20 +267,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) > * XXX This code is not needed for 3430/AM35xx; can it be optimized > * out in non-multi-OMAP builds for those chips? > */ > -#ifdef CONFIG_COMMON_CLK > static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) > -#else > -static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) > -#endif > { > unsigned long clkinp, sd; /* watch out for overflow */ > int mod1, mod2; > > -#ifdef CONFIG_COMMON_CLK > clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); > -#else > - clkinp = __clk_get_rate(__clk_get_parent(clk)); > -#endif > > /* > * target sigma-delta to near 250MHz > @@ -355,12 +299,8 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) > * Program the DPLL with the supplied M, N values, and wait for the DPLL to > * lock.. Returns -EINVAL upon error, or 0 upon success. > */ > -#ifdef CONFIG_COMMON_CLK > static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n, > u16 freqsel) > -#else > -static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) > -#endif > { > struct dpll_data *dd = clk->dpll_data; > u8 dco, sd_div; > @@ -417,14 +357,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) > * > * Recalculate and propagate the DPLL rate. > */ > -#ifdef CONFIG_COMMON_CLK > unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) > { > struct clk_hw_omap *clk = to_clk_hw_omap(hw); > -#else > -unsigned long omap3_dpll_recalc(struct clk *clk) > -{ > -#endif > + > return omap2_get_dpll_rate(clk); > } > > @@ -444,14 +380,9 @@ unsigned long omap3_dpll_recalc(struct clk *clk) > * support low-power stop, or if the DPLL took too long to enter > * bypass or lock, return -EINVAL; otherwise, return 0. > */ > -#ifdef CONFIG_COMMON_CLK > int omap3_noncore_dpll_enable(struct clk_hw *hw) > { > struct clk_hw_omap *clk = to_clk_hw_omap(hw); > -#else > -int omap3_noncore_dpll_enable(struct clk *clk) > -{ > -#endif > int r; > struct dpll_data *dd; > struct clk *parent; > @@ -460,7 +391,6 @@ int omap3_noncore_dpll_enable(struct clk *clk) > if (!dd) > return -EINVAL; > > -#ifdef CONFIG_COMMON_CLK > if (clk->clkdm) { > r = clkdm_clk_enable(clk->clkdm, hw->clk); > if (r) { > @@ -475,11 +405,6 @@ int omap3_noncore_dpll_enable(struct clk *clk) > parent = __clk_get_parent(hw->clk); > > if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { > -#else > - parent = __clk_get_parent(clk); > - > - if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { > -#endif > WARN_ON(parent != dd->clk_bypass); > r = _omap3_noncore_dpll_bypass(clk); > } else { > @@ -487,16 +412,6 @@ int omap3_noncore_dpll_enable(struct clk *clk) > r = _omap3_noncore_dpll_lock(clk); > } > > -#ifndef CONFIG_COMMON_CLK > - /* > - *FIXME: this is dubious - if clk->rate has changed, what about > - * propagating? > - */ > - if (!r) > - clk->rate = (clk->recalc) ? clk->recalc(clk) : > - omap2_get_dpll_rate(clk); > -#endif > - > return r; > } > > @@ -507,7 +422,6 @@ int omap3_noncore_dpll_enable(struct clk *clk) > * Instructs a non-CORE DPLL to enter low-power stop. This function is > * intended for use in struct clkops. No return value. > */ > -#ifdef CONFIG_COMMON_CLK > void omap3_noncore_dpll_disable(struct clk_hw *hw) > { > struct clk_hw_omap *clk = to_clk_hw_omap(hw); > @@ -515,13 +429,6 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw) > _omap3_noncore_dpll_stop(clk); > if (clk->clkdm) > clkdm_clk_disable(clk->clkdm, hw->clk); > -#else > -void omap3_noncore_dpll_disable(struct clk *clk) > -{ > - _omap3_noncore_dpll_stop(clk); > - if (clk->clkdm) > - clkdm_clk_disable(clk->clkdm, clk); > -#endif > } > > > @@ -538,7 +445,6 @@ void omap3_noncore_dpll_disable(struct clk *clk) > * target rate if it hasn't been done already, then program and lock > * the DPLL. Returns -EINVAL upon error, or 0 upon success. > */ > -#ifdef CONFIG_COMMON_CLK > int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, > unsigned long parent_rate) > { > @@ -608,85 +514,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, > > return 0; > } > -#else > -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) > -{ > - struct clk *new_parent = NULL; > - unsigned long hw_rate, bypass_rate; > - u16 freqsel = 0; > - struct dpll_data *dd; > - int ret; > - > - if (!clk || !rate) > - return -EINVAL; > - > - dd = clk->dpll_data; > - if (!dd) > - return -EINVAL; > - > - hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); > - if (rate == hw_rate) > - return 0; > - > - /* > - * Ensure both the bypass and ref clocks are enabled prior to > - * doing anything; we need the bypass clock running to reprogram > - * the DPLL. > - */ > - omap2_clk_enable(dd->clk_bypass); > - omap2_clk_enable(dd->clk_ref); > - > - bypass_rate = __clk_get_rate(dd->clk_bypass); > - if (bypass_rate == rate && > - (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { > - pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); > - > - ret = _omap3_noncore_dpll_bypass(clk); > - if (!ret) > - new_parent = dd->clk_bypass; > - } else { > - if (dd->last_rounded_rate != rate) > - rate = clk->round_rate(clk, rate); > - > - if (dd->last_rounded_rate == 0) > - return -EINVAL; > - > - /* No freqsel on OMAP4 and OMAP3630 */ > - if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { > - freqsel = _omap3_dpll_compute_freqsel(clk, > - dd->last_rounded_n); > - if (!freqsel) > - WARN_ON(1); > - } > - > - pr_debug("clock: %s: set rate: locking rate to %lu.\n", > - __clk_get_name(clk), rate); > - > - ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, > - dd->last_rounded_n, freqsel); > - if (!ret) > - new_parent = dd->clk_ref; > - } > - if (!ret) { > - /* > - * Switch the parent clock in the hierarchy, and make sure > - * that the new parent's usecount is correct. Note: we > - * enable the new parent before disabling the old to avoid > - * any unnecessary hardware disable->enable transitions. > - */ > - if (clk->usecount) { > - omap2_clk_enable(new_parent); > - omap2_clk_disable(clk->parent); > - } > - clk_reparent(clk, new_parent); > - clk->rate = rate; > - } > - omap2_clk_disable(dd->clk_ref); > - omap2_clk_disable(dd->clk_bypass); > - > - return 0; > -} > -#endif > > /* DPLL autoidle read/set code */ > > @@ -698,11 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) > * -EINVAL if passed a null pointer or if the struct clk does not > * appear to refer to a DPLL. > */ > -#ifdef CONFIG_COMMON_CLK > u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) > -#else > -u32 omap3_dpll_autoidle_read(struct clk *clk) > -#endif > { > const struct dpll_data *dd; > u32 v; > @@ -731,11 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) > * OMAP3430. The DPLL will enter low-power stop when its downstream > * clocks are gated. No return value. > */ > -#ifdef CONFIG_COMMON_CLK > void omap3_dpll_allow_idle(struct clk_hw_omap *clk) > -#else > -void omap3_dpll_allow_idle(struct clk *clk) > -#endif > { > const struct dpll_data *dd; > u32 v; > @@ -745,13 +564,8 @@ void omap3_dpll_allow_idle(struct clk *clk) > > dd = clk->dpll_data; > > - if (!dd->autoidle_reg) { > -#ifndef CONFIG_COMMON_CLK > - pr_debug("clock: DPLL %s: autoidle not supported\n", > - __clk_get_name(clk)); > -#endif > + if (!dd->autoidle_reg) > return; > - } > > /* > * REVISIT: CORE DPLL can optionally enter low-power bypass > @@ -771,11 +585,7 @@ void omap3_dpll_allow_idle(struct clk *clk) > * > * Disable DPLL automatic idle control. No return value. > */ > -#ifdef CONFIG_COMMON_CLK > void omap3_dpll_deny_idle(struct clk_hw_omap *clk) > -#else > -void omap3_dpll_deny_idle(struct clk *clk) > -#endif > { > const struct dpll_data *dd; > u32 v; > @@ -785,13 +595,8 @@ void omap3_dpll_deny_idle(struct clk *clk) > > dd = clk->dpll_data; > > - if (!dd->autoidle_reg) { > -#ifndef CONFIG_COMMON_CLK > - pr_debug("clock: DPLL %s: autoidle not supported\n", > - __clk_get_name(clk)); > -#endif > + if (!dd->autoidle_reg) > return; > - } > > v = __raw_readl(dd->autoidle_reg); > v &= ~dd->autoidle_mask; > @@ -809,7 +614,6 @@ void omap3_dpll_deny_idle(struct clk *clk) > * Using parent clock DPLL data, look up DPLL state. If locked, set our > * rate to the dpll_clk * 2; otherwise, just use dpll_clk. > */ > -#ifdef CONFIG_COMMON_CLK > unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, > unsigned long parent_rate) > { > @@ -829,22 +633,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, > break; > pclk = to_clk_hw_omap(hw); > } while (pclk && !pclk->dpll_data); > -#else > -unsigned long omap3_clkoutx2_recalc(struct clk *clk) > -{ > - const struct dpll_data *dd; > - unsigned long rate; > - u32 v; > - struct clk *pclk; > - unsigned long parent_rate; > > - /* Walk up the parents of clk, looking for a DPLL */ > - pclk = __clk_get_parent(clk); > - while (pclk && !pclk->dpll_data) > - pclk = __clk_get_parent(pclk); > - > - parent_rate = __clk_get_rate(__clk_get_parent(clk)); > -#endif > /* clk does not have a DPLL as a parent? error in the clock data */ > if (!pclk) { > WARN_ON(1); > @@ -865,21 +654,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) > } > > /* OMAP3/4 non-CORE DPLL clkops */ > -#ifdef CONFIG_COMMON_CLK > const struct clk_hw_omap_ops clkhwops_omap3_dpll = { > .allow_idle = omap3_dpll_allow_idle, > .deny_idle = omap3_dpll_deny_idle, > }; > -#else > -const struct clkops clkops_omap3_noncore_dpll_ops = { > - .enable = omap3_noncore_dpll_enable, > - .disable = omap3_noncore_dpll_disable, > - .allow_idle = omap3_dpll_allow_idle, > - .deny_idle = omap3_dpll_deny_idle, > -}; > - > -const struct clkops clkops_omap3_core_dpll_ops = { > - .allow_idle = omap3_dpll_allow_idle, > - .deny_idle = omap3_dpll_deny_idle, > -}; > -#endif > -- > 1.7.10.4 ^ permalink raw reply [flat|nested] 67+ messages in thread
[parent not found: <1352337181-29427-16-git-send-email-mturquette@ti.com>]
[parent not found: <alpine.DEB.2.00.1211081532210.20703@utopia.booyaka.com>]
* Re: [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk [not found] ` <alpine.DEB.2.00.1211081532210.20703@utopia.booyaka.com> @ 2012-11-09 20:32 ` Paul Walmsley 2012-11-09 21:05 ` Mike Turquette 0 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 20:32 UTC (permalink / raw) To: Mike Turquette; +Cc: linux-omap, rnayak, linux-arm-kernel, patches Here's another update on this one to add the twl.fck clock alias, recently added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix compile for twl-core.c by removing cpu_is_omap usage"). - Paul From: Rajendra Nayak <rnayak@ti.com> Date: Wed, 7 Nov 2012 21:09:35 -0700 Subject: [PATCH] ARM: OMAP2: clock: Add 24xx data using common struct clk The patch is the output from a python script which converts from the old OMAP clk format to COMMON clk format using a JSON parser in between which was developed by Paul Walmsley. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflowed macros; dropped 243x clkdev aliases in 242x file; added recalc_rate fn ptrs to APLL clocks; fixed some checkpatch warnings] [mturquette@ti.com: removed deprecated variables from omap24x0_clk_init] Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: fixed boot crash due to missing clock init code; added twl.fck alias] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/cclock2420_data.c | 1962 ++++++++++++++++++++++++++++++ arch/arm/mach-omap2/cclock2430_data.c | 2076 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/cm-regbits-24xx.h | 5 + arch/arm/mach-omap2/prm-regbits-24xx.h | 2 + 4 files changed, 4045 insertions(+) create mode 100644 arch/arm/mach-omap2/cclock2420_data.c create mode 100644 arch/arm/mach-omap2/cclock2430_data.c diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c new file mode 100644 index 0000000..f1ee478 --- /dev/null +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -0,0 +1,1962 @@ +/* + * OMAP2420 clock data + * + * Copyright (C) 2005-2012 Texas Instruments, Inc. + * Copyright (C) 2004-2011 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/clk-private.h> +#include <linux/list.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock2xxx.h" +#include "opp2xxx.h" +#include "cm2xxx.h" +#include "prm2xxx.h" +#include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" +#include "sdrc.h" +#include "control.h" + +#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR + +/* + * 2420 clock tree. + * + * NOTE:In many cases here we are assigning a 'default' parent. In + * many cases the parent is selectable. The set parent calls will + * also switch sources. + * + * Several sources are given initial rates which may be wrong, this will + * be fixed up in the init func. + * + * Things are broadly separated below by clock domains. It is + * noteworthy that most peripherals have dependencies on multiple clock + * domains. Many get their interface clocks from the L4 domain, but get + * functional clocks from fixed sources or other core domain derived + * clocks. + */ + +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); + +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); + +static struct clk osc_ck; + +static const struct clk_ops osc_ck_ops = { + .recalc_rate = &omap2_osc_clk_recalc, +}; + +static struct clk_hw_omap osc_ck_hw = { + .hw = { + .clk = &osc_ck, + }, +}; + +static struct clk osc_ck = { + .name = "osc_ck", + .ops = &osc_ck_ops, + .hw = &osc_ck_hw.hw, + .flags = CLK_IS_ROOT, +}; + +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +static struct clk sys_ck; + +static const char *sys_ck_parent_names[] = { + "osc_ck", +}; + +static const struct clk_ops sys_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2xxx_sys_clk_recalc, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); + +static struct dpll_data dpll_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP24XX_DPLL_MULT_MASK, + .div1_mask = OMAP24XX_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP24XX_EN_DPLL_MASK, + .max_multiplier = 1023, + .min_divider = 1, + .max_divider = 16, +}; + +static struct clk dpll_ck; + +static const char *dpll_ck_parent_names[] = { + "sys_ck", +}; + +static const struct clk_ops dpll_ck_ops = { + .init = &omap2_init_clk_clkdm, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap2_dpllcore_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap2_reprogram_dpllcore, +}; + +static struct clk_hw_omap dpll_ck_hw = { + .hw = { + .clk = &dpll_ck, + }, + .ops = &clkhwops_omap2xxx_dpll, + .dpll_data = &dpll_dd, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); + +static struct clk core_ck; + +static const char *core_ck_parent_names[] = { + "dpll_ck", +}; + +static const struct clk_ops core_ck_ops = { + .init = &omap2_init_clk_clkdm, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); + +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk aes_ick; + +static const char *aes_ick_parent_names[] = { + "l4_ck", +}; + +static const struct clk_ops aes_ick_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap aes_ick_hw = { + .hw = { + .clk = &aes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_AES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk apll54_ck; + +static const struct clk_ops apll54_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll54_enable, + .disable = &omap2_clk_apll_disable, + .recalc_rate = &omap2_clk_apll54_recalc, +}; + +static struct clk_hw_omap apll54_ck_hw = { + .hw = { + .clk = &apll54_ck, + }, + .ops = &clkhwops_apll54, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); + +static struct clk apll96_ck; + +static const struct clk_ops apll96_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll96_enable, + .disable = &omap2_clk_apll_disable, + .recalc_rate = &omap2_clk_apll96_recalc, +}; + +static struct clk_hw_omap apll96_ck_hw = { + .hw = { + .clk = &apll96_ck, + }, + .ops = &clkhwops_apll96, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); + +static struct clk func_96m_ck; + +static const char *func_96m_ck_parent_names[] = { + "apll96_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); + +static struct clk cam_fck; + +static const char *cam_fck_parent_names[] = { + "func_96m_ck", +}; + +static struct clk_hw_omap cam_fck_hw = { + .hw = { + .clk = &cam_fck, + }, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk cam_ick; + +static struct clk_hw_omap cam_ick_hw = { + .hw = { + .clk = &cam_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk des_ick; + +static struct clk_hw_omap des_ick_hw = { + .hw = { + .clk = &des_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_DES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate dsp_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 12, .val = 12, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel dsp_fck_clksel[] = { + { .parent = &core_ck, .rates = dsp_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dsp_fck_parent_names[] = { + "core_ck", +}; + +static const struct clk_ops dsp_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static const struct clksel dsp_ick_clksel[] = { + { .parent = &dsp_fck, .rates = dsp_ick_rates }, + { .parent = NULL }, +}; + +static const char *dsp_ick_parent_names[] = { + "dsp_fck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_IF_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), + OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait, + dsp_ick_parent_names, dsp_fck_ops); + +static const struct clksel_rate dss1_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss1_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_24XX }, + { .div = 8, .val = 8, .flags = RATE_IN_24XX }, + { .div = 9, .val = 9, .flags = RATE_IN_24XX }, + { .div = 12, .val = 12, .flags = RATE_IN_24XX }, + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dss1_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, + { .parent = &core_ck, .rates = dss1_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dss1_fck_parent_names[] = { + "sys_ck", "core_ck", +}; + +static struct clk dss1_fck; + +static const struct clk_ops dss1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS1_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS1_SHIFT, NULL, + dss1_fck_parent_names, dss1_fck_ops); + +static const struct clksel_rate dss2_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss2_fck_48m_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_apll96_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel func_48m_clksel[] = { + { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, + { .parent = &alt_ck, .rates = func_48m_alt_rates }, + { .parent = NULL }, +}; + +static const char *func_48m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +static struct clk func_48m_ck; + +static const struct clk_ops func_48m_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap func_48m_ck_hw = { + .hw = { + .clk = &func_48m_ck, + }, + .clksel = func_48m_clksel, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); + +static const struct clksel dss2_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, + { .parent = NULL }, +}; + +static const char *dss2_fck_parent_names[] = { + "sys_ck", "func_48m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS2_SHIFT, NULL, + dss2_fck_parent_names, dss1_fck_ops); + +static const char *func_54m_ck_parent_names[] = { + "apll54_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, + 0x0, NULL); + +static struct clk dss_54m_fck; + +static const char *dss_54m_fck_parent_names[] = { + "func_54m_ck", +}; + +static struct clk_hw_omap dss_54m_fck_hw = { + .hw = { + .clk = &dss_54m_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); + +static struct clk dss_ick; + +static struct clk_hw_omap dss_ick_hw = { + .hw = { + .clk = &dss_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk eac_fck; + +static struct clk_hw_omap eac_fck_hw = { + .hw = { + .clk = &eac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_EAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk eac_ick; + +static struct clk_hw_omap eac_ick_hw = { + .hw = { + .clk = &eac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_EAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk emul_ck; + +static struct clk_hw_omap emul_ck_hw = { + .hw = { + .clk = &emul_ck, + }, + .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); + +static struct clk fac_fck; + +static const char *fac_fck_parent_names[] = { + "func_12m_ck", +}; + +static struct clk_hw_omap fac_fck_hw = { + .hw = { + .clk = &fac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk fac_ick; + +static struct clk_hw_omap fac_ick_hw = { + .hw = { + .clk = &fac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel gfx_fck_clksel[] = { + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, + { .parent = NULL }, +}; + +static const char *gfx_2d_fck_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +static struct clk gfx_ick; + +static const char *gfx_ick_parent_names[] = { + "core_l3_ck", +}; + +static struct clk_hw_omap gfx_ick_hw = { + .hw = { + .clk = &gfx_ick, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .clkdm_name = "gfx_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk gpios_fck; + +static const char *gpios_fck_parent_names[] = { + "func_32k_ck", +}; + +static struct clk_hw_omap gpios_fck_hw = { + .hw = { + .clk = &gpios_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wu_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); + +static struct clk gpios_ick; + +static const char *gpios_ick_parent_names[] = { + "wu_l4_ick", +}; + +static struct clk_hw_omap gpios_ick_hw = { + .hw = { + .clk = &gpios_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk gpmc_fck; + +static struct clk_hw_omap gpmc_fck_hw = { + .hw = { + .clk = &gpmc_fck, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); + +static const struct clksel_rate gpt_alt_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel omap24xx_gpt_clksel[] = { + { .parent = &func_32k_ck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = &alt_ck, .rates = gpt_alt_rates }, + { .parent = NULL }, +}; + +static const char *gpt10_fck_parent_names[] = { + "func_32k_ck", "sys_ck", "alt_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT10_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt10_ick; + +static struct clk_hw_omap gpt10_ick_hw = { + .hw = { + .clk = &gpt10_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT10_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT11_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt11_ick; + +static struct clk_hw_omap gpt11_ick_hw = { + .hw = { + .clk = &gpt11_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT11_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT12_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt12_ick; + +static struct clk_hw_omap gpt12_ick_hw = { + .hw = { + .clk = &gpt12_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT12_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clk_ops gpt1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_GPT1_MASK, + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, gpt1_fck_ops); + +static struct clk gpt1_ick; + +static struct clk_hw_omap gpt1_ick_hw = { + .hw = { + .clk = &gpt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt2_ick; + +static struct clk_hw_omap gpt2_ick_hw = { + .hw = { + .clk = &gpt2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT3_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt3_ick; + +static struct clk_hw_omap gpt3_ick_hw = { + .hw = { + .clk = &gpt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT4_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt4_ick; + +static struct clk_hw_omap gpt4_ick_hw = { + .hw = { + .clk = &gpt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT5_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt5_ick; + +static struct clk_hw_omap gpt5_ick_hw = { + .hw = { + .clk = &gpt5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT6_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt6_ick; + +static struct clk_hw_omap gpt6_ick_hw = { + .hw = { + .clk = &gpt6_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT6_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT7_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt7_ick; + +static struct clk_hw_omap gpt7_ick_hw = { + .hw = { + .clk = &gpt7_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT7_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT8_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt8_ick; + +static struct clk_hw_omap gpt8_ick_hw = { + .hw = { + .clk = &gpt8_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT8_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT9_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt9_ick; + +static struct clk_hw_omap gpt9_ick_hw = { + .hw = { + .clk = &gpt9_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT9_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk hdq_fck; + +static struct clk_hw_omap hdq_fck_hw = { + .hw = { + .clk = &hdq_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk hdq_ick; + +static struct clk_hw_omap hdq_ick_hw = { + .hw = { + .clk = &hdq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c1_fck; + +static struct clk_hw_omap i2c1_fck_hw = { + .hw = { + .clk = &i2c1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk i2c1_ick; + +static struct clk_hw_omap i2c1_ick_hw = { + .hw = { + .clk = &i2c1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c2_fck; + +static struct clk_hw_omap i2c2_fck_hw = { + .hw = { + .clk = &i2c2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk i2c2_ick; + +static struct clk_hw_omap i2c2_ick_hw = { + .hw = { + .clk = &i2c2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP2420_CLKSEL_IVA_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static struct clk iva1_mpu_int_ifck; + +static const char *iva1_mpu_int_ifck_parent_names[] = { + "iva1_ifck", +}; + +static const struct clk_ops iva1_mpu_int_ifck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap_fixed_divisor_recalc, +}; + +static struct clk_hw_omap iva1_mpu_int_ifck_hw = { + .hw = { + .clk = &iva1_mpu_int_ifck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, + .clkdm_name = "iva1_clkdm", + .fixed_div = 2, +}; + +DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, + iva1_mpu_int_ifck_ops); + +static struct clk mailboxes_ick; + +static struct clk_hw_omap mailboxes_ick_hw = { + .hw = { + .clk = &mailboxes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parent_names[] = { + "func_96m_ck", "mcbsp_clks", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP1_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp1_ick; + +static struct clk_hw_omap mcbsp1_ick_hw = { + .hw = { + .clk = &mcbsp1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP2_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp2_ick; + +static struct clk_hw_omap mcbsp2_ick_hw = { + .hw = { + .clk = &mcbsp2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi1_fck; + +static const char *mcspi1_fck_parent_names[] = { + "func_48m_ck", +}; + +static struct clk_hw_omap mcspi1_fck_hw = { + .hw = { + .clk = &mcspi1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi1_ick; + +static struct clk_hw_omap mcspi1_ick_hw = { + .hw = { + .clk = &mcspi1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi2_fck; + +static struct clk_hw_omap mcspi2_fck_hw = { + .hw = { + .clk = &mcspi2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi2_ick; + +static struct clk_hw_omap mcspi2_ick_hw = { + .hw = { + .clk = &mcspi2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmc_fck; + +static struct clk_hw_omap mmc_fck_hw = { + .hw = { + .clk = &mmc_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_MMC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmc_ick; + +static struct clk_hw_omap mmc_ick_hw = { + .hw = { + .clk = &mmc_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_MMC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk mpu_wdt_fck; + +static struct clk_hw_omap mpu_wdt_fck_hw = { + .hw = { + .clk = &mpu_wdt_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk mpu_wdt_ick; + +static struct clk_hw_omap mpu_wdt_ick_hw = { + .hw = { + .clk = &mpu_wdt_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk mspro_fck; + +static struct clk_hw_omap mspro_fck_hw = { + .hw = { + .clk = &mspro_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mspro_ick; + +static struct clk_hw_omap mspro_ick_hw = { + .hw = { + .clk = &mspro_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk omapctrl_ick; + +static struct clk_hw_omap omapctrl_ick_hw = { + .hw = { + .clk = &omapctrl_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk pka_ick; + +static struct clk_hw_omap pka_ick_hw = { + .hw = { + .clk = &pka_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_PKA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk rng_ick; + +static struct clk_hw_omap rng_ick_hw = { + .hw = { + .clk = &rng_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_RNG_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk sdma_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdma_ick; + +static struct clk_hw_omap sdma_ick_hw = { + .hw = { + .clk = &sdma_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdrc_ick; + +static struct clk_hw_omap sdrc_ick_hw = { + .hw = { + .clk = &sdrc_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sha_ick; + +static struct clk_hw_omap sha_ick_hw = { + .hw = { + .clk = &sha_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_SHA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk ssi_l4_ick; + +static struct clk_hw_omap ssi_l4_ick_hw = { + .hw = { + .clk = &ssi_l4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_sst_fck_clksel[] = { + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *ssi_ssr_sst_fck_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", + ssi_ssr_sst_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_SSI_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, + ssi_ssr_sst_fck_parent_names, dsp_fck_ops); + +static struct clk sync_32k_ick; + +static struct clk_hw_omap sync_32k_ick_hw = { + .hw = { + .clk = &sync_32k_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_clkout_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel common_clkout_src_clksel[] = { + { .parent = &core_ck, .rates = common_clkout_src_core_rates }, + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, + { .parent = NULL }, +}; + +static const char *sys_clkout_src_parent_names[] = { + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm", + common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL, + OMAP2420_CLKOUT2_SOURCE_MASK, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, + OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +static struct clk uart1_fck; + +static struct clk_hw_omap uart1_fck_hw = { + .hw = { + .clk = &uart1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart1_ick; + +static struct clk_hw_omap uart1_ick_hw = { + .hw = { + .clk = &uart1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart2_fck; + +static struct clk_hw_omap uart2_fck_hw = { + .hw = { + .clk = &uart2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart2_ick; + +static struct clk_hw_omap uart2_ick_hw = { + .hw = { + .clk = &uart2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart3_fck; + +static struct clk_hw_omap uart3_fck_hw = { + .hw = { + .clk = &uart3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart3_ick; + +static struct clk_hw_omap uart3_ick_hw = { + .hw = { + .clk = &uart3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk usb_fck; + +static struct clk_hw_omap usb_fck_hw = { + .hw = { + .clk = &usb_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_USB_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel usb_l4_ick_clksel[] = { + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, + { .parent = NULL }, +}; + +static const char *usb_l4_ick_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_USB_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, + usb_l4_ick_parent_names, dsp_fck_ops); + +static struct clk virt_prcm_set; + +static const char *virt_prcm_set_parent_names[] = { + "mpu_ck", +}; + +static const struct clk_ops virt_prcm_set_ops = { + .recalc_rate = &omap2_table_mpu_recalc, + .set_rate = &omap2_select_table_rate, + .round_rate = &omap2_round_to_table_rate, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); + +static const struct clksel_rate vlynq_fck_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel_rate vlynq_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_242X }, + { .div = 2, .val = 2, .flags = RATE_IN_242X }, + { .div = 3, .val = 3, .flags = RATE_IN_242X }, + { .div = 4, .val = 4, .flags = RATE_IN_242X }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 9, .val = 9, .flags = RATE_IN_242X }, + { .div = 12, .val = 12, .flags = RATE_IN_242X }, + { .div = 16, .val = 16, .flags = RATE_IN_242X }, + { .div = 18, .val = 18, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel vlynq_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, + { .parent = &core_ck, .rates = vlynq_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *vlynq_fck_parent_names[] = { + "func_96m_ck", "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP2420_CLKSEL_VLYNQ_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, + vlynq_fck_parent_names, dss1_fck_ops); + +static struct clk vlynq_ick; + +static struct clk_hw_omap vlynq_ick_hw = { + .hw = { + .clk = &vlynq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_ick; + +static struct clk_hw_omap wdt1_ick_hw = { + .hw = { + .clk = &wdt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_WDT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_osc_ck; + +static const struct clk_ops wdt1_osc_ck_ops = {}; + +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); + +static struct clk wdt3_fck; + +static struct clk_hw_omap wdt3_fck_hw = { + .hw = { + .clk = &wdt3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_WDT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wdt3_ick; + +static struct clk_hw_omap wdt3_ick_hw = { + .hw = { + .clk = &wdt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_WDT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk wdt4_fck; + +static struct clk_hw_omap wdt4_fck_hw = { + .hw = { + .clk = &wdt4_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wdt4_ick; + +static struct clk_hw_omap wdt4_ick_hw = { + .hw = { + .clk = &wdt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); + +/* + * clkdev integration + */ + +static struct omap_clk omap2420_clks[] = { + /* external root sources */ + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), + CLK(NULL, "osc_ck", &osc_ck, CK_242X), + CLK(NULL, "sys_ck", &sys_ck, CK_242X), + CLK(NULL, "alt_ck", &alt_ck, CK_242X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), + /* internal analog sources */ + CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), + CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), + CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), + /* internal prcm root sources */ + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), + CLK(NULL, "core_ck", &core_ck, CK_242X), + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), + CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), + CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), + CLK(NULL, "emul_ck", &emul_ck, CK_242X), + /* mpu domain clocks */ + CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), + /* dsp domain clocks */ + CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), + CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), + CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), + CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), + /* GFX domain clocks */ + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), + /* DSS domain clocks */ + CLK("omapdss_dss", "ick", &dss_ick, CK_242X), + CLK(NULL, "dss_ick", &dss_ick, CK_242X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), + /* L4 domain clocks */ + CLK(NULL, "l4_ck", &l4_ck, CK_242X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X), + /* virtual meta-group clock */ + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), + /* general l4 interface ck, multi-parent functional clk */ + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), + CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), + CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), + CLK("omap24xxcam", "fck", &cam_fck, CK_242X), + CLK(NULL, "cam_fck", &cam_fck, CK_242X), + CLK("omap24xxcam", "ick", &cam_ick, CK_242X), + CLK(NULL, "cam_ick", &cam_ick, CK_242X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), + CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), + CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), + CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), + CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), + CLK(NULL, "fac_ick", &fac_ick, CK_242X), + CLK(NULL, "fac_fck", &fac_fck, CK_242X), + CLK(NULL, "eac_ick", &eac_ick, CK_242X), + CLK(NULL, "eac_fck", &eac_fck, CK_242X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), + CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), + CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), + CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), + CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), + CLK(NULL, "des_ick", &des_ick, CK_242X), + CLK("omap-sham", "ick", &sha_ick, CK_242X), + CLK(NULL, "sha_ick", &sha_ick, CK_242X), + CLK("omap_rng", "ick", &rng_ick, CK_242X), + CLK(NULL, "rng_ick", &rng_ick, CK_242X), + CLK("omap-aes", "ick", &aes_ick, CK_242X), + CLK(NULL, "aes_ick", &aes_ick, CK_242X), + CLK(NULL, "pka_ick", &pka_ick, CK_242X), + CLK(NULL, "usb_fck", &usb_fck, CK_242X), + CLK("musb-hdrc", "fck", &osc_ck, CK_242X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), +}; + + +static const char *enable_init_clks[] = { + "apll96_ck", + "apll54_ck", + "sync_32k_ick", + "omapctrl_ick", + "gpmc_fck", + "sdrc_ick", +}; + +/* + * init code + */ + +int __init omap2420_clk_init(void) +{ + const struct prcm_config *prcm; + struct omap_clk *c; + unsigned long clkrate; + + prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; + cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); + cpu_mask = RATE_IN_242X; + rate_table = omap2420_rate_table; + + /* Check the MPU rate set by bootloader */ + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw); + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + if (prcm->xtal_speed != sys_ck.rate) + continue; + if (prcm->dpll_speed <= clkrate) + break; + } + + curr_prcm_set = prcm; + + for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); + c++) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", + (clk_get_rate(&sys_ck) / 1000000), + (clk_get_rate(&sys_ck) / 100000) % 10, + (clk_get_rate(&dpll_ck) / 1000000), + (clk_get_rate(&mpu_ck) / 1000000)); + + return 0; +} diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c new file mode 100644 index 0000000..102fbba --- /dev/null +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -0,0 +1,2076 @@ +/* + * OMAP2430 clock data + * + * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc. + * Copyright (C) 2004-2011 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clk-private.h> +#include <linux/list.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock2xxx.h" +#include "opp2xxx.h" +#include "cm2xxx.h" +#include "prm2xxx.h" +#include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" +#include "sdrc.h" +#include "control.h" + +#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR + +/* + * 2430 clock tree. + * + * NOTE:In many cases here we are assigning a 'default' parent. In + * many cases the parent is selectable. The set parent calls will + * also switch sources. + * + * Several sources are given initial rates which may be wrong, this will + * be fixed up in the init func. + * + * Things are broadly separated below by clock domains. It is + * noteworthy that most peripherals have dependencies on multiple clock + * domains. Many get their interface clocks from the L4 domain, but get + * functional clocks from fixed sources or other core domain derived + * clocks. + */ + +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); + +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); + +static struct clk osc_ck; + +static const struct clk_ops osc_ck_ops = { + .enable = &omap2_enable_osc_ck, + .disable = omap2_disable_osc_ck, + .recalc_rate = &omap2_osc_clk_recalc, +}; + +static struct clk_hw_omap osc_ck_hw = { + .hw = { + .clk = &osc_ck, + }, +}; + +static struct clk osc_ck = { + .name = "osc_ck", + .ops = &osc_ck_ops, + .hw = &osc_ck_hw.hw, + .flags = CLK_IS_ROOT, +}; + +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +static struct clk sys_ck; + +static const char *sys_ck_parent_names[] = { + "osc_ck", +}; + +static const struct clk_ops sys_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2xxx_sys_clk_recalc, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); + +static struct dpll_data dpll_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP24XX_DPLL_MULT_MASK, + .div1_mask = OMAP24XX_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP24XX_EN_DPLL_MASK, + .max_multiplier = 1023, + .min_divider = 1, + .max_divider = 16, +}; + +static struct clk dpll_ck; + +static const char *dpll_ck_parent_names[] = { + "sys_ck", +}; + +static const struct clk_ops dpll_ck_ops = { + .init = &omap2_init_clk_clkdm, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap2_dpllcore_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap2_reprogram_dpllcore, +}; + +static struct clk_hw_omap dpll_ck_hw = { + .hw = { + .clk = &dpll_ck, + }, + .ops = &clkhwops_omap2xxx_dpll, + .dpll_data = &dpll_dd, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); + +static struct clk core_ck; + +static const char *core_ck_parent_names[] = { + "dpll_ck", +}; + +static const struct clk_ops core_ck_ops = { + .init = &omap2_init_clk_clkdm, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); + +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk aes_ick; + +static const char *aes_ick_parent_names[] = { + "l4_ck", +}; + +static const struct clk_ops aes_ick_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap aes_ick_hw = { + .hw = { + .clk = &aes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_AES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk apll54_ck; + +static const struct clk_ops apll54_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll54_enable, + .disable = &omap2_clk_apll_disable, + .recalc_rate = &omap2_clk_apll54_recalc, +}; + +static struct clk_hw_omap apll54_ck_hw = { + .hw = { + .clk = &apll54_ck, + }, + .ops = &clkhwops_apll54, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); + +static struct clk apll96_ck; + +static const struct clk_ops apll96_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll96_enable, + .disable = &omap2_clk_apll_disable, + .recalc_rate = &omap2_clk_apll96_recalc, +}; + +static struct clk_hw_omap apll96_ck_hw = { + .hw = { + .clk = &apll96_ck, + }, + .ops = &clkhwops_apll96, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); + +static const char *func_96m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, + OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); + +static struct clk cam_fck; + +static const char *cam_fck_parent_names[] = { + "func_96m_ck", +}; + +static struct clk_hw_omap cam_fck_hw = { + .hw = { + .clk = &cam_fck, + }, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk cam_ick; + +static struct clk_hw_omap cam_ick_hw = { + .hw = { + .clk = &cam_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk des_ick; + +static struct clk_hw_omap des_ick_hw = { + .hw = { + .clk = &des_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_DES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate dsp_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dsp_fck_clksel[] = { + { .parent = &core_ck, .rates = dsp_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dsp_fck_parent_names[] = { + "core_ck", +}; + +static struct clk dsp_fck; + +static const struct clk_ops dsp_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static const struct clksel_rate dss1_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss1_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_24XX }, + { .div = 8, .val = 8, .flags = RATE_IN_24XX }, + { .div = 9, .val = 9, .flags = RATE_IN_24XX }, + { .div = 12, .val = 12, .flags = RATE_IN_24XX }, + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dss1_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, + { .parent = &core_ck, .rates = dss1_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dss1_fck_parent_names[] = { + "sys_ck", "core_ck", +}; + +static const struct clk_ops dss1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS1_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS1_SHIFT, NULL, + dss1_fck_parent_names, dss1_fck_ops); + +static const struct clksel_rate dss2_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss2_fck_48m_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_apll96_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel func_48m_clksel[] = { + { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, + { .parent = &alt_ck, .rates = func_48m_alt_rates }, + { .parent = NULL }, +}; + +static const char *func_48m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +static struct clk func_48m_ck; + +static const struct clk_ops func_48m_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap func_48m_ck_hw = { + .hw = { + .clk = &func_48m_ck, + }, + .clksel = func_48m_clksel, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); + +static const struct clksel dss2_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, + { .parent = NULL }, +}; + +static const char *dss2_fck_parent_names[] = { + "sys_ck", "func_48m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS2_SHIFT, NULL, + dss2_fck_parent_names, dss1_fck_ops); + +static const char *func_54m_ck_parent_names[] = { + "apll54_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); + +static struct clk dss_54m_fck; + +static const char *dss_54m_fck_parent_names[] = { + "func_54m_ck", +}; + +static struct clk_hw_omap dss_54m_fck_hw = { + .hw = { + .clk = &dss_54m_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); + +static struct clk dss_ick; + +static struct clk_hw_omap dss_ick_hw = { + .hw = { + .clk = &dss_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk emul_ck; + +static struct clk_hw_omap emul_ck_hw = { + .hw = { + .clk = &emul_ck, + }, + .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); + +static struct clk fac_fck; + +static const char *fac_fck_parent_names[] = { + "func_12m_ck", +}; + +static struct clk_hw_omap fac_fck_hw = { + .hw = { + .clk = &fac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk fac_ick; + +static struct clk_hw_omap fac_ick_hw = { + .hw = { + .clk = &fac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel gfx_fck_clksel[] = { + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, + { .parent = NULL }, +}; + +static const char *gfx_2d_fck_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +static struct clk gfx_ick; + +static const char *gfx_ick_parent_names[] = { + "core_l3_ck", +}; + +static struct clk_hw_omap gfx_ick_hw = { + .hw = { + .clk = &gfx_ick, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .clkdm_name = "gfx_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk gpio5_fck; + +static const char *gpio5_fck_parent_names[] = { + "func_32k_ck", +}; + +static struct clk_hw_omap gpio5_fck_hw = { + .hw = { + .clk = &gpio5_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_GPIO5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk gpio5_ick; + +static struct clk_hw_omap gpio5_ick_hw = { + .hw = { + .clk = &gpio5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_GPIO5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk gpios_fck; + +static struct clk_hw_omap gpios_fck_hw = { + .hw = { + .clk = &gpios_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk wu_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); + +static struct clk gpios_ick; + +static const char *gpios_ick_parent_names[] = { + "wu_l4_ick", +}; + +static struct clk_hw_omap gpios_ick_hw = { + .hw = { + .clk = &gpios_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk gpmc_fck; + +static struct clk_hw_omap gpmc_fck_hw = { + .hw = { + .clk = &gpmc_fck, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); + +static const struct clksel_rate gpt_alt_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel omap24xx_gpt_clksel[] = { + { .parent = &func_32k_ck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = &alt_ck, .rates = gpt_alt_rates }, + { .parent = NULL }, +}; + +static const char *gpt10_fck_parent_names[] = { + "func_32k_ck", "sys_ck", "alt_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT10_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt10_ick; + +static struct clk_hw_omap gpt10_ick_hw = { + .hw = { + .clk = &gpt10_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT10_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT11_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt11_ick; + +static struct clk_hw_omap gpt11_ick_hw = { + .hw = { + .clk = &gpt11_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT11_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT12_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt12_ick; + +static struct clk_hw_omap gpt12_ick_hw = { + .hw = { + .clk = &gpt12_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT12_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clk_ops gpt1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_GPT1_MASK, + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, gpt1_fck_ops); + +static struct clk gpt1_ick; + +static struct clk_hw_omap gpt1_ick_hw = { + .hw = { + .clk = &gpt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt2_ick; + +static struct clk_hw_omap gpt2_ick_hw = { + .hw = { + .clk = &gpt2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT3_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt3_ick; + +static struct clk_hw_omap gpt3_ick_hw = { + .hw = { + .clk = &gpt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT4_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt4_ick; + +static struct clk_hw_omap gpt4_ick_hw = { + .hw = { + .clk = &gpt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT5_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt5_ick; + +static struct clk_hw_omap gpt5_ick_hw = { + .hw = { + .clk = &gpt5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT6_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt6_ick; + +static struct clk_hw_omap gpt6_ick_hw = { + .hw = { + .clk = &gpt6_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT6_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT7_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt7_ick; + +static struct clk_hw_omap gpt7_ick_hw = { + .hw = { + .clk = &gpt7_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT7_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk gpt8_fck; + +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT8_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt8_ick; + +static struct clk_hw_omap gpt8_ick_hw = { + .hw = { + .clk = &gpt8_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT8_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT9_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt9_ick; + +static struct clk_hw_omap gpt9_ick_hw = { + .hw = { + .clk = &gpt9_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT9_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk hdq_fck; + +static struct clk_hw_omap hdq_fck_hw = { + .hw = { + .clk = &hdq_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk hdq_ick; + +static struct clk_hw_omap hdq_ick_hw = { + .hw = { + .clk = &hdq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c1_ick; + +static struct clk_hw_omap i2c1_ick_hw = { + .hw = { + .clk = &i2c1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c2_ick; + +static struct clk_hw_omap i2c2_ick_hw = { + .hw = { + .clk = &i2c2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2chs1_fck; + +static struct clk_hw_omap i2chs1_fck_hw = { + .hw = { + .clk = &i2chs1_fck, + }, + .ops = &clkhwops_omap2430_i2chs_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk i2chs2_fck; + +static struct clk_hw_omap i2chs2_fck_hw = { + .hw = { + .clk = &i2chs2_fck, + }, + .ops = &clkhwops_omap2430_i2chs_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk icr_ick; + +static struct clk_hw_omap icr_ick_hw = { + .hw = { + .clk = &icr_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP2430_EN_ICR_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel dsp_ick_clksel[] = { + { .parent = &dsp_fck, .rates = dsp_ick_rates }, + { .parent = NULL }, +}; + +static const char *iva2_1_ick_parent_names[] = { + "dsp_fck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_IF_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + iva2_1_ick_parent_names, dsp_fck_ops); + +static struct clk mailboxes_ick; + +static struct clk_hw_omap mailboxes_ick_hw = { + .hw = { + .clk = &mailboxes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parent_names[] = { + "func_96m_ck", "mcbsp_clks", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP1_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp1_ick; + +static struct clk_hw_omap mcbsp1_ick_hw = { + .hw = { + .clk = &mcbsp1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP2_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp2_ick; + +static struct clk_hw_omap mcbsp2_ick_hw = { + .hw = { + .clk = &mcbsp2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP3_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp3_ick; + +static struct clk_hw_omap mcbsp3_ick_hw = { + .hw = { + .clk = &mcbsp3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP4_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp4_ick; + +static struct clk_hw_omap mcbsp4_ick_hw = { + .hw = { + .clk = &mcbsp4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP5_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp5_ick; + +static struct clk_hw_omap mcbsp5_ick_hw = { + .hw = { + .clk = &mcbsp5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi1_fck; + +static const char *mcspi1_fck_parent_names[] = { + "func_48m_ck", +}; + +static struct clk_hw_omap mcspi1_fck_hw = { + .hw = { + .clk = &mcspi1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi1_ick; + +static struct clk_hw_omap mcspi1_ick_hw = { + .hw = { + .clk = &mcspi1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi2_fck; + +static struct clk_hw_omap mcspi2_fck_hw = { + .hw = { + .clk = &mcspi2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi2_ick; + +static struct clk_hw_omap mcspi2_ick_hw = { + .hw = { + .clk = &mcspi2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi3_fck; + +static struct clk_hw_omap mcspi3_fck_hw = { + .hw = { + .clk = &mcspi3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi3_ick; + +static struct clk_hw_omap mcspi3_ick_hw = { + .hw = { + .clk = &mcspi3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate mdm_ick_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_243X }, + { .div = 4, .val = 4, .flags = RATE_IN_243X }, + { .div = 6, .val = 6, .flags = RATE_IN_243X }, + { .div = 9, .val = 9, .flags = RATE_IN_243X }, + { .div = 0 } +}; + +static const struct clksel mdm_ick_clksel[] = { + { .parent = &core_ck, .rates = mdm_ick_core_rates }, + { .parent = NULL }, +}; + +static const char *mdm_ick_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), + OMAP2430_CLKSEL_MDM_MASK, + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), + OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, + &clkhwops_iclk_wait, mdm_ick_parent_names, + dsp_fck_ops); + +static struct clk mdm_intc_ick; + +static struct clk_hw_omap mdm_intc_ick_hw = { + .hw = { + .clk = &mdm_intc_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mdm_osc_ck; + +static struct clk_hw_omap mdm_osc_ck_hw = { + .hw = { + .clk = &mdm_osc_ck, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), + .enable_bit = OMAP2430_EN_OSC_SHIFT, + .clkdm_name = "mdm_clkdm", +}; + +DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); + +static struct clk mmchs1_fck; + +static struct clk_hw_omap mmchs1_fck_hw = { + .hw = { + .clk = &mmchs1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmchs1_ick; + +static struct clk_hw_omap mmchs1_ick_hw = { + .hw = { + .clk = &mmchs1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmchs2_fck; + +static struct clk_hw_omap mmchs2_fck_hw = { + .hw = { + .clk = &mmchs2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmchs2_ick; + +static struct clk_hw_omap mmchs2_ick_hw = { + .hw = { + .clk = &mmchs2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmchsdb1_fck; + +static struct clk_hw_omap mmchsdb1_fck_hw = { + .hw = { + .clk = &mmchsdb1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk mmchsdb2_fck; + +static struct clk_hw_omap mmchsdb2_fck_hw = { + .hw = { + .clk = &mmchsdb2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk mpu_wdt_fck; + +static struct clk_hw_omap mpu_wdt_fck_hw = { + .hw = { + .clk = &mpu_wdt_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk mpu_wdt_ick; + +static struct clk_hw_omap mpu_wdt_ick_hw = { + .hw = { + .clk = &mpu_wdt_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk mspro_fck; + +static struct clk_hw_omap mspro_fck_hw = { + .hw = { + .clk = &mspro_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mspro_ick; + +static struct clk_hw_omap mspro_ick_hw = { + .hw = { + .clk = &mspro_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk omapctrl_ick; + +static struct clk_hw_omap omapctrl_ick_hw = { + .hw = { + .clk = &omapctrl_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk pka_ick; + +static struct clk_hw_omap pka_ick_hw = { + .hw = { + .clk = &pka_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_PKA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk rng_ick; + +static struct clk_hw_omap rng_ick_hw = { + .hw = { + .clk = &rng_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_RNG_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk sdma_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdma_ick; + +static struct clk_hw_omap sdma_ick_hw = { + .hw = { + .clk = &sdma_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdrc_ick; + +static struct clk_hw_omap sdrc_ick_hw = { + .hw = { + .clk = &sdrc_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP2430_EN_SDRC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sha_ick; + +static struct clk_hw_omap sha_ick_hw = { + .hw = { + .clk = &sha_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_SHA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk ssi_l4_ick; + +static struct clk_hw_omap ssi_l4_ick_hw = { + .hw = { + .clk = &ssi_l4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_243X }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_sst_fck_clksel[] = { + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *ssi_ssr_sst_fck_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", + ssi_ssr_sst_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_SSI_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, + ssi_ssr_sst_fck_parent_names, dsp_fck_ops); + +static struct clk sync_32k_ick; + +static struct clk_hw_omap sync_32k_ick_hw = { + .hw = { + .clk = &sync_32k_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_clkout_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel common_clkout_src_clksel[] = { + { .parent = &core_ck, .rates = common_clkout_src_core_rates }, + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, + { .parent = NULL }, +}; + +static const char *sys_clkout_src_parent_names[] = { + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +static struct clk uart1_fck; + +static struct clk_hw_omap uart1_fck_hw = { + .hw = { + .clk = &uart1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart1_ick; + +static struct clk_hw_omap uart1_ick_hw = { + .hw = { + .clk = &uart1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart2_fck; + +static struct clk_hw_omap uart2_fck_hw = { + .hw = { + .clk = &uart2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart2_ick; + +static struct clk_hw_omap uart2_ick_hw = { + .hw = { + .clk = &uart2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart3_fck; + +static struct clk_hw_omap uart3_fck_hw = { + .hw = { + .clk = &uart3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart3_ick; + +static struct clk_hw_omap uart3_ick_hw = { + .hw = { + .clk = &uart3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk usb_fck; + +static struct clk_hw_omap usb_fck_hw = { + .hw = { + .clk = &usb_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_USB_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel usb_l4_ick_clksel[] = { + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, + { .parent = NULL }, +}; + +static const char *usb_l4_ick_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_USB_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, + usb_l4_ick_parent_names, dsp_fck_ops); + +static struct clk usbhs_ick; + +static struct clk_hw_omap usbhs_ick_hw = { + .hw = { + .clk = &usbhs_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_USBHS_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk virt_prcm_set; + +static const char *virt_prcm_set_parent_names[] = { + "mpu_ck", +}; + +static const struct clk_ops virt_prcm_set_ops = { + .recalc_rate = &omap2_table_mpu_recalc, + .set_rate = &omap2_select_table_rate, + .round_rate = &omap2_round_to_table_rate, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); + +static struct clk wdt1_ick; + +static struct clk_hw_omap wdt1_ick_hw = { + .hw = { + .clk = &wdt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_WDT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_osc_ck; + +static const struct clk_ops wdt1_osc_ck_ops = {}; + +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); + +static struct clk wdt4_fck; + +static struct clk_hw_omap wdt4_fck_hw = { + .hw = { + .clk = &wdt4_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk wdt4_ick; + +static struct clk_hw_omap wdt4_ick_hw = { + .hw = { + .clk = &wdt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); + +/* + * clkdev integration + */ + +static struct omap_clk omap2430_clks[] = { + /* external root sources */ + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), + CLK(NULL, "osc_ck", &osc_ck, CK_243X), + CLK("twl", "fck", &osc_ck, CK_243X), + CLK(NULL, "sys_ck", &sys_ck, CK_243X), + CLK(NULL, "alt_ck", &alt_ck, CK_243X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), + /* internal analog sources */ + CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), + CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), + CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), + /* internal prcm root sources */ + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), + CLK(NULL, "core_ck", &core_ck, CK_243X), + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), + CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), + CLK(NULL, "emul_ck", &emul_ck, CK_243X), + /* mpu domain clocks */ + CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), + /* dsp domain clocks */ + CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), + CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), + /* GFX domain clocks */ + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), + /* Modem domain clocks */ + CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), + /* DSS domain clocks */ + CLK("omapdss_dss", "ick", &dss_ick, CK_243X), + CLK(NULL, "dss_ick", &dss_ick, CK_243X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), + /* L4 domain clocks */ + CLK(NULL, "l4_ck", &l4_ck, CK_243X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X), + /* virtual meta-group clock */ + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), + /* general l4 interface ck, multi-parent functional clk */ + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), + CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), + CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), + CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), + CLK(NULL, "icr_ick", &icr_ick, CK_243X), + CLK("omap24xxcam", "fck", &cam_fck, CK_243X), + CLK(NULL, "cam_fck", &cam_fck, CK_243X), + CLK("omap24xxcam", "ick", &cam_ick, CK_243X), + CLK(NULL, "cam_ick", &cam_ick, CK_243X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), + CLK(NULL, "fac_ick", &fac_ick, CK_243X), + CLK(NULL, "fac_fck", &fac_fck, CK_243X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), + CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), + CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), + CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), + CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), + CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), + CLK(NULL, "des_ick", &des_ick, CK_243X), + CLK("omap-sham", "ick", &sha_ick, CK_243X), + CLK("omap_rng", "ick", &rng_ick, CK_243X), + CLK(NULL, "rng_ick", &rng_ick, CK_243X), + CLK("omap-aes", "ick", &aes_ick, CK_243X), + CLK(NULL, "pka_ick", &pka_ick, CK_243X), + CLK(NULL, "usb_fck", &usb_fck, CK_243X), + CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), + CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), + CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), + CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), + CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), + CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), + CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), + CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), + CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), + CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), + CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), +}; + +static const char *enable_init_clks[] = { + "apll96_ck", + "apll54_ck", + "sync_32k_ick", + "omapctrl_ick", + "gpmc_fck", + "sdrc_ick", +}; + +/* + * init code + */ + +int __init omap2430_clk_init(void) +{ + const struct prcm_config *prcm; + struct omap_clk *c; + unsigned long clkrate; + + prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; + cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); + cpu_mask = RATE_IN_243X; + rate_table = omap2430_rate_table; + + /* Check the MPU rate set by bootloader */ + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw); + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + if (prcm->xtal_speed != sys_ck.rate) + continue; + if (prcm->dpll_speed <= clkrate) + break; + } + curr_prcm_set = prcm; + + for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); + c++) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", + (clk_get_rate(&sys_ck) / 1000000), + (clk_get_rate(&sys_ck) / 100000) % 10, + (clk_get_rate(&dpll_ck) / 1000000), + (clk_get_rate(&mpu_ck) / 1000000)); + + return 0; +} diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 6862904..f3fcba2 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -59,6 +59,7 @@ /* CM_CLKSEL_MPU */ #define OMAP24XX_CLKSEL_MPU_SHIFT 0 #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) +#define OMAP24XX_CLKSEL_MPU_WIDTH 5 /* CM_CLKSTCTRL_MPU */ #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 @@ -237,8 +238,10 @@ #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) #define OMAP24XX_CLKSEL_L4_SHIFT 5 #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) +#define OMAP24XX_CLKSEL_L4_WIDTH 2 #define OMAP24XX_CLKSEL_L3_SHIFT 0 #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) +#define OMAP24XX_CLKSEL_L3_WIDTH 5 /* CM_CLKSEL2_CORE */ #define OMAP24XX_CLKSEL_GPT12_SHIFT 22 @@ -361,8 +364,10 @@ #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) #define OMAP24XX_54M_SOURCE_SHIFT 5 #define OMAP24XX_54M_SOURCE_MASK (1 << 5) +#define OMAP24XX_54M_SOURCE_WIDTH 1 #define OMAP2430_96M_SOURCE_SHIFT 4 #define OMAP2430_96M_SOURCE_MASK (1 << 4) +#define OMAP2430_96M_SOURCE_WIDTH 1 #define OMAP24XX_48M_SOURCE_SHIFT 3 #define OMAP24XX_48M_SOURCE_MASK (1 << 3) #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 638da6d..91aa510 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -107,12 +107,14 @@ #define OMAP2420_CLKOUT2_EN_MASK (1 << 15) #define OMAP2420_CLKOUT2_DIV_SHIFT 11 #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) +#define OMAP2420_CLKOUT2_DIV_WIDTH 3 #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) #define OMAP24XX_CLKOUT_EN_SHIFT 7 #define OMAP24XX_CLKOUT_EN_MASK (1 << 7) #define OMAP24XX_CLKOUT_DIV_SHIFT 3 #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) +#define OMAP24XX_CLKOUT_DIV_WIDTH 3 #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk 2012-11-09 20:32 ` [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk Paul Walmsley @ 2012-11-09 21:05 ` Mike Turquette 2012-11-09 21:22 ` Paul Walmsley 0 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-09 21:05 UTC (permalink / raw) To: Paul Walmsley; +Cc: linux-omap, rnayak, linux-arm-kernel, patches Quoting Paul Walmsley (2012-11-09 12:32:59) > Here's another update on this one to add the twl.fck clock alias, recently > added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix > compile for twl-core.c by removing cpu_is_omap usage"). > I'll post a new series to the list with these fixes rolled in. Do you want me to squash the clkdm_clk_disable/usecount patch into another patch in the series or keep it separate? Separate might be good since we're going to replace that solution with some force-disable thing in the future. Regards, Mike > > - Paul > > From: Rajendra Nayak <rnayak@ti.com> > Date: Wed, 7 Nov 2012 21:09:35 -0700 > Subject: [PATCH] ARM: OMAP2: clock: Add 24xx data using common struct clk > > The patch is the output from a python script which converts > from the old OMAP clk format to COMMON clk format using a > JSON parser in between which was developed by Paul Walmsley. > > Signed-off-by: Rajendra Nayak <rnayak@ti.com> > [paul@pwsan.com: replace omap2_init_clksel_parent() with > omap2_clksel_find_parent_index(); reflowed macros; dropped 243x clkdev > aliases in 242x file; added recalc_rate fn ptrs to APLL clocks; > fixed some checkpatch warnings] > [mturquette@ti.com: removed deprecated variables from omap24x0_clk_init] > Signed-off-by: Mike Turquette <mturquette@ti.com> > [paul@pwsan.com: fixed boot crash due to missing clock init code; added twl.fck > alias] > Signed-off-by: Paul Walmsley <paul@pwsan.com> > --- > arch/arm/mach-omap2/cclock2420_data.c | 1962 ++++++++++++++++++++++++++++++ > arch/arm/mach-omap2/cclock2430_data.c | 2076 ++++++++++++++++++++++++++++++++ > arch/arm/mach-omap2/cm-regbits-24xx.h | 5 + > arch/arm/mach-omap2/prm-regbits-24xx.h | 2 + > 4 files changed, 4045 insertions(+) > create mode 100644 arch/arm/mach-omap2/cclock2420_data.c > create mode 100644 arch/arm/mach-omap2/cclock2430_data.c > > diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c > new file mode 100644 > index 0000000..f1ee478 > --- /dev/null > +++ b/arch/arm/mach-omap2/cclock2420_data.c > @@ -0,0 +1,1962 @@ > +/* > + * OMAP2420 clock data > + * > + * Copyright (C) 2005-2012 Texas Instruments, Inc. > + * Copyright (C) 2004-2011 Nokia Corporation > + * > + * Contacts: > + * Richard Woodruff <r-woodruff2@ti.com> > + * Paul Walmsley > + * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/kernel.h> > +#include <linux/io.h> > +#include <linux/clk.h> > +#include <linux/clk-private.h> > +#include <linux/list.h> > + > +#include "soc.h" > +#include "iomap.h" > +#include "clock.h" > +#include "clock2xxx.h" > +#include "opp2xxx.h" > +#include "cm2xxx.h" > +#include "prm2xxx.h" > +#include "prm-regbits-24xx.h" > +#include "cm-regbits-24xx.h" > +#include "sdrc.h" > +#include "control.h" > + > +#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR > + > +/* > + * 2420 clock tree. > + * > + * NOTE:In many cases here we are assigning a 'default' parent. In > + * many cases the parent is selectable. The set parent calls will > + * also switch sources. > + * > + * Several sources are given initial rates which may be wrong, this will > + * be fixed up in the init func. > + * > + * Things are broadly separated below by clock domains. It is > + * noteworthy that most peripherals have dependencies on multiple clock > + * domains. Many get their interface clocks from the L4 domain, but get > + * functional clocks from fixed sources or other core domain derived > + * clocks. > + */ > + > +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); > + > +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); > + > +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); > + > +static struct clk osc_ck; > + > +static const struct clk_ops osc_ck_ops = { > + .recalc_rate = &omap2_osc_clk_recalc, > +}; > + > +static struct clk_hw_omap osc_ck_hw = { > + .hw = { > + .clk = &osc_ck, > + }, > +}; > + > +static struct clk osc_ck = { > + .name = "osc_ck", > + .ops = &osc_ck_ops, > + .hw = &osc_ck_hw.hw, > + .flags = CLK_IS_ROOT, > +}; > + > +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); > + > +static struct clk sys_ck; > + > +static const char *sys_ck_parent_names[] = { > + "osc_ck", > +}; > + > +static const struct clk_ops sys_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .recalc_rate = &omap2xxx_sys_clk_recalc, > +}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); > +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); > + > +static struct dpll_data dpll_dd = { > + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), > + .mult_mask = OMAP24XX_DPLL_MULT_MASK, > + .div1_mask = OMAP24XX_DPLL_DIV_MASK, > + .clk_bypass = &sys_ck, > + .clk_ref = &sys_ck, > + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), > + .enable_mask = OMAP24XX_EN_DPLL_MASK, > + .max_multiplier = 1023, > + .min_divider = 1, > + .max_divider = 16, > +}; > + > +static struct clk dpll_ck; > + > +static const char *dpll_ck_parent_names[] = { > + "sys_ck", > +}; > + > +static const struct clk_ops dpll_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .get_parent = &omap2_init_dpll_parent, > + .recalc_rate = &omap2_dpllcore_recalc, > + .round_rate = &omap2_dpll_round_rate, > + .set_rate = &omap2_reprogram_dpllcore, > +}; > + > +static struct clk_hw_omap dpll_ck_hw = { > + .hw = { > + .clk = &dpll_ck, > + }, > + .ops = &clkhwops_omap2xxx_dpll, > + .dpll_data = &dpll_dd, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); > + > +static struct clk core_ck; > + > +static const char *core_ck_parent_names[] = { > + "dpll_ck", > +}; > + > +static const struct clk_ops core_ck_ops = { > + .init = &omap2_init_clk_clkdm, > +}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); > +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); > + > +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, > + CLK_DIVIDER_ONE_BASED, NULL); > + > +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, > + CLK_DIVIDER_ONE_BASED, NULL); > + > +static struct clk aes_ick; > + > +static const char *aes_ick_parent_names[] = { > + "l4_ck", > +}; > + > +static const struct clk_ops aes_ick_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > +}; > + > +static struct clk_hw_omap aes_ick_hw = { > + .hw = { > + .clk = &aes_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_AES_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk apll54_ck; > + > +static const struct clk_ops apll54_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_clk_apll54_enable, > + .disable = &omap2_clk_apll_disable, > + .recalc_rate = &omap2_clk_apll54_recalc, > +}; > + > +static struct clk_hw_omap apll54_ck_hw = { > + .hw = { > + .clk = &apll54_ck, > + }, > + .ops = &clkhwops_apll54, > + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), > + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); > + > +static struct clk apll96_ck; > + > +static const struct clk_ops apll96_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_clk_apll96_enable, > + .disable = &omap2_clk_apll_disable, > + .recalc_rate = &omap2_clk_apll96_recalc, > +}; > + > +static struct clk_hw_omap apll96_ck_hw = { > + .hw = { > + .clk = &apll96_ck, > + }, > + .ops = &clkhwops_apll96, > + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), > + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); > + > +static struct clk func_96m_ck; > + > +static const char *func_96m_ck_parent_names[] = { > + "apll96_ck", > +}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); > +DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); > + > +static struct clk cam_fck; > + > +static const char *cam_fck_parent_names[] = { > + "func_96m_ck", > +}; > + > +static struct clk_hw_omap cam_fck_hw = { > + .hw = { > + .clk = &cam_fck, > + }, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_CAM_SHIFT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk cam_ick; > + > +static struct clk_hw_omap cam_ick_hw = { > + .hw = { > + .clk = &cam_ick, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_CAM_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk des_ick; > + > +static struct clk_hw_omap des_ick_hw = { > + .hw = { > + .clk = &des_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_DES_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate dsp_fck_core_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, > + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, > + { .div = 6, .val = 6, .flags = RATE_IN_242X }, > + { .div = 8, .val = 8, .flags = RATE_IN_242X }, > + { .div = 12, .val = 12, .flags = RATE_IN_242X }, > + { .div = 0 } > +}; > + > +static const struct clksel dsp_fck_clksel[] = { > + { .parent = &core_ck, .rates = dsp_fck_core_rates }, > + { .parent = NULL }, > +}; > + > +static const char *dsp_fck_parent_names[] = { > + "core_ck", > +}; > + > +static const struct clk_ops dsp_fck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > + .recalc_rate = &omap2_clksel_recalc, > + .set_rate = &omap2_clksel_set_rate, > + .round_rate = &omap2_clksel_round_rate, > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), > + OMAP24XX_CLKSEL_DSP_MASK, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), > + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, > + dsp_fck_parent_names, dsp_fck_ops); > + > +static const struct clksel dsp_ick_clksel[] = { > + { .parent = &dsp_fck, .rates = dsp_ick_rates }, > + { .parent = NULL }, > +}; > + > +static const char *dsp_ick_parent_names[] = { > + "dsp_fck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), > + OMAP24XX_CLKSEL_DSP_IF_MASK, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), > + OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait, > + dsp_ick_parent_names, dsp_fck_ops); > + > +static const struct clksel_rate dss1_fck_sys_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate dss1_fck_core_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, > + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, > + { .div = 5, .val = 5, .flags = RATE_IN_24XX }, > + { .div = 6, .val = 6, .flags = RATE_IN_24XX }, > + { .div = 8, .val = 8, .flags = RATE_IN_24XX }, > + { .div = 9, .val = 9, .flags = RATE_IN_24XX }, > + { .div = 12, .val = 12, .flags = RATE_IN_24XX }, > + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel dss1_fck_clksel[] = { > + { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, > + { .parent = &core_ck, .rates = dss1_fck_core_rates }, > + { .parent = NULL }, > +}; > + > +static const char *dss1_fck_parent_names[] = { > + "sys_ck", "core_ck", > +}; > + > +static struct clk dss1_fck; > + > +static const struct clk_ops dss1_fck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > + .recalc_rate = &omap2_clksel_recalc, > + .get_parent = &omap2_clksel_find_parent_index, > + .set_parent = &omap2_clksel_set_parent, > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_DSS1_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_DSS1_SHIFT, NULL, > + dss1_fck_parent_names, dss1_fck_ops); > + > +static const struct clksel_rate dss2_fck_sys_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate dss2_fck_48m_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate func_48m_apll96_rates[] = { > + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate func_48m_alt_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel func_48m_clksel[] = { > + { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, > + { .parent = &alt_ck, .rates = func_48m_alt_rates }, > + { .parent = NULL }, > +}; > + > +static const char *func_48m_ck_parent_names[] = { > + "apll96_ck", "alt_ck", > +}; > + > +static struct clk func_48m_ck; > + > +static const struct clk_ops func_48m_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .recalc_rate = &omap2_clksel_recalc, > + .set_rate = &omap2_clksel_set_rate, > + .round_rate = &omap2_clksel_round_rate, > + .get_parent = &omap2_clksel_find_parent_index, > + .set_parent = &omap2_clksel_set_parent, > +}; > + > +static struct clk_hw_omap func_48m_ck_hw = { > + .hw = { > + .clk = &func_48m_ck, > + }, > + .clksel = func_48m_clksel, > + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), > + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); > + > +static const struct clksel dss2_fck_clksel[] = { > + { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, > + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, > + { .parent = NULL }, > +}; > + > +static const char *dss2_fck_parent_names[] = { > + "sys_ck", "func_48m_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_DSS2_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_DSS2_SHIFT, NULL, > + dss2_fck_parent_names, dss1_fck_ops); > + > +static const char *func_54m_ck_parent_names[] = { > + "apll54_ck", "alt_ck", > +}; > + > +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, > + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), > + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, > + 0x0, NULL); > + > +static struct clk dss_54m_fck; > + > +static const char *dss_54m_fck_parent_names[] = { > + "func_54m_ck", > +}; > + > +static struct clk_hw_omap dss_54m_fck_hw = { > + .hw = { > + .clk = &dss_54m_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_TV_SHIFT, > + .clkdm_name = "dss_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); > + > +static struct clk dss_ick; > + > +static struct clk_hw_omap dss_ick_hw = { > + .hw = { > + .clk = &dss_ick, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_DSS1_SHIFT, > + .clkdm_name = "dss_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk eac_fck; > + > +static struct clk_hw_omap eac_fck_hw = { > + .hw = { > + .clk = &eac_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP2420_EN_EAC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk eac_ick; > + > +static struct clk_hw_omap eac_ick_hw = { > + .hw = { > + .clk = &eac_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP2420_EN_EAC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk emul_ck; > + > +static struct clk_hw_omap emul_ck_hw = { > + .hw = { > + .clk = &emul_ck, > + }, > + .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, > + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); > + > +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); > + > +static struct clk fac_fck; > + > +static const char *fac_fck_parent_names[] = { > + "func_12m_ck", > +}; > + > +static struct clk_hw_omap fac_fck_hw = { > + .hw = { > + .clk = &fac_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_FAC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); > + > +static struct clk fac_ick; > + > +static struct clk_hw_omap fac_ick_hw = { > + .hw = { > + .clk = &fac_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_FAC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel gfx_fck_clksel[] = { > + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, > + { .parent = NULL }, > +}; > + > +static const char *gfx_2d_fck_parent_names[] = { > + "core_l3_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, > + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), > + OMAP_CLKSEL_GFX_MASK, > + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), > + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, > + gfx_2d_fck_parent_names, dsp_fck_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, > + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), > + OMAP_CLKSEL_GFX_MASK, > + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), > + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, > + gfx_2d_fck_parent_names, dsp_fck_ops); > + > +static struct clk gfx_ick; > + > +static const char *gfx_ick_parent_names[] = { > + "core_l3_ck", > +}; > + > +static struct clk_hw_omap gfx_ick_hw = { > + .hw = { > + .clk = &gfx_ick, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), > + .enable_bit = OMAP_EN_GFX_SHIFT, > + .clkdm_name = "gfx_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); > + > +static struct clk gpios_fck; > + > +static const char *gpios_fck_parent_names[] = { > + "func_32k_ck", > +}; > + > +static struct clk_hw_omap gpios_fck_hw = { > + .hw = { > + .clk = &gpios_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), > + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); > + > +static struct clk wu_l4_ick; > + > +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); > +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); > + > +static struct clk gpios_ick; > + > +static const char *gpios_ick_parent_names[] = { > + "wu_l4_ick", > +}; > + > +static struct clk_hw_omap gpios_ick_hw = { > + .hw = { > + .clk = &gpios_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static struct clk gpmc_fck; > + > +static struct clk_hw_omap gpmc_fck_hw = { > + .hw = { > + .clk = &gpmc_fck, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), > + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); > + > +static const struct clksel_rate gpt_alt_rates[] = { > + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel omap24xx_gpt_clksel[] = { > + { .parent = &func_32k_ck, .rates = gpt_32k_rates }, > + { .parent = &sys_ck, .rates = gpt_sys_rates }, > + { .parent = &alt_ck, .rates = gpt_alt_rates }, > + { .parent = NULL }, > +}; > + > +static const char *gpt10_fck_parent_names[] = { > + "func_32k_ck", "sys_ck", "alt_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT10_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt10_ick; > + > +static struct clk_hw_omap gpt10_ick_hw = { > + .hw = { > + .clk = &gpt10_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT10_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT11_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt11_ick; > + > +static struct clk_hw_omap gpt11_ick_hw = { > + .hw = { > + .clk = &gpt11_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT11_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT12_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt12_ick; > + > +static struct clk_hw_omap gpt12_ick_hw = { > + .hw = { > + .clk = &gpt12_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT12_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clk_ops gpt1_fck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > + .recalc_rate = &omap2_clksel_recalc, > + .set_rate = &omap2_clksel_set_rate, > + .round_rate = &omap2_clksel_round_rate, > + .get_parent = &omap2_clksel_find_parent_index, > + .set_parent = &omap2_clksel_set_parent, > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_GPT1_MASK, > + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), > + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, gpt1_fck_ops); > + > +static struct clk gpt1_ick; > + > +static struct clk_hw_omap gpt1_ick_hw = { > + .hw = { > + .clk = &gpt1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_GPT1_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT2_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt2_ick; > + > +static struct clk_hw_omap gpt2_ick_hw = { > + .hw = { > + .clk = &gpt2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT3_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt3_ick; > + > +static struct clk_hw_omap gpt3_ick_hw = { > + .hw = { > + .clk = &gpt3_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT4_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt4_ick; > + > +static struct clk_hw_omap gpt4_ick_hw = { > + .hw = { > + .clk = &gpt4_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT4_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT5_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt5_ick; > + > +static struct clk_hw_omap gpt5_ick_hw = { > + .hw = { > + .clk = &gpt5_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT5_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT6_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt6_ick; > + > +static struct clk_hw_omap gpt6_ick_hw = { > + .hw = { > + .clk = &gpt6_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT6_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT7_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt7_ick; > + > +static struct clk_hw_omap gpt7_ick_hw = { > + .hw = { > + .clk = &gpt7_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT7_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT8_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt8_ick; > + > +static struct clk_hw_omap gpt8_ick_hw = { > + .hw = { > + .clk = &gpt8_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT8_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT9_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt9_ick; > + > +static struct clk_hw_omap gpt9_ick_hw = { > + .hw = { > + .clk = &gpt9_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT9_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk hdq_fck; > + > +static struct clk_hw_omap hdq_fck_hw = { > + .hw = { > + .clk = &hdq_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); > + > +static struct clk hdq_ick; > + > +static struct clk_hw_omap hdq_ick_hw = { > + .hw = { > + .clk = &hdq_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk i2c1_fck; > + > +static struct clk_hw_omap i2c1_fck_hw = { > + .hw = { > + .clk = &i2c1_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP2420_EN_I2C1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); > + > +static struct clk i2c1_ick; > + > +static struct clk_hw_omap i2c1_ick_hw = { > + .hw = { > + .clk = &i2c1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP2420_EN_I2C1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk i2c2_fck; > + > +static struct clk_hw_omap i2c2_fck_hw = { > + .hw = { > + .clk = &i2c2_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP2420_EN_I2C2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); > + > +static struct clk i2c2_ick; > + > +static struct clk_hw_omap i2c2_ick_hw = { > + .hw = { > + .clk = &i2c2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP2420_EN_I2C2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), > + OMAP2420_CLKSEL_IVA_MASK, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), > + OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, > + dsp_fck_parent_names, dsp_fck_ops); > + > +static struct clk iva1_mpu_int_ifck; > + > +static const char *iva1_mpu_int_ifck_parent_names[] = { > + "iva1_ifck", > +}; > + > +static const struct clk_ops iva1_mpu_int_ifck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > + .recalc_rate = &omap_fixed_divisor_recalc, > +}; > + > +static struct clk_hw_omap iva1_mpu_int_ifck_hw = { > + .hw = { > + .clk = &iva1_mpu_int_ifck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), > + .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, > + .clkdm_name = "iva1_clkdm", > + .fixed_div = 2, > +}; > + > +DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, > + iva1_mpu_int_ifck_ops); > + > +static struct clk mailboxes_ick; > + > +static struct clk_hw_omap mailboxes_ick_hw = { > + .hw = { > + .clk = &mailboxes_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate common_mcbsp_96m_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel mcbsp_fck_clksel[] = { > + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, > + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, > + { .parent = NULL }, > +}; > + > +static const char *mcbsp1_fck_parent_names[] = { > + "func_96m_ck", "mcbsp_clks", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, > + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), > + OMAP2_MCBSP1_CLKS_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, > + mcbsp1_fck_parent_names, dss1_fck_ops); > + > +static struct clk mcbsp1_ick; > + > +static struct clk_hw_omap mcbsp1_ick_hw = { > + .hw = { > + .clk = &mcbsp1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, > + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), > + OMAP2_MCBSP2_CLKS_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, > + mcbsp1_fck_parent_names, dss1_fck_ops); > + > +static struct clk mcbsp2_ick; > + > +static struct clk_hw_omap mcbsp2_ick_hw = { > + .hw = { > + .clk = &mcbsp2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mcspi1_fck; > + > +static const char *mcspi1_fck_parent_names[] = { > + "func_48m_ck", > +}; > + > +static struct clk_hw_omap mcspi1_fck_hw = { > + .hw = { > + .clk = &mcspi1_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk mcspi1_ick; > + > +static struct clk_hw_omap mcspi1_ick_hw = { > + .hw = { > + .clk = &mcspi1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mcspi2_fck; > + > +static struct clk_hw_omap mcspi2_fck_hw = { > + .hw = { > + .clk = &mcspi2_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk mcspi2_ick; > + > +static struct clk_hw_omap mcspi2_ick_hw = { > + .hw = { > + .clk = &mcspi2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mmc_fck; > + > +static struct clk_hw_omap mmc_fck_hw = { > + .hw = { > + .clk = &mmc_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP2420_EN_MMC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk mmc_ick; > + > +static struct clk_hw_omap mmc_ick_hw = { > + .hw = { > + .clk = &mmc_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP2420_EN_MMC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, > + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), > + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, > + CLK_DIVIDER_ONE_BASED, NULL); > + > +static struct clk mpu_wdt_fck; > + > +static struct clk_hw_omap mpu_wdt_fck_hw = { > + .hw = { > + .clk = &mpu_wdt_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), > + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); > + > +static struct clk mpu_wdt_ick; > + > +static struct clk_hw_omap mpu_wdt_ick_hw = { > + .hw = { > + .clk = &mpu_wdt_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static struct clk mspro_fck; > + > +static struct clk_hw_omap mspro_fck_hw = { > + .hw = { > + .clk = &mspro_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk mspro_ick; > + > +static struct clk_hw_omap mspro_ick_hw = { > + .hw = { > + .clk = &mspro_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk omapctrl_ick; > + > +static struct clk_hw_omap omapctrl_ick_hw = { > + .hw = { > + .clk = &omapctrl_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static struct clk pka_ick; > + > +static struct clk_hw_omap pka_ick_hw = { > + .hw = { > + .clk = &pka_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_PKA_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk rng_ick; > + > +static struct clk_hw_omap rng_ick_hw = { > + .hw = { > + .clk = &rng_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_RNG_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk sdma_fck; > + > +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); > +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); > + > +static struct clk sdma_ick; > + > +static struct clk_hw_omap sdma_ick_hw = { > + .hw = { > + .clk = &sdma_ick, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), > + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); > + > +static struct clk sdrc_ick; > + > +static struct clk_hw_omap sdrc_ick_hw = { > + .hw = { > + .clk = &sdrc_ick, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), > + .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); > + > +static struct clk sha_ick; > + > +static struct clk_hw_omap sha_ick_hw = { > + .hw = { > + .clk = &sha_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_SHA_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk ssi_l4_ick; > + > +static struct clk_hw_omap ssi_l4_ick_hw = { > + .hw = { > + .clk = &ssi_l4_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP24XX_EN_SSI_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, > + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, > + { .div = 6, .val = 6, .flags = RATE_IN_242X }, > + { .div = 8, .val = 8, .flags = RATE_IN_242X }, > + { .div = 0 } > +}; > + > +static const struct clksel ssi_ssr_sst_fck_clksel[] = { > + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, > + { .parent = NULL }, > +}; > + > +static const char *ssi_ssr_sst_fck_parent_names[] = { > + "core_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", > + ssi_ssr_sst_fck_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_SSI_MASK, > + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, > + ssi_ssr_sst_fck_parent_names, dsp_fck_ops); > + > +static struct clk sync_32k_ick; > + > +static struct clk_hw_omap sync_32k_ick_hw = { > + .hw = { > + .clk = &sync_32k_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate common_clkout_src_core_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate common_clkout_src_sys_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate common_clkout_src_96m_rates[] = { > + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate common_clkout_src_54m_rates[] = { > + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel common_clkout_src_clksel[] = { > + { .parent = &core_ck, .rates = common_clkout_src_core_rates }, > + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, > + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, > + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, > + { .parent = NULL }, > +}; > + > +static const char *sys_clkout_src_parent_names[] = { > + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, > + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, > + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, > + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); > + > +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, > + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, > + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); > + > +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm", > + common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL, > + OMAP2420_CLKOUT2_SOURCE_MASK, > + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT, > + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); > + > +DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, > + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, > + OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); > + > +static struct clk uart1_fck; > + > +static struct clk_hw_omap uart1_fck_hw = { > + .hw = { > + .clk = &uart1_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_UART1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk uart1_ick; > + > +static struct clk_hw_omap uart1_ick_hw = { > + .hw = { > + .clk = &uart1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_UART1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk uart2_fck; > + > +static struct clk_hw_omap uart2_fck_hw = { > + .hw = { > + .clk = &uart2_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_UART2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk uart2_ick; > + > +static struct clk_hw_omap uart2_ick_hw = { > + .hw = { > + .clk = &uart2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_UART2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk uart3_fck; > + > +static struct clk_hw_omap uart3_fck_hw = { > + .hw = { > + .clk = &uart3_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP24XX_EN_UART3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk uart3_ick; > + > +static struct clk_hw_omap uart3_ick_hw = { > + .hw = { > + .clk = &uart3_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP24XX_EN_UART3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk usb_fck; > + > +static struct clk_hw_omap usb_fck_hw = { > + .hw = { > + .clk = &usb_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP24XX_EN_USB_SHIFT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel usb_l4_ick_clksel[] = { > + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, > + { .parent = NULL }, > +}; > + > +static const char *usb_l4_ick_parent_names[] = { > + "core_l3_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_USB_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, > + usb_l4_ick_parent_names, dsp_fck_ops); > + > +static struct clk virt_prcm_set; > + > +static const char *virt_prcm_set_parent_names[] = { > + "mpu_ck", > +}; > + > +static const struct clk_ops virt_prcm_set_ops = { > + .recalc_rate = &omap2_table_mpu_recalc, > + .set_rate = &omap2_select_table_rate, > + .round_rate = &omap2_round_to_table_rate, > +}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); > +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); > + > +static const struct clksel_rate vlynq_fck_96m_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_242X }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate vlynq_fck_core_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_242X }, > + { .div = 2, .val = 2, .flags = RATE_IN_242X }, > + { .div = 3, .val = 3, .flags = RATE_IN_242X }, > + { .div = 4, .val = 4, .flags = RATE_IN_242X }, > + { .div = 6, .val = 6, .flags = RATE_IN_242X }, > + { .div = 8, .val = 8, .flags = RATE_IN_242X }, > + { .div = 9, .val = 9, .flags = RATE_IN_242X }, > + { .div = 12, .val = 12, .flags = RATE_IN_242X }, > + { .div = 16, .val = 16, .flags = RATE_IN_242X }, > + { .div = 18, .val = 18, .flags = RATE_IN_242X }, > + { .div = 0 } > +}; > + > +static const struct clksel vlynq_fck_clksel[] = { > + { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, > + { .parent = &core_ck, .rates = vlynq_fck_core_rates }, > + { .parent = NULL }, > +}; > + > +static const char *vlynq_fck_parent_names[] = { > + "func_96m_ck", "core_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP2420_CLKSEL_VLYNQ_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, > + vlynq_fck_parent_names, dss1_fck_ops); > + > +static struct clk vlynq_ick; > + > +static struct clk_hw_omap vlynq_ick_hw = { > + .hw = { > + .clk = &vlynq_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); > + > +static struct clk wdt1_ick; > + > +static struct clk_hw_omap wdt1_ick_hw = { > + .hw = { > + .clk = &wdt1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_WDT1_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static struct clk wdt1_osc_ck; > + > +static const struct clk_ops wdt1_osc_ck_ops = {}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); > +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); > + > +static struct clk wdt3_fck; > + > +static struct clk_hw_omap wdt3_fck_hw = { > + .hw = { > + .clk = &wdt3_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP2420_EN_WDT3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); > + > +static struct clk wdt3_ick; > + > +static struct clk_hw_omap wdt3_ick_hw = { > + .hw = { > + .clk = &wdt3_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP2420_EN_WDT3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk wdt4_fck; > + > +static struct clk_hw_omap wdt4_fck_hw = { > + .hw = { > + .clk = &wdt4_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); > + > +static struct clk wdt4_ick; > + > +static struct clk_hw_omap wdt4_ick_hw = { > + .hw = { > + .clk = &wdt4_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); > + > +/* > + * clkdev integration > + */ > + > +static struct omap_clk omap2420_clks[] = { > + /* external root sources */ > + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), > + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), > + CLK(NULL, "osc_ck", &osc_ck, CK_242X), > + CLK(NULL, "sys_ck", &sys_ck, CK_242X), > + CLK(NULL, "alt_ck", &alt_ck, CK_242X), > + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), > + /* internal analog sources */ > + CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), > + CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), > + CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), > + /* internal prcm root sources */ > + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), > + CLK(NULL, "core_ck", &core_ck, CK_242X), > + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), > + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), > + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), > + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), > + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), > + CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), > + CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), > + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), > + CLK(NULL, "emul_ck", &emul_ck, CK_242X), > + /* mpu domain clocks */ > + CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), > + /* dsp domain clocks */ > + CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), > + CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), > + CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), > + CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), > + /* GFX domain clocks */ > + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), > + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), > + CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), > + /* DSS domain clocks */ > + CLK("omapdss_dss", "ick", &dss_ick, CK_242X), > + CLK(NULL, "dss_ick", &dss_ick, CK_242X), > + CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), > + CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), > + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), > + /* L3 domain clocks */ > + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), > + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), > + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), > + /* L4 domain clocks */ > + CLK(NULL, "l4_ck", &l4_ck, CK_242X), > + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), > + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X), > + /* virtual meta-group clock */ > + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), > + /* general l4 interface ck, multi-parent functional clk */ > + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), > + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), > + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), > + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), > + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), > + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), > + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), > + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), > + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), > + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), > + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), > + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), > + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), > + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), > + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), > + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), > + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), > + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), > + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), > + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), > + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), > + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), > + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), > + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), > + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), > + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), > + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), > + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), > + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), > + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), > + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), > + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), > + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), > + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), > + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), > + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), > + CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), > + CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), > + CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), > + CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), > + CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), > + CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), > + CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), > + CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), > + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), > + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), > + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), > + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), > + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), > + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), > + CLK("omap24xxcam", "fck", &cam_fck, CK_242X), > + CLK(NULL, "cam_fck", &cam_fck, CK_242X), > + CLK("omap24xxcam", "ick", &cam_ick, CK_242X), > + CLK(NULL, "cam_ick", &cam_ick, CK_242X), > + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), > + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), > + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), > + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), > + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), > + CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), > + CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), > + CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), > + CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), > + CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), > + CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), > + CLK(NULL, "fac_ick", &fac_ick, CK_242X), > + CLK(NULL, "fac_fck", &fac_fck, CK_242X), > + CLK(NULL, "eac_ick", &eac_ick, CK_242X), > + CLK(NULL, "eac_fck", &eac_fck, CK_242X), > + CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), > + CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), > + CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), > + CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), > + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), > + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), > + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), > + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), > + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), > + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), > + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), > + CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), > + CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), > + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), > + CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), > + CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), > + CLK(NULL, "des_ick", &des_ick, CK_242X), > + CLK("omap-sham", "ick", &sha_ick, CK_242X), > + CLK(NULL, "sha_ick", &sha_ick, CK_242X), > + CLK("omap_rng", "ick", &rng_ick, CK_242X), > + CLK(NULL, "rng_ick", &rng_ick, CK_242X), > + CLK("omap-aes", "ick", &aes_ick, CK_242X), > + CLK(NULL, "aes_ick", &aes_ick, CK_242X), > + CLK(NULL, "pka_ick", &pka_ick, CK_242X), > + CLK(NULL, "usb_fck", &usb_fck, CK_242X), > + CLK("musb-hdrc", "fck", &osc_ck, CK_242X), > + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), > + CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), > + CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), > + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), > +}; > + > + > +static const char *enable_init_clks[] = { > + "apll96_ck", > + "apll54_ck", > + "sync_32k_ick", > + "omapctrl_ick", > + "gpmc_fck", > + "sdrc_ick", > +}; > + > +/* > + * init code > + */ > + > +int __init omap2420_clk_init(void) > +{ > + const struct prcm_config *prcm; > + struct omap_clk *c; > + unsigned long clkrate; > + > + prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; > + cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); > + cpu_mask = RATE_IN_242X; > + rate_table = omap2420_rate_table; > + > + /* Check the MPU rate set by bootloader */ > + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw); > + for (prcm = rate_table; prcm->mpu_speed; prcm++) { > + if (!(prcm->flags & cpu_mask)) > + continue; > + if (prcm->xtal_speed != sys_ck.rate) > + continue; > + if (prcm->dpll_speed <= clkrate) > + break; > + } > + > + curr_prcm_set = prcm; > + > + for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); > + c++) { > + clkdev_add(&c->lk); > + if (!__clk_init(NULL, c->lk.clk)) > + omap2_init_clk_hw_omap_clocks(c->lk.clk); > + } > + > + omap2_clk_disable_autoidle_all(); > + > + omap2_clk_enable_init_clocks(enable_init_clks, > + ARRAY_SIZE(enable_init_clks)); > + > + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", > + (clk_get_rate(&sys_ck) / 1000000), > + (clk_get_rate(&sys_ck) / 100000) % 10, > + (clk_get_rate(&dpll_ck) / 1000000), > + (clk_get_rate(&mpu_ck) / 1000000)); > + > + return 0; > +} > diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c > new file mode 100644 > index 0000000..102fbba > --- /dev/null > +++ b/arch/arm/mach-omap2/cclock2430_data.c > @@ -0,0 +1,2076 @@ > +/* > + * OMAP2430 clock data > + * > + * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc. > + * Copyright (C) 2004-2011 Nokia Corporation > + * > + * Contacts: > + * Richard Woodruff <r-woodruff2@ti.com> > + * Paul Walmsley > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/kernel.h> > +#include <linux/clk.h> > +#include <linux/clk-private.h> > +#include <linux/list.h> > + > +#include "soc.h" > +#include "iomap.h" > +#include "clock.h" > +#include "clock2xxx.h" > +#include "opp2xxx.h" > +#include "cm2xxx.h" > +#include "prm2xxx.h" > +#include "prm-regbits-24xx.h" > +#include "cm-regbits-24xx.h" > +#include "sdrc.h" > +#include "control.h" > + > +#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR > + > +/* > + * 2430 clock tree. > + * > + * NOTE:In many cases here we are assigning a 'default' parent. In > + * many cases the parent is selectable. The set parent calls will > + * also switch sources. > + * > + * Several sources are given initial rates which may be wrong, this will > + * be fixed up in the init func. > + * > + * Things are broadly separated below by clock domains. It is > + * noteworthy that most peripherals have dependencies on multiple clock > + * domains. Many get their interface clocks from the L4 domain, but get > + * functional clocks from fixed sources or other core domain derived > + * clocks. > + */ > + > +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); > + > +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); > + > +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); > + > +static struct clk osc_ck; > + > +static const struct clk_ops osc_ck_ops = { > + .enable = &omap2_enable_osc_ck, > + .disable = omap2_disable_osc_ck, > + .recalc_rate = &omap2_osc_clk_recalc, > +}; > + > +static struct clk_hw_omap osc_ck_hw = { > + .hw = { > + .clk = &osc_ck, > + }, > +}; > + > +static struct clk osc_ck = { > + .name = "osc_ck", > + .ops = &osc_ck_ops, > + .hw = &osc_ck_hw.hw, > + .flags = CLK_IS_ROOT, > +}; > + > +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); > + > +static struct clk sys_ck; > + > +static const char *sys_ck_parent_names[] = { > + "osc_ck", > +}; > + > +static const struct clk_ops sys_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .recalc_rate = &omap2xxx_sys_clk_recalc, > +}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); > +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); > + > +static struct dpll_data dpll_dd = { > + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), > + .mult_mask = OMAP24XX_DPLL_MULT_MASK, > + .div1_mask = OMAP24XX_DPLL_DIV_MASK, > + .clk_bypass = &sys_ck, > + .clk_ref = &sys_ck, > + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), > + .enable_mask = OMAP24XX_EN_DPLL_MASK, > + .max_multiplier = 1023, > + .min_divider = 1, > + .max_divider = 16, > +}; > + > +static struct clk dpll_ck; > + > +static const char *dpll_ck_parent_names[] = { > + "sys_ck", > +}; > + > +static const struct clk_ops dpll_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .get_parent = &omap2_init_dpll_parent, > + .recalc_rate = &omap2_dpllcore_recalc, > + .round_rate = &omap2_dpll_round_rate, > + .set_rate = &omap2_reprogram_dpllcore, > +}; > + > +static struct clk_hw_omap dpll_ck_hw = { > + .hw = { > + .clk = &dpll_ck, > + }, > + .ops = &clkhwops_omap2xxx_dpll, > + .dpll_data = &dpll_dd, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); > + > +static struct clk core_ck; > + > +static const char *core_ck_parent_names[] = { > + "dpll_ck", > +}; > + > +static const struct clk_ops core_ck_ops = { > + .init = &omap2_init_clk_clkdm, > +}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); > +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); > + > +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, > + CLK_DIVIDER_ONE_BASED, NULL); > + > +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, > + CLK_DIVIDER_ONE_BASED, NULL); > + > +static struct clk aes_ick; > + > +static const char *aes_ick_parent_names[] = { > + "l4_ck", > +}; > + > +static const struct clk_ops aes_ick_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > +}; > + > +static struct clk_hw_omap aes_ick_hw = { > + .hw = { > + .clk = &aes_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_AES_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk apll54_ck; > + > +static const struct clk_ops apll54_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_clk_apll54_enable, > + .disable = &omap2_clk_apll_disable, > + .recalc_rate = &omap2_clk_apll54_recalc, > +}; > + > +static struct clk_hw_omap apll54_ck_hw = { > + .hw = { > + .clk = &apll54_ck, > + }, > + .ops = &clkhwops_apll54, > + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), > + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); > + > +static struct clk apll96_ck; > + > +static const struct clk_ops apll96_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_clk_apll96_enable, > + .disable = &omap2_clk_apll_disable, > + .recalc_rate = &omap2_clk_apll96_recalc, > +}; > + > +static struct clk_hw_omap apll96_ck_hw = { > + .hw = { > + .clk = &apll96_ck, > + }, > + .ops = &clkhwops_apll96, > + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), > + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); > + > +static const char *func_96m_ck_parent_names[] = { > + "apll96_ck", "alt_ck", > +}; > + > +DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, > + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, > + OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); > + > +static struct clk cam_fck; > + > +static const char *cam_fck_parent_names[] = { > + "func_96m_ck", > +}; > + > +static struct clk_hw_omap cam_fck_hw = { > + .hw = { > + .clk = &cam_fck, > + }, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_CAM_SHIFT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk cam_ick; > + > +static struct clk_hw_omap cam_ick_hw = { > + .hw = { > + .clk = &cam_ick, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_CAM_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk des_ick; > + > +static struct clk_hw_omap des_ick_hw = { > + .hw = { > + .clk = &des_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_DES_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate dsp_fck_core_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, > + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel dsp_fck_clksel[] = { > + { .parent = &core_ck, .rates = dsp_fck_core_rates }, > + { .parent = NULL }, > +}; > + > +static const char *dsp_fck_parent_names[] = { > + "core_ck", > +}; > + > +static struct clk dsp_fck; > + > +static const struct clk_ops dsp_fck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > + .recalc_rate = &omap2_clksel_recalc, > + .set_rate = &omap2_clksel_set_rate, > + .round_rate = &omap2_clksel_round_rate, > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), > + OMAP24XX_CLKSEL_DSP_MASK, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), > + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, > + dsp_fck_parent_names, dsp_fck_ops); > + > +static const struct clksel_rate dss1_fck_sys_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate dss1_fck_core_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, > + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, > + { .div = 5, .val = 5, .flags = RATE_IN_24XX }, > + { .div = 6, .val = 6, .flags = RATE_IN_24XX }, > + { .div = 8, .val = 8, .flags = RATE_IN_24XX }, > + { .div = 9, .val = 9, .flags = RATE_IN_24XX }, > + { .div = 12, .val = 12, .flags = RATE_IN_24XX }, > + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel dss1_fck_clksel[] = { > + { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, > + { .parent = &core_ck, .rates = dss1_fck_core_rates }, > + { .parent = NULL }, > +}; > + > +static const char *dss1_fck_parent_names[] = { > + "sys_ck", "core_ck", > +}; > + > +static const struct clk_ops dss1_fck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > + .recalc_rate = &omap2_clksel_recalc, > + .get_parent = &omap2_clksel_find_parent_index, > + .set_parent = &omap2_clksel_set_parent, > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_DSS1_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_DSS1_SHIFT, NULL, > + dss1_fck_parent_names, dss1_fck_ops); > + > +static const struct clksel_rate dss2_fck_sys_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate dss2_fck_48m_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate func_48m_apll96_rates[] = { > + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate func_48m_alt_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel func_48m_clksel[] = { > + { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, > + { .parent = &alt_ck, .rates = func_48m_alt_rates }, > + { .parent = NULL }, > +}; > + > +static const char *func_48m_ck_parent_names[] = { > + "apll96_ck", "alt_ck", > +}; > + > +static struct clk func_48m_ck; > + > +static const struct clk_ops func_48m_ck_ops = { > + .init = &omap2_init_clk_clkdm, > + .recalc_rate = &omap2_clksel_recalc, > + .set_rate = &omap2_clksel_set_rate, > + .round_rate = &omap2_clksel_round_rate, > + .get_parent = &omap2_clksel_find_parent_index, > + .set_parent = &omap2_clksel_set_parent, > +}; > + > +static struct clk_hw_omap func_48m_ck_hw = { > + .hw = { > + .clk = &func_48m_ck, > + }, > + .clksel = func_48m_clksel, > + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), > + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); > + > +static const struct clksel dss2_fck_clksel[] = { > + { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, > + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, > + { .parent = NULL }, > +}; > + > +static const char *dss2_fck_parent_names[] = { > + "sys_ck", "func_48m_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_DSS2_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_DSS2_SHIFT, NULL, > + dss2_fck_parent_names, dss1_fck_ops); > + > +static const char *func_54m_ck_parent_names[] = { > + "apll54_ck", "alt_ck", > +}; > + > +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, > + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), > + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); > + > +static struct clk dss_54m_fck; > + > +static const char *dss_54m_fck_parent_names[] = { > + "func_54m_ck", > +}; > + > +static struct clk_hw_omap dss_54m_fck_hw = { > + .hw = { > + .clk = &dss_54m_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_TV_SHIFT, > + .clkdm_name = "dss_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); > + > +static struct clk dss_ick; > + > +static struct clk_hw_omap dss_ick_hw = { > + .hw = { > + .clk = &dss_ick, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_DSS1_SHIFT, > + .clkdm_name = "dss_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk emul_ck; > + > +static struct clk_hw_omap emul_ck_hw = { > + .hw = { > + .clk = &emul_ck, > + }, > + .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, > + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); > + > +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); > + > +static struct clk fac_fck; > + > +static const char *fac_fck_parent_names[] = { > + "func_12m_ck", > +}; > + > +static struct clk_hw_omap fac_fck_hw = { > + .hw = { > + .clk = &fac_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_FAC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); > + > +static struct clk fac_ick; > + > +static struct clk_hw_omap fac_ick_hw = { > + .hw = { > + .clk = &fac_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_FAC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel gfx_fck_clksel[] = { > + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, > + { .parent = NULL }, > +}; > + > +static const char *gfx_2d_fck_parent_names[] = { > + "core_l3_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, > + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), > + OMAP_CLKSEL_GFX_MASK, > + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), > + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, > + gfx_2d_fck_parent_names, dsp_fck_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, > + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), > + OMAP_CLKSEL_GFX_MASK, > + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), > + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, > + gfx_2d_fck_parent_names, dsp_fck_ops); > + > +static struct clk gfx_ick; > + > +static const char *gfx_ick_parent_names[] = { > + "core_l3_ck", > +}; > + > +static struct clk_hw_omap gfx_ick_hw = { > + .hw = { > + .clk = &gfx_ick, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), > + .enable_bit = OMAP_EN_GFX_SHIFT, > + .clkdm_name = "gfx_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); > + > +static struct clk gpio5_fck; > + > +static const char *gpio5_fck_parent_names[] = { > + "func_32k_ck", > +}; > + > +static struct clk_hw_omap gpio5_fck_hw = { > + .hw = { > + .clk = &gpio5_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP2430_EN_GPIO5_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); > + > +static struct clk gpio5_ick; > + > +static struct clk_hw_omap gpio5_ick_hw = { > + .hw = { > + .clk = &gpio5_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_GPIO5_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk gpios_fck; > + > +static struct clk_hw_omap gpios_fck_hw = { > + .hw = { > + .clk = &gpios_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), > + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); > + > +static struct clk wu_l4_ick; > + > +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); > +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); > + > +static struct clk gpios_ick; > + > +static const char *gpios_ick_parent_names[] = { > + "wu_l4_ick", > +}; > + > +static struct clk_hw_omap gpios_ick_hw = { > + .hw = { > + .clk = &gpios_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static struct clk gpmc_fck; > + > +static struct clk_hw_omap gpmc_fck_hw = { > + .hw = { > + .clk = &gpmc_fck, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), > + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); > + > +static const struct clksel_rate gpt_alt_rates[] = { > + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel omap24xx_gpt_clksel[] = { > + { .parent = &func_32k_ck, .rates = gpt_32k_rates }, > + { .parent = &sys_ck, .rates = gpt_sys_rates }, > + { .parent = &alt_ck, .rates = gpt_alt_rates }, > + { .parent = NULL }, > +}; > + > +static const char *gpt10_fck_parent_names[] = { > + "func_32k_ck", "sys_ck", "alt_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT10_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt10_ick; > + > +static struct clk_hw_omap gpt10_ick_hw = { > + .hw = { > + .clk = &gpt10_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT10_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT11_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt11_ick; > + > +static struct clk_hw_omap gpt11_ick_hw = { > + .hw = { > + .clk = &gpt11_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT11_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT12_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt12_ick; > + > +static struct clk_hw_omap gpt12_ick_hw = { > + .hw = { > + .clk = &gpt12_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT12_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clk_ops gpt1_fck_ops = { > + .init = &omap2_init_clk_clkdm, > + .enable = &omap2_dflt_clk_enable, > + .disable = &omap2_dflt_clk_disable, > + .is_enabled = &omap2_dflt_clk_is_enabled, > + .recalc_rate = &omap2_clksel_recalc, > + .set_rate = &omap2_clksel_set_rate, > + .round_rate = &omap2_clksel_round_rate, > + .get_parent = &omap2_clksel_find_parent_index, > + .set_parent = &omap2_clksel_set_parent, > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_GPT1_MASK, > + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), > + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, gpt1_fck_ops); > + > +static struct clk gpt1_ick; > + > +static struct clk_hw_omap gpt1_ick_hw = { > + .hw = { > + .clk = &gpt1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_GPT1_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT2_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt2_ick; > + > +static struct clk_hw_omap gpt2_ick_hw = { > + .hw = { > + .clk = &gpt2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT3_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt3_ick; > + > +static struct clk_hw_omap gpt3_ick_hw = { > + .hw = { > + .clk = &gpt3_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT4_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt4_ick; > + > +static struct clk_hw_omap gpt4_ick_hw = { > + .hw = { > + .clk = &gpt4_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT4_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT5_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt5_ick; > + > +static struct clk_hw_omap gpt5_ick_hw = { > + .hw = { > + .clk = &gpt5_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT5_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT6_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt6_ick; > + > +static struct clk_hw_omap gpt6_ick_hw = { > + .hw = { > + .clk = &gpt6_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT6_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT7_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt7_ick; > + > +static struct clk_hw_omap gpt7_ick_hw = { > + .hw = { > + .clk = &gpt7_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT7_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk gpt8_fck; > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT8_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt8_ick; > + > +static struct clk_hw_omap gpt8_ick_hw = { > + .hw = { > + .clk = &gpt8_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT8_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), > + OMAP24XX_CLKSEL_GPT9_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, > + gpt10_fck_parent_names, dss1_fck_ops); > + > +static struct clk gpt9_ick; > + > +static struct clk_hw_omap gpt9_ick_hw = { > + .hw = { > + .clk = &gpt9_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_GPT9_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk hdq_fck; > + > +static struct clk_hw_omap hdq_fck_hw = { > + .hw = { > + .clk = &hdq_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); > + > +static struct clk hdq_ick; > + > +static struct clk_hw_omap hdq_ick_hw = { > + .hw = { > + .clk = &hdq_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk i2c1_ick; > + > +static struct clk_hw_omap i2c1_ick_hw = { > + .hw = { > + .clk = &i2c1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP2420_EN_I2C1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk i2c2_ick; > + > +static struct clk_hw_omap i2c2_ick_hw = { > + .hw = { > + .clk = &i2c2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP2420_EN_I2C2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk i2chs1_fck; > + > +static struct clk_hw_omap i2chs1_fck_hw = { > + .hw = { > + .clk = &i2chs1_fck, > + }, > + .ops = &clkhwops_omap2430_i2chs_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk i2chs2_fck; > + > +static struct clk_hw_omap i2chs2_fck_hw = { > + .hw = { > + .clk = &i2chs2_fck, > + }, > + .ops = &clkhwops_omap2430_i2chs_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk icr_ick; > + > +static struct clk_hw_omap icr_ick_hw = { > + .hw = { > + .clk = &icr_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP2430_EN_ICR_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static const struct clksel dsp_ick_clksel[] = { > + { .parent = &dsp_fck, .rates = dsp_ick_rates }, > + { .parent = NULL }, > +}; > + > +static const char *iva2_1_ick_parent_names[] = { > + "dsp_fck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), > + OMAP24XX_CLKSEL_DSP_IF_MASK, > + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), > + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, > + iva2_1_ick_parent_names, dsp_fck_ops); > + > +static struct clk mailboxes_ick; > + > +static struct clk_hw_omap mailboxes_ick_hw = { > + .hw = { > + .clk = &mailboxes_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate common_mcbsp_96m_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel mcbsp_fck_clksel[] = { > + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, > + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, > + { .parent = NULL }, > +}; > + > +static const char *mcbsp1_fck_parent_names[] = { > + "func_96m_ck", "mcbsp_clks", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, > + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), > + OMAP2_MCBSP1_CLKS_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, > + mcbsp1_fck_parent_names, dss1_fck_ops); > + > +static struct clk mcbsp1_ick; > + > +static struct clk_hw_omap mcbsp1_ick_hw = { > + .hw = { > + .clk = &mcbsp1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, > + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), > + OMAP2_MCBSP2_CLKS_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, > + mcbsp1_fck_parent_names, dss1_fck_ops); > + > +static struct clk mcbsp2_ick; > + > +static struct clk_hw_omap mcbsp2_ick_hw = { > + .hw = { > + .clk = &mcbsp2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, > + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), > + OMAP2_MCBSP3_CLKS_MASK, > + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, > + mcbsp1_fck_parent_names, dss1_fck_ops); > + > +static struct clk mcbsp3_ick; > + > +static struct clk_hw_omap mcbsp3_ick_hw = { > + .hw = { > + .clk = &mcbsp3_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, > + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), > + OMAP2_MCBSP4_CLKS_MASK, > + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, > + mcbsp1_fck_parent_names, dss1_fck_ops); > + > +static struct clk mcbsp4_ick; > + > +static struct clk_hw_omap mcbsp4_ick_hw = { > + .hw = { > + .clk = &mcbsp4_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops); > + > +DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, > + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), > + OMAP2_MCBSP5_CLKS_MASK, > + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, > + mcbsp1_fck_parent_names, dss1_fck_ops); > + > +static struct clk mcbsp5_ick; > + > +static struct clk_hw_omap mcbsp5_ick_hw = { > + .hw = { > + .clk = &mcbsp5_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mcspi1_fck; > + > +static const char *mcspi1_fck_parent_names[] = { > + "func_48m_ck", > +}; > + > +static struct clk_hw_omap mcspi1_fck_hw = { > + .hw = { > + .clk = &mcspi1_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk mcspi1_ick; > + > +static struct clk_hw_omap mcspi1_ick_hw = { > + .hw = { > + .clk = &mcspi1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mcspi2_fck; > + > +static struct clk_hw_omap mcspi2_fck_hw = { > + .hw = { > + .clk = &mcspi2_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk mcspi2_ick; > + > +static struct clk_hw_omap mcspi2_ick_hw = { > + .hw = { > + .clk = &mcspi2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mcspi3_fck; > + > +static struct clk_hw_omap mcspi3_fck_hw = { > + .hw = { > + .clk = &mcspi3_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk mcspi3_ick; > + > +static struct clk_hw_omap mcspi3_ick_hw = { > + .hw = { > + .clk = &mcspi3_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate mdm_ick_core_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_243X }, > + { .div = 4, .val = 4, .flags = RATE_IN_243X }, > + { .div = 6, .val = 6, .flags = RATE_IN_243X }, > + { .div = 9, .val = 9, .flags = RATE_IN_243X }, > + { .div = 0 } > +}; > + > +static const struct clksel mdm_ick_clksel[] = { > + { .parent = &core_ck, .rates = mdm_ick_core_rates }, > + { .parent = NULL }, > +}; > + > +static const char *mdm_ick_parent_names[] = { > + "core_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, > + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), > + OMAP2430_CLKSEL_MDM_MASK, > + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), > + OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, > + &clkhwops_iclk_wait, mdm_ick_parent_names, > + dsp_fck_ops); > + > +static struct clk mdm_intc_ick; > + > +static struct clk_hw_omap mdm_intc_ick_hw = { > + .hw = { > + .clk = &mdm_intc_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mdm_osc_ck; > + > +static struct clk_hw_omap mdm_osc_ck_hw = { > + .hw = { > + .clk = &mdm_osc_ck, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), > + .enable_bit = OMAP2430_EN_OSC_SHIFT, > + .clkdm_name = "mdm_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); > + > +static struct clk mmchs1_fck; > + > +static struct clk_hw_omap mmchs1_fck_hw = { > + .hw = { > + .clk = &mmchs1_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk mmchs1_ick; > + > +static struct clk_hw_omap mmchs1_ick_hw = { > + .hw = { > + .clk = &mmchs1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mmchs2_fck; > + > +static struct clk_hw_omap mmchs2_fck_hw = { > + .hw = { > + .clk = &mmchs2_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk mmchs2_ick; > + > +static struct clk_hw_omap mmchs2_ick_hw = { > + .hw = { > + .clk = &mmchs2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk mmchsdb1_fck; > + > +static struct clk_hw_omap mmchsdb1_fck_hw = { > + .hw = { > + .clk = &mmchsdb1_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); > + > +static struct clk mmchsdb2_fck; > + > +static struct clk_hw_omap mmchsdb2_fck_hw = { > + .hw = { > + .clk = &mmchsdb2_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops); > + > +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, > + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), > + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, > + CLK_DIVIDER_ONE_BASED, NULL); > + > +static struct clk mpu_wdt_fck; > + > +static struct clk_hw_omap mpu_wdt_fck_hw = { > + .hw = { > + .clk = &mpu_wdt_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), > + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); > + > +static struct clk mpu_wdt_ick; > + > +static struct clk_hw_omap mpu_wdt_ick_hw = { > + .hw = { > + .clk = &mpu_wdt_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static struct clk mspro_fck; > + > +static struct clk_hw_omap mspro_fck_hw = { > + .hw = { > + .clk = &mspro_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); > + > +static struct clk mspro_ick; > + > +static struct clk_hw_omap mspro_ick_hw = { > + .hw = { > + .clk = &mspro_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk omapctrl_ick; > + > +static struct clk_hw_omap omapctrl_ick_hw = { > + .hw = { > + .clk = &omapctrl_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static struct clk pka_ick; > + > +static struct clk_hw_omap pka_ick_hw = { > + .hw = { > + .clk = &pka_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_PKA_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk rng_ick; > + > +static struct clk_hw_omap rng_ick_hw = { > + .hw = { > + .clk = &rng_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_RNG_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk sdma_fck; > + > +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); > +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); > + > +static struct clk sdma_ick; > + > +static struct clk_hw_omap sdma_ick_hw = { > + .hw = { > + .clk = &sdma_ick, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), > + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); > + > +static struct clk sdrc_ick; > + > +static struct clk_hw_omap sdrc_ick_hw = { > + .hw = { > + .clk = &sdrc_ick, > + }, > + .ops = &clkhwops_iclk, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), > + .enable_bit = OMAP2430_EN_SDRC_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); > + > +static struct clk sha_ick; > + > +static struct clk_hw_omap sha_ick_hw = { > + .hw = { > + .clk = &sha_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), > + .enable_bit = OMAP24XX_EN_SHA_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk ssi_l4_ick; > + > +static struct clk_hw_omap ssi_l4_ick_hw = { > + .hw = { > + .clk = &ssi_l4_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP24XX_EN_SSI_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, > + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, > + { .div = 5, .val = 5, .flags = RATE_IN_243X }, > + { .div = 0 } > +}; > + > +static const struct clksel ssi_ssr_sst_fck_clksel[] = { > + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, > + { .parent = NULL }, > +}; > + > +static const char *ssi_ssr_sst_fck_parent_names[] = { > + "core_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", > + ssi_ssr_sst_fck_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_SSI_MASK, > + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, > + ssi_ssr_sst_fck_parent_names, dsp_fck_ops); > + > +static struct clk sync_32k_ick; > + > +static struct clk_hw_omap sync_32k_ick_hw = { > + .hw = { > + .clk = &sync_32k_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, > + .flags = ENABLE_ON_INIT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static const struct clksel_rate common_clkout_src_core_rates[] = { > + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate common_clkout_src_sys_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate common_clkout_src_96m_rates[] = { > + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel_rate common_clkout_src_54m_rates[] = { > + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel common_clkout_src_clksel[] = { > + { .parent = &core_ck, .rates = common_clkout_src_core_rates }, > + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, > + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, > + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, > + { .parent = NULL }, > +}; > + > +static const char *sys_clkout_src_parent_names[] = { > + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, > + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, > + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, > + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); > + > +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, > + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, > + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); > + > +static struct clk uart1_fck; > + > +static struct clk_hw_omap uart1_fck_hw = { > + .hw = { > + .clk = &uart1_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_UART1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk uart1_ick; > + > +static struct clk_hw_omap uart1_ick_hw = { > + .hw = { > + .clk = &uart1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_UART1_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk uart2_fck; > + > +static struct clk_hw_omap uart2_fck_hw = { > + .hw = { > + .clk = &uart2_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_UART2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk uart2_ick; > + > +static struct clk_hw_omap uart2_ick_hw = { > + .hw = { > + .clk = &uart2_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_UART2_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk uart3_fck; > + > +static struct clk_hw_omap uart3_fck_hw = { > + .hw = { > + .clk = &uart3_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP24XX_EN_UART3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static struct clk uart3_ick; > + > +static struct clk_hw_omap uart3_ick_hw = { > + .hw = { > + .clk = &uart3_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP24XX_EN_UART3_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); > + > +static struct clk usb_fck; > + > +static struct clk_hw_omap usb_fck_hw = { > + .hw = { > + .clk = &usb_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), > + .enable_bit = OMAP24XX_EN_USB_SHIFT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); > + > +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { > + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, > + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, > + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, > + { .div = 0 } > +}; > + > +static const struct clksel usb_l4_ick_clksel[] = { > + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, > + { .parent = NULL }, > +}; > + > +static const char *usb_l4_ick_parent_names[] = { > + "core_l3_ck", > +}; > + > +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, > + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), > + OMAP24XX_CLKSEL_USB_MASK, > + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, > + usb_l4_ick_parent_names, dsp_fck_ops); > + > +static struct clk usbhs_ick; > + > +static struct clk_hw_omap usbhs_ick_hw = { > + .hw = { > + .clk = &usbhs_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), > + .enable_bit = OMAP2430_EN_USBHS_SHIFT, > + .clkdm_name = "core_l3_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); > + > +static struct clk virt_prcm_set; > + > +static const char *virt_prcm_set_parent_names[] = { > + "mpu_ck", > +}; > + > +static const struct clk_ops virt_prcm_set_ops = { > + .recalc_rate = &omap2_table_mpu_recalc, > + .set_rate = &omap2_select_table_rate, > + .round_rate = &omap2_round_to_table_rate, > +}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); > +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); > + > +static struct clk wdt1_ick; > + > +static struct clk_hw_omap wdt1_ick_hw = { > + .hw = { > + .clk = &wdt1_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), > + .enable_bit = OMAP24XX_EN_WDT1_SHIFT, > + .clkdm_name = "wkup_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); > + > +static struct clk wdt1_osc_ck; > + > +static const struct clk_ops wdt1_osc_ck_ops = {}; > + > +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); > +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); > + > +static struct clk wdt4_fck; > + > +static struct clk_hw_omap wdt4_fck_hw = { > + .hw = { > + .clk = &wdt4_fck, > + }, > + .ops = &clkhwops_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), > + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); > + > +static struct clk wdt4_ick; > + > +static struct clk_hw_omap wdt4_ick_hw = { > + .hw = { > + .clk = &wdt4_ick, > + }, > + .ops = &clkhwops_iclk_wait, > + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), > + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, > + .clkdm_name = "core_l4_clkdm", > +}; > + > +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); > + > +/* > + * clkdev integration > + */ > + > +static struct omap_clk omap2430_clks[] = { > + /* external root sources */ > + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), > + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), > + CLK(NULL, "osc_ck", &osc_ck, CK_243X), > + CLK("twl", "fck", &osc_ck, CK_243X), > + CLK(NULL, "sys_ck", &sys_ck, CK_243X), > + CLK(NULL, "alt_ck", &alt_ck, CK_243X), > + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), > + /* internal analog sources */ > + CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), > + CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), > + CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), > + /* internal prcm root sources */ > + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), > + CLK(NULL, "core_ck", &core_ck, CK_243X), > + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), > + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), > + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), > + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), > + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), > + CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), > + CLK(NULL, "emul_ck", &emul_ck, CK_243X), > + /* mpu domain clocks */ > + CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), > + /* dsp domain clocks */ > + CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), > + CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), > + /* GFX domain clocks */ > + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), > + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), > + CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), > + /* Modem domain clocks */ > + CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), > + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), > + /* DSS domain clocks */ > + CLK("omapdss_dss", "ick", &dss_ick, CK_243X), > + CLK(NULL, "dss_ick", &dss_ick, CK_243X), > + CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), > + CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), > + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), > + /* L3 domain clocks */ > + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), > + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), > + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), > + /* L4 domain clocks */ > + CLK(NULL, "l4_ck", &l4_ck, CK_243X), > + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), > + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X), > + /* virtual meta-group clock */ > + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), > + /* general l4 interface ck, multi-parent functional clk */ > + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), > + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), > + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), > + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), > + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), > + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), > + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), > + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), > + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), > + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), > + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), > + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), > + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), > + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), > + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), > + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), > + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), > + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), > + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), > + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), > + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), > + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), > + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), > + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), > + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), > + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), > + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), > + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), > + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), > + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), > + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), > + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), > + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), > + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), > + CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), > + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), > + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), > + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), > + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), > + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), > + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), > + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), > + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), > + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), > + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), > + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), > + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), > + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), > + CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), > + CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), > + CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), > + CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), > + CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), > + CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), > + CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), > + CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), > + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), > + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), > + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), > + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), > + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), > + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), > + CLK(NULL, "icr_ick", &icr_ick, CK_243X), > + CLK("omap24xxcam", "fck", &cam_fck, CK_243X), > + CLK(NULL, "cam_fck", &cam_fck, CK_243X), > + CLK("omap24xxcam", "ick", &cam_ick, CK_243X), > + CLK(NULL, "cam_ick", &cam_ick, CK_243X), > + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), > + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), > + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), > + CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), > + CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), > + CLK(NULL, "fac_ick", &fac_ick, CK_243X), > + CLK(NULL, "fac_fck", &fac_fck, CK_243X), > + CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), > + CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), > + CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), > + CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), > + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), > + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), > + CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), > + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), > + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), > + CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), > + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), > + CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), > + CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), > + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), > + CLK(NULL, "des_ick", &des_ick, CK_243X), > + CLK("omap-sham", "ick", &sha_ick, CK_243X), > + CLK("omap_rng", "ick", &rng_ick, CK_243X), > + CLK(NULL, "rng_ick", &rng_ick, CK_243X), > + CLK("omap-aes", "ick", &aes_ick, CK_243X), > + CLK(NULL, "pka_ick", &pka_ick, CK_243X), > + CLK(NULL, "usb_fck", &usb_fck, CK_243X), > + CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), > + CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), > + CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), > + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), > + CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), > + CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), > + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), > + CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), > + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), > + CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), > + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), > + CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), > + CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), > + CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), > + CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), > + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), > + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), > + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), > + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), > +}; > + > +static const char *enable_init_clks[] = { > + "apll96_ck", > + "apll54_ck", > + "sync_32k_ick", > + "omapctrl_ick", > + "gpmc_fck", > + "sdrc_ick", > +}; > + > +/* > + * init code > + */ > + > +int __init omap2430_clk_init(void) > +{ > + const struct prcm_config *prcm; > + struct omap_clk *c; > + unsigned long clkrate; > + > + prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; > + cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); > + cpu_mask = RATE_IN_243X; > + rate_table = omap2430_rate_table; > + > + /* Check the MPU rate set by bootloader */ > + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck_hw); > + for (prcm = rate_table; prcm->mpu_speed; prcm++) { > + if (!(prcm->flags & cpu_mask)) > + continue; > + if (prcm->xtal_speed != sys_ck.rate) > + continue; > + if (prcm->dpll_speed <= clkrate) > + break; > + } > + curr_prcm_set = prcm; > + > + for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); > + c++) { > + clkdev_add(&c->lk); > + if (!__clk_init(NULL, c->lk.clk)) > + omap2_init_clk_hw_omap_clocks(c->lk.clk); > + } > + > + omap2_clk_disable_autoidle_all(); > + > + omap2_clk_enable_init_clocks(enable_init_clks, > + ARRAY_SIZE(enable_init_clks)); > + > + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", > + (clk_get_rate(&sys_ck) / 1000000), > + (clk_get_rate(&sys_ck) / 100000) % 10, > + (clk_get_rate(&dpll_ck) / 1000000), > + (clk_get_rate(&mpu_ck) / 1000000)); > + > + return 0; > +} > diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h > index 6862904..f3fcba2 100644 > --- a/arch/arm/mach-omap2/cm-regbits-24xx.h > +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h > @@ -59,6 +59,7 @@ > /* CM_CLKSEL_MPU */ > #define OMAP24XX_CLKSEL_MPU_SHIFT 0 > #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) > +#define OMAP24XX_CLKSEL_MPU_WIDTH 5 > > /* CM_CLKSTCTRL_MPU */ > #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 > @@ -237,8 +238,10 @@ > #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) > #define OMAP24XX_CLKSEL_L4_SHIFT 5 > #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) > +#define OMAP24XX_CLKSEL_L4_WIDTH 2 > #define OMAP24XX_CLKSEL_L3_SHIFT 0 > #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) > +#define OMAP24XX_CLKSEL_L3_WIDTH 5 > > /* CM_CLKSEL2_CORE */ > #define OMAP24XX_CLKSEL_GPT12_SHIFT 22 > @@ -361,8 +364,10 @@ > #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) > #define OMAP24XX_54M_SOURCE_SHIFT 5 > #define OMAP24XX_54M_SOURCE_MASK (1 << 5) > +#define OMAP24XX_54M_SOURCE_WIDTH 1 > #define OMAP2430_96M_SOURCE_SHIFT 4 > #define OMAP2430_96M_SOURCE_MASK (1 << 4) > +#define OMAP2430_96M_SOURCE_WIDTH 1 > #define OMAP24XX_48M_SOURCE_SHIFT 3 > #define OMAP24XX_48M_SOURCE_MASK (1 << 3) > #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 > diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h > index 638da6d..91aa510 100644 > --- a/arch/arm/mach-omap2/prm-regbits-24xx.h > +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h > @@ -107,12 +107,14 @@ > #define OMAP2420_CLKOUT2_EN_MASK (1 << 15) > #define OMAP2420_CLKOUT2_DIV_SHIFT 11 > #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) > +#define OMAP2420_CLKOUT2_DIV_WIDTH 3 > #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 > #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) > #define OMAP24XX_CLKOUT_EN_SHIFT 7 > #define OMAP24XX_CLKOUT_EN_MASK (1 << 7) > #define OMAP24XX_CLKOUT_DIV_SHIFT 3 > #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) > +#define OMAP24XX_CLKOUT_DIV_WIDTH 3 > #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 > #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) > > -- > 1.7.10.4 ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk 2012-11-09 21:05 ` Mike Turquette @ 2012-11-09 21:22 ` Paul Walmsley 2012-11-09 22:21 ` Mike Turquette 0 siblings, 1 reply; 67+ messages in thread From: Paul Walmsley @ 2012-11-09 21:22 UTC (permalink / raw) To: Mike Turquette; +Cc: rnayak, linux-omap, linux-arm-kernel, patches On Fri, 9 Nov 2012, Mike Turquette wrote: > Quoting Paul Walmsley (2012-11-09 12:32:59) > > Here's another update on this one to add the twl.fck clock alias, recently > > added by commit defa6be1c8216ed2d52d65db81a8a148e73be5f7 ("mfd: Fix > > compile for twl-core.c by removing cpu_is_omap usage"). > > > > I'll post a new series to the list with these fixes rolled in. Unless you've got other changes, no need to worry about it - will deal with it here. > Do you want me to squash the clkdm_clk_disable/usecount patch into > another patch in the series or keep it separate? Separate might be good > since we're going to replace that solution with some force-disable thing > in the future. Have moved that one up earlier in the patch stack and added the matching cleanup to the last patch. Will repush the branch once it completes testing again. Re the upstream CCF support for this, would suggest adding the CCF support for the new function pointer in this merge window (3.8) since it should be relatively straightforward. Then during the 3.9 merge window, the OMAP code can be switched over to use it. - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk 2012-11-09 21:22 ` Paul Walmsley @ 2012-11-09 22:21 ` Mike Turquette 0 siblings, 0 replies; 67+ messages in thread From: Mike Turquette @ 2012-11-09 22:21 UTC (permalink / raw) To: Paul Walmsley; +Cc: rnayak, linux-omap, linux-arm-kernel, patches Quoting Paul Walmsley (2012-11-09 13:22:00) > On Fri, 9 Nov 2012, Mike Turquette wrote: > > > Quoting Paul Walmsley (2012-11-09 12:32:59) > Re the upstream CCF support for this, would suggest adding the CCF support > for the new function pointer in this merge window (3.8) since it should > be relatively straightforward. Then during the 3.9 merge window, the > OMAP code can be switched over to use it. > Will do. Regards, Mike > > - Paul ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk [not found] ` <1352337181-29427-16-git-send-email-mturquette@ti.com> [not found] ` <alpine.DEB.2.00.1211081532210.20703@utopia.booyaka.com> @ 2012-11-12 22:13 ` Paul Walmsley 1 sibling, 0 replies; 67+ messages in thread From: Paul Walmsley @ 2012-11-12 22:13 UTC (permalink / raw) To: Mike Turquette; +Cc: linux-omap, rnayak, linux-arm-kernel, patches This patch needed some updates during the rebase, mostly surrounding the APLL and virt_prcm_set clock handling. Updated patch follows. - Paul ARM: OMAP2: clock: Add 24xx data using common struct clk From: Rajendra Nayak <rnayak@ti.com> The patch is the output from a python script which converts from the old OMAP clk format to COMMON clk format using a JSON parser in between which was developed by Paul Walmsley. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflowed macros; dropped 243x clkdev aliases in 242x file; added recalc_rate fn ptrs to APLL clocks; fixed some checkpatch warnings] [mturquette@ti.com: removed deprecated variables from omap24x0_clk_init] Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: fixed boot crash due to missing clock init code; added twl.fck alias; fix DPLL rate initialization; fix APLL clocks and virt_prcm_set initialization] Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/cclock2420_data.c | 1950 ++++++++++++++++++++++++++++++ arch/arm/mach-omap2/cclock2430_data.c | 2065 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/cm-regbits-24xx.h | 5 arch/arm/mach-omap2/prm-regbits-24xx.h | 2 4 files changed, 4022 insertions(+) create mode 100644 arch/arm/mach-omap2/cclock2420_data.c create mode 100644 arch/arm/mach-omap2/cclock2430_data.c diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c new file mode 100644 index 0000000..7e5febe --- /dev/null +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -0,0 +1,1950 @@ +/* + * OMAP2420 clock data + * + * Copyright (C) 2005-2012 Texas Instruments, Inc. + * Copyright (C) 2004-2011 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/clk-private.h> +#include <linux/list.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock2xxx.h" +#include "opp2xxx.h" +#include "cm2xxx.h" +#include "prm2xxx.h" +#include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" +#include "sdrc.h" +#include "control.h" + +#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR + +/* + * 2420 clock tree. + * + * NOTE:In many cases here we are assigning a 'default' parent. In + * many cases the parent is selectable. The set parent calls will + * also switch sources. + * + * Several sources are given initial rates which may be wrong, this will + * be fixed up in the init func. + * + * Things are broadly separated below by clock domains. It is + * noteworthy that most peripherals have dependencies on multiple clock + * domains. Many get their interface clocks from the L4 domain, but get + * functional clocks from fixed sources or other core domain derived + * clocks. + */ + +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); + +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); + +static struct clk osc_ck; + +static const struct clk_ops osc_ck_ops = { + .recalc_rate = &omap2_osc_clk_recalc, +}; + +static struct clk_hw_omap osc_ck_hw = { + .hw = { + .clk = &osc_ck, + }, +}; + +static struct clk osc_ck = { + .name = "osc_ck", + .ops = &osc_ck_ops, + .hw = &osc_ck_hw.hw, + .flags = CLK_IS_ROOT, +}; + +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +static struct clk sys_ck; + +static const char *sys_ck_parent_names[] = { + "osc_ck", +}; + +static const struct clk_ops sys_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2xxx_sys_clk_recalc, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); + +static struct dpll_data dpll_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP24XX_DPLL_MULT_MASK, + .div1_mask = OMAP24XX_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP24XX_EN_DPLL_MASK, + .max_multiplier = 1023, + .min_divider = 1, + .max_divider = 16, +}; + +static struct clk dpll_ck; + +static const char *dpll_ck_parent_names[] = { + "sys_ck", +}; + +static const struct clk_ops dpll_ck_ops = { + .init = &omap2_init_clk_clkdm, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap2_dpllcore_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap2_reprogram_dpllcore, +}; + +static struct clk_hw_omap dpll_ck_hw = { + .hw = { + .clk = &dpll_ck, + }, + .ops = &clkhwops_omap2xxx_dpll, + .dpll_data = &dpll_dd, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); + +static struct clk core_ck; + +static const char *core_ck_parent_names[] = { + "dpll_ck", +}; + +static const struct clk_ops core_ck_ops = { + .init = &omap2_init_clk_clkdm, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); + +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk aes_ick; + +static const char *aes_ick_parent_names[] = { + "l4_ck", +}; + +static const struct clk_ops aes_ick_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap aes_ick_hw = { + .hw = { + .clk = &aes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_AES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk apll54_ck; + +static const struct clk_ops apll54_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll54_enable, + .disable = &omap2_clk_apll54_disable, + .recalc_rate = &omap2_clk_apll54_recalc, +}; + +static struct clk_hw_omap apll54_ck_hw = { + .hw = { + .clk = &apll54_ck, + }, + .ops = &clkhwops_apll54, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); + +static struct clk apll96_ck; + +static const struct clk_ops apll96_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll96_enable, + .disable = &omap2_clk_apll96_disable, + .recalc_rate = &omap2_clk_apll96_recalc, +}; + +static struct clk_hw_omap apll96_ck_hw = { + .hw = { + .clk = &apll96_ck, + }, + .ops = &clkhwops_apll96, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); + +static struct clk func_96m_ck; + +static const char *func_96m_ck_parent_names[] = { + "apll96_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); + +static struct clk cam_fck; + +static const char *cam_fck_parent_names[] = { + "func_96m_ck", +}; + +static struct clk_hw_omap cam_fck_hw = { + .hw = { + .clk = &cam_fck, + }, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk cam_ick; + +static struct clk_hw_omap cam_ick_hw = { + .hw = { + .clk = &cam_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk des_ick; + +static struct clk_hw_omap des_ick_hw = { + .hw = { + .clk = &des_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_DES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate dsp_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 12, .val = 12, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel dsp_fck_clksel[] = { + { .parent = &core_ck, .rates = dsp_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dsp_fck_parent_names[] = { + "core_ck", +}; + +static const struct clk_ops dsp_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static const struct clksel dsp_ick_clksel[] = { + { .parent = &dsp_fck, .rates = dsp_ick_rates }, + { .parent = NULL }, +}; + +static const char *dsp_ick_parent_names[] = { + "dsp_fck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_IF_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), + OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait, + dsp_ick_parent_names, dsp_fck_ops); + +static const struct clksel_rate dss1_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss1_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_24XX }, + { .div = 8, .val = 8, .flags = RATE_IN_24XX }, + { .div = 9, .val = 9, .flags = RATE_IN_24XX }, + { .div = 12, .val = 12, .flags = RATE_IN_24XX }, + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dss1_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, + { .parent = &core_ck, .rates = dss1_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dss1_fck_parent_names[] = { + "sys_ck", "core_ck", +}; + +static struct clk dss1_fck; + +static const struct clk_ops dss1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS1_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS1_SHIFT, NULL, + dss1_fck_parent_names, dss1_fck_ops); + +static const struct clksel_rate dss2_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss2_fck_48m_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_apll96_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel func_48m_clksel[] = { + { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, + { .parent = &alt_ck, .rates = func_48m_alt_rates }, + { .parent = NULL }, +}; + +static const char *func_48m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +static struct clk func_48m_ck; + +static const struct clk_ops func_48m_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap func_48m_ck_hw = { + .hw = { + .clk = &func_48m_ck, + }, + .clksel = func_48m_clksel, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); + +static const struct clksel dss2_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, + { .parent = NULL }, +}; + +static const char *dss2_fck_parent_names[] = { + "sys_ck", "func_48m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS2_SHIFT, NULL, + dss2_fck_parent_names, dss1_fck_ops); + +static const char *func_54m_ck_parent_names[] = { + "apll54_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, + 0x0, NULL); + +static struct clk dss_54m_fck; + +static const char *dss_54m_fck_parent_names[] = { + "func_54m_ck", +}; + +static struct clk_hw_omap dss_54m_fck_hw = { + .hw = { + .clk = &dss_54m_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); + +static struct clk dss_ick; + +static struct clk_hw_omap dss_ick_hw = { + .hw = { + .clk = &dss_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk eac_fck; + +static struct clk_hw_omap eac_fck_hw = { + .hw = { + .clk = &eac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_EAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk eac_ick; + +static struct clk_hw_omap eac_ick_hw = { + .hw = { + .clk = &eac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_EAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk emul_ck; + +static struct clk_hw_omap emul_ck_hw = { + .hw = { + .clk = &emul_ck, + }, + .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); + +static struct clk fac_fck; + +static const char *fac_fck_parent_names[] = { + "func_12m_ck", +}; + +static struct clk_hw_omap fac_fck_hw = { + .hw = { + .clk = &fac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk fac_ick; + +static struct clk_hw_omap fac_ick_hw = { + .hw = { + .clk = &fac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel gfx_fck_clksel[] = { + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, + { .parent = NULL }, +}; + +static const char *gfx_2d_fck_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +static struct clk gfx_ick; + +static const char *gfx_ick_parent_names[] = { + "core_l3_ck", +}; + +static struct clk_hw_omap gfx_ick_hw = { + .hw = { + .clk = &gfx_ick, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .clkdm_name = "gfx_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk gpios_fck; + +static const char *gpios_fck_parent_names[] = { + "func_32k_ck", +}; + +static struct clk_hw_omap gpios_fck_hw = { + .hw = { + .clk = &gpios_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wu_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); + +static struct clk gpios_ick; + +static const char *gpios_ick_parent_names[] = { + "wu_l4_ick", +}; + +static struct clk_hw_omap gpios_ick_hw = { + .hw = { + .clk = &gpios_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk gpmc_fck; + +static struct clk_hw_omap gpmc_fck_hw = { + .hw = { + .clk = &gpmc_fck, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); + +static const struct clksel_rate gpt_alt_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel omap24xx_gpt_clksel[] = { + { .parent = &func_32k_ck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = &alt_ck, .rates = gpt_alt_rates }, + { .parent = NULL }, +}; + +static const char *gpt10_fck_parent_names[] = { + "func_32k_ck", "sys_ck", "alt_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT10_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt10_ick; + +static struct clk_hw_omap gpt10_ick_hw = { + .hw = { + .clk = &gpt10_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT10_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT11_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt11_ick; + +static struct clk_hw_omap gpt11_ick_hw = { + .hw = { + .clk = &gpt11_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT11_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT12_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt12_ick; + +static struct clk_hw_omap gpt12_ick_hw = { + .hw = { + .clk = &gpt12_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT12_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clk_ops gpt1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_GPT1_MASK, + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, gpt1_fck_ops); + +static struct clk gpt1_ick; + +static struct clk_hw_omap gpt1_ick_hw = { + .hw = { + .clk = &gpt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt2_ick; + +static struct clk_hw_omap gpt2_ick_hw = { + .hw = { + .clk = &gpt2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT3_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt3_ick; + +static struct clk_hw_omap gpt3_ick_hw = { + .hw = { + .clk = &gpt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT4_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt4_ick; + +static struct clk_hw_omap gpt4_ick_hw = { + .hw = { + .clk = &gpt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT5_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt5_ick; + +static struct clk_hw_omap gpt5_ick_hw = { + .hw = { + .clk = &gpt5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT6_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt6_ick; + +static struct clk_hw_omap gpt6_ick_hw = { + .hw = { + .clk = &gpt6_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT6_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT7_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt7_ick; + +static struct clk_hw_omap gpt7_ick_hw = { + .hw = { + .clk = &gpt7_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT7_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT8_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt8_ick; + +static struct clk_hw_omap gpt8_ick_hw = { + .hw = { + .clk = &gpt8_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT8_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT9_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt9_ick; + +static struct clk_hw_omap gpt9_ick_hw = { + .hw = { + .clk = &gpt9_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT9_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk hdq_fck; + +static struct clk_hw_omap hdq_fck_hw = { + .hw = { + .clk = &hdq_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk hdq_ick; + +static struct clk_hw_omap hdq_ick_hw = { + .hw = { + .clk = &hdq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c1_fck; + +static struct clk_hw_omap i2c1_fck_hw = { + .hw = { + .clk = &i2c1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk i2c1_ick; + +static struct clk_hw_omap i2c1_ick_hw = { + .hw = { + .clk = &i2c1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c2_fck; + +static struct clk_hw_omap i2c2_fck_hw = { + .hw = { + .clk = &i2c2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk i2c2_ick; + +static struct clk_hw_omap i2c2_ick_hw = { + .hw = { + .clk = &i2c2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP2420_CLKSEL_IVA_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static struct clk iva1_mpu_int_ifck; + +static const char *iva1_mpu_int_ifck_parent_names[] = { + "iva1_ifck", +}; + +static const struct clk_ops iva1_mpu_int_ifck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap_fixed_divisor_recalc, +}; + +static struct clk_hw_omap iva1_mpu_int_ifck_hw = { + .hw = { + .clk = &iva1_mpu_int_ifck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, + .clkdm_name = "iva1_clkdm", + .fixed_div = 2, +}; + +DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, + iva1_mpu_int_ifck_ops); + +static struct clk mailboxes_ick; + +static struct clk_hw_omap mailboxes_ick_hw = { + .hw = { + .clk = &mailboxes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parent_names[] = { + "func_96m_ck", "mcbsp_clks", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP1_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp1_ick; + +static struct clk_hw_omap mcbsp1_ick_hw = { + .hw = { + .clk = &mcbsp1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP2_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp2_ick; + +static struct clk_hw_omap mcbsp2_ick_hw = { + .hw = { + .clk = &mcbsp2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi1_fck; + +static const char *mcspi1_fck_parent_names[] = { + "func_48m_ck", +}; + +static struct clk_hw_omap mcspi1_fck_hw = { + .hw = { + .clk = &mcspi1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi1_ick; + +static struct clk_hw_omap mcspi1_ick_hw = { + .hw = { + .clk = &mcspi1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi2_fck; + +static struct clk_hw_omap mcspi2_fck_hw = { + .hw = { + .clk = &mcspi2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi2_ick; + +static struct clk_hw_omap mcspi2_ick_hw = { + .hw = { + .clk = &mcspi2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmc_fck; + +static struct clk_hw_omap mmc_fck_hw = { + .hw = { + .clk = &mmc_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_MMC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmc_ick; + +static struct clk_hw_omap mmc_ick_hw = { + .hw = { + .clk = &mmc_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_MMC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk mpu_wdt_fck; + +static struct clk_hw_omap mpu_wdt_fck_hw = { + .hw = { + .clk = &mpu_wdt_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk mpu_wdt_ick; + +static struct clk_hw_omap mpu_wdt_ick_hw = { + .hw = { + .clk = &mpu_wdt_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk mspro_fck; + +static struct clk_hw_omap mspro_fck_hw = { + .hw = { + .clk = &mspro_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mspro_ick; + +static struct clk_hw_omap mspro_ick_hw = { + .hw = { + .clk = &mspro_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk omapctrl_ick; + +static struct clk_hw_omap omapctrl_ick_hw = { + .hw = { + .clk = &omapctrl_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk pka_ick; + +static struct clk_hw_omap pka_ick_hw = { + .hw = { + .clk = &pka_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_PKA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk rng_ick; + +static struct clk_hw_omap rng_ick_hw = { + .hw = { + .clk = &rng_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_RNG_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk sdma_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdma_ick; + +static struct clk_hw_omap sdma_ick_hw = { + .hw = { + .clk = &sdma_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdrc_ick; + +static struct clk_hw_omap sdrc_ick_hw = { + .hw = { + .clk = &sdrc_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sha_ick; + +static struct clk_hw_omap sha_ick_hw = { + .hw = { + .clk = &sha_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_SHA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk ssi_l4_ick; + +static struct clk_hw_omap ssi_l4_ick_hw = { + .hw = { + .clk = &ssi_l4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_sst_fck_clksel[] = { + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *ssi_ssr_sst_fck_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", + ssi_ssr_sst_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_SSI_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, + ssi_ssr_sst_fck_parent_names, dsp_fck_ops); + +static struct clk sync_32k_ick; + +static struct clk_hw_omap sync_32k_ick_hw = { + .hw = { + .clk = &sync_32k_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_clkout_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel common_clkout_src_clksel[] = { + { .parent = &core_ck, .rates = common_clkout_src_core_rates }, + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, + { .parent = NULL }, +}; + +static const char *sys_clkout_src_parent_names[] = { + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm", + common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL, + OMAP2420_CLKOUT2_SOURCE_MASK, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, + OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +static struct clk uart1_fck; + +static struct clk_hw_omap uart1_fck_hw = { + .hw = { + .clk = &uart1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart1_ick; + +static struct clk_hw_omap uart1_ick_hw = { + .hw = { + .clk = &uart1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart2_fck; + +static struct clk_hw_omap uart2_fck_hw = { + .hw = { + .clk = &uart2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart2_ick; + +static struct clk_hw_omap uart2_ick_hw = { + .hw = { + .clk = &uart2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart3_fck; + +static struct clk_hw_omap uart3_fck_hw = { + .hw = { + .clk = &uart3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart3_ick; + +static struct clk_hw_omap uart3_ick_hw = { + .hw = { + .clk = &uart3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk usb_fck; + +static struct clk_hw_omap usb_fck_hw = { + .hw = { + .clk = &usb_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_USB_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel usb_l4_ick_clksel[] = { + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, + { .parent = NULL }, +}; + +static const char *usb_l4_ick_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_USB_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, + usb_l4_ick_parent_names, dsp_fck_ops); + +static struct clk virt_prcm_set; + +static const char *virt_prcm_set_parent_names[] = { + "mpu_ck", +}; + +static const struct clk_ops virt_prcm_set_ops = { + .recalc_rate = &omap2_table_mpu_recalc, + .set_rate = &omap2_select_table_rate, + .round_rate = &omap2_round_to_table_rate, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); + +static const struct clksel_rate vlynq_fck_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel_rate vlynq_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_242X }, + { .div = 2, .val = 2, .flags = RATE_IN_242X }, + { .div = 3, .val = 3, .flags = RATE_IN_242X }, + { .div = 4, .val = 4, .flags = RATE_IN_242X }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 9, .val = 9, .flags = RATE_IN_242X }, + { .div = 12, .val = 12, .flags = RATE_IN_242X }, + { .div = 16, .val = 16, .flags = RATE_IN_242X }, + { .div = 18, .val = 18, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel vlynq_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, + { .parent = &core_ck, .rates = vlynq_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *vlynq_fck_parent_names[] = { + "func_96m_ck", "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP2420_CLKSEL_VLYNQ_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, + vlynq_fck_parent_names, dss1_fck_ops); + +static struct clk vlynq_ick; + +static struct clk_hw_omap vlynq_ick_hw = { + .hw = { + .clk = &vlynq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_ick; + +static struct clk_hw_omap wdt1_ick_hw = { + .hw = { + .clk = &wdt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_WDT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_osc_ck; + +static const struct clk_ops wdt1_osc_ck_ops = {}; + +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); + +static struct clk wdt3_fck; + +static struct clk_hw_omap wdt3_fck_hw = { + .hw = { + .clk = &wdt3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_WDT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wdt3_ick; + +static struct clk_hw_omap wdt3_ick_hw = { + .hw = { + .clk = &wdt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_WDT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk wdt4_fck; + +static struct clk_hw_omap wdt4_fck_hw = { + .hw = { + .clk = &wdt4_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wdt4_ick; + +static struct clk_hw_omap wdt4_ick_hw = { + .hw = { + .clk = &wdt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); + +/* + * clkdev integration + */ + +static struct omap_clk omap2420_clks[] = { + /* external root sources */ + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), + CLK(NULL, "osc_ck", &osc_ck, CK_242X), + CLK(NULL, "sys_ck", &sys_ck, CK_242X), + CLK(NULL, "alt_ck", &alt_ck, CK_242X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), + /* internal analog sources */ + CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), + CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), + CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), + /* internal prcm root sources */ + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), + CLK(NULL, "core_ck", &core_ck, CK_242X), + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), + CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), + CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), + CLK(NULL, "emul_ck", &emul_ck, CK_242X), + /* mpu domain clocks */ + CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), + /* dsp domain clocks */ + CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), + CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), + CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), + CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), + /* GFX domain clocks */ + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), + /* DSS domain clocks */ + CLK("omapdss_dss", "ick", &dss_ick, CK_242X), + CLK(NULL, "dss_ick", &dss_ick, CK_242X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), + /* L4 domain clocks */ + CLK(NULL, "l4_ck", &l4_ck, CK_242X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X), + /* virtual meta-group clock */ + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), + /* general l4 interface ck, multi-parent functional clk */ + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), + CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), + CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), + CLK("omap24xxcam", "fck", &cam_fck, CK_242X), + CLK(NULL, "cam_fck", &cam_fck, CK_242X), + CLK("omap24xxcam", "ick", &cam_ick, CK_242X), + CLK(NULL, "cam_ick", &cam_ick, CK_242X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), + CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), + CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), + CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), + CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), + CLK(NULL, "fac_ick", &fac_ick, CK_242X), + CLK(NULL, "fac_fck", &fac_fck, CK_242X), + CLK(NULL, "eac_ick", &eac_ick, CK_242X), + CLK(NULL, "eac_fck", &eac_fck, CK_242X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), + CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), + CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), + CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), + CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), + CLK(NULL, "des_ick", &des_ick, CK_242X), + CLK("omap-sham", "ick", &sha_ick, CK_242X), + CLK(NULL, "sha_ick", &sha_ick, CK_242X), + CLK("omap_rng", "ick", &rng_ick, CK_242X), + CLK(NULL, "rng_ick", &rng_ick, CK_242X), + CLK("omap-aes", "ick", &aes_ick, CK_242X), + CLK(NULL, "aes_ick", &aes_ick, CK_242X), + CLK(NULL, "pka_ick", &pka_ick, CK_242X), + CLK(NULL, "usb_fck", &usb_fck, CK_242X), + CLK("musb-hdrc", "fck", &osc_ck, CK_242X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), +}; + + +static const char *enable_init_clks[] = { + "apll96_ck", + "apll54_ck", + "sync_32k_ick", + "omapctrl_ick", + "gpmc_fck", + "sdrc_ick", +}; + +/* + * init code + */ + +int __init omap2420_clk_init(void) +{ + struct omap_clk *c; + + prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; + cpu_mask = RATE_IN_242X; + rate_table = omap2420_rate_table; + + omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); + + omap2xxx_clkt_vps_check_bootloader_rates(); + + for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); + c++) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", + (clk_get_rate(&sys_ck) / 1000000), + (clk_get_rate(&sys_ck) / 100000) % 10, + (clk_get_rate(&dpll_ck) / 1000000), + (clk_get_rate(&mpu_ck) / 1000000)); + + return 0; +} diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c new file mode 100644 index 0000000..eda079b --- /dev/null +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -0,0 +1,2065 @@ +/* + * OMAP2430 clock data + * + * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc. + * Copyright (C) 2004-2011 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clk-private.h> +#include <linux/list.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock2xxx.h" +#include "opp2xxx.h" +#include "cm2xxx.h" +#include "prm2xxx.h" +#include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" +#include "sdrc.h" +#include "control.h" + +#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR + +/* + * 2430 clock tree. + * + * NOTE:In many cases here we are assigning a 'default' parent. In + * many cases the parent is selectable. The set parent calls will + * also switch sources. + * + * Several sources are given initial rates which may be wrong, this will + * be fixed up in the init func. + * + * Things are broadly separated below by clock domains. It is + * noteworthy that most peripherals have dependencies on multiple clock + * domains. Many get their interface clocks from the L4 domain, but get + * functional clocks from fixed sources or other core domain derived + * clocks. + */ + +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); + +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); + +static struct clk osc_ck; + +static const struct clk_ops osc_ck_ops = { + .enable = &omap2_enable_osc_ck, + .disable = omap2_disable_osc_ck, + .recalc_rate = &omap2_osc_clk_recalc, +}; + +static struct clk_hw_omap osc_ck_hw = { + .hw = { + .clk = &osc_ck, + }, +}; + +static struct clk osc_ck = { + .name = "osc_ck", + .ops = &osc_ck_ops, + .hw = &osc_ck_hw.hw, + .flags = CLK_IS_ROOT, +}; + +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +static struct clk sys_ck; + +static const char *sys_ck_parent_names[] = { + "osc_ck", +}; + +static const struct clk_ops sys_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2xxx_sys_clk_recalc, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); + +static struct dpll_data dpll_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP24XX_DPLL_MULT_MASK, + .div1_mask = OMAP24XX_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP24XX_EN_DPLL_MASK, + .max_multiplier = 1023, + .min_divider = 1, + .max_divider = 16, +}; + +static struct clk dpll_ck; + +static const char *dpll_ck_parent_names[] = { + "sys_ck", +}; + +static const struct clk_ops dpll_ck_ops = { + .init = &omap2_init_clk_clkdm, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap2_dpllcore_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap2_reprogram_dpllcore, +}; + +static struct clk_hw_omap dpll_ck_hw = { + .hw = { + .clk = &dpll_ck, + }, + .ops = &clkhwops_omap2xxx_dpll, + .dpll_data = &dpll_dd, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); + +static struct clk core_ck; + +static const char *core_ck_parent_names[] = { + "dpll_ck", +}; + +static const struct clk_ops core_ck_ops = { + .init = &omap2_init_clk_clkdm, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); + +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk aes_ick; + +static const char *aes_ick_parent_names[] = { + "l4_ck", +}; + +static const struct clk_ops aes_ick_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap aes_ick_hw = { + .hw = { + .clk = &aes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_AES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk apll54_ck; + +static const struct clk_ops apll54_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll54_enable, + .disable = &omap2_clk_apll54_disable, + .recalc_rate = &omap2_clk_apll54_recalc, +}; + +static struct clk_hw_omap apll54_ck_hw = { + .hw = { + .clk = &apll54_ck, + }, + .ops = &clkhwops_apll54, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); + +static struct clk apll96_ck; + +static const struct clk_ops apll96_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll96_enable, + .disable = &omap2_clk_apll96_disable, + .recalc_rate = &omap2_clk_apll96_recalc, +}; + +static struct clk_hw_omap apll96_ck_hw = { + .hw = { + .clk = &apll96_ck, + }, + .ops = &clkhwops_apll96, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); + +static const char *func_96m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, + OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); + +static struct clk cam_fck; + +static const char *cam_fck_parent_names[] = { + "func_96m_ck", +}; + +static struct clk_hw_omap cam_fck_hw = { + .hw = { + .clk = &cam_fck, + }, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk cam_ick; + +static struct clk_hw_omap cam_ick_hw = { + .hw = { + .clk = &cam_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk des_ick; + +static struct clk_hw_omap des_ick_hw = { + .hw = { + .clk = &des_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_DES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate dsp_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dsp_fck_clksel[] = { + { .parent = &core_ck, .rates = dsp_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dsp_fck_parent_names[] = { + "core_ck", +}; + +static struct clk dsp_fck; + +static const struct clk_ops dsp_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static const struct clksel_rate dss1_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss1_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_24XX }, + { .div = 8, .val = 8, .flags = RATE_IN_24XX }, + { .div = 9, .val = 9, .flags = RATE_IN_24XX }, + { .div = 12, .val = 12, .flags = RATE_IN_24XX }, + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dss1_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, + { .parent = &core_ck, .rates = dss1_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dss1_fck_parent_names[] = { + "sys_ck", "core_ck", +}; + +static const struct clk_ops dss1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS1_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS1_SHIFT, NULL, + dss1_fck_parent_names, dss1_fck_ops); + +static const struct clksel_rate dss2_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss2_fck_48m_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_apll96_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel func_48m_clksel[] = { + { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, + { .parent = &alt_ck, .rates = func_48m_alt_rates }, + { .parent = NULL }, +}; + +static const char *func_48m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +static struct clk func_48m_ck; + +static const struct clk_ops func_48m_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap func_48m_ck_hw = { + .hw = { + .clk = &func_48m_ck, + }, + .clksel = func_48m_clksel, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); + +static const struct clksel dss2_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, + { .parent = NULL }, +}; + +static const char *dss2_fck_parent_names[] = { + "sys_ck", "func_48m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS2_SHIFT, NULL, + dss2_fck_parent_names, dss1_fck_ops); + +static const char *func_54m_ck_parent_names[] = { + "apll54_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); + +static struct clk dss_54m_fck; + +static const char *dss_54m_fck_parent_names[] = { + "func_54m_ck", +}; + +static struct clk_hw_omap dss_54m_fck_hw = { + .hw = { + .clk = &dss_54m_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); + +static struct clk dss_ick; + +static struct clk_hw_omap dss_ick_hw = { + .hw = { + .clk = &dss_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk emul_ck; + +static struct clk_hw_omap emul_ck_hw = { + .hw = { + .clk = &emul_ck, + }, + .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); + +static struct clk fac_fck; + +static const char *fac_fck_parent_names[] = { + "func_12m_ck", +}; + +static struct clk_hw_omap fac_fck_hw = { + .hw = { + .clk = &fac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk fac_ick; + +static struct clk_hw_omap fac_ick_hw = { + .hw = { + .clk = &fac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel gfx_fck_clksel[] = { + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, + { .parent = NULL }, +}; + +static const char *gfx_2d_fck_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +static struct clk gfx_ick; + +static const char *gfx_ick_parent_names[] = { + "core_l3_ck", +}; + +static struct clk_hw_omap gfx_ick_hw = { + .hw = { + .clk = &gfx_ick, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .clkdm_name = "gfx_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk gpio5_fck; + +static const char *gpio5_fck_parent_names[] = { + "func_32k_ck", +}; + +static struct clk_hw_omap gpio5_fck_hw = { + .hw = { + .clk = &gpio5_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_GPIO5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk gpio5_ick; + +static struct clk_hw_omap gpio5_ick_hw = { + .hw = { + .clk = &gpio5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_GPIO5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk gpios_fck; + +static struct clk_hw_omap gpios_fck_hw = { + .hw = { + .clk = &gpios_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk wu_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); + +static struct clk gpios_ick; + +static const char *gpios_ick_parent_names[] = { + "wu_l4_ick", +}; + +static struct clk_hw_omap gpios_ick_hw = { + .hw = { + .clk = &gpios_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk gpmc_fck; + +static struct clk_hw_omap gpmc_fck_hw = { + .hw = { + .clk = &gpmc_fck, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); + +static const struct clksel_rate gpt_alt_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel omap24xx_gpt_clksel[] = { + { .parent = &func_32k_ck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = &alt_ck, .rates = gpt_alt_rates }, + { .parent = NULL }, +}; + +static const char *gpt10_fck_parent_names[] = { + "func_32k_ck", "sys_ck", "alt_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT10_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt10_ick; + +static struct clk_hw_omap gpt10_ick_hw = { + .hw = { + .clk = &gpt10_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT10_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT11_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt11_ick; + +static struct clk_hw_omap gpt11_ick_hw = { + .hw = { + .clk = &gpt11_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT11_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT12_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt12_ick; + +static struct clk_hw_omap gpt12_ick_hw = { + .hw = { + .clk = &gpt12_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT12_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clk_ops gpt1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_GPT1_MASK, + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, gpt1_fck_ops); + +static struct clk gpt1_ick; + +static struct clk_hw_omap gpt1_ick_hw = { + .hw = { + .clk = &gpt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt2_ick; + +static struct clk_hw_omap gpt2_ick_hw = { + .hw = { + .clk = &gpt2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT3_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt3_ick; + +static struct clk_hw_omap gpt3_ick_hw = { + .hw = { + .clk = &gpt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT4_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt4_ick; + +static struct clk_hw_omap gpt4_ick_hw = { + .hw = { + .clk = &gpt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT5_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt5_ick; + +static struct clk_hw_omap gpt5_ick_hw = { + .hw = { + .clk = &gpt5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT6_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt6_ick; + +static struct clk_hw_omap gpt6_ick_hw = { + .hw = { + .clk = &gpt6_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT6_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT7_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt7_ick; + +static struct clk_hw_omap gpt7_ick_hw = { + .hw = { + .clk = &gpt7_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT7_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk gpt8_fck; + +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT8_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt8_ick; + +static struct clk_hw_omap gpt8_ick_hw = { + .hw = { + .clk = &gpt8_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT8_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT9_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt9_ick; + +static struct clk_hw_omap gpt9_ick_hw = { + .hw = { + .clk = &gpt9_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT9_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk hdq_fck; + +static struct clk_hw_omap hdq_fck_hw = { + .hw = { + .clk = &hdq_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk hdq_ick; + +static struct clk_hw_omap hdq_ick_hw = { + .hw = { + .clk = &hdq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c1_ick; + +static struct clk_hw_omap i2c1_ick_hw = { + .hw = { + .clk = &i2c1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c2_ick; + +static struct clk_hw_omap i2c2_ick_hw = { + .hw = { + .clk = &i2c2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2chs1_fck; + +static struct clk_hw_omap i2chs1_fck_hw = { + .hw = { + .clk = &i2chs1_fck, + }, + .ops = &clkhwops_omap2430_i2chs_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk i2chs2_fck; + +static struct clk_hw_omap i2chs2_fck_hw = { + .hw = { + .clk = &i2chs2_fck, + }, + .ops = &clkhwops_omap2430_i2chs_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk icr_ick; + +static struct clk_hw_omap icr_ick_hw = { + .hw = { + .clk = &icr_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP2430_EN_ICR_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel dsp_ick_clksel[] = { + { .parent = &dsp_fck, .rates = dsp_ick_rates }, + { .parent = NULL }, +}; + +static const char *iva2_1_ick_parent_names[] = { + "dsp_fck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_IF_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + iva2_1_ick_parent_names, dsp_fck_ops); + +static struct clk mailboxes_ick; + +static struct clk_hw_omap mailboxes_ick_hw = { + .hw = { + .clk = &mailboxes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parent_names[] = { + "func_96m_ck", "mcbsp_clks", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP1_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp1_ick; + +static struct clk_hw_omap mcbsp1_ick_hw = { + .hw = { + .clk = &mcbsp1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP2_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp2_ick; + +static struct clk_hw_omap mcbsp2_ick_hw = { + .hw = { + .clk = &mcbsp2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP3_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp3_ick; + +static struct clk_hw_omap mcbsp3_ick_hw = { + .hw = { + .clk = &mcbsp3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP4_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp4_ick; + +static struct clk_hw_omap mcbsp4_ick_hw = { + .hw = { + .clk = &mcbsp4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP5_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp5_ick; + +static struct clk_hw_omap mcbsp5_ick_hw = { + .hw = { + .clk = &mcbsp5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi1_fck; + +static const char *mcspi1_fck_parent_names[] = { + "func_48m_ck", +}; + +static struct clk_hw_omap mcspi1_fck_hw = { + .hw = { + .clk = &mcspi1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi1_ick; + +static struct clk_hw_omap mcspi1_ick_hw = { + .hw = { + .clk = &mcspi1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi2_fck; + +static struct clk_hw_omap mcspi2_fck_hw = { + .hw = { + .clk = &mcspi2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi2_ick; + +static struct clk_hw_omap mcspi2_ick_hw = { + .hw = { + .clk = &mcspi2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi3_fck; + +static struct clk_hw_omap mcspi3_fck_hw = { + .hw = { + .clk = &mcspi3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi3_ick; + +static struct clk_hw_omap mcspi3_ick_hw = { + .hw = { + .clk = &mcspi3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate mdm_ick_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_243X }, + { .div = 4, .val = 4, .flags = RATE_IN_243X }, + { .div = 6, .val = 6, .flags = RATE_IN_243X }, + { .div = 9, .val = 9, .flags = RATE_IN_243X }, + { .div = 0 } +}; + +static const struct clksel mdm_ick_clksel[] = { + { .parent = &core_ck, .rates = mdm_ick_core_rates }, + { .parent = NULL }, +}; + +static const char *mdm_ick_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), + OMAP2430_CLKSEL_MDM_MASK, + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), + OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, + &clkhwops_iclk_wait, mdm_ick_parent_names, + dsp_fck_ops); + +static struct clk mdm_intc_ick; + +static struct clk_hw_omap mdm_intc_ick_hw = { + .hw = { + .clk = &mdm_intc_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mdm_osc_ck; + +static struct clk_hw_omap mdm_osc_ck_hw = { + .hw = { + .clk = &mdm_osc_ck, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), + .enable_bit = OMAP2430_EN_OSC_SHIFT, + .clkdm_name = "mdm_clkdm", +}; + +DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); + +static struct clk mmchs1_fck; + +static struct clk_hw_omap mmchs1_fck_hw = { + .hw = { + .clk = &mmchs1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmchs1_ick; + +static struct clk_hw_omap mmchs1_ick_hw = { + .hw = { + .clk = &mmchs1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmchs2_fck; + +static struct clk_hw_omap mmchs2_fck_hw = { + .hw = { + .clk = &mmchs2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmchs2_ick; + +static struct clk_hw_omap mmchs2_ick_hw = { + .hw = { + .clk = &mmchs2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmchsdb1_fck; + +static struct clk_hw_omap mmchsdb1_fck_hw = { + .hw = { + .clk = &mmchsdb1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk mmchsdb2_fck; + +static struct clk_hw_omap mmchsdb2_fck_hw = { + .hw = { + .clk = &mmchsdb2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk mpu_wdt_fck; + +static struct clk_hw_omap mpu_wdt_fck_hw = { + .hw = { + .clk = &mpu_wdt_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk mpu_wdt_ick; + +static struct clk_hw_omap mpu_wdt_ick_hw = { + .hw = { + .clk = &mpu_wdt_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk mspro_fck; + +static struct clk_hw_omap mspro_fck_hw = { + .hw = { + .clk = &mspro_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mspro_ick; + +static struct clk_hw_omap mspro_ick_hw = { + .hw = { + .clk = &mspro_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk omapctrl_ick; + +static struct clk_hw_omap omapctrl_ick_hw = { + .hw = { + .clk = &omapctrl_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk pka_ick; + +static struct clk_hw_omap pka_ick_hw = { + .hw = { + .clk = &pka_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_PKA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk rng_ick; + +static struct clk_hw_omap rng_ick_hw = { + .hw = { + .clk = &rng_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_RNG_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk sdma_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdma_ick; + +static struct clk_hw_omap sdma_ick_hw = { + .hw = { + .clk = &sdma_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdrc_ick; + +static struct clk_hw_omap sdrc_ick_hw = { + .hw = { + .clk = &sdrc_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP2430_EN_SDRC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sha_ick; + +static struct clk_hw_omap sha_ick_hw = { + .hw = { + .clk = &sha_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_SHA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk ssi_l4_ick; + +static struct clk_hw_omap ssi_l4_ick_hw = { + .hw = { + .clk = &ssi_l4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_243X }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_sst_fck_clksel[] = { + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *ssi_ssr_sst_fck_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", + ssi_ssr_sst_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_SSI_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, + ssi_ssr_sst_fck_parent_names, dsp_fck_ops); + +static struct clk sync_32k_ick; + +static struct clk_hw_omap sync_32k_ick_hw = { + .hw = { + .clk = &sync_32k_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_clkout_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel common_clkout_src_clksel[] = { + { .parent = &core_ck, .rates = common_clkout_src_core_rates }, + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, + { .parent = NULL }, +}; + +static const char *sys_clkout_src_parent_names[] = { + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +static struct clk uart1_fck; + +static struct clk_hw_omap uart1_fck_hw = { + .hw = { + .clk = &uart1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart1_ick; + +static struct clk_hw_omap uart1_ick_hw = { + .hw = { + .clk = &uart1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart2_fck; + +static struct clk_hw_omap uart2_fck_hw = { + .hw = { + .clk = &uart2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart2_ick; + +static struct clk_hw_omap uart2_ick_hw = { + .hw = { + .clk = &uart2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart3_fck; + +static struct clk_hw_omap uart3_fck_hw = { + .hw = { + .clk = &uart3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart3_ick; + +static struct clk_hw_omap uart3_ick_hw = { + .hw = { + .clk = &uart3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk usb_fck; + +static struct clk_hw_omap usb_fck_hw = { + .hw = { + .clk = &usb_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_USB_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel usb_l4_ick_clksel[] = { + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, + { .parent = NULL }, +}; + +static const char *usb_l4_ick_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_USB_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, + usb_l4_ick_parent_names, dsp_fck_ops); + +static struct clk usbhs_ick; + +static struct clk_hw_omap usbhs_ick_hw = { + .hw = { + .clk = &usbhs_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_USBHS_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk virt_prcm_set; + +static const char *virt_prcm_set_parent_names[] = { + "mpu_ck", +}; + +static const struct clk_ops virt_prcm_set_ops = { + .recalc_rate = &omap2_table_mpu_recalc, + .set_rate = &omap2_select_table_rate, + .round_rate = &omap2_round_to_table_rate, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); + +static struct clk wdt1_ick; + +static struct clk_hw_omap wdt1_ick_hw = { + .hw = { + .clk = &wdt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_WDT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_osc_ck; + +static const struct clk_ops wdt1_osc_ck_ops = {}; + +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); + +static struct clk wdt4_fck; + +static struct clk_hw_omap wdt4_fck_hw = { + .hw = { + .clk = &wdt4_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk wdt4_ick; + +static struct clk_hw_omap wdt4_ick_hw = { + .hw = { + .clk = &wdt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); + +/* + * clkdev integration + */ + +static struct omap_clk omap2430_clks[] = { + /* external root sources */ + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), + CLK(NULL, "osc_ck", &osc_ck, CK_243X), + CLK("twl", "fck", &osc_ck, CK_243X), + CLK(NULL, "sys_ck", &sys_ck, CK_243X), + CLK(NULL, "alt_ck", &alt_ck, CK_243X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), + /* internal analog sources */ + CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), + CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), + CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), + /* internal prcm root sources */ + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), + CLK(NULL, "core_ck", &core_ck, CK_243X), + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), + CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), + CLK(NULL, "emul_ck", &emul_ck, CK_243X), + /* mpu domain clocks */ + CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), + /* dsp domain clocks */ + CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), + CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), + /* GFX domain clocks */ + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), + /* Modem domain clocks */ + CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), + /* DSS domain clocks */ + CLK("omapdss_dss", "ick", &dss_ick, CK_243X), + CLK(NULL, "dss_ick", &dss_ick, CK_243X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), + /* L4 domain clocks */ + CLK(NULL, "l4_ck", &l4_ck, CK_243X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X), + /* virtual meta-group clock */ + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), + /* general l4 interface ck, multi-parent functional clk */ + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), + CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), + CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), + CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), + CLK(NULL, "icr_ick", &icr_ick, CK_243X), + CLK("omap24xxcam", "fck", &cam_fck, CK_243X), + CLK(NULL, "cam_fck", &cam_fck, CK_243X), + CLK("omap24xxcam", "ick", &cam_ick, CK_243X), + CLK(NULL, "cam_ick", &cam_ick, CK_243X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), + CLK(NULL, "fac_ick", &fac_ick, CK_243X), + CLK(NULL, "fac_fck", &fac_fck, CK_243X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), + CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), + CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), + CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), + CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), + CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), + CLK(NULL, "des_ick", &des_ick, CK_243X), + CLK("omap-sham", "ick", &sha_ick, CK_243X), + CLK("omap_rng", "ick", &rng_ick, CK_243X), + CLK(NULL, "rng_ick", &rng_ick, CK_243X), + CLK("omap-aes", "ick", &aes_ick, CK_243X), + CLK(NULL, "pka_ick", &pka_ick, CK_243X), + CLK(NULL, "usb_fck", &usb_fck, CK_243X), + CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), + CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), + CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), + CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), + CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), + CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), + CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), + CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), + CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), + CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), + CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), +}; + +static const char *enable_init_clks[] = { + "apll96_ck", + "apll54_ck", + "sync_32k_ick", + "omapctrl_ick", + "gpmc_fck", + "sdrc_ick", +}; + +/* + * init code + */ + +int __init omap2430_clk_init(void) +{ + struct omap_clk *c; + + prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; + cpu_mask = RATE_IN_243X; + rate_table = omap2430_rate_table; + + omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); + + omap2xxx_clkt_vps_check_bootloader_rates(); + + for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); + c++) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", + (clk_get_rate(&sys_ck) / 1000000), + (clk_get_rate(&sys_ck) / 100000) % 10, + (clk_get_rate(&dpll_ck) / 1000000), + (clk_get_rate(&mpu_ck) / 1000000)); + + return 0; +} diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 11eaf16..669ef51 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -59,6 +59,7 @@ /* CM_CLKSEL_MPU */ #define OMAP24XX_CLKSEL_MPU_SHIFT 0 #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) +#define OMAP24XX_CLKSEL_MPU_WIDTH 5 /* CM_CLKSTCTRL_MPU */ #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 @@ -237,8 +238,10 @@ #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) #define OMAP24XX_CLKSEL_L4_SHIFT 5 #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) +#define OMAP24XX_CLKSEL_L4_WIDTH 2 #define OMAP24XX_CLKSEL_L3_SHIFT 0 #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) +#define OMAP24XX_CLKSEL_L3_WIDTH 5 /* CM_CLKSEL2_CORE */ #define OMAP24XX_CLKSEL_GPT12_SHIFT 22 @@ -363,8 +366,10 @@ #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) #define OMAP24XX_54M_SOURCE_SHIFT 5 #define OMAP24XX_54M_SOURCE_MASK (1 << 5) +#define OMAP24XX_54M_SOURCE_WIDTH 1 #define OMAP2430_96M_SOURCE_SHIFT 4 #define OMAP2430_96M_SOURCE_MASK (1 << 4) +#define OMAP2430_96M_SOURCE_WIDTH 1 #define OMAP24XX_48M_SOURCE_SHIFT 3 #define OMAP24XX_48M_SOURCE_MASK (1 << 3) #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 638da6d..91aa510 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -107,12 +107,14 @@ #define OMAP2420_CLKOUT2_EN_MASK (1 << 15) #define OMAP2420_CLKOUT2_DIV_SHIFT 11 #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) +#define OMAP2420_CLKOUT2_DIV_WIDTH 3 #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) #define OMAP24XX_CLKOUT_EN_SHIFT 7 #define OMAP24XX_CLKOUT_EN_MASK (1 << 7) #define OMAP24XX_CLKOUT_DIV_SHIFT 3 #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) +#define OMAP24XX_CLKOUT_DIV_WIDTH 3 #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) ^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette ` (27 preceding siblings ...) [not found] ` <1352337181-29427-16-git-send-email-mturquette@ti.com> @ 2012-11-13 13:42 ` Laurent Pinchart 2012-11-13 16:43 ` Mike Turquette 28 siblings, 1 reply; 67+ messages in thread From: Laurent Pinchart @ 2012-11-13 13:42 UTC (permalink / raw) To: Mike Turquette Cc: paul, rnayak, linux-omap, linux-arm-kernel, patches, Mike Turquette Hi Mike, Thank you for the patches. On Wednesday 07 November 2012 17:12:35 Mike Turquette wrote: > From: Mike Turquette <mturquette@linaro.org> > > Hi all, > > This series is based on top of Paul's PRM/CM clean-up work. It is a > refresh of the patches Rajendra sent out a while back[1], with the > addition of several fixes for PM regressions[2] across several > platforms. > > I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF > patches (delta is zero) and also suspend/resume. > > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > appears sane. However Panda-ES never comes back from suspend/resume. > This problem exists on the PRM/CM branch I based on and was not > introduced by this series. I am investigating that independently of > this series. > > Anyone wanting to pull the work can find it at: > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771 > [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015 I've tested the whole series on a Beagleboard-xM. The kernel boots fine but spits a couple of WARN_ON due to missing clk_prepare in USB-related drivers. I haven't noticed any regression in the OMAP3 ISP driver. I've also successfully tested rate back-propagation (CLK_SET_RATE_PARENT) on the dpll4_m5x2_ck and cam_mclk clocks with the OMAP3 ISP driver. I'll send a patch for that on top of your v3. So, Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-13 13:42 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Laurent Pinchart @ 2012-11-13 16:43 ` Mike Turquette 2012-11-15 0:57 ` Laurent Pinchart 0 siblings, 1 reply; 67+ messages in thread From: Mike Turquette @ 2012-11-13 16:43 UTC (permalink / raw) To: Laurent Pinchart; +Cc: paul, rnayak, linux-omap, linux-arm-kernel, patches Quoting Laurent Pinchart (2012-11-13 05:42:35) > Hi Mike, > > Thank you for the patches. > > On Wednesday 07 November 2012 17:12:35 Mike Turquette wrote: > > From: Mike Turquette <mturquette@linaro.org> > > > > Hi all, > > > > This series is based on top of Paul's PRM/CM clean-up work. It is a > > refresh of the patches Rajendra sent out a while back[1], with the > > addition of several fixes for PM regressions[2] across several > > platforms. > > > > I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF > > patches (delta is zero) and also suspend/resume. > > > > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > > appears sane. However Panda-ES never comes back from suspend/resume. > > This problem exists on the PRM/CM branch I based on and was not > > introduced by this series. I am investigating that independently of > > this series. > > > > Anyone wanting to pull the work can find it at: > > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771 > > [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015 > > I've tested the whole series on a Beagleboard-xM. The kernel boots fine but > spits a couple of WARN_ON due to missing clk_prepare in USB-related drivers. I > haven't noticed any regression in the OMAP3 ISP driver. > Those drivers need to be fixed. Can you provide a log? > I've also successfully tested rate back-propagation (CLK_SET_RATE_PARENT) on > the dpll4_m5x2_ck and cam_mclk clocks with the OMAP3 ISP driver. I'll send a > patch for that on top of your v3. > It is great to see this feature in action. Do you think the OMAP3 ISP driver can have parent clock info removed? The goal of the CLK_SET_RATE_PARENT flag is to make life easier for drivers by not having to know the details of the clock tree topology. > So, > > Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Thanks for testing! Regards, Mike > -- > Regards, > > Laurent Pinchart ^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH v2 00/26] Move OMAP2+ over to common clk framework 2012-11-13 16:43 ` Mike Turquette @ 2012-11-15 0:57 ` Laurent Pinchart 0 siblings, 0 replies; 67+ messages in thread From: Laurent Pinchart @ 2012-11-15 0:57 UTC (permalink / raw) To: Mike Turquette; +Cc: paul, rnayak, linux-omap, linux-arm-kernel, patches [-- Attachment #1: Type: text/plain, Size: 2664 bytes --] Hi Mike, On Tuesday 13 November 2012 08:43:23 Mike Turquette wrote: > Quoting Laurent Pinchart (2012-11-13 05:42:35) > > On Wednesday 07 November 2012 17:12:35 Mike Turquette wrote: > > > From: Mike Turquette <mturquette@linaro.org> > > > > > > Hi all, > > > > > > This series is based on top of Paul's PRM/CM clean-up work. It is a > > > refresh of the patches Rajendra sent out a while back[1], with the > > > addition of several fixes for PM regressions[2] across several > > > platforms. > > > > > > I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF > > > patches (delta is zero) and also suspend/resume. > > > > > > I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming > > > appears sane. However Panda-ES never comes back from suspend/resume. > > > This problem exists on the PRM/CM branch I based on and was not > > > introduced by this series. I am investigating that independently of > > > this series. > > > > > > Anyone wanting to pull the work can find it at: > > > git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8 > > > > > > [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771 > > > [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015 > > > > I've tested the whole series on a Beagleboard-xM. The kernel boots fine > > but > > spits a couple of WARN_ON due to missing clk_prepare in USB-related > > drivers. I haven't noticed any regression in the OMAP3 ISP driver. > > Those drivers need to be fixed. Can you provide a log? Complete boot log attached to this e-mail. My tree is based on your clk- omap-3.8 branch in git://git.linaro.org/people/mturquette/linux.git. I haven't checked yet if patches for the following warnings have been posted to linux- omap or other mailing lists. > > I've also successfully tested rate back-propagation (CLK_SET_RATE_PARENT) > > on the dpll4_m5x2_ck and cam_mclk clocks with the OMAP3 ISP driver. I'll > > send a patch for that on top of your v3. > > It is great to see this feature in action. Do you think the OMAP3 ISP > driver can have parent clock info removed? The goal of the > CLK_SET_RATE_PARENT flag is to make life easier for drivers by not > having to know the details of the clock tree topology. If you mean removing the explicit handling of dpll4_m5_ck and setting the cam_mclk rate directly then yes, that's the goal, and I'll submit patches for that when the successor to thiis patch series will reach mainline. If you mean something different please elaborate :-) > > So, > > > > Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > Thanks for testing! -- Regards, Laurent Pinchart [-- Attachment #2: clk-omap-3.8.log --] [-- Type: text/x-log, Size: 31266 bytes --] [ 0.000000] Booting Linux on physical CPU 0 [ 0.000000] Linux version 3.7.0-rc2-00295-g2d0135b (laurent@avalon) (gcc version 4.4.1 ('cs2009q3-67-hard-sb4') ) #454 Thu Nov 15 01:52:32 CET 2012 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine: OMAP3 Beagle Board [ 0.000000] Ignoring tag cmdline (using the default kernel command line) [ 0.000000] Reserving 16777216 bytes SDRAM for VRAM [ 0.000000] cma: CMA: reserved 16 MiB at 9dc00000 [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] OMAP3630 ES1.2 (l2cache iva sgx neon isp 192mhz_clk ) [ 0.000000] Clocking rate (Crystal/Core/MPU): 26.0/332/600 MHz [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 125696 [ 0.000000] Kernel command line: console=ttyO2,115200 omapfb.mode=dvi:1024x768MR-32@60 omapdss.def_disp=dvi [ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.000000] Memory: 495MB = 495MB total [ 0.000000] Memory: 471724k/471724k available, 52564k reserved, 0K highmem [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xe0800000 - 0xff000000 ( 488 MB) [ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc0624dd0 (6260 kB) [ 0.000000] .init : 0xc0625000 - 0xc065a300 ( 213 kB) [ 0.000000] .data : 0xc065c000 - 0xc0815e50 (1768 kB) [ 0.000000] .bss : 0xc0815e74 - 0xc0dd87c0 (5899 kB) [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts [ 0.000000] Total of 96 interrupts on 1 active controller [ 0.000000] OMAP clockevent source: GPTIMER12 at 32768 Hz [ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms [ 0.000000] OMAP clocksource: 32k_counter at 32768 Hz [ 0.000000] Console: colour dummy device 80x30 [ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8 [ 0.000000] ... MAX_LOCK_DEPTH: 48 [ 0.000000] ... MAX_LOCKDEP_KEYS: 8191 [ 0.000000] ... CLASSHASH_SIZE: 4096 [ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384 [ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768 [ 0.000000] ... CHAINHASH_SIZE: 16384 [ 0.000000] memory used by lock dependency info: 3951 kB [ 0.000000] per task-struct memory footprint: 2304 bytes [ 0.001037] Calibrating delay loop... 309.35 BogoMIPS (lpj=1210368) [ 0.085479] pid_max: default: 32768 minimum: 301 [ 0.085968] Security Framework initialized [ 0.086120] Mount-cache hash table entries: 512 [ 0.091644] CPU: Testing write buffer coherency: ok [ 0.092742] Setting up static identity map for 0x80454970 - 0x804549c8 [ 0.145568] pinctrl core: initialized pinctrl subsystem [ 0.154937] regulator-dummy: no parameters [ 0.158966] NET: Registered protocol family 16 [ 0.167388] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.170501] omap-gpmc omap-gpmc: GPMC revision 5.0 [ 0.188903] OMAP GPIO hardware version 2.5 [ 0.218780] omap_mux_init: Add partition: #1: core, flags: 0 [ 0.222503] OMAP3 Beagle Rev: xM C [ 0.241485] _omap_mux_get_by_name: Could not find signal uart4_rx.uart4_rx [ 0.248382] Reprogramming SDRC clock to 332000000 Hz [ 0.254669] find_device_opp: Invalid parameters [ 0.254852] find_device_opp: Invalid parameters [ 0.254913] find_device_opp: Invalid parameters [ 0.254974] find_device_opp: Invalid parameters [ 0.255279] platform mpu.0: opp_set_availability: Device OPP not found (-19) [ 0.255310] beagle_opp_init: failed to enable higher opp -19 [ 0.255340] platform mpu.0: opp_set_availability: Device OPP not found (-19) [ 0.255371] hw-breakpoint: debug architecture 0x4 unsupported. [ 0.282226] OMAP DMA hardware revision 5.0 [ 0.290405] arm-pmu: alias fck already exists [ 0.400115] bio: create slab <bio-0> at 0 [ 0.544433] omap-dma-engine omap-dma-engine: OMAP DMA engine driver [ 0.553558] SCSI subsystem initialized [ 0.557891] usbcore: registered new interface driver usbfs [ 0.558776] usbcore: registered new interface driver hub [ 0.560089] usbcore: registered new device driver usb [ 0.562927] musb-omap2430 musb-omap2430: invalid resource [ 0.598785] twl 1-0048: PIH (irq 23) chaining IRQs 338..346 [ 0.599578] twl 1-0048: power (irq 343) chaining IRQs 346..353 [ 0.604217] twl4030_gpio twl4030_gpio: gpio (irq 338) chaining IRQs 354..371 [ 0.614929] VUSB1V5: 1500 mV normal standby [ 0.618560] VUSB1V8: 1800 mV normal standby [ 0.622131] VUSB3V1: 3100 mV normal standby [ 0.630798] twl4030_usb twl4030_usb: Initialized TWL4030 USB module [ 0.636505] vdd_mpu_iva: 600 <--> 1450 mV normal [ 0.639984] vdd_core: 600 <--> 1450 mV normal [ 0.644073] VMMC1: 1850 <--> 3150 mV at 3000 mV normal standby [ 0.647918] VDAC: 1800 mV normal standby [ 0.651733] VDVI: 1800 mV normal standby [ 0.656005] VSIM: 1800 <--> 3000 mV at 1800 mV normal standby [ 0.660705] VAUX3: 1800 mV normal standby [ 0.665435] VAUX4: 1800 mV normal standby [ 0.666839] omap_i2c omap_i2c.1: bus 1 rev1.4.0 at 2600 kHz [ 0.679962] omap_i2c omap_i2c.3: bus 3 rev1.4.0 at 100 kHz [ 0.681274] media: Linux media interface: v0.10 [ 0.682159] Linux video capture interface: v2.00 [ 0.688049] omap-iommu omap-iommu.0: isp registered [ 0.690521] Advanced Linux Sound Architecture Driver Initialized. [ 0.696594] Switching to clocksource 32k_counter [ 0.899322] NET: Registered protocol family 2 [ 0.902099] TCP established hash table entries: 16384 (order: 5, 131072 bytes) [ 0.902862] TCP bind hash table entries: 16384 (order: 7, 720896 bytes) [ 0.912445] TCP: Hash tables configured (established 16384 bind 16384) [ 0.912719] TCP: reno registered [ 0.912750] UDP hash table entries: 256 (order: 2, 24576 bytes) [ 0.913085] UDP-Lite hash table entries: 256 (order: 2, 24576 bytes) [ 0.914337] NET: Registered protocol family 1 [ 0.916259] RPC: Registered named UNIX socket transport module. [ 0.916290] RPC: Registered udp transport module. [ 0.916320] RPC: Registered tcp transport module. [ 0.916320] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.916870] usbhs_omap usbhs_omap: xclk60mhsp2_ck set parentfailed error:-38 [ 0.917388] ------------[ cut here ]------------ [ 0.917419] WARNING: at drivers/clk/clk.c:512 __clk_enable+0x28/0x94() [ 0.917449] Modules linked in: [ 0.917480] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) [ 0.917510] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) [ 0.917541] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606f4>] (__clk_enable+0x28/0x94) [ 0.917572] [<c03606f4>] (__clk_enable+0x28/0x94) from [<c0360780>] (clk_enable+0x20/0x3c) [ 0.917602] [<c0360780>] (clk_enable+0x20/0x3c) from [<c029f2b8>] (usbhs_runtime_resume+0x74/0x90) [ 0.917633] [<c029f2b8>] (usbhs_runtime_resume+0x74/0x90) from [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) [ 0.917663] [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) from [<c02922bc>] (__rpm_callback+0x30/0x58) [ 0.917663] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28) [ 0.917694] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02931d8>] (rpm_resume+0x3b0/0x4cc) [ 0.917724] [<c02931d8>] (rpm_resume+0x3b0/0x4cc) from [<c0293558>] (__pm_runtime_resume+0x48/0x60) [ 0.917755] [<c0293558>] (__pm_runtime_resume+0x48/0x60) from [<c0445260>] (usbhs_omap_probe+0x3b4/0x810) [ 0.917785] [<c0445260>] (usbhs_omap_probe+0x3b4/0x810) from [<c028be64>] (platform_drv_probe+0x18/0x1c) [ 0.917816] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8) [ 0.917846] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c) [ 0.917846] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74) [ 0.917877] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218) [ 0.917907] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138) [ 0.917938] [<c028b444>] (driver_register+0xa0/0x138) from [<c028c124>] (platform_driver_probe+0x18/0x8c) [ 0.917968] [<c028c124>] (platform_driver_probe+0x18/0x8c) from [<c0008840>] (do_one_initcall+0x94/0x168) [ 0.917968] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0) [ 0.917999] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24) [ 0.918182] ---[ end trace 0eaa05360b28dfab ]--- [ 0.918212] ------------[ cut here ]------------ [ 0.918212] WARNING: at drivers/clk/clk.c:512 __clk_enable+0x28/0x94() [ 0.918243] Modules linked in: [ 0.918273] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) [ 0.918273] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) [ 0.918304] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606f4>] (__clk_enable+0x28/0x94) [ 0.918334] [<c03606f4>] (__clk_enable+0x28/0x94) from [<c0360780>] (clk_enable+0x20/0x3c) [ 0.918365] [<c0360780>] (clk_enable+0x20/0x3c) from [<c029f2c0>] (usbhs_runtime_resume+0x7c/0x90) [ 0.918395] [<c029f2c0>] (usbhs_runtime_resume+0x7c/0x90) from [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) [ 0.918395] [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) from [<c02922bc>] (__rpm_callback+0x30/0x58) [ 0.918426] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28) [ 0.918457] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02931d8>] (rpm_resume+0x3b0/0x4cc) [ 0.918487] [<c02931d8>] (rpm_resume+0x3b0/0x4cc) from [<c0293558>] (__pm_runtime_resume+0x48/0x60) [ 0.918518] [<c0293558>] (__pm_runtime_resume+0x48/0x60) from [<c0445260>] (usbhs_omap_probe+0x3b4/0x810) [ 0.918518] [<c0445260>] (usbhs_omap_probe+0x3b4/0x810) from [<c028be64>] (platform_drv_probe+0x18/0x1c) [ 0.918548] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8) [ 0.918579] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c) [ 0.918609] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74) [ 0.918640] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218) [ 0.918640] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138) [ 0.918670] [<c028b444>] (driver_register+0xa0/0x138) from [<c028c124>] (platform_driver_probe+0x18/0x8c) [ 0.918701] [<c028c124>] (platform_driver_probe+0x18/0x8c) from [<c0008840>] (do_one_initcall+0x94/0x168) [ 0.918731] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0) [ 0.918762] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24) [ 0.918762] ---[ end trace 0eaa05360b28dfac ]--- [ 0.918823] ------------[ cut here ]------------ [ 0.918853] WARNING: at drivers/clk/clk.c:471 clk_disable+0x20/0x34() [ 0.918853] Modules linked in: [ 0.918884] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) [ 0.918914] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) [ 0.918945] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606b8>] (clk_disable+0x20/0x34) [ 0.918945] [<c03606b8>] (clk_disable+0x20/0x34) from [<c029f32c>] (usbhs_runtime_suspend+0x58/0x90) [ 0.918975] [<c029f32c>] (usbhs_runtime_suspend+0x58/0x90) from [<c028e8b8>] (pm_generic_runtime_suspend+0x2c/0x38) [ 0.919006] [<c028e8b8>] (pm_generic_runtime_suspend+0x2c/0x38) from [<c00246b0>] (_od_runtime_suspend+0xc/0x24) [ 0.919036] [<c00246b0>] (_od_runtime_suspend+0xc/0x24) from [<c02922bc>] (__rpm_callback+0x30/0x58) [ 0.919067] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28) [ 0.919067] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02927a4>] (rpm_suspend+0x28c/0x45c) [ 0.919097] [<c02927a4>] (rpm_suspend+0x28c/0x45c) from [<c02937a4>] (__pm_runtime_suspend+0x54/0x6c) [ 0.919128] [<c02937a4>] (__pm_runtime_suspend+0x54/0x6c) from [<c028eda8>] (pm_generic_runtime_idle+0x44/0x4c) [ 0.919158] [<c028eda8>] (pm_generic_runtime_idle+0x44/0x4c) from [<c02922bc>] (__rpm_callback+0x30/0x58) [ 0.919189] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c0292b64>] (rpm_idle+0x184/0x208) [ 0.919189] [<c0292b64>] (rpm_idle+0x184/0x208) from [<c0292c9c>] (__pm_runtime_idle+0x54/0x6c) [ 0.919219] [<c0292c9c>] (__pm_runtime_idle+0x54/0x6c) from [<c04453c4>] (usbhs_omap_probe+0x518/0x810) [ 0.919250] [<c04453c4>] (usbhs_omap_probe+0x518/0x810) from [<c028be64>] (platform_drv_probe+0x18/0x1c) [ 0.919281] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8) [ 0.919311] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c) [ 0.919311] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74) [ 0.919342] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218) [ 0.919372] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138) [ 0.919403] [<c028b444>] (driver_register+0xa0/0x138) from [<c028c124>] (platform_driver_probe+0x18/0x8c) [ 0.919433] [<c028c124>] (platform_driver_probe+0x18/0x8c) from [<c0008840>] (do_one_initcall+0x94/0x168) [ 0.919433] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0) [ 0.919464] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24) [ 0.919494] ---[ end trace 0eaa05360b28dfad ]--- [ 0.919494] ------------[ cut here ]------------ [ 0.919525] WARNING: at drivers/clk/clk.c:471 clk_disable+0x20/0x34() [ 0.919525] Modules linked in: [ 0.919555] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) [ 0.919586] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) [ 0.919586] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606b8>] (clk_disable+0x20/0x34) [ 0.919616] [<c03606b8>] (clk_disable+0x20/0x34) from [<c029f334>] (usbhs_runtime_suspend+0x60/0x90) [ 0.919647] [<c029f334>] (usbhs_runtime_suspend+0x60/0x90) from [<c028e8b8>] (pm_generic_runtime_suspend+0x2c/0x38) [ 0.919677] [<c028e8b8>] (pm_generic_runtime_suspend+0x2c/0x38) from [<c00246b0>] (_od_runtime_suspend+0xc/0x24) [ 0.919677] [<c00246b0>] (_od_runtime_suspend+0xc/0x24) from [<c02922bc>] (__rpm_callback+0x30/0x58) [ 0.919708] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28) [ 0.919738] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02927a4>] (rpm_suspend+0x28c/0x45c) [ 0.919769] [<c02927a4>] (rpm_suspend+0x28c/0x45c) from [<c02937a4>] (__pm_runtime_suspend+0x54/0x6c) [ 0.919799] [<c02937a4>] (__pm_runtime_suspend+0x54/0x6c) from [<c028eda8>] (pm_generic_runtime_idle+0x44/0x4c) [ 0.919799] [<c028eda8>] (pm_generic_runtime_idle+0x44/0x4c) from [<c02922bc>] (__rpm_callback+0x30/0x58) [ 0.919830] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c0292b64>] (rpm_idle+0x184/0x208) [ 0.919860] [<c0292b64>] (rpm_idle+0x184/0x208) from [<c0292c9c>] (__pm_runtime_idle+0x54/0x6c) [ 0.919891] [<c0292c9c>] (__pm_runtime_idle+0x54/0x6c) from [<c04453c4>] (usbhs_omap_probe+0x518/0x810) [ 0.919921] [<c04453c4>] (usbhs_omap_probe+0x518/0x810) from [<c028be64>] (platform_drv_probe+0x18/0x1c) [ 0.919921] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8) [ 0.919952] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c) [ 0.919982] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74) [ 0.920013] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218) [ 0.920043] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138) [ 0.920043] [<c028b444>] (driver_register+0xa0/0x138) from [<c028c124>] (platform_driver_probe+0x18/0x8c) [ 0.920074] [<c028c124>] (platform_driver_probe+0x18/0x8c) from [<c0008840>] (do_one_initcall+0x94/0x168) [ 0.920104] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0) [ 0.920135] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24) [ 0.920135] ---[ end trace 0eaa05360b28dfae ]--- [ 0.926208] NetWinder Floating Point Emulator V0.97 (double precision) [ 0.926727] CPU PMU: probing PMU on CPU 0 [ 0.926910] hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available [ 1.136230] VFS: Disk quotas dquot_6.5.2 [ 1.136352] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 1.139221] NFS: Registering the id_resolver key type [ 1.139862] Key type id_resolver registered [ 1.139892] Key type id_legacy registered [ 1.140136] jffs2: version 2.2. (NAND) (SUMMARY) �© 2001-2006 Red Hat, Inc. [ 1.140930] msgmni has been set to 953 [ 1.149475] io scheduler noop registered [ 1.149505] io scheduler deadline registered [ 1.149658] io scheduler cfq registered (default) [ 1.158386] OMAP DSS rev 2.0 [ 1.177276] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 1.188354] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 88) is a OMAP UART0 [ 1.191680] omap_uart.2: ttyO2 at MMIO 0x49020000 (irq = 90) is a OMAP UART2 [ 2.921600] console [ttyO2] enabled [ 2.928222] omap_uart.3: ttyO3 at MMIO 0x49042000 (irq = 96) is a OMAP UART3 [ 2.987121] brd: module loaded [ 3.018829] loop: module loaded [ 3.028900] mtdoops: mtd device (mtddev=name/number) must be supplied [ 3.036804] No NAND device found [ 3.040374] No NAND device found [ 3.045074] OneNAND driver initializing [ 3.066711] usbcore: registered new interface driver asix [ 3.073333] usbcore: registered new interface driver cdc_ether [ 3.080474] usbcore: registered new interface driver smsc95xx [ 3.087554] usbcore: registered new interface driver cdc_ncm [ 3.096282] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 3.104125] ------------[ cut here ]------------ [ 3.108978] WARNING: at drivers/clk/clk.c:512 __clk_enable+0x28/0x94() [ 3.115814] Modules linked in: [ 3.119018] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) [ 3.128845] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) [ 3.138946] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606f4>] (__clk_enable+0x28/0x94) [ 3.148315] [<c03606f4>] (__clk_enable+0x28/0x94) from [<c0360780>] (clk_enable+0x20/0x3c) [ 3.156951] [<c0360780>] (clk_enable+0x20/0x3c) from [<c029f2b8>] (usbhs_runtime_resume+0x74/0x90) [ 3.166320] [<c029f2b8>] (usbhs_runtime_resume+0x74/0x90) from [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) [ 3.177062] [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) from [<c02922bc>] (__rpm_callback+0x30/0x58) [ 3.187225] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28) [ 3.196258] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02931d8>] (rpm_resume+0x3b0/0x4cc) [ 3.205078] [<c02931d8>] (rpm_resume+0x3b0/0x4cc) from [<c0293104>] (rpm_resume+0x2dc/0x4cc) [ 3.213897] [<c0293104>] (rpm_resume+0x2dc/0x4cc) from [<c0293558>] (__pm_runtime_resume+0x48/0x60) [ 3.223358] [<c0293558>] (__pm_runtime_resume+0x48/0x60) from [<c030ad1c>] (ehci_hcd_omap_probe+0x194/0x220) [ 3.233642] [<c030ad1c>] (ehci_hcd_omap_probe+0x194/0x220) from [<c028be64>] (platform_drv_probe+0x18/0x1c) [ 3.243835] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8) [ 3.253906] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c) [ 3.263732] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74) [ 3.273193] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218) [ 3.282653] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138) [ 3.292114] [<c028b444>] (driver_register+0xa0/0x138) from [<c0644298>] (ehci_hcd_init+0xac/0x108) [ 3.301483] [<c0644298>] (ehci_hcd_init+0xac/0x108) from [<c0008840>] (do_one_initcall+0x94/0x168) [ 3.310852] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0) [ 3.320037] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24) [ 3.328948] ---[ end trace 0eaa05360b28dfaf ]--- [ 3.333770] ------------[ cut here ]------------ [ 3.338592] WARNING: at drivers/clk/clk.c:512 __clk_enable+0x28/0x94() [ 3.345397] Modules linked in: [ 3.348602] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) [ 3.358428] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) [ 3.368530] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c03606f4>] (__clk_enable+0x28/0x94) [ 3.377899] [<c03606f4>] (__clk_enable+0x28/0x94) from [<c0360780>] (clk_enable+0x20/0x3c) [ 3.386535] [<c0360780>] (clk_enable+0x20/0x3c) from [<c029f2c0>] (usbhs_runtime_resume+0x7c/0x90) [ 3.395904] [<c029f2c0>] (usbhs_runtime_resume+0x7c/0x90) from [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) [ 3.406616] [<c028e8f0>] (pm_generic_runtime_resume+0x2c/0x38) from [<c02922bc>] (__rpm_callback+0x30/0x58) [ 3.416809] [<c02922bc>] (__rpm_callback+0x30/0x58) from [<c02922fc>] (rpm_callback+0x18/0x28) [ 3.425811] [<c02922fc>] (rpm_callback+0x18/0x28) from [<c02931d8>] (rpm_resume+0x3b0/0x4cc) [ 3.434631] [<c02931d8>] (rpm_resume+0x3b0/0x4cc) from [<c0293104>] (rpm_resume+0x2dc/0x4cc) [ 3.443450] [<c0293104>] (rpm_resume+0x2dc/0x4cc) from [<c0293558>] (__pm_runtime_resume+0x48/0x60) [ 3.452911] [<c0293558>] (__pm_runtime_resume+0x48/0x60) from [<c030ad1c>] (ehci_hcd_omap_probe+0x194/0x220) [ 3.463195] [<c030ad1c>] (ehci_hcd_omap_probe+0x194/0x220) from [<c028be64>] (platform_drv_probe+0x18/0x1c) [ 3.473358] [<c028be64>] (platform_drv_probe+0x18/0x1c) from [<c028aca4>] (driver_probe_device+0xb0/0x1e8) [ 3.483459] [<c028aca4>] (driver_probe_device+0xb0/0x1e8) from [<c028ae44>] (__driver_attach+0x68/0x8c) [ 3.493286] [<c028ae44>] (__driver_attach+0x68/0x8c) from [<c0289728>] (bus_for_each_dev+0x44/0x74) [ 3.502716] [<c0289728>] (bus_for_each_dev+0x44/0x74) from [<c0289e10>] (bus_add_driver+0xa0/0x218) [ 3.512176] [<c0289e10>] (bus_add_driver+0xa0/0x218) from [<c028b444>] (driver_register+0xa0/0x138) [ 3.521636] [<c028b444>] (driver_register+0xa0/0x138) from [<c0644298>] (ehci_hcd_init+0xac/0x108) [ 3.531005] [<c0644298>] (ehci_hcd_init+0xac/0x108) from [<c0008840>] (do_one_initcall+0x94/0x168) [ 3.540374] [<c0008840>] (do_one_initcall+0x94/0x168) from [<c0440744>] (kernel_init+0xd8/0x2a0) [ 3.549560] [<c0440744>] (kernel_init+0xd8/0x2a0) from [<c0012a90>] (ret_from_fork+0x14/0x24) [ 3.558441] ---[ end trace 0eaa05360b28dfb0 ]--- [ 3.563446] ehci-omap ehci-omap.0: OMAP-EHCI Host Controller [ 3.573059] ehci-omap ehci-omap.0: new USB bus registered, assigned bus number 1 [ 4.618804] ehci-omap ehci-omap.0: irq 93, io mem 0x48064800 [ 4.634338] ehci-omap ehci-omap.0: USB 2.0 started, EHCI 1.00 [ 4.641845] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 4.649047] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 4.656677] usb usb1: Product: OMAP-EHCI Host Controller [ 4.662292] usb usb1: Manufacturer: Linux 3.7.0-rc2-00295-g2d0135b ehci_hcd [ 4.669647] usb usb1: SerialNumber: ehci-omap.0 [ 4.680297] hub 1-0:1.0: USB hub found [ 4.684539] hub 1-0:1.0: 3 ports detected [ 4.692901] musb-hdrc: version 6.0, ?dma?, otg (peripheral+host) [ 4.719635] input: twl4030_pwrbutton as /devices/platform/omap_i2c.1/i2c-1/1-0049/twl4030_pwrbutton/input/input0 [ 4.733947] twl_rtc twl_rtc: Enabling TWL-RTC [ 4.745208] twl_rtc twl_rtc: rtc core: registered twl_rtc as rtc0 [ 4.753814] i2c /dev entries driver [ 4.764495] omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec [ 4.773651] twl4030_wdt twl4030_wdt: Failed to register misc device [ 4.780364] twl4030_wdt: probe of twl4030_wdt failed with error -16 [ 4.789031] cpu cpu0: opp_init_cpufreq_table: Device OPP not found (-19) [ 4.796478] cpu cpu0: omap_cpu_init: cpu0: failed creating freq table[-19] [ 4.803894] cpuidle: using governor ladder [ 4.808319] cpuidle: using governor menu [ 4.818847] omap_hsmmc omap_hsmmc.0: Failed to get debounce clk [ 4.825256] omap-dma-engine omap-dma-engine: allocating channel for 62 [ 4.832244] omap-dma-engine omap-dma-engine: allocating channel for 61 [ 5.032897] usb 1-2: new high-speed USB device number 2 using ehci-omap [ 5.197692] usb 1-2: New USB device found, idVendor=0424, idProduct=9514 [ 5.204803] usb 1-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 5.224517] hub 1-2:1.0: USB hub found [ 5.230926] hub 1-2:1.0: 5 ports detected [ 5.253845] usbcore: registered new interface driver usbhid [ 5.259826] usbhid: USB HID core driver [ 5.275726] oprofile: using arm/armv7 [ 5.280517] TCP: cubic registered [ 5.284118] Initializing XFRM netlink socket [ 5.288757] NET: Registered protocol family 17 [ 5.293731] NET: Registered protocol family 15 [ 5.299041] Key type dns_resolver registered [ 5.303680] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3 [ 5.328308] omap2_set_init_voltage: unable to find boot up OPP for vdd_mpu_iva [ 5.335998] omap2_set_init_voltage: unable to set vdd_mpu_iva [ 5.359069] mmc0: host does not support reading read-only switch. assuming write-enable. [ 5.371734] mmc0: new high speed SDHC card at address 5ffa [ 5.383026] omap_i2c omap_i2c.2: bus 2 rev1.4.0 at 100 kHz [ 5.389923] mmcblk0: mmc0:5ffa SD04G 3.69 GiB [ 5.396697] ThumbEE CPU extension supported. [ 5.401672] SmartReflex Class3 initialized [ 5.412811] mmcblk0: p1 p2 p3 p4 [ 5.425964] fbcvt: 1024x768@60: CVT Name - .786M3-R [ 5.448333] VDVI: incomplete constraints, leaving on [ 5.453918] VDAC: incomplete constraints, leaving on [ 5.467254] input: gpio-keys as /devices/platform/gpio-keys/input/input1 [ 5.478210] twl_rtc twl_rtc: setting system clock to 2012-10-16 18:17:33 UTC (1350411453) [ 5.487365] omap_vout omap_vout: Buffer Size = 3932160 [ 5.496765] omap_vout omap_vout: : registered and initialized video device 0 [ 5.504364] omap_vout omap_vout: Buffer Size = 3932160 [ 5.512420] omap_vout omap_vout: : registered and initialized video device 1 [ 5.521179] sr_init: No PMIC hook to init smartreflex [ 5.527221] smartreflex smartreflex.0: omap_sr_probe: SmartReflex driver initialized [ 5.536834] smartreflex smartreflex.1: omap_sr_probe: SmartReflex driver initialized [ 5.547363] ------------[ cut here ]------------ [ 5.552246] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 clkdm_clk_disable+0x70/0xd0() [ 5.560943] Modules linked in: [ 5.564178] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) [ 5.574005] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) [ 5.584106] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c0029dfc>] (clkdm_clk_disable+0x70/0xd0) [ 5.593933] [<c0029dfc>] (clkdm_clk_disable+0x70/0xd0) from [<c035fc94>] (clk_disable_unused_subtree+0x74/0x88) [ 5.604461] [<c035fc94>] (clk_disable_unused_subtree+0x74/0x88) from [<c035fc40>] (clk_disable_unused_subtree+0x20/0x88) [ 5.615814] ---[ end trace 0eaa05360b28dfb2 ]--- [ 5.621215] ------------[ cut here ]------------ [ 5.626068] WARNING: at arch/arm/mach-omap2/clockdomain.c:961 clkdm_clk_disable+0x70/0xd0() [ 5.634765] Modules linked in: [ 5.637969] [<c0018ac0>] (unwind_backtrace+0x0/0xec) from [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) [ 5.647796] [<c0033e3c>] (warn_slowpath_common+0x4c/0x64) from [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) [ 5.657897] [<c0033e6c>] (warn_slowpath_null+0x18/0x1c) from [<c0029dfc>] (clkdm_clk_disable+0x70/0xd0) [ 5.667724] [<c0029dfc>] (clkdm_clk_disable+0x70/0xd0) from [<c035fc94>] (clk_disable_unused_subtree+0x74/0x88) [ 5.678253] [<c035fc94>] (clk_disable_unused_subtree+0x74/0x88) from [<c035fc40>] (clk_disable_unused_subtree+0x20/0x88) [ 5.689605] ---[ end trace 0eaa05360b28dfb3 ]--- [ 5.794860] usb 1-2.1: new high-speed USB device number 3 using ehci-omap [ 5.916992] usb 1-2.1: New USB device found, idVendor=0424, idProduct=ec00 [ 5.924255] usb 1-2.1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 5.938629] smsc95xx v1.0.4 [ 6.039916] smsc95xx 1-2.1:1.0 eth0: register 'smsc95xx' at usb-ehci-omap.0-2.1, smsc95xx USB 2.0 Ethernet, ae:b1:2c:0c:25:0d [ 6.134948] usb 1-2.5: new low-speed USB device number 4 using ehci-omap [ 6.276367] usb 1-2.5: New USB device found, idVendor=045e, idProduct=001e [ 6.283660] usb 1-2.5: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 6.291381] usb 1-2.5: Product: Microsoft IntelliMouse�® Explorer [ 6.297790] usb 1-2.5: Manufacturer: Microsoft [ 6.322143] input: Microsoft Microsoft IntelliMouse�® Explorer as /devices/platform/usbhs_omap/ehci-omap.0/usb1/1-2/1-2.5/1-2.5:1.0/input/input2 [ 6.335937] hid-generic 0003:045E:001E.0001: input: USB HID v1.00 Mouse [Microsoft Microsoft IntelliMouse�® Explorer] on usb-ehci-omap.0-2.5/input0 [ 8.332000] smsc95xx 1-2.1:1.0 eth0: link up, 100Mbps, full-duplex, lpa 0xCDE1 ^ permalink raw reply [flat|nested] 67+ messages in thread
end of thread, other threads:[~2012-11-15 0:56 UTC | newest]
Thread overview: 67+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-11-08 1:12 [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette
2012-11-08 1:12 ` [PATCH 01/26] ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap Mike Turquette
2012-11-08 1:12 ` [PATCH 02/26] ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses Mike Turquette
2012-11-12 22:15 ` Paul Walmsley
2012-11-08 1:12 ` [PATCH 03/26] ARM: OMAP4: clock: Convert to common clk Mike Turquette
2012-11-12 22:52 ` Paul Walmsley
2012-11-13 2:17 ` Paul Walmsley
2012-11-08 1:12 ` [PATCH 04/26] ARM: OMAP3: " Mike Turquette
2012-11-08 1:12 ` [PATCH 05/26] ARM: OMAP2: " Mike Turquette
2012-11-12 22:16 ` Paul Walmsley
2012-11-08 1:12 ` [PATCH 06/26] ARM: OMAP2xxx: clock: add APLL rate recalculation functions Mike Turquette
2012-11-08 1:12 ` [PATCH 07/26] ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable autoidle Mike Turquette
2012-11-12 23:00 ` Paul Walmsley
2012-11-08 1:12 ` [PATCH 08/26] ARM: OMAP: clock: Define a function to enable clocks at init Mike Turquette
2012-11-12 23:01 ` Paul Walmsley
2012-11-08 1:12 ` [PATCH 09/26] ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions Mike Turquette
2012-11-08 1:12 ` [PATCH 10/26] ARM: OMAP: clock: Get rid of some clkdm assocations within clks Mike Turquette
2012-11-08 1:12 ` [PATCH 11/26] ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h Mike Turquette
2012-11-08 1:12 ` [PATCH 12/26] ARM: OMAP4: clock: Add 44xx data using common struct clk Mike Turquette
2012-11-13 1:37 ` Paul Walmsley
2012-11-13 2:16 ` Paul Walmsley
2012-11-08 1:12 ` [PATCH 13/26] ARM: AM33XX: clock: add clock data in common clock format Mike Turquette
2012-11-08 1:12 ` [PATCH 16/26] ARM: OMAP: clock: Switch to COMMON clk Mike Turquette
2012-11-08 1:12 ` [PATCH 17/26] ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette
2012-11-08 1:12 ` [PATCH 18/26] ARM: OMAP4: clock: " Mike Turquette
2012-11-08 1:12 ` [PATCH 20/26] ARM: omap3: " Mike Turquette
2012-11-08 1:12 ` [PATCH 22/26] ARM: AM33xx: clock: drop obsolete clock data Mike Turquette
2012-11-08 1:12 ` [PATCH 23/26] ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette
2012-11-08 1:13 ` [PATCH 25/26] ARM: OMAP2+: clock: remove unnecessary declarations Mike Turquette
2012-11-08 1:13 ` [PATCH 26/26] ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts Mike Turquette
2012-11-08 1:31 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Mike Turquette
2012-11-08 1:42 ` Tony Lindgren
2012-11-08 1:54 ` Mike Turquette
2012-11-08 2:50 ` Paul Walmsley
2012-11-08 5:02 ` Rajendra Nayak
2012-11-08 5:19 ` Mike Turquette
2012-11-08 19:20 ` Kevin Hilman
[not found] ` <1352337181-29427-15-git-send-email-mturquette@ti.com>
2012-11-08 18:08 ` [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk Paul Walmsley
2012-11-08 21:52 ` Mike Turquette
2012-11-08 22:01 ` Paul Walmsley
2012-11-09 0:11 ` Paul Walmsley
2012-11-09 0:33 ` Paul Walmsley
2012-11-09 0:49 ` Paul Walmsley
2012-11-09 0:57 ` Mike Turquette
2012-11-08 23:31 ` [PATCH] ARM: OMAP2+: clockdomain: disabling unused clks Mike Turquette
2012-11-09 0:58 ` Paul Walmsley
2012-11-09 1:17 ` Mike Turquette
2012-11-09 19:06 ` Paul Walmsley
2012-11-09 19:08 ` Paul Walmsley
2012-11-09 19:40 ` Mike Turquette
2012-11-09 19:52 ` Paul Walmsley
2012-11-09 20:53 ` Paul Walmsley
2012-11-08 19:04 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Vaibhav Hiremath
2012-11-09 21:12 ` Paul Walmsley
2012-11-09 22:09 ` Tony Lindgren
2012-11-09 22:18 ` Mike Turquette
2012-11-09 23:47 ` Paul Walmsley
2012-11-12 21:50 ` [PATCH] ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections Paul Walmsley
2012-11-12 22:30 ` Mike Turquette
[not found] ` <1352337181-29427-16-git-send-email-mturquette@ti.com>
[not found] ` <alpine.DEB.2.00.1211081532210.20703@utopia.booyaka.com>
2012-11-09 20:32 ` [PATCH 15/26] ARM: omap2: clock: Add 24xx data using common struct clk Paul Walmsley
2012-11-09 21:05 ` Mike Turquette
2012-11-09 21:22 ` Paul Walmsley
2012-11-09 22:21 ` Mike Turquette
2012-11-12 22:13 ` Paul Walmsley
2012-11-13 13:42 ` [PATCH v2 00/26] Move OMAP2+ over to common clk framework Laurent Pinchart
2012-11-13 16:43 ` Mike Turquette
2012-11-15 0:57 ` Laurent Pinchart
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