[PATCH 00/15] OMAP SHAM & AES Crypto Updates

[PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

[This series supersedes the hwmod related patches sent in the
 "crypto: omap-sham updates" and "crypto: omap-aes updates"
 series a few weeks ago.]

This series adds hwmod support for the OMAP SHAM and AES
modules on OMAP2, OMAP3, and OMAP4/AM33XX SoCs.  It also
adds device tree info for those modules.

The patches are based on the latest k.o. kernel, plus:
 - patches from the EDMA dmaengine series submitted by Matt Porter
   "[RFC PATCH v3 00/16] DMA Engine support for AM33XX"
   (https://lkml.org/lkml/2012/10/18/256).
 - some misc patches required by the EDMA patches
 - a hack to fix the compilation error that it currently has

The driver changes that will take advantage of these changes will
be submitted in a different series (and to a different mail list).

A working example is here:

	git@github.com:mgreeraz/linux-mag.git submitted/crypto/hwmod

Mark A. Greer (15):
  ARM: OMAP2xxx: hwmod: Convert SHAM crypto device data to hwmod
  ARM: OMAP2xxx: hwmod: Add DMA support for SHAM module
  ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod
  ARM: OMAP2+: Remove unnecessary message when no SHA IP is present
  ARM: OMAP2+: Only manually add hwmod data when DT not used.
  ARM: AM33XX: Add sha0 crypto clock data
  ARM: AM33XX: hwmod: Update and uncomment SHA0 module data
  ARM: dts: Add SHAM data and documentation for AM33XX
  ARM: OMAP2xxx: hwmod: Convert AES crypto devcie data to hwmod
  ARM: OMAP3xxx: hwmod: Convert AES crypto device data to hwmod
  ARM: OMAP2+: Remove unnecessary message when no AES IP is present
  ARM: OMAP2+: Only manually add hwmod data when DT not used.
  ARM: AM33XX: Add aes0 crypto clock data
  ARM: AM33XX: hwmod: Update and uncomment AES0 module data
  ARM: dts: Add AES data and documentation for AM33XX

 .../devicetree/bindings/crypto/omap-aes.txt        |  37 +++++
 .../devicetree/bindings/crypto/omap-sham.txt       |  35 +++++
 arch/arm/boot/dts/am335x-bone.dts                  |   8 ++
 arch/arm/boot/dts/am335x-evm.dts                   |   8 ++
 arch/arm/boot/dts/am335x-evmsk.dts                 |   8 ++
 arch/arm/boot/dts/am33xx.dtsi                      |  25 ++++
 arch/arm/mach-omap2/cclock2430_data.c              |   4 +-
 arch/arm/mach-omap2/cclock33xx_data.c              |  10 ++
 arch/arm/mach-omap2/cclock3xxx_data.c              |   4 +-
 arch/arm/mach-omap2/devices.c                      | 149 +++------------------
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   2 +
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   2 +
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |  36 +++++
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |  81 +++++++++++
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c         |  92 +++++++++++--
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         | 128 ++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |   4 +
 17 files changed, 488 insertions(+), 145 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/omap-aes.txt
 create mode 100644 Documentation/devicetree/bindings/crypto/omap-sham.txt

-- 
1.7.12

[PATCH 01/15] ARM: OMAP2xxx: hwmod: Convert SHAM crypto device data to hwmod

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Convert the device data for the OMAP2 SHAM crypto IP from
explicit platform_data to hwmod.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/cclock2430_data.c              |  1 +
 arch/arm/mach-omap2/devices.c                      | 32 +++++++------------
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |  1 +
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |  1 +
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c | 18 +++++++++++
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 37 ++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |  2 ++
 7 files changed, 71 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index eda079b..a60c16d 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -1992,6 +1992,7 @@ static struct omap_clk omap2430_clks[] = {
 	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_243X),
 	CLK(NULL,	"des_ick",	&des_ick,	CK_243X),
 	CLK("omap-sham",	"ick",	&sha_ick,	CK_243X),
+	CLK(NULL,	"sha_ick",	&sha_ick,	CK_243X),
 	CLK("omap_rng",	"ick",		&rng_ick,	CK_243X),
 	CLK(NULL,	"rng_ick",	&rng_ick,	CK_243X),
 	CLK("omap-aes",	"ick",	&aes_ick,	CK_243X),
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 5e304d0..9465351 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -466,24 +466,6 @@ static void omap_init_rng(void)
 
 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_sham_resources[] = {
-	{
-		.start	= OMAP24XX_SEC_SHA1MD5_BASE,
-		.end	= OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= 51 + OMAP_INTC_START,
-		.flags	= IORESOURCE_IRQ,
-	}
-};
-static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
-#else
-#define omap2_sham_resources		NULL
-#define omap2_sham_resources_sz		0
-#endif
-
 #ifdef CONFIG_ARCH_OMAP3
 static struct resource omap3_sham_resources[] = {
 	{
@@ -514,16 +496,24 @@ static struct platform_device sham_device = {
 static void omap_init_sham(void)
 {
 	if (cpu_is_omap24xx()) {
-		sham_device.resource = omap2_sham_resources;
-		sham_device.num_resources = omap2_sham_resources_sz;
+		struct omap_hwmod *oh;
+		struct platform_device *pdev;
+
+		oh = omap_hwmod_lookup("sham");
+		if (!oh)
+			return;
+
+		pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL,
+					 0, 0);
+		WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
 	} else if (cpu_is_omap34xx()) {
 		sham_device.resource = omap3_sham_resources;
 		sham_device.num_resources = omap3_sham_resources_sz;
+		platform_device_register(&sham_device);
 	} else {
 		pr_err("%s: platform not supported\n", __func__);
 		return;
 	}
-	platform_device_register(&sham_device);
 }
 #else
 static inline void omap_init_sham(void) { }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b5efe58..b718167 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -605,6 +605,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 	&omap2420_l4_core__mcbsp2,
 	&omap2420_l4_core__msdi1,
 	&omap2xxx_l4_core__rng,
+	&omap2xxx_l4_core__sham,
 	&omap2420_l4_core__hdq1w,
 	&omap2420_l4_wkup__counter_32k,
 	&omap2420_l3__gpmc,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index d2d3840..3c19b08 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -963,6 +963,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 	&omap2430_l4_core__mcbsp5,
 	&omap2430_l4_core__hdq1w,
 	&omap2xxx_l4_core__rng,
+	&omap2xxx_l4_core__sham,
 	&omap2430_l4_wkup__counter_32k,
 	&omap2430_l3__gpmc,
 	NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 47901a5..8a9b67a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -138,6 +138,15 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
 	{ }
 };
 
+struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
+	{
+		.pa_start	= 0x480a4000,
+		.pa_end		= 0x480a4000 + 0x64 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
 /*
  * Common interconnect data
  */
@@ -389,3 +398,12 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
 	.addr		= omap2_rng_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
+
+/* l4 core -> sham interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_sham_hwmod,
+	.clk		= "sha_ick",
+	.addr		= omap2xxx_sham_addrs,
+	.user		= OCP_USER_MPU,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index e596117..e72132d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -864,3 +864,40 @@ struct omap_hwmod omap2xxx_rng_hwmod = {
 	.flags		= HWMOD_INIT_NO_RESET,
 	.class		= &omap2_rng_hwmod_class,
 };
+
+/* SHAM */
+
+static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
+	.rev_offs	= 0x5c,
+	.sysc_offs	= 0x60,
+	.syss_offs	= 0x64,
+	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_sham_class = {
+	.name	= "sham",
+	.sysc	= &omap2_sham_sysc,
+};
+
+struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
+	{ .irq = 51 + OMAP_INTC_START, },
+	{ .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_sham_hwmod = {
+	.name		= "sham",
+	.mpu_irqs	= omap2_sham_mpu_irqs,
+	.main_clk	= "l4_ck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 4,
+			.module_bit = OMAP24XX_EN_SHA_SHIFT,
+			.idlest_reg_id = 4,
+			.idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
+		},
+	},
+	.class		= &omap2xxx_sham_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index cfcce29..928acd5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -78,6 +78,7 @@ extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
 extern struct omap_hwmod omap2xxx_gpmc_hwmod;
 extern struct omap_hwmod omap2xxx_rng_hwmod;
+extern struct omap_hwmod omap2xxx_sham_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -105,6 +106,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
-- 
1.7.12

[PATCH 02/15] ARM: OMAP2xxx: hwmod: Add DMA support for SHAM module

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

The current OMAP2 SHAM support doesn't enable DMA
so add that support so it can use DMA just like OMAP3.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c | 2 +-
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c      | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 8a9b67a..510f584 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -405,5 +405,5 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
 	.slave		= &omap2xxx_sham_hwmod,
 	.clk		= "sha_ick",
 	.addr		= omap2xxx_sham_addrs,
-	.user		= OCP_USER_MPU,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index e72132d..ab3305b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -886,9 +886,15 @@ struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
 	{ .irq = -1 }
 };
 
+struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
+	{ .name = "rx", .dma_req = 13 },
+	{ .dma_req = -1 }
+};
+
 struct omap_hwmod omap2xxx_sham_hwmod = {
 	.name		= "sham",
 	.mpu_irqs	= omap2_sham_mpu_irqs,
+	.sdma_reqs	= omap2_sham_sdma_chs,
 	.main_clk	= "l4_ck",
 	.prcm		= {
 		.omap2 = {
-- 
1.7.12

[PATCH 03/15] ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Convert the device data for the OMAP3 SHAM2 (SHA1/MD5) crypto IP
from explicit platform_data to hwmod.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/cclock3xxx_data.c      |  1 +
 arch/arm/mach-omap2/devices.c              | 41 +------------------
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 66 ++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index bdf3948..34c3371 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3334,6 +3334,7 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
 	CLK("omap-aes",	"ick",	&aes2_ick,	CK_34XX | CK_36XX),
 	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_36XX),
+	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_36XX),
 	CLK(NULL,	"des2_ick",	&des2_ick,	CK_34XX | CK_36XX),
 	CLK("omap_hsmmc.1",	"ick",	&mmchs2_ick,	CK_3XXX),
 	CLK("omap_hsmmc.0",	"ick",	&mmchs1_ick,	CK_3XXX),
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 9465351..a217408 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -464,38 +464,9 @@ static void omap_init_rng(void)
 	WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 
-#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_sham_resources[] = {
-	{
-		.start	= OMAP34XX_SEC_SHA1MD5_BASE,
-		.end	= OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= 49 + OMAP_INTC_START,
-		.flags	= IORESOURCE_IRQ,
-	},
-	{
-		.start	= OMAP34XX_DMA_SHA1MD5_RX,
-		.flags	= IORESOURCE_DMA,
-	}
-};
-static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
-#else
-#define omap3_sham_resources		NULL
-#define omap3_sham_resources_sz		0
-#endif
-
-static struct platform_device sham_device = {
-	.name		= "omap-sham",
-	.id		= -1,
-};
-
-static void omap_init_sham(void)
+static void __init omap_init_sham(void)
 {
-	if (cpu_is_omap24xx()) {
+	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 		struct omap_hwmod *oh;
 		struct platform_device *pdev;
 
@@ -506,18 +477,10 @@ static void omap_init_sham(void)
 		pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL,
 					 0, 0);
 		WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
-	} else if (cpu_is_omap34xx()) {
-		sham_device.resource = omap3_sham_resources;
-		sham_device.num_resources = omap3_sham_resources_sz;
-		platform_device_register(&sham_device);
 	} else {
 		pr_err("%s: platform not supported\n", __func__);
-		return;
 	}
 }
-#else
-static inline void omap_init_sham(void) { }
-#endif
 
 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8bb2628..122b4dc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3540,6 +3540,71 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
+static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
+	.sidle_shift	= 4,
+	.srst_shift	= 1,
+	.autoidle_shift	= 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
+	.rev_offs	= 0x5c,
+	.sysc_offs	= 0x60,
+	.syss_offs	= 0x64,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+	.sysc_fields	= &omap3_sham_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_sham_class = {
+	.name	= "sham",
+	.sysc	= &omap3_sham_sysc,
+};
+
+struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
+	{ .irq = 49 + OMAP_INTC_START, },
+	{ .irq = -1 }
+};
+
+struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
+	{ .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+	{ .dma_req = -1 }
+};
+
+struct omap_hwmod omap3xxx_sham_hwmod = {
+	.name		= "sham",
+	.mpu_irqs	= omap3_sham_mpu_irqs,
+	.sdma_reqs	= omap3_sham_sdma_reqs,
+	.main_clk	= "sha12_ick",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_SHA12_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
+		},
+	},
+	.class		= &omap3xxx_sham_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
+	{
+		.pa_start	= 0x480c3000,
+		.pa_end		= 0x480c3000 + 0x64 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_sham_hwmod,
+	.clk		= "sha12_ick",
+	.addr		= omap3xxx_sham_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 	&omap3xxx_l3_main__l4_core,
 	&omap3xxx_l3_main__l4_per,
@@ -3593,6 +3658,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 /* GP-only hwmod links */
 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
 	&omap3xxx_l4_sec__timer12,
+	&omap3xxx_l4_core__sham,
 	NULL
 };
 
-- 
1.7.12

Re: [PATCH 03/15] ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod

[Paul Walmsley]

Hi Mark,

On Fri, 21 Dec 2012, Mark A. Greer wrote:

> From: "Mark A. Greer" <mgreer@animalcreek.com>
> 
> Convert the device data for the OMAP3 SHAM2 (SHA1/MD5) crypto IP
> from explicit platform_data to hwmod.
> 
> CC: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>

This one has been updated here to split the OMAP3xxx GP hwmod lists, as we 
discussed.  Updated patch follows.

- Paul

From: "Mark A. Greer" <mgreer@animalcreek.com>
Date: Fri, 21 Dec 2012 09:28:03 -0700
Subject: [PATCH] ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to
 hwmod

Convert the device data for the OMAP3 SHAM2 (SHA1/MD5) crypto IP
from explicit platform_data to hwmod.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
[paul@pwsan.com: updated to use per-SoC registration lists for GP-only hwmods;
 fixed lines causing sparse warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/cclock3xxx_data.c      |    1 +
 arch/arm/mach-omap2/devices.c              |   41 +----------
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |  107 +++++++++++++++++++++++++---
 3 files changed, 101 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 6ef8758..2853d72 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3336,6 +3336,7 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
 	CLK("omap-aes",	"ick",	&aes2_ick,	CK_34XX | CK_36XX),
 	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_36XX),
+	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_36XX),
 	CLK(NULL,	"des2_ick",	&des2_ick,	CK_34XX | CK_36XX),
 	CLK("omap_hsmmc.1",	"ick",	&mmchs2_ick,	CK_3XXX),
 	CLK("omap_hsmmc.0",	"ick",	&mmchs1_ick,	CK_3XXX),
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index b3f6818..8afc592 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -464,38 +464,9 @@ static void omap_init_rng(void)
 	WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 
-#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_sham_resources[] = {
-	{
-		.start	= OMAP34XX_SEC_SHA1MD5_BASE,
-		.end	= OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= 49 + OMAP_INTC_START,
-		.flags	= IORESOURCE_IRQ,
-	},
-	{
-		.start	= OMAP34XX_DMA_SHA1MD5_RX,
-		.flags	= IORESOURCE_DMA,
-	}
-};
-static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
-#else
-#define omap3_sham_resources		NULL
-#define omap3_sham_resources_sz		0
-#endif
-
-static struct platform_device sham_device = {
-	.name		= "omap-sham",
-	.id		= -1,
-};
-
-static void omap_init_sham(void)
+static void __init omap_init_sham(void)
 {
-	if (cpu_is_omap24xx()) {
+	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 		struct omap_hwmod *oh;
 		struct platform_device *pdev;
 
@@ -506,18 +477,10 @@ static void omap_init_sham(void)
 		pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL,
 					 0, 0);
 		WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
-	} else if (cpu_is_omap34xx()) {
-		sham_device.resource = omap3_sham_resources;
-		sham_device.num_resources = omap3_sham_resources_sz;
-		platform_device_register(&sham_device);
 	} else {
 		pr_err("%s: platform not supported\n", __func__);
-		return;
 	}
 }
-#else
-static inline void omap_init_sham(void) { }
-#endif
 
 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8bb2628..8f54564 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3540,6 +3540,71 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
+static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
+	.sidle_shift	= 4,
+	.srst_shift	= 1,
+	.autoidle_shift	= 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
+	.rev_offs	= 0x5c,
+	.sysc_offs	= 0x60,
+	.syss_offs	= 0x64,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+	.sysc_fields	= &omap3_sham_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_sham_class = {
+	.name	= "sham",
+	.sysc	= &omap3_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
+	{ .irq = 49 + OMAP_INTC_START, },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
+	{ .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+	{ .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_sham_hwmod = {
+	.name		= "sham",
+	.mpu_irqs	= omap3_sham_mpu_irqs,
+	.sdma_reqs	= omap3_sham_sdma_reqs,
+	.main_clk	= "sha12_ick",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_SHA12_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
+		},
+	},
+	.class		= &omap3xxx_sham_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
+	{
+		.pa_start	= 0x480c3000,
+		.pa_end		= 0x480c3000 + 0x64 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_sham_hwmod,
+	.clk		= "sha12_ick",
+	.addr		= omap3xxx_sham_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 	&omap3xxx_l3_main__l4_core,
 	&omap3xxx_l3_main__l4_per,
@@ -3591,8 +3656,28 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 };
 
 /* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
+static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
+	&omap3xxx_l4_sec__timer12,
+	&omap3xxx_l4_core__sham,
+	NULL
+};
+
+static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
 	&omap3xxx_l4_sec__timer12,
+	&omap3xxx_l4_core__sham,
+	NULL
+};
+
+static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
+	&omap3xxx_l4_sec__timer12,
+	/*
+	 * Apparently the SHA/MD5 accelerator IP block is only present
+	 * on some AM35xx chips, and no one knows which ones.  See
+	 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
+	 * if you need this IP block on an AM35xx, try uncommenting
+	 * the next line.
+	 */
+	/* &omap3xxx_l4_core__sham, */
 	NULL
 };
 
@@ -3699,7 +3784,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
 int __init omap3xxx_hwmod_init(void)
 {
 	int r;
-	struct omap_hwmod_ocp_if **h = NULL;
+	struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
 	unsigned int rev;
 
 	omap_hwmod_init();
@@ -3709,13 +3794,6 @@ int __init omap3xxx_hwmod_init(void)
 	if (r < 0)
 		return r;
 
-	/* Register GP-only hwmod links. */
-	if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
-		r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
-		if (r < 0)
-			return r;
-	}
-
 	rev = omap_rev();
 
 	/*
@@ -3727,11 +3805,14 @@ int __init omap3xxx_hwmod_init(void)
 	    rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
 	    rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
 		h = omap34xx_hwmod_ocp_ifs;
+		h_gp = omap34xx_gp_hwmod_ocp_ifs;
 	} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
 		h = am35xx_hwmod_ocp_ifs;
+		h_gp = am35xx_gp_hwmod_ocp_ifs;
 	} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
 		   rev == OMAP3630_REV_ES1_2) {
 		h = omap36xx_hwmod_ocp_ifs;
+		h_gp = omap36xx_gp_hwmod_ocp_ifs;
 	} else {
 		WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
 		return -EINVAL;
@@ -3741,6 +3822,14 @@ int __init omap3xxx_hwmod_init(void)
 	if (r < 0)
 		return r;
 
+	/* Register GP-only hwmod links. */
+	if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
+		r = omap_hwmod_register_links(h_gp);
+		if (r < 0)
+			return r;
+	}
+
+
 	/*
 	 * Register hwmod links specific to certain ES levels of a
 	 * particular family of silicon (e.g., 34xx ES1.0)
-- 
1.7.10.4

Re: [PATCH 03/15] ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod

[Mark A. Greer]

On Fri, Feb 08, 2013 at 05:42:13PM +0000, Paul Walmsley wrote:
> Hi Mark,
> 
> On Fri, 21 Dec 2012, Mark A. Greer wrote:
> 
> > From: "Mark A. Greer" <mgreer@animalcreek.com>
> > 
> > Convert the device data for the OMAP3 SHAM2 (SHA1/MD5) crypto IP
> > from explicit platform_data to hwmod.
> > 
> > CC: Paul Walmsley <paul@pwsan.com>
> > Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
> 
> This one has been updated here to split the OMAP3xxx GP hwmod lists, as we 
> discussed.  Updated patch follows.

Thanks Paul.

[PATCH 04/15] ARM: OMAP2+: Remove unnecessary message when no SHA IP is present

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Remove the error message that prints when there is no SHA IP
present to make it consistent with all the other IPs.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/devices.c | 19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index a217408..598ab1e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -466,20 +466,15 @@ static void omap_init_rng(void)
 
 static void __init omap_init_sham(void)
 {
-	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-		struct omap_hwmod *oh;
-		struct platform_device *pdev;
+	struct omap_hwmod *oh;
+	struct platform_device *pdev;
 
-		oh = omap_hwmod_lookup("sham");
-		if (!oh)
-			return;
+	oh = omap_hwmod_lookup("sham");
+	if (!oh)
+		return;
 
-		pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL,
-					 0, 0);
-		WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
-	} else {
-		pr_err("%s: platform not supported\n", __func__);
-	}
+	pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL, 0, 0);
+	WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
 }
 
 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
-- 
1.7.12

[PATCH 05/15] ARM: OMAP2+: Only manually add hwmod data when DT not used.

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

The omap_init_sham() routine in devices.c only needs to be
called when there is no device tree present.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/devices.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 598ab1e..c8f878a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -672,10 +672,10 @@ static int __init omap2_init_devices(void)
 		omap_init_dmic();
 		omap_init_mcpdm();
 		omap_init_mcspi();
+		omap_init_sham();
 	}
 	omap_init_sti();
 	omap_init_rng();
-	omap_init_sham();
 	omap_init_aes();
 	omap_init_vout();
 	omap_init_ocp2scp();
-- 
1.7.12

[PATCH 06/15] ARM: AM33XX: Add sha0 crypto clock data

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Add clock data for for the SHA0 crypto module
on the am33xx SoC.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/cclock33xx_data.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ea64ad6..56d6755 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -412,6 +412,10 @@ static struct clk smartreflex1_fck;
 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
 DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
 
+static struct clk sha0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
+DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
+
 /*
  * Modules clock nodes
  *
@@ -876,6 +880,7 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"mmu_fck",		&mmu_fck,	CK_AM33XX),
 	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck,	CK_AM33XX),
 	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck,	CK_AM33XX),
+	CLK(NULL,	"sha0_fck",		&sha0_fck,	CK_AM33XX),
 	CLK(NULL,	"timer1_fck",		&timer1_fck,	CK_AM33XX),
 	CLK(NULL,	"timer2_fck",		&timer2_fck,	CK_AM33XX),
 	CLK(NULL,	"timer3_fck",		&timer3_fck,	CK_AM33XX),
-- 
1.7.12

[PATCH 07/15] ARM: AM33XX: hwmod: Update and uncomment SHA0 module data

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Update the SHA0 HIB2 module's hwmod data for the am33xx SoC.
Also, remove it from the '#if 0' block that its currently
inside so the data is actually available for use.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 43 +++++++++++++++++++++++++-----
 1 file changed, 37 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 081c71e..9f7aadd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -417,7 +417,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  *    - ocmc ram
  *    - ocp watch point
  *    - aes0
- *    - sha0
  */
 #if 0
 /*
@@ -543,22 +542,37 @@ static struct omap_hwmod am33xx_aes0_hwmod = {
 		},
 	},
 };
+#endif
+
+/* sha0 HIB2 (the 'P' (public) device) */
+static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
+	.rev_offs	= 0x100,
+	.sysc_offs	= 0x110,
+	.syss_offs	= 0x114,
+	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+};
 
-/* sha0 */
 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 	.name		= "sha0",
+	.sysc		= &am33xx_sha0_sysc,
 };
 
 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
-	{ .irq = 108 + OMAP_INTC_START, },
+	{ .irq = 109 + OMAP_INTC_START, },
 	{ .irq = -1 },
 };
 
+struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
+	{ .name = "rx", .dma_req = 36, },
+	{ .dma_req = -1 }
+};
+
 static struct omap_hwmod am33xx_sha0_hwmod = {
-	.name		= "sha0",
+	.name		= "sham",
 	.class		= &am33xx_sha0_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
 	.mpu_irqs	= am33xx_sha0_irqs,
+	.sdma_reqs	= am33xx_sha0_edma_reqs,
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -568,8 +582,6 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
 	},
 };
 
-#endif
-
 /* 'smartreflex' class */
 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 	.name		= "smartreflex",
@@ -3328,6 +3340,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
 	.flags		= OCPIF_SWSUP_IDLE,
 };
 
+/* l3 main -> sha0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
+	{
+		.pa_start	= 0x53100000,
+		.pa_end		= 0x53100000 + SZ_512 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
+	.master		= &am33xx_l3_main_hwmod,
+	.slave		= &am33xx_sha0_hwmod,
+	.clk		= "sha0_fck",
+	.addr		= am33xx_sha0_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_fw__emif_fw,
 	&am33xx_l3_main__emif,
@@ -3401,6 +3431,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l3_s__usbss,
 	&am33xx_l4_hs__cpgmac0,
 	&am33xx_cpgmac0__mdio,
+	&am33xx_l3_main__sha0,
 	NULL,
 };
 
-- 
1.7.12

[PATCH 08/15] ARM: dts: Add SHAM data and documentation for AM33XX

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Add the generic AM33XX SHAM module's device tree data and
enable it for the am335x-evm, am335x-evmsk, and am335x-bone
platforms.  Also add Documentation file describing the data
for the SHAM module.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 .../devicetree/bindings/crypto/omap-sham.txt       | 35 ++++++++++++++++++++++
 arch/arm/boot/dts/am335x-bone.dts                  |  4 +++
 arch/arm/boot/dts/am335x-evm.dts                   |  4 +++
 arch/arm/boot/dts/am335x-evmsk.dts                 |  4 +++
 arch/arm/boot/dts/am33xx.dtsi                      | 12 ++++++++
 5 files changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/omap-sham.txt

diff --git a/Documentation/devicetree/bindings/crypto/omap-sham.txt b/Documentation/devicetree/bindings/crypto/omap-sham.txt
new file mode 100644
index 0000000..53839cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/omap-sham.txt
@@ -0,0 +1,35 @@
+OMAP SoC SHA crypto Module
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+  SHAM versions:
+  - "ti,omap2-sham" for OMAP2 & OMAP3.
+  - "ti,omap4-sham" for OMAP4 and AM33XX.
+  Note that these two versions are incompatible.
+- ti,hwmods: Name of the hwmod associated with the SHAM module
+- reg : Offset and length of the register set for the module
+- interrupt-parent : the phandle for the interrupt controller that
+  services interrupts for this module.
+- interrupts : the interrupt number for the SHAM module.
+
+Optional properties:
+- dmas: DMA controller phandle and DMA request ordered pair.
+	Only one rx pair is valid per SHAM module.
+- dma-names: DMA request name. This string corresponds 1:1 with
+	the ordered pair in dmas. The string naming is to be
+	"rx" for RX request.
+
+Example:
+	/* AM335x */
+	sham: sham@53100000 {
+		compatible = "ti,omap4-sham";
+		ti,hwmods = "sham";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x53100000 0x200>;
+		interrupt-parent = <&intc>;
+		interrupts = <109>;
+		dmas = <&edma 36>;
+		dma-names = "rx";
+	};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 9075198..1c35f83 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -192,3 +192,7 @@
 &edma {
 	ti,edma-xbar-event-map = <32 12>;
 };
+
+&sham {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 70ac496..57515cd 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -259,3 +259,7 @@
 		reg = <0>;
 	};
 };
+
+&sham {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..b322919 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,7 @@
 		};
 	};
 };
+
+&sham {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index c02ade7..671135e 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -455,5 +455,17 @@
 				mac-address = [ 00 00 00 00 00 00 ];
 			};
 		};
+
+		sham: sham@53100000 {
+			compatible = "ti,omap4-sham";
+			ti,hwmods = "sham";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x53100000 0x200>;
+			interrupt-parent = <&intc>;
+			interrupts = <109>;
+			dmas = <&edma 36>;
+			dma-names = "rx";
+		};
 	};
 };
-- 
1.7.12

[PATCH 09/15] ARM: OMAP2xxx: hwmod: Convert AES crypto devcie data to hwmod

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Convert the device data for the OMAP2 AES crypto IP from
explicit platform_data to hwmod.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/cclock2430_data.c              |  3 +-
 arch/arm/mach-omap2/devices.c                      | 36 +++++++-------------
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |  1 +
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |  1 +
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c | 18 ++++++++++
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 38 ++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |  2 ++
 7 files changed, 73 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index a60c16d..6f721b2 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -1995,7 +1995,8 @@ static struct omap_clk omap2430_clks[] = {
 	CLK(NULL,	"sha_ick",	&sha_ick,	CK_243X),
 	CLK("omap_rng",	"ick",		&rng_ick,	CK_243X),
 	CLK(NULL,	"rng_ick",	&rng_ick,	CK_243X),
-	CLK("omap-aes",	"ick",	&aes_ick,	CK_243X),
+	CLK("omap-aes",	"ick",		&aes_ick,	CK_243X),
+	CLK(NULL,	"aes_ick",	&aes_ick,	CK_243X),
 	CLK(NULL,	"pka_ick",	&pka_ick,	CK_243X),
 	CLK(NULL,	"usb_fck",	&usb_fck,	CK_243X),
 	CLK("musb-omap2430",	"ick",	&usbhs_ick,	CK_243X),
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c8f878a..2a4a9f3 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -479,28 +479,6 @@ static void __init omap_init_sham(void)
 
 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
 
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_aes_resources[] = {
-	{
-		.start	= OMAP24XX_SEC_AES_BASE,
-		.end	= OMAP24XX_SEC_AES_BASE + 0x4C,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= OMAP24XX_DMA_AES_TX,
-		.flags	= IORESOURCE_DMA,
-	},
-	{
-		.start	= OMAP24XX_DMA_AES_RX,
-		.flags	= IORESOURCE_DMA,
-	}
-};
-static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
-#else
-#define omap2_aes_resources		NULL
-#define omap2_aes_resources_sz		0
-#endif
-
 #ifdef CONFIG_ARCH_OMAP3
 static struct resource omap3_aes_resources[] = {
 	{
@@ -531,16 +509,24 @@ static struct platform_device aes_device = {
 static void omap_init_aes(void)
 {
 	if (cpu_is_omap24xx()) {
-		aes_device.resource = omap2_aes_resources;
-		aes_device.num_resources = omap2_aes_resources_sz;
+		struct omap_hwmod *oh;
+		struct platform_device *pdev;
+
+		oh = omap_hwmod_lookup("aes");
+		if (!oh)
+			return;
+
+		pdev = omap_device_build("omap-aes", -1, oh, NULL, 0, NULL,
+					 0, 0);
+		WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
 	} else if (cpu_is_omap34xx()) {
 		aes_device.resource = omap3_aes_resources;
 		aes_device.num_resources = omap3_aes_resources_sz;
+		platform_device_register(&aes_device);
 	} else {
 		pr_err("%s: platform not supported\n", __func__);
 		return;
 	}
-	platform_device_register(&aes_device);
 }
 
 #else
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b718167..2a73d4b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -606,6 +606,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 	&omap2420_l4_core__msdi1,
 	&omap2xxx_l4_core__rng,
 	&omap2xxx_l4_core__sham,
+	&omap2xxx_l4_core__aes,
 	&omap2420_l4_core__hdq1w,
 	&omap2420_l4_wkup__counter_32k,
 	&omap2420_l3__gpmc,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 3c19b08..4ce999e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -964,6 +964,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 	&omap2430_l4_core__hdq1w,
 	&omap2xxx_l4_core__rng,
 	&omap2xxx_l4_core__sham,
+	&omap2xxx_l4_core__aes,
 	&omap2430_l4_wkup__counter_32k,
 	&omap2430_l3__gpmc,
 	NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 510f584..8d4d53d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -147,6 +147,15 @@ struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
 	{ }
 };
 
+struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
+	{
+		.pa_start	= 0x480a6000,
+		.pa_end		= 0x480a6000 + 0x50 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
 /*
  * Common interconnect data
  */
@@ -407,3 +416,12 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
 	.addr		= omap2xxx_sham_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
+
+/* l4 core -> aes interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_aes_hwmod,
+	.clk		= "aes_ick",
+	.addr		= omap2xxx_aes_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index ab3305b..da5b790 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -907,3 +907,41 @@ struct omap_hwmod omap2xxx_sham_hwmod = {
 	},
 	.class		= &omap2xxx_sham_class,
 };
+
+/* AES */
+
+static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
+	.rev_offs	= 0x44,
+	.sysc_offs	= 0x48,
+	.syss_offs	= 0x4c,
+	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_aes_class = {
+	.name	= "aes",
+	.sysc	= &omap2_aes_sysc,
+};
+
+struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
+	{ .name = "tx", .dma_req = 9 },
+	{ .name = "rx", .dma_req = 10 },
+	{ .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_aes_hwmod = {
+	.name		= "aes",
+	.sdma_reqs	= omap2_aes_sdma_chs,
+	.main_clk	= "l4_ck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 4,
+			.module_bit = OMAP24XX_EN_AES_SHIFT,
+			.idlest_reg_id = 4,
+			.idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
+		},
+	},
+	.class		= &omap2xxx_aes_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 928acd5..6e04ff7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -79,6 +79,7 @@ extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
 extern struct omap_hwmod omap2xxx_gpmc_hwmod;
 extern struct omap_hwmod omap2xxx_rng_hwmod;
 extern struct omap_hwmod omap2xxx_sham_hwmod;
+extern struct omap_hwmod omap2xxx_aes_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -107,6 +108,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
-- 
1.7.12

[PATCH 10/15] ARM: OMAP3xxx: hwmod: Convert AES crypto device data to hwmod

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Convert the device data for the OMAP3 AES crypto IP
from explicit platform_data to hwmod.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/cclock3xxx_data.c      |  3 +-
 arch/arm/mach-omap2/devices.c              | 42 +-------------------
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 62 ++++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+), 41 deletions(-)

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 34c3371..582b055 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3332,7 +3332,8 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK("omap_hsmmc.2",	"ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
 	CLK(NULL,	"mmchs3_ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
 	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
-	CLK("omap-aes",	"ick",	&aes2_ick,	CK_34XX | CK_36XX),
+	CLK("omap-aes",	"ick",		&aes2_ick,	CK_34XX | CK_36XX),
+	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_34XX | CK_36XX),
 	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_36XX),
 	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_36XX),
 	CLK(NULL,	"des2_ick",	&des2_ick,	CK_34XX | CK_36XX),
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2a4a9f3..f5d5c89 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -477,38 +477,9 @@ static void __init omap_init_sham(void)
 	WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
 }
 
-#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_aes_resources[] = {
-	{
-		.start	= OMAP34XX_SEC_AES_BASE,
-		.end	= OMAP34XX_SEC_AES_BASE + 0x4C,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= OMAP34XX_DMA_AES2_TX,
-		.flags	= IORESOURCE_DMA,
-	},
-	{
-		.start	= OMAP34XX_DMA_AES2_RX,
-		.flags	= IORESOURCE_DMA,
-	}
-};
-static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
-#else
-#define omap3_aes_resources		NULL
-#define omap3_aes_resources_sz		0
-#endif
-
-static struct platform_device aes_device = {
-	.name		= "omap-aes",
-	.id		= -1,
-};
-
-static void omap_init_aes(void)
+static void __init omap_init_aes(void)
 {
-	if (cpu_is_omap24xx()) {
+	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 		struct omap_hwmod *oh;
 		struct platform_device *pdev;
 
@@ -519,20 +490,11 @@ static void omap_init_aes(void)
 		pdev = omap_device_build("omap-aes", -1, oh, NULL, 0, NULL,
 					 0, 0);
 		WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
-	} else if (cpu_is_omap34xx()) {
-		aes_device.resource = omap3_aes_resources;
-		aes_device.num_resources = omap3_aes_resources_sz;
-		platform_device_register(&aes_device);
 	} else {
 		pr_err("%s: platform not supported\n", __func__);
-		return;
 	}
 }
 
-#else
-static inline void omap_init_aes(void) { }
-#endif
-
 /*-------------------------------------------------------------------------*/
 
 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 122b4dc..85d1b08 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3605,6 +3605,67 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> AES */
+static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
+	.sidle_shift	= 6,
+	.srst_shift	= 1,
+	.autoidle_shift	= 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
+	.rev_offs	= 0x44,
+	.sysc_offs	= 0x48,
+	.syss_offs	= 0x4c,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap3xxx_aes_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_aes_class = {
+	.name	= "aes",
+	.sysc	= &omap3_aes_sysc,
+};
+
+struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
+	{ .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
+	{ .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
+	{ .dma_req = -1 }
+};
+
+struct omap_hwmod omap3xxx_aes_hwmod = {
+	.name		= "aes",
+	.sdma_reqs	= omap3_aes_sdma_reqs,
+	.main_clk	= "aes2_ick",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_AES2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
+		},
+	},
+	.class		= &omap3xxx_aes_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
+	{
+		.pa_start	= 0x480c5000,
+		.pa_end		= 0x480c5000 + 0x50 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap3xxx_aes_hwmod,
+	.clk		= "aes2_ick",
+	.addr		= omap3xxx_aes_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 	&omap3xxx_l3_main__l4_core,
 	&omap3xxx_l3_main__l4_per,
@@ -3659,6 +3720,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
 	&omap3xxx_l4_sec__timer12,
 	&omap3xxx_l4_core__sham,
+	&omap3xxx_l4_core__aes,
 	NULL
 };
 
-- 
1.7.12

[PATCH 11/15] ARM: OMAP2+: Remove unnecessary message when no AES IP is present

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Remove the error message that prints when there is no AES IP
present to make it consistent with all the other IPs.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/devices.c | 23 +++++++++--------------
 1 file changed, 9 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index f5d5c89..ab8658c 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -479,20 +479,15 @@ static void __init omap_init_sham(void)
 
 static void __init omap_init_aes(void)
 {
-	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-		struct omap_hwmod *oh;
-		struct platform_device *pdev;
-
-		oh = omap_hwmod_lookup("aes");
-		if (!oh)
-			return;
-
-		pdev = omap_device_build("omap-aes", -1, oh, NULL, 0, NULL,
-					 0, 0);
-		WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
-	} else {
-		pr_err("%s: platform not supported\n", __func__);
-	}
+	struct omap_hwmod *oh;
+	struct platform_device *pdev;
+
+	oh = omap_hwmod_lookup("aes");
+	if (!oh)
+		return;
+
+	pdev = omap_device_build("omap-aes", -1, oh, NULL, 0, NULL, 0, 0);
+	WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
 }
 
 /*-------------------------------------------------------------------------*/
-- 
1.7.12

[PATCH 12/15] ARM: OMAP2+: Only manually add hwmod data when DT not used.

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

The omap_init_aes() routine in devices.c only needs to be
called when there is no device tree present.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/devices.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index ab8658c..a261773 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -616,10 +616,10 @@ static int __init omap2_init_devices(void)
 		omap_init_mcpdm();
 		omap_init_mcspi();
 		omap_init_sham();
+		omap_init_aes();
 	}
 	omap_init_sti();
 	omap_init_rng();
-	omap_init_aes();
 	omap_init_vout();
 	omap_init_ocp2scp();
 
-- 
1.7.12

[PATCH 13/15] ARM: AM33XX: Add aes0 crypto clock data

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Add clock data for for the SHA0 crypto module
on the am33xx SoC.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/cclock33xx_data.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 56d6755..ca8e6cb 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -416,6 +416,10 @@ static struct clk sha0_fck;
 DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
 DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
 
+static struct clk aes0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
+DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
+
 /*
  * Modules clock nodes
  *
@@ -881,6 +885,7 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck,	CK_AM33XX),
 	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck,	CK_AM33XX),
 	CLK(NULL,	"sha0_fck",		&sha0_fck,	CK_AM33XX),
+	CLK(NULL,	"aes0_fck",		&aes0_fck,	CK_AM33XX),
 	CLK(NULL,	"timer1_fck",		&timer1_fck,	CK_AM33XX),
 	CLK(NULL,	"timer2_fck",		&timer2_fck,	CK_AM33XX),
 	CLK(NULL,	"timer3_fck",		&timer3_fck,	CK_AM33XX),
-- 
1.7.12

Re: [PATCH 13/15] ARM: AM33XX: Add aes0 crypto clock data

[Peter Korsgaard]

>>>>> "Mark" == Mark A Greer <mgreer@animalcreek.com> writes:

 Mark> From: "Mark A. Greer" <mgreer@animalcreek.com>
 Mark> Add clock data for for the SHA0 crypto module

s/SHA/AES/

Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
 
 Mark> +static struct clk aes0_fck;
 Mark> +DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
 Mark> +DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);

-- 
Bye, Peter Korsgaard

[PATCH 14/15] ARM: AM33XX: hwmod: Update and uncomment AES0 module data

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Update the AES0 HIB2 module's hwmod data for the am33xx SoC.
Also, remove it from the '#if 0' block that its currently
inside so the data is actually available for use.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 51 ++++++++++++++++++++++++------
 1 file changed, 42 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 9f7aadd..ece1162 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -416,7 +416,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  *    - debugss
  *    - ocmc ram
  *    - ocp watch point
- *    - aes0
  */
 #if 0
 /*
@@ -516,25 +515,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = {
 		},
 	},
 };
+#endif
 
 /*
- * 'aes' class
+ * 'aes0' class
  */
-static struct omap_hwmod_class am33xx_aes_hwmod_class = {
-	.name		= "aes",
+static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
+	.rev_offs	= 0x80,
+	.sysc_offs	= 0x84,
+	.syss_offs	= 0x88,
+	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
+	.name		= "aes0",
+	.sysc		= &am33xx_aes0_sysc,
 };
 
 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
-	{ .irq = 102 + OMAP_INTC_START, },
+	{ .irq = 103 + OMAP_INTC_START, },
 	{ .irq = -1 },
 };
 
+struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
+	{ .name = "tx", .dma_req = 6, },
+	{ .name = "rx", .dma_req = 5, },
+	{ .dma_req = -1 }
+};
+
 static struct omap_hwmod am33xx_aes0_hwmod = {
-	.name		= "aes0",
-	.class		= &am33xx_aes_hwmod_class,
+	.name		= "aes",
+	.class		= &am33xx_aes0_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
 	.mpu_irqs	= am33xx_aes0_irqs,
-	.main_clk	= "l3_gclk",
+	.sdma_reqs	= am33xx_aes0_edma_reqs,
+	.main_clk	= "aes0_fck",
 	.prcm		= {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
@@ -542,7 +557,6 @@ static struct omap_hwmod am33xx_aes0_hwmod = {
 		},
 	},
 };
-#endif
 
 /* sha0 HIB2 (the 'P' (public) device) */
 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
@@ -3358,6 +3372,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3 main -> AES0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
+	{
+		.pa_start	= 0x53500000,
+		.pa_end		= 0x53500000 + SZ_1M - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
+	.master		= &am33xx_l3_main_hwmod,
+	.slave		= &am33xx_aes0_hwmod,
+	.clk		= "aes0_fck",
+	.addr		= am33xx_aes0_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_fw__emif_fw,
 	&am33xx_l3_main__emif,
@@ -3432,6 +3464,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_hs__cpgmac0,
 	&am33xx_cpgmac0__mdio,
 	&am33xx_l3_main__sha0,
+	&am33xx_l3_main__aes0,
 	NULL,
 };
 
-- 
1.7.12

[PATCH 15/15] ARM: dts: Add AES data and documentation for AM33XX

[Mark A. Greer]

From: "Mark A. Greer" <mgreer@animalcreek.com>

Add the generic AM33XX AES module's device tree data and
enable it for the am335x-evm, am335x-evmsk, and am335x-bone
platforms.  Also add Documentation file describing the data
for the AES module.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
 .../devicetree/bindings/crypto/omap-aes.txt        | 37 ++++++++++++++++++++++
 arch/arm/boot/dts/am335x-bone.dts                  |  4 +++
 arch/arm/boot/dts/am335x-evm.dts                   |  4 +++
 arch/arm/boot/dts/am335x-evmsk.dts                 |  4 +++
 arch/arm/boot/dts/am33xx.dtsi                      | 13 ++++++++
 5 files changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/omap-aes.txt

diff --git a/Documentation/devicetree/bindings/crypto/omap-aes.txt b/Documentation/devicetree/bindings/crypto/omap-aes.txt
new file mode 100644
index 0000000..6b21256
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/omap-aes.txt
@@ -0,0 +1,37 @@
+OMAP SoC AES crypto Module
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+  AES versions:
+  - "ti,omap2-aes" for OMAP2.
+  - "ti,omap3-aes" for OMAP3.
+  - "ti,omap4-aes" for OMAP4 and AM33XX.
+  Note that the OMAP2 and 3 versions are compatible (OMAP3 supports
+  more algorithms) but they are incompatible with OMAP4.
+- ti,hwmods: Name of the hwmod associated with the AES odule
+- reg : Offset and length of the register set for the module
+- interrupt-parent : the phandle for the interrupt controller that
+  services interrupts for this module.
+- interrupts : the interrupt number for the AES odule.
+
+Optional properties:
+- dmas: DMA controller phandle and DMA request ordered pairs.
+- dma-names: DMA request names. This string corresponds 1:1 with
+	the ordered pairs in dmas. The string naming is to be
+	"tx" for TX request and "rx" for RX request.
+
+Example:
+	/* AM335x */
+	aes: aes@53500000 {
+		compatible = "ti,omap4-aes";
+		ti,hwmods = "aes";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x53500000 0xa0>;
+		interrupt-parent = <&intc>;
+		interrupts = <102>;
+		dmas = <&edma 6
+			&edma 5>;
+		dma-names = "tx", "rx";
+	};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 1c35f83..4ade888 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -196,3 +196,7 @@
 &sham {
 	status = "okay";
 };
+
+&aes {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 57515cd..743635b 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -263,3 +263,7 @@
 &sham {
 	status = "okay";
 };
+
+&aes {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index b322919..1cf8fe1 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -252,3 +252,7 @@
 &sham {
 	status = "okay";
 };
+
+&aes {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 671135e..0aa1a53 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -467,5 +467,18 @@
 			dmas = <&edma 36>;
 			dma-names = "rx";
 		};
+
+		aes: aes@53500000 {
+			compatible = "ti,omap4-aes";
+			ti,hwmods = "aes";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x53500000 0xa0>;
+			interrupt-parent = <&intc>;
+			interrupts = <102>;
+			dmas = <&edma 6
+				&edma 5>;
+			dma-names = "tx", "rx";
+		};
 	};
 };
-- 
1.7.12

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Peter Korsgaard]

>>>>> "Mark" == Mark A Greer <mgreer@animalcreek.com> writes:

 Mark> From: "Mark A. Greer" <mgreer@animalcreek.com>
 Mark> [This series supersedes the hwmod related patches sent in the
 Mark>  "crypto: omap-sham updates" and "crypto: omap-aes updates"
 Mark>  series a few weeks ago.]

 Mark> This series adds hwmod support for the OMAP SHAM and AES
 Mark> modules on OMAP2, OMAP3, and OMAP4/AM33XX SoCs.  It also
 Mark> adds device tree info for those modules.

Huh, does am335x have a sham module? I don't see any mention of that in
spruh73g.pdf

-- 
Bye, Peter Korsgaard

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

On Fri, Dec 21, 2012 at 08:09:25PM +0100, Peter Korsgaard wrote:
> >>>>> "Mark" == Mark A Greer <mgreer@animalcreek.com> writes:
> 
>  Mark> From: "Mark A. Greer" <mgreer@animalcreek.com>
>  Mark> [This series supersedes the hwmod related patches sent in the
>  Mark>  "crypto: omap-sham updates" and "crypto: omap-aes updates"
>  Mark>  series a few weeks ago.]
> 
>  Mark> This series adds hwmod support for the OMAP SHAM and AES
>  Mark> modules on OMAP2, OMAP3, and OMAP4/AM33XX SoCs.  It also
>  Mark> adds device tree info for those modules.
> 
> Huh, does am335x have a sham module? I don't see any mention of that in
> spruh73g.pdf

Yes.  It has sham, aes, and rng modules.

They are not described in the TRM.  In fact, I had to use the omap4
description (closely guarded by TI) because AFAIK there isn't a doc
for the am33xx.  The am33xx modules are identical to the omap4 ones
except for the register addresses and dma channels so that doc worked.

Mark
--

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Peter Korsgaard]

>>>>> "Mark" == Mark A Greer <mgreer@animalcreek.com> writes:

Hi,

 >> Huh, does am335x have a sham module? I don't see any mention of that
 >> in spruh73g.pdf

 Mark> Yes.  It has sham, aes, and rng modules.

Ok, interesting.

 Mark> They are not described in the TRM.  In fact, I had to use the
 Mark> omap4 description (closely guarded by TI) because AFAIK there
 Mark> isn't a doc for the am33xx.  The am33xx modules are identical to
 Mark> the omap4 ones except for the register addresses and dma channels
 Mark> so that doc worked.

Odd. How did you figure out the am335x base address / dma channels?

-- 
Bye, Peter Korsgaard

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

On Sun, Dec 23, 2012 at 05:03:45PM +0100, Peter Korsgaard wrote:
> >>>>> "Mark" == Mark A Greer <mgreer@animalcreek.com> writes:
> 
> Hi,
> 
>  >> Huh, does am335x have a sham module? I don't see any mention of that
>  >> in spruh73g.pdf
> 
>  Mark> Yes.  It has sham, aes, and rng modules.
> 
> Ok, interesting.
> 
>  Mark> They are not described in the TRM.  In fact, I had to use the
>  Mark> omap4 description (closely guarded by TI) because AFAIK there
>  Mark> isn't a doc for the am33xx.  The am33xx modules are identical to
>  Mark> the omap4 ones except for the register addresses and dma channels
>  Mark> so that doc worked.
> 
> Odd. How did you figure out the am335x base address / dma channels?

>From the SDK code.  :)

That is, the am335x evm SDK from TI.  I looked at it to determine the
addresses, etc.

Mark
--

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Paul Walmsley]

Hi Mark,

On Fri, 21 Dec 2012, Mark A. Greer wrote:

> From: "Mark A. Greer" <mgreer@animalcreek.com>
> 
> [This series supersedes the hwmod related patches sent in the
>  "crypto: omap-sham updates" and "crypto: omap-aes updates"
>  series a few weeks ago.]
> 
> This series adds hwmod support for the OMAP SHAM and AES
> modules on OMAP2, OMAP3, and OMAP4/AM33XX SoCs.  It also
> adds device tree info for those modules.

Thanks for working on this, this will get us much closer to being able to 
convert the hwmod code into an OMAP bus.  I haven't looked closely at 
these patches yet, but a few comments/questions:

- Looks like the two DTS patches are the ones with direct dependencies on 
the DMA Engine support patches that you mentioned.  Any objection to me 
taking the series without those two patches?  Then once the DMA Engine 
series goes in, maybe those AM33xx DTS patches can go up?

- The patch series causes AM3517/3505 to crash.  I'd guess this is due to 
the SHAM/AES modules being initialized on those chips, but they probably 
don't exist there.  Can you change the initialization for those on OMAP3 
to only take place on OMAP34xx/36xx GP?  I guess you'd need to create new 
lists for those in the hwmod init.


- Paul

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

On Sun, Dec 23, 2012 at 08:40:43AM +0000, Paul Walmsley wrote:
> Hi Mark,
> 
> On Fri, 21 Dec 2012, Mark A. Greer wrote:
> 
> > From: "Mark A. Greer" <mgreer@animalcreek.com>
> > 
> > [This series supersedes the hwmod related patches sent in the
> >  "crypto: omap-sham updates" and "crypto: omap-aes updates"
> >  series a few weeks ago.]
> > 
> > This series adds hwmod support for the OMAP SHAM and AES
> > modules on OMAP2, OMAP3, and OMAP4/AM33XX SoCs.  It also
> > adds device tree info for those modules.
> 
> Thanks for working on this, this will get us much closer to being able to 
> convert the hwmod code into an OMAP bus.  I haven't looked closely at 
> these patches yet, but a few comments/questions:
> 
> - Looks like the two DTS patches are the ones with direct dependencies on 
> the DMA Engine support patches that you mentioned.

The patch(es) that convert the drivers to use
dma_request_slave_channel_compat() will cause problems too if the
patch that adds that call isn't in your branch.  AFAIK, this is the
latest version, https://patchwork.kernel.org/patch/1459231/ from
Jon Hunter.

> Any objection to me 
> taking the series without those two patches?  Then once the DMA Engine 
> series goes in, maybe those AM33xx DTS patches can go up?

No, no objections at all.  I will track/resubmit/whatever the ones that
need to go in later.

> - The patch series causes AM3517/3505 to crash.  I'd guess this is due to 
> the SHAM/AES modules being initialized on those chips, but they probably 
> don't exist there.  Can you change the initialization for those on OMAP3 
> to only take place on OMAP34xx/36xx GP?  I guess you'd need to create new 
> lists for those in the hwmod init.

Oh.  :(

Sure, I'll do what you suggest when I'm back to work in the new year.

Thanks Paul.

Mark
--

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

On Tue, Dec 25, 2012 at 12:29:37PM -0700, Mark A. Greer wrote:
> On Sun, Dec 23, 2012 at 08:40:43AM +0000, Paul Walmsley wrote:
> > Hi Mark,
> > 
> > On Fri, 21 Dec 2012, Mark A. Greer wrote:
> > 
> > > From: "Mark A. Greer" <mgreer@animalcreek.com>
> > > 
> > > [This series supersedes the hwmod related patches sent in the
> > >  "crypto: omap-sham updates" and "crypto: omap-aes updates"
> > >  series a few weeks ago.]
> > > 
> > > This series adds hwmod support for the OMAP SHAM and AES
> > > modules on OMAP2, OMAP3, and OMAP4/AM33XX SoCs.  It also
> > > adds device tree info for those modules.
> > 
> > Thanks for working on this, this will get us much closer to being able to 
> > convert the hwmod code into an OMAP bus.  I haven't looked closely at 
> > these patches yet, but a few comments/questions:
> > 
> > - Looks like the two DTS patches are the ones with direct dependencies on 
> > the DMA Engine support patches that you mentioned.
> 
> The patch(es) that convert the drivers to use
> dma_request_slave_channel_compat() will cause problems too if the
> patch that adds that call isn't in your branch.  AFAIK, this is the
> latest version, https://patchwork.kernel.org/patch/1459231/ from
> Jon Hunter.

Oops, sorry, please disregard this comment.  I had the wrong patchset
in mind when I wrote it.

Mark
--

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

On Sun, Dec 23, 2012 at 08:40:43AM +0000, Paul Walmsley wrote:
> Hi Mark,

Hi Paul.

> On Fri, 21 Dec 2012, Mark A. Greer wrote:
> 
> > From: "Mark A. Greer" <mgreer@animalcreek.com>
> > 
> > [This series supersedes the hwmod related patches sent in the
> >  "crypto: omap-sham updates" and "crypto: omap-aes updates"
> >  series a few weeks ago.]
> > 
> > This series adds hwmod support for the OMAP SHAM and AES
> > modules on OMAP2, OMAP3, and OMAP4/AM33XX SoCs.  It also
> > adds device tree info for those modules.
> 
> Thanks for working on this, this will get us much closer to being able to 
> convert the hwmod code into an OMAP bus.  I haven't looked closely at 
> these patches yet, but a few comments/questions:

> - The patch series causes AM3517/3505 to crash.  I'd guess this is due to 
> the SHAM/AES modules being initialized on those chips, but they probably 
> don't exist there.  Can you change the initialization for those on OMAP3 
> to only take place on OMAP34xx/36xx GP?  I guess you'd need to create new 
> lists for those in the hwmod init.

All am35xx GPs have the SHAM and AES modules except some very old ones.
I've been told that there should be very few of the "old" ones around
(I don't know how to differentiate them).  We're likely safe since the
SHAM & AES modules are not enabled in omap2plus_defconfig so nobody
should be enabling them on an am35xx unless they know that they have
the modules.  Do you agree?

The issue that you're likely running into is that 'CK_AM35XX' needs to be
added for aes2_ick & sha12_ick in cclock3xxx_data.c.   The following
patch should fix it (applies to my submitted/crypto/hwmod branch):

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 582b055..aa5bdf6 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3332,10 +3332,10 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK("omap_hsmmc.2",	"ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
 	CLK(NULL,	"mmchs3_ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
 	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
-	CLK("omap-aes",	"ick",		&aes2_ick,	CK_34XX | CK_36XX),
-	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_34XX | CK_36XX),
-	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_36XX),
-	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_36XX),
+	CLK("omap-aes",	"ick",		&aes2_ick,	CK_34XX | CK_AM35XX | CK_36XX),
+	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_34XX | CK_AM35XX | CK_36XX),
+	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_AM35XX | CK_36XX),
+	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_AM35XX | CK_36XX),
 	CLK(NULL,	"des2_ick",	&des2_ick,	CK_34XX | CK_36XX),
 	CLK("omap_hsmmc.1",	"ick",	&mmchs2_ick,	CK_3XXX),
 	CLK("omap_hsmmc.0",	"ick",	&mmchs1_ick,	CK_3XXX),


Please let me know if this patch works for you and, if it does, I'll respin
my patches to add those changes.

Thanks,

Mark
--

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 3359 bytes --]

Hi Mark,

I regret the delay,

On Tue, 8 Jan 2013, Mark A. Greer wrote:

> On Sun, Dec 23, 2012 at 08:40:43AM +0000, Paul Walmsley wrote:
>
> > - The patch series causes AM3517/3505 to crash.  I'd guess this is due to 
> > the SHAM/AES modules being initialized on those chips, but they probably 
> > don't exist there.  Can you change the initialization for those on OMAP3 
> > to only take place on OMAP34xx/36xx GP?  I guess you'd need to create new 
> > lists for those in the hwmod init.
> 
> All am35xx GPs have the SHAM and AES modules except some very old ones.
> I've been told that there should be very few of the "old" ones around
> (I don't know how to differentiate them).  We're likely safe since the
> SHAM & AES modules are not enabled in omap2plus_defconfig so nobody
> should be enabling them on an am35xx unless they know that they have
> the modules.  Do you agree?

Those will presumably only enable or disable the device drivers.  The 
hwmod code will probably still try to write to those IP blocks if they are 
listed as present in the hwmod data, during the initial reset-and-idle 
phase.

What do you think about adding an am35xx_es11plus_hwmod_ocp_ifs[] array to 
omap_hwmod_3xxx_data.c for these secure hwmods?  That carries the implicit 
and possibly wrong assumption that it's likely to be ES1.0 devices that 
are missing the SHAM/AES, but it seems unlikely that TI would have 
multiple silicon revs running around claiming to be ES1.1?  Or maybe I'm 
just being naïve.

> The issue that you're likely running into is that 'CK_AM35XX' needs to be
> added for aes2_ick & sha12_ick in cclock3xxx_data.c.   The following
> patch should fix it (applies to my submitted/crypto/hwmod branch):
> 
> diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
> index 582b055..aa5bdf6 100644
> --- a/arch/arm/mach-omap2/cclock3xxx_data.c
> +++ b/arch/arm/mach-omap2/cclock3xxx_data.c
> @@ -3332,10 +3332,10 @@ static struct omap_clk omap3xxx_clks[] = {
>  	CLK("omap_hsmmc.2",	"ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
>  	CLK(NULL,	"mmchs3_ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
>  	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
> -	CLK("omap-aes",	"ick",		&aes2_ick,	CK_34XX | CK_36XX),
> -	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_34XX | CK_36XX),
> -	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_36XX),
> -	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_36XX),
> +	CLK("omap-aes",	"ick",		&aes2_ick,	CK_34XX | CK_AM35XX | CK_36XX),
> +	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_34XX | CK_AM35XX | CK_36XX),
> +	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_AM35XX | CK_36XX),
> +	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_AM35XX | CK_36XX),
>  	CLK(NULL,	"des2_ick",	&des2_ick,	CK_34XX | CK_36XX),
>  	CLK("omap_hsmmc.1",	"ick",	&mmchs2_ick,	CK_3XXX),
>  	CLK("omap_hsmmc.0",	"ick",	&mmchs1_ick,	CK_3XXX),
> 
> 
> Please let me know if this patch works for you and, if it does, I'll respin
> my patches to add those changes.

If those clocks are referenced by the hwmods, that that patch makes sense 
to me.  Haven't had the chance to test it yet but maybe tomorrow.  On the 
other hand it looks 'obviously correct' so maybe just add that change to 
your patches and repost that one?


- Paul

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

On Thu, Jan 17, 2013 at 07:13:36PM +0000, Paul Walmsley wrote:
> Hi Mark,

Hi Paul.

> I regret the delay,
> 
> On Tue, 8 Jan 2013, Mark A. Greer wrote:
> 
> > On Sun, Dec 23, 2012 at 08:40:43AM +0000, Paul Walmsley wrote:
> >
> > > - The patch series causes AM3517/3505 to crash.  I'd guess this is due to 
> > > the SHAM/AES modules being initialized on those chips, but they probably 
> > > don't exist there.  Can you change the initialization for those on OMAP3 
> > > to only take place on OMAP34xx/36xx GP?  I guess you'd need to create new 
> > > lists for those in the hwmod init.
> > 
> > All am35xx GPs have the SHAM and AES modules except some very old ones.
> > I've been told that there should be very few of the "old" ones around
> > (I don't know how to differentiate them).  We're likely safe since the
> > SHAM & AES modules are not enabled in omap2plus_defconfig so nobody
> > should be enabling them on an am35xx unless they know that they have
> > the modules.  Do you agree?
> 
> Those will presumably only enable or disable the device drivers.  The 
> hwmod code will probably still try to write to those IP blocks if they are 
> listed as present in the hwmod data, during the initial reset-and-idle 
> phase.

Um, yeah, good point. :)

> What do you think about adding an am35xx_es11plus_hwmod_ocp_ifs[] array to 
> omap_hwmod_3xxx_data.c for these secure hwmods?  That carries the implicit 
> and possibly wrong assumption that it's likely to be ES1.0 devices that 
> are missing the SHAM/AES, but it seems unlikely that TI would have 
> multiple silicon revs running around claiming to be ES1.1?  Or maybe I'm 
> just being naïve.

Something like that makes sense to me.  I'll re-read my email, etc. and
see if I can find something to help us figure it out.

> > The issue that you're likely running into is that 'CK_AM35XX' needs to be
> > added for aes2_ick & sha12_ick in cclock3xxx_data.c.   The following
> > patch should fix it (applies to my submitted/crypto/hwmod branch):
> > 
> > diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
> > index 582b055..aa5bdf6 100644
> > --- a/arch/arm/mach-omap2/cclock3xxx_data.c
> > +++ b/arch/arm/mach-omap2/cclock3xxx_data.c
> > @@ -3332,10 +3332,10 @@ static struct omap_clk omap3xxx_clks[] = {
> >  	CLK("omap_hsmmc.2",	"ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
> >  	CLK(NULL,	"mmchs3_ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
> >  	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
> > -	CLK("omap-aes",	"ick",		&aes2_ick,	CK_34XX | CK_36XX),
> > -	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_34XX | CK_36XX),
> > -	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_36XX),
> > -	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_36XX),
> > +	CLK("omap-aes",	"ick",		&aes2_ick,	CK_34XX | CK_AM35XX | CK_36XX),
> > +	CLK(NULL,	"aes2_ick",	&aes2_ick,	CK_34XX | CK_AM35XX | CK_36XX),
> > +	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_AM35XX | CK_36XX),
> > +	CLK(NULL,	"sha12_ick",	&sha12_ick,	CK_34XX | CK_AM35XX | CK_36XX),
> >  	CLK(NULL,	"des2_ick",	&des2_ick,	CK_34XX | CK_36XX),
> >  	CLK("omap_hsmmc.1",	"ick",	&mmchs2_ick,	CK_3XXX),
> >  	CLK("omap_hsmmc.0",	"ick",	&mmchs1_ick,	CK_3XXX),
> > 
> > 
> > Please let me know if this patch works for you and, if it does, I'll respin
> > my patches to add those changes.
> 
> If those clocks are referenced by the hwmods, that that patch makes sense 
> to me.  Haven't had the chance to test it yet but maybe tomorrow.  On the 
> other hand it looks 'obviously correct' so maybe just add that change to 
> your patches and repost that one?

Will do.

Mark
--

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

On Thu, Jan 17, 2013 at 03:27:28PM -0700, Mark A. Greer wrote:
> On Thu, Jan 17, 2013 at 07:13:36PM +0000, Paul Walmsley wrote:
> > Hi Mark,
> 
> Hi Paul.

Hi again, Paul.  Sorry for the delay, I've been under the weather.

> > I regret the delay,
> > 
> > On Tue, 8 Jan 2013, Mark A. Greer wrote:
> > 
> > > On Sun, Dec 23, 2012 at 08:40:43AM +0000, Paul Walmsley wrote:

> > What do you think about adding an am35xx_es11plus_hwmod_ocp_ifs[] array to 
> > omap_hwmod_3xxx_data.c for these secure hwmods?  That carries the implicit 
> > and possibly wrong assumption that it's likely to be ES1.0 devices that 
> > are missing the SHAM/AES, but it seems unlikely that TI would have 
> > multiple silicon revs running around claiming to be ES1.1?  Or maybe I'm 
> > just being naïve.
> 
> Something like that makes sense to me.  I'll re-read my email, etc. and
> see if I can find something to help us figure it out.

I couldn't find any information that helped with this so AFAIK there is no
good way to tell if a particular am35xx has the crypto hardware available
or not.  At this point, I vote for moving 'omap3xxx_l4_core__sham' and
'omap3xxx_l4_core__aes' from omap3xxx_gp_hwmod_ocp_ifs[] and putting them
in omap34xx_hwmod_ocp_ifs[] and omap36xx_hwmod_ocp_ifs[].  That should be
safe in general and if someone with an am35xx wants to use those modules,
they can edit am35xx_hwmod_ocp_ifs[] locally.

What do you think?
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Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 2545 bytes --]

Hi Mark

On Mon, 28 Jan 2013, Mark A. Greer wrote:

> On Thu, Jan 17, 2013 at 03:27:28PM -0700, Mark A. Greer wrote:
> > On Thu, Jan 17, 2013 at 07:13:36PM +0000, Paul Walmsley wrote:
> > > On Tue, 8 Jan 2013, Mark A. Greer wrote:
> > > 
> > > > On Sun, Dec 23, 2012 at 08:40:43AM +0000, Paul Walmsley wrote:
> 
> > > What do you think about adding an am35xx_es11plus_hwmod_ocp_ifs[] array to 
> > > omap_hwmod_3xxx_data.c for these secure hwmods?  That carries the implicit 
> > > and possibly wrong assumption that it's likely to be ES1.0 devices that 
> > > are missing the SHAM/AES, but it seems unlikely that TI would have 
> > > multiple silicon revs running around claiming to be ES1.1?  Or maybe I'm 
> > > just being naïve.
> > 
> > Something like that makes sense to me.  I'll re-read my email, etc. and
> > see if I can find something to help us figure it out.
> 
> I couldn't find any information that helped with this so AFAIK there is no
> good way to tell if a particular am35xx has the crypto hardware available
> or not.

I was thinking that we might assume that they are present on AM35xx 
ES1.1+.  If the TI folks are saying that they aren't available on only a 
few early devices, I'd guess that means ES1.0.  I personally have never 
seen an ES1.0 AM35xx device... 

Discriminating between ES1.0 and ES1.1+ should be pretty easy in the hwmod 
init...

>  At this point, I vote for moving 'omap3xxx_l4_core__sham' and
> 'omap3xxx_l4_core__aes' from omap3xxx_gp_hwmod_ocp_ifs[] and putting them
> in omap34xx_hwmod_ocp_ifs[] and omap36xx_hwmod_ocp_ifs[].  

I'm pretty sure that's going to break on HS OMAPs, like the HS OMAP3430 in 
the N900.  I don't think those IP blocks are directly accessible from 
Linux on most HS setups, although this might vary by device.  I'd feel 
more comfortable if you created an omap34xx_gp_hwmod_ocp_ifs[] list and an 
omap36xx_gp_hwmod_ocp_ifs[] list.  We should probably get rid of 
omap3xxx_gp_hwmod_ocp_ifs[] altogether.

> That should be safe in general and if someone with an am35xx wants to 
> use those modules, they can edit am35xx_hwmod_ocp_ifs[] locally.

If you want to just leave them commented in am35xx_hwmod_ocp_ifs[], rather 
than enabling them for ES1.1+ AM35xx, that's fine with me too, since we 
don't know that they are ES-level-based.  Maybe put a comment there that 
says that these are likely to be present, but no one seems to know for 
certain?  Seems ludicrous, but I guess that's what we're reduced to!


- Paul

Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Mark A. Greer]

On Fri, Feb 01, 2013 at 05:35:05PM +0000, Paul Walmsley wrote:
> Hi Mark
> 
> On Mon, 28 Jan 2013, Mark A. Greer wrote:
> 
> > On Thu, Jan 17, 2013 at 03:27:28PM -0700, Mark A. Greer wrote:
> > > On Thu, Jan 17, 2013 at 07:13:36PM +0000, Paul Walmsley wrote:
> > > > On Tue, 8 Jan 2013, Mark A. Greer wrote:
> > > > 
> > > > > On Sun, Dec 23, 2012 at 08:40:43AM +0000, Paul Walmsley wrote:
> > 
> > > > What do you think about adding an am35xx_es11plus_hwmod_ocp_ifs[] array to 
> > > > omap_hwmod_3xxx_data.c for these secure hwmods?  That carries the implicit 
> > > > and possibly wrong assumption that it's likely to be ES1.0 devices that 
> > > > are missing the SHAM/AES, but it seems unlikely that TI would have 
> > > > multiple silicon revs running around claiming to be ES1.1?  Or maybe I'm 
> > > > just being naïve.
> > > 
> > > Something like that makes sense to me.  I'll re-read my email, etc. and
> > > see if I can find something to help us figure it out.
> > 
> > I couldn't find any information that helped with this so AFAIK there is no
> > good way to tell if a particular am35xx has the crypto hardware available
> > or not.
> 
> I was thinking that we might assume that they are present on AM35xx 
> ES1.1+.  If the TI folks are saying that they aren't available on only a 
> few early devices, I'd guess that means ES1.0.  I personally have never 
> seen an ES1.0 AM35xx device... 
> 
> Discriminating between ES1.0 and ES1.1+ should be pretty easy in the hwmod 
> init...
> 
> >  At this point, I vote for moving 'omap3xxx_l4_core__sham' and
> > 'omap3xxx_l4_core__aes' from omap3xxx_gp_hwmod_ocp_ifs[] and putting them
> > in omap34xx_hwmod_ocp_ifs[] and omap36xx_hwmod_ocp_ifs[].  
> 
> I'm pretty sure that's going to break on HS OMAPs, like the HS OMAP3430 in 
> the N900.  I don't think those IP blocks are directly accessible from 
> Linux on most HS setups, although this might vary by device.  I'd feel 
> more comfortable if you created an omap34xx_gp_hwmod_ocp_ifs[] list and an 
> omap36xx_gp_hwmod_ocp_ifs[] list.  We should probably get rid of 
> omap3xxx_gp_hwmod_ocp_ifs[] altogether.
> 
> > That should be safe in general and if someone with an am35xx wants to 
> > use those modules, they can edit am35xx_hwmod_ocp_ifs[] locally.
> 
> If you want to just leave them commented in am35xx_hwmod_ocp_ifs[], rather 
> than enabling them for ES1.1+ AM35xx, that's fine with me too, since we 
> don't know that they are ES-level-based.  Maybe put a comment there that 
> says that these are likely to be present, but no one seems to know for 
> certain?  Seems ludicrous, but I guess that's what we're reduced to!

Thanks Paul.  I will have some patches early next week.

Mark
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Re: [PATCH 00/15] OMAP SHAM & AES Crypto Updates

[Paul Walmsley]

Hi Mark,

just FYI, these patches caused several warnings from sparse:

> arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c:141:30: warning: 
symbol 'omap2xxx_sham_addrs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c:150:30: warning: 
symbol 'omap2xxx_aes_addrs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c:884:28: warning: 
symbol 'omap2_sham_mpu_irqs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c:889:28: warning: 
symbol 'omap2_sham_sdma_chs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c:927:28: warning: 
symbol 'omap2_aes_sdma_chs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c:540:28: warning: symbol 
'am33xx_aes0_edma_reqs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c:579:28: warning: symbol 
'am33xx_sha0_edma_reqs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c:3564:28: warning: symbol 
'omap3_sham_mpu_irqs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c:3569:28: warning: symbol 
'omap3_sham_sdma_reqs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c:3574:19: warning: symbol 
'omap3xxx_sham_hwmod' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c:3630:28: warning: symbol 
'omap3_aes_sdma_reqs' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c:3636:19: warning: symbol 
'omap3xxx_aes_hwmod' was not declared. Should it be static?


I've fixed them up here, but please don't forget to make sure that patches 
don't add any sparse warnings.  sparse info is here:

https://sparse.wiki.kernel.org/index.php/Main_Page

regards,

- Paul