* ARM: dts: omap3: NAND support - how?
@ 2013-04-18 19:03 Christoph Fritz
2013-04-18 19:39 ` Jon Hunter
0 siblings, 1 reply; 19+ messages in thread
From: Christoph Fritz @ 2013-04-18 19:03 UTC (permalink / raw)
To: Javier Martinez Canillas, Jon Hunter, Daniel Mack; +Cc: linux-omap
Hi
I'm trying to setup nand support for an omap3 board for linux-next
(next-20130417). This is my approach so far:
+&gpmc {
+ ranges = <0 0 0x30000000 0x1000000>;
+ nand@0,0 {
+ reg = <0 0 0xff>; /* <- ? not sure about that */
+ nand-bus-width = <16>;
+ ti,nand-ecc-opt = "bch8";
+ /* no elm on omap3 */
+
+ gpmc,time-para-granularity = <0>;
+ gpmc,mux-add-data = <0>;
+ gpmc,device-nand = <1>;
+ gpmc,device-width = <2>;
+ gpmc,wait-pin = <0>;
+ gpmc,wait-on-write = <0>;
+ gpmc,wait-on-read = <0>;
+ gpmc,burst-length= <4>;
+ gpmc,sync-write = <0>;
+ gpmc,burst-write = <0>;
+ gpmc,sync-read = <0>;
+ gpmc,burst-read = <0>;
+ gpmc,burst-wrap = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-extra-delay = <0>;
+ gpmc,cs-rd-off-ns = <0x14>;
+ gpmc,cs-wr-off-ns = <0x14>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-extra-delay = <0>;
+ gpmc,adv-rd-off-ns = <0x14>;
+ gpmc,adv-wr-off-ns = <0x14>;
+ gpmc,oe-on-ns = <0x1>;
+ gpmc,oe-extra-delay = <0>;
+ gpmc,oe-off-ns = <0xF>;
+ gpmc,we-on-ns = <0x1>;
+ gpmc,we-extra-delay = <0>;
+ gpmc,we-off-ns = <0xF>;
+ gpmc,rd-cycle-ns = <0x14>;
+ gpmc,wr-cycle-ns = <0x14>;
+ gpmc,access-ns = <0xC>;
+ gpmc,page-burst-access-ns = <0x1>;
+ gpmc,bus-turnaround-ns = <0x0>;
+ gpmc,cycle2cycle-diffcsen = <0x0>;
+ gpmc,cycle2cycle-samecsen = <0x1>;
+ gpmc,cycle2cycle-delay-ns = <0xA>;
+ gpmc,wr-data-mux-bus-ns = <0xF>;
+ gpmc,wr-access-ns = <0x1F>;
+
+ #address-cells = <1>; /* <- ? not sure about that */
+ #size-cells = <1>; /* <- ? not sure about that */
+ };
+};
+
I took the GPMC NAND config from u-boot where it's working correct.
Without the additional nand approach from above, the board is working
more or less fine. But with this patch I do get the following crash:
[ 1.372467] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 1.380615] Missing elm_id property, fall back to Software BCH
[ 1.389373] enabling NAND BCH ecc with 8-bit correction
[ 1.394927] nand_read_byte16, 166, 0xc8852000
[ 1.403625] Unhandled fault: external abort on non-linefetch (0x1008) at 0xc8852000
[ 1.411651] Internal error: : 1008 [#1] PREEMPT ARM
[ 1.416778] Modules linked in:
[ 1.419982] CPU: 0 Not tainted (3.9.0-rc7-next-20130417-00036-ga693803-dirty #373)
[ 1.428283] PC is at nand_read_byte16+0x30/0x64
[ 1.433044] LR is at nand_read_byte16+0x2c/0x64
[ 1.437774] pc : [<c032f358>] lr : [<c032f354>] psr: 20000113
[ 1.437774] sp : c7057dd8 ip : c7055440 fp : 00000000
[ 1.449798] r10: c7057e4c r9 : c7057e48 r8 : ffffffff
[ 1.455291] r7 : c72ce370 r6 : c72ce370 r5 : c05f9bb8 r4 : c051c270
[ 1.462158] r3 : c7055440 r2 : c8852000 r1 : 00000001 r0 : 00000021
[ 1.468994] Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
[ 1.476623] Control: 10c5387d Table: 80004019 DAC: 00000015
[ 1.482635] Process swapper (pid: 1, stack limit = 0xc7056238)
[ 1.488739] Stack: (0xc7057dd8 to 0xc7058000)
[ 1.493316] 7dc0: c72ce050 000000ff
[ 1.501861] 7de0: ffffffff c033194c 00000000 c72ce370 c72ce050 00000000 c7057e18 c03320bc
[ 1.510437] 7e00: 00000001 00000000 c72c7b80 c72ce000 c72ce050 00000002 00000000 c0c74054
[ 1.519042] 7e20: c72ce370 c72ce050 00000000 00000001 00000002 0000008e c0702a20 c0332674
[ 1.527648] 7e40: c7057e48 00000000 c0637790 00000008 00000000 c72ce000 c72ce050 c700a690
[ 1.536285] 7e60: 00000000 c0c74054 0000008e c0336300 00000000 c72c7f50 c7120ef0 00000000
[ 1.544921] 7e80: 00000000 c0702a20 c0702a28 c0c73628 c072a57c c0702a20 00000000 c072a57c
[ 1.553527] 7ea0: c06d12fc c02ef658 c0c73628 c02ee32c c0702a20 c072a57c c0702a54 00000000
[ 1.562133] 7ec0: c06c709c c02ee4e4 c0702a20 c072a57c c0702a54 c02ee590 c072a57c c02ee4fc
[ 1.570709] 7ee0: c7057ee8 c02ecc5c c704b2a8 c7115690 c704b2d8 c072a57c c0723888 c72ba640
[ 1.579284] 7f00: 00000000 c02ed504 c05fed1c c072a57c c073bd40 c06d12f4 c072a57c c073bd40
[ 1.587890] 7f20: 00000000 c02eeb80 c06d12f4 c06db898 c073bd40 00000000 c06c709c c000874c
[ 1.596496] 7f40: 00000000 c06d12f4 00000006 c073bd40 c06d12f4 c06db898 c073bd40 00000007
[ 1.605072] 7f60: c06aa3e8 c06aa2b0 00000006 00000006 c06aa3e8 00000000 c06db460 c06db460
[ 1.613616] 7f80: 00000000 00000000 00000000 00000000 00000000 c06aa350 00000000 c04eb510
[ 1.622192] 7fa0: 00000000 c04eb518 00000000 c0009ec8 00000000 00000000 00000000 00000000
[ 1.630767] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 1.639312] 7fe0: 00000000 00000000 00000000 00000000 00000013 00000000 10d18100 04440800
[ 1.647888] [<c032f358>] (nand_read_byte16+0x30/0x64) from [<c033194c>] (nand_command+0x174/0x1ec)
[ 1.657287] [<c033194c>] (nand_command+0x174/0x1ec) from [<c03320bc>] (nand_get_flash_type+0x4c/0x5b8)
[ 1.667053] [<c03320bc>] (nand_get_flash_type+0x4c/0x5b8) from [<c0332674>] (nand_scan_ident+0x4c/0x1a8)
[ 1.676971] [<c0332674>] (nand_scan_ident+0x4c/0x1a8) from [<c0336300>] (omap_nand_probe+0x2dc/0x6dc)
[ 1.686614] [<c0336300>] (omap_nand_probe+0x2dc/0x6dc) from [<c02ef658>] (platform_drv_probe+0x18/0x1c)
[ 1.696502] [<c02ef658>] (platform_drv_probe+0x18/0x1c) from [<c02ee32c>] (really_probe+0x70/0x1f8)
[ 1.705963] [<c02ee32c>] (really_probe+0x70/0x1f8) from [<c02ee4e4>] (driver_probe_device+0x30/0x48)
[ 1.715545] [<c02ee4e4>] (driver_probe_device+0x30/0x48) from [<c02ee590>] (__driver_attach+0x94/0x98)
[ 1.725341] [<c02ee590>] (__driver_attach+0x94/0x98) from [<c02ecc5c>] (bus_for_each_dev+0x74/0x98)
[ 1.734832] [<c02ecc5c>] (bus_for_each_dev+0x74/0x98) from [<c02ed504>] (bus_add_driver+0x1c8/0x234)
[ 1.744445] [<c02ed504>] (bus_add_driver+0x1c8/0x234) from [<c02eeb80>] (driver_register+0x78/0x140)
[ 1.754058] [<c02eeb80>] (driver_register+0x78/0x140) from [<c000874c>] (do_one_initcall+0xc0/0x134)
[ 1.763702] [<c000874c>] (do_one_initcall+0xc0/0x134) from [<c06aa2b0>] (do_basic_setup+0x84/0xc4)
[ 1.773132] [<c06aa2b0>] (do_basic_setup+0x84/0xc4) from [<c06aa350>] (kernel_init_freeable+0x60/0xf8)
[ 1.782958] [<c06aa350>] (kernel_init_freeable+0x60/0xf8) from [<c04eb518>] (kernel_init+0x8/0xe4)
[ 1.792419] [<c04eb518>] (kernel_init+0x8/0xe4) from [<c0009ec8>] (ret_from_fork+0x14/0x2c)
[ 1.801239] Code: e3a020a6 e5963000 eb06f2ce e5962000 (e1d230b0)
[ 1.807708] ---[ end trace 8c2fb2c3b59ab3aa ]---
[ 1.812591] ------------[ cut here ]------------
[ 1.817443] Kernel BUG at c0287f84 [verbose debug info unavailable]
[ 1.824035] Internal error: Oops - BUG: 0 [#2] PREEMPT ARM
[ 1.829772] Modules linked in:
[ 1.833007] CPU: 0 Tainted: G D (3.9.0-rc7-next-20130417-00036-ga693803-dirty #373)
[ 1.842285] PC is at omap3_l3_app_irq+0xa4/0x128
[ 1.847137] LR is at handle_irq_event_percpu+0x50/0x1b4
[ 1.852630] pc : [<c0287f84>] lr : [<c0082600>] psr: 20000193
[ 1.852630] sp : c7057bc8 ip : c7057bf8 fp : c073bc1e
[ 1.864624] r10: c70055b8 r9 : 3ccf0000 r8 : 0b6db6c3
[ 1.870117] r7 : 00000000 r6 : 00000000 r5 : 00020000 r4 : 00000000
[ 1.876953] r3 : 00020000 r2 : 00000004 r1 : f8000000 r0 : 00020000
[ 1.883789] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
[ 1.891387] Control: 10c5387d Table: 80004019 DAC: 00000015
[ 1.897399] Process swapper (pid: 1, stack limit = 0xc7056238)
[ 1.903503] Stack: (0xc7057bc8 to 0xc7058000)
[ 1.908081] 7bc0: 00000000 60000193 00000001 c7097a00 c7005590 00000000
[ 1.916656] 7be0: 00000000 0000001a c7005540 c70055b8 c073bc1e c0082600 c7056000 00000000
[ 1.925231] 7c00: 60000193 c7005540 c7005590 c7097a00 c073c814 ffffffff c7057e48 c7057e4c
[ 1.933807] 7c20: 00000000 c00827a0 c7005540 c7005590 00000000 c0084cec 0000001a 0000001a
[ 1.942382] 7c40: 00000000 c00825a0 c071c5c4 c000a69c fa200000 0000001a c7057c78 c0008538
[ 1.950958] 7c60: c04efa78 60000113 ffffffff c7057cac ffffffff c00099c4 00000001 00000001
[ 1.959533] 7c80: c7055440 00000000 c06e803c c7056000 0000000b 00000001 ffffffff c7057e48
[ 1.968078] 7ca0: c7057e4c 00000000 c7057c98 c7057cc0 c04efa70 c04efa78 60000113 ffffffff
[ 1.976684] 7cc0: c7055440 c0034090 60000193 c06e8540 0000000b c7057d90 ffffffff c000d3b0
[ 1.985260] 7ce0: 00001008 c06e8fc4 c8852000 c00084c4 00000000 00000000 00000007 00000000
[ 1.993835] 7d00: 00000000 c8852000 ffffffff c00099e8 00000001 00000001 00000000 c7055440
[ 2.002410] 7d20: 00000000 00000000 00000021 c073d288 00000000 60000113 00000000 00000000
[ 2.010986] 7d40: c7055440 c7057d58 c006af80 c0030cfc 20000113 ffffffff 00000000 00000000
[ 2.019561] 7d60: 00000000 00000000 c073dbba 00000021 20000193 c0708248 00000000 c032f358
[ 2.028137] 7d80: 20000113 ffffffff c7057dc4 c000995c 00000021 00000001 c8852000 c7055440
[ 2.036743] 7da0: c051c270 c05f9bb8 c72ce370 c72ce370 ffffffff c7057e48 c7057e4c 00000000
[ 2.045318] 7dc0: c7055440 c7057dd8 c032f354 c032f358 20000113 ffffffff c72ce050 000000ff
[ 2.053894] 7de0: ffffffff c033194c 00000000 c72ce370 c72ce050 00000000 c7057e18 c03320bc
[ 2.062469] 7e00: 00000001 00000000 c72c7b80 c72ce000 c72ce050 00000002 00000000 c0c74054
[ 2.071044] 7e20: c72ce370 c72ce050 00000000 00000001 00000002 0000008e c0702a20 c0332674
[ 2.079620] 7e40: c7057e48 00000000 c0637790 00000008 00000000 c72ce000 c72ce050 c700a690
[ 2.088195] 7e60: 00000000 c0c74054 0000008e c0336300 00000000 c72c7f50 c7120ef0 00000000
[ 2.096771] 7e80: 00000000 c0702a20 c0702a28 c0c73628 c072a57c c0702a20 00000000 c072a57c
[ 2.105346] 7ea0: c06d12fc c02ef658 c0c73628 c02ee32c c0702a20 c072a57c c0702a54 00000000
[ 2.113952] 7ec0: c06c709c c02ee4e4 c0702a20 c072a57c c0702a54 c02ee590 c072a57c c02ee4fc
[ 2.122528] 7ee0: c7057ee8 c02ecc5c c704b2a8 c7115690 c704b2d8 c072a57c c0723888 c72ba640
[ 2.131103] 7f00: 00000000 c02ed504 c05fed1c c072a57c c073bd40 c06d12f4 c072a57c c073bd40
[ 2.139709] 7f20: 00000000 c02eeb80 c06d12f4 c06db898 c073bd40 00000000 c06c709c c000874c
[ 2.148254] 7f40: 00000000 c06d12f4 00000006 c073bd40 c06d12f4 c06db898 c073bd40 00000007
[ 2.156829] 7f60: c06aa3e8 c06aa2b0 00000006 00000006 c06aa3e8 00000000 c06db460 c06db460
[ 2.165405] 7f80: 00000000 00000000 00000000 00000000 00000000 c06aa350 00000000 c04eb510
[ 2.173980] 7fa0: 00000000 c04eb518 00000000 c0009ec8 00000000 00000000 00000000 00000000
[ 2.182525] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 2.191101] 7fe0: 00000000 00000000 00000000 00000000 00000013 00000000 10d18100 04440800
[ 2.199676] [<c0287f84>] (omap3_l3_app_irq+0xa4/0x128) from [<c0082600>] (handle_irq_event_percpu+0x50/0x1b4)
[ 2.210083] [<c0082600>] (handle_irq_event_percpu+0x50/0x1b4) from [<c00827a0>] (handle_irq_event+0x3c/0x5c)
[ 2.220428] [<c00827a0>] (handle_irq_event+0x3c/0x5c) from [<c0084cec>] (handle_level_irq+0x8c/0x118)
[ 2.230102] [<c0084cec>] (handle_level_irq+0x8c/0x118) from [<c00825a0>] (generic_handle_irq+0x28/0x30)
[ 2.239959] [<c00825a0>] (generic_handle_irq+0x28/0x30) from [<c000a69c>] (handle_IRQ+0x30/0x84)
[ 2.249176] [<c000a69c>] (handle_IRQ+0x30/0x84) from [<c0008538>] (omap3_intc_handle_irq+0x64/0x74)
[ 2.258636] [<c0008538>] (omap3_intc_handle_irq+0x64/0x74) from [<c00099c4>] (__irq_svc+0x44/0x78)
[ 2.268005] Exception stack(0xc7057c78 to 0xc7057cc0)
[ 2.273315] 7c60: 00000001 00000001
[ 2.281890] 7c80: c7055440 00000000 c06e803c c7056000 0000000b 00000001 ffffffff c7057e48
[ 2.290466] 7ca0: c7057e4c 00000000 c7057c98 c7057cc0 c04efa70 c04efa78 60000113 ffffffff
[ 2.299041] [<c00099c4>] (__irq_svc+0x44/0x78) from [<c04efa78>] (_raw_spin_unlock_irq+0x2c/0x50)
[ 2.308349] [<c04efa78>] (_raw_spin_unlock_irq+0x2c/0x50) from [<c0034090>] (do_exit+0x268/0x358)
[ 2.317687] [<c0034090>] (do_exit+0x268/0x358) from [<c000d3b0>] (oops_end+0xb8/0xe8)
[ 2.325897] [<c000d3b0>] (oops_end+0xb8/0xe8) from [<c00084c4>] (do_DataAbort+0x88/0x98)
[ 2.334381] [<c00084c4>] (do_DataAbort+0x88/0x98) from [<c000995c>] (__dabt_svc+0x3c/0x60)
[ 2.343048] Exception stack(0xc7057d90 to 0xc7057dd8)
[ 2.348358] 7d80: 00000021 00000001 c8852000 c7055440
[ 2.356964] 7da0: c051c270 c05f9bb8 c72ce370 c72ce370 ffffffff c7057e48 c7057e4c 00000000
[ 2.365539] 7dc0: c7055440 c7057dd8 c032f354 c032f358 20000113 ffffffff
[ 2.372497] [<c000995c>] (__dabt_svc+0x3c/0x60) from [<c032f358>] (nand_read_byte16+0x30/0x64)
[ 2.381530] [<c032f358>] (nand_read_byte16+0x30/0x64) from [<c033194c>] (nand_command+0x174/0x1ec)
[ 2.390960] [<c033194c>] (nand_command+0x174/0x1ec) from [<c03320bc>] (nand_get_flash_type+0x4c/0x5b8)
[ 2.400756] [<c03320bc>] (nand_get_flash_type+0x4c/0x5b8) from [<c0332674>] (nand_scan_ident+0x4c/0x1a8)
[ 2.410736] [<c0332674>] (nand_scan_ident+0x4c/0x1a8) from [<c0336300>] (omap_nand_probe+0x2dc/0x6dc)
[ 2.420440] [<c0336300>] (omap_nand_probe+0x2dc/0x6dc) from [<c02ef658>] (platform_drv_probe+0x18/0x1c)
[ 2.430297] [<c02ef658>] (platform_drv_probe+0x18/0x1c) from [<c02ee32c>] (really_probe+0x70/0x1f8)
[ 2.439819] [<c02ee32c>] (really_probe+0x70/0x1f8) from [<c02ee4e4>] (driver_probe_device+0x30/0x48)
[ 2.449401] [<c02ee4e4>] (driver_probe_device+0x30/0x48) from [<c02ee590>] (__driver_attach+0x94/0x98)
[ 2.459167] [<c02ee590>] (__driver_attach+0x94/0x98) from [<c02ecc5c>] (bus_for_each_dev+0x74/0x98)
[ 2.468658] [<c02ecc5c>] (bus_for_each_dev+0x74/0x98) from [<c02ed504>] (bus_add_driver+0x1c8/0x234)
[ 2.478271] [<c02ed504>] (bus_add_driver+0x1c8/0x234) from [<c02eeb80>] (driver_register+0x78/0x140)
[ 2.487854] [<c02eeb80>] (driver_register+0x78/0x140) from [<c000874c>] (do_one_initcall+0xc0/0x134)
[ 2.497436] [<c000874c>] (do_one_initcall+0xc0/0x134) from [<c06aa2b0>] (do_basic_setup+0x84/0xc4)
[ 2.506835] [<c06aa2b0>] (do_basic_setup+0x84/0xc4) from [<c06aa350>] (kernel_init_freeable+0x60/0xf8)
[ 2.516601] [<c06aa350>] (kernel_init_freeable+0x60/0xf8) from [<c04eb518>] (kernel_init+0x8/0xe4)
[ 2.526031] [<c04eb518>] (kernel_init+0x8/0xe4) from [<c0009ec8>] (ret_from_fork+0x14/0x2c)
[ 2.534759] Code: e5911008 e2813e53 e1c320d0 eaffffe8 (e7f001f2)
[ 2.541168] ---[ end trace 8c2fb2c3b59ab3ab ]---
[ 2.545989] Kernel panic - not syncing: Fatal exception in interrupt
Any hints?
-- Christoph
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: ARM: dts: omap3: NAND support - how? 2013-04-18 19:03 ARM: dts: omap3: NAND support - how? Christoph Fritz @ 2013-04-18 19:39 ` Jon Hunter 2013-04-18 20:23 ` Christoph Fritz 0 siblings, 1 reply; 19+ messages in thread From: Jon Hunter @ 2013-04-18 19:39 UTC (permalink / raw) To: Christoph Fritz; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On 04/18/2013 02:03 PM, Christoph Fritz wrote: > Hi > > I'm trying to setup nand support for an omap3 board for linux-next > (next-20130417). This is my approach so far: > > > +&gpmc { > + ranges = <0 0 0x30000000 0x1000000>; > + nand@0,0 { > + reg = <0 0 0xff>; /* <- ? not sure about that */ I had put the complete size in here so ... + reg = <0 0 0x1000000>; > + nand-bus-width = <16>; > + ti,nand-ecc-opt = "bch8"; > + /* no elm on omap3 */ > + > + gpmc,time-para-granularity = <0>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,mux-add-data = <0>; This should be either 1 or 2. > + gpmc,device-nand = <1>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,device-width = <2>; > + gpmc,wait-pin = <0>; > + gpmc,wait-on-write = <0>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,wait-on-read = <0>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,burst-length= <4>; > + gpmc,sync-write = <0>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,burst-write = <0>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,sync-read = <0>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,burst-read = <0>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,burst-wrap = <0>; This is a boolean parameter so you don't need the "= <0>". > + gpmc,cs-on-ns = <0>; > + gpmc,cs-extra-delay = <0>; > + gpmc,cs-rd-off-ns = <0x14>; > + gpmc,cs-wr-off-ns = <0x14>; > + gpmc,adv-on-ns = <0>; > + gpmc,adv-extra-delay = <0>; > + gpmc,adv-rd-off-ns = <0x14>; > + gpmc,adv-wr-off-ns = <0x14>; > + gpmc,oe-on-ns = <0x1>; > + gpmc,oe-extra-delay = <0>; > + gpmc,oe-off-ns = <0xF>; > + gpmc,we-on-ns = <0x1>; > + gpmc,we-extra-delay = <0>; > + gpmc,we-off-ns = <0xF>; > + gpmc,rd-cycle-ns = <0x14>; > + gpmc,wr-cycle-ns = <0x14>; > + gpmc,access-ns = <0xC>; > + gpmc,page-burst-access-ns = <0x1>; > + gpmc,bus-turnaround-ns = <0x0>; > + gpmc,cycle2cycle-diffcsen = <0x0>; > + gpmc,cycle2cycle-samecsen = <0x1>; > + gpmc,cycle2cycle-delay-ns = <0xA>; > + gpmc,wr-data-mux-bus-ns = <0xF>; > + gpmc,wr-access-ns = <0x1F>; > + > + #address-cells = <1>; /* <- ? not sure about that */ > + #size-cells = <1>; /* <- ? not sure about that */ This is just needed in case you wish to list partition info. Seeing as you don't you can omit. > + }; > +}; > + > > I took the GPMC NAND config from u-boot where it's working correct. > Without the additional nand approach from above, the board is working > more or less fine. But with this patch I do get the following crash: > > [ 1.372467] mtdoops: mtd device (mtddev=name/number) must be supplied > [ 1.380615] Missing elm_id property, fall back to Software BCH > [ 1.389373] enabling NAND BCH ecc with 8-bit correction > [ 1.394927] nand_read_byte16, 166, 0xc8852000 > [ 1.403625] Unhandled fault: external abort on non-linefetch (0x1008) at 0xc8852000 > [ 1.411651] Internal error: : 1008 [#1] PREEMPT ARM > [ 1.416778] Modules linked in: > [ 1.419982] CPU: 0 Not tainted (3.9.0-rc7-next-20130417-00036-ga693803-dirty #373) > [ 1.428283] PC is at nand_read_byte16+0x30/0x64 > [ 1.433044] LR is at nand_read_byte16+0x2c/0x64 > [ 1.437774] pc : [<c032f358>] lr : [<c032f354>] psr: 20000113 > [ 1.437774] sp : c7057dd8 ip : c7055440 fp : 00000000 > [ 1.449798] r10: c7057e4c r9 : c7057e48 r8 : ffffffff > [ 1.455291] r7 : c72ce370 r6 : c72ce370 r5 : c05f9bb8 r4 : c051c270 > [ 1.462158] r3 : c7055440 r2 : c8852000 r1 : 00000001 r0 : 00000021 > [ 1.468994] Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel > [ 1.476623] Control: 10c5387d Table: 80004019 DAC: 00000015 > [ 1.482635] Process swapper (pid: 1, stack limit = 0xc7056238) > [ 1.488739] Stack: (0xc7057dd8 to 0xc7058000) > [ 1.493316] 7dc0: c72ce050 000000ff > [ 1.501861] 7de0: ffffffff c033194c 00000000 c72ce370 c72ce050 00000000 c7057e18 c03320bc > [ 1.510437] 7e00: 00000001 00000000 c72c7b80 c72ce000 c72ce050 00000002 00000000 c0c74054 > [ 1.519042] 7e20: c72ce370 c72ce050 00000000 00000001 00000002 0000008e c0702a20 c0332674 > [ 1.527648] 7e40: c7057e48 00000000 c0637790 00000008 00000000 c72ce000 c72ce050 c700a690 > [ 1.536285] 7e60: 00000000 c0c74054 0000008e c0336300 00000000 c72c7f50 c7120ef0 00000000 > [ 1.544921] 7e80: 00000000 c0702a20 c0702a28 c0c73628 c072a57c c0702a20 00000000 c072a57c > [ 1.553527] 7ea0: c06d12fc c02ef658 c0c73628 c02ee32c c0702a20 c072a57c c0702a54 00000000 > [ 1.562133] 7ec0: c06c709c c02ee4e4 c0702a20 c072a57c c0702a54 c02ee590 c072a57c c02ee4fc > [ 1.570709] 7ee0: c7057ee8 c02ecc5c c704b2a8 c7115690 c704b2d8 c072a57c c0723888 c72ba640 > [ 1.579284] 7f00: 00000000 c02ed504 c05fed1c c072a57c c073bd40 c06d12f4 c072a57c c073bd40 > [ 1.587890] 7f20: 00000000 c02eeb80 c06d12f4 c06db898 c073bd40 00000000 c06c709c c000874c > [ 1.596496] 7f40: 00000000 c06d12f4 00000006 c073bd40 c06d12f4 c06db898 c073bd40 00000007 > [ 1.605072] 7f60: c06aa3e8 c06aa2b0 00000006 00000006 c06aa3e8 00000000 c06db460 c06db460 > [ 1.613616] 7f80: 00000000 00000000 00000000 00000000 00000000 c06aa350 00000000 c04eb510 > [ 1.622192] 7fa0: 00000000 c04eb518 00000000 c0009ec8 00000000 00000000 00000000 00000000 > [ 1.630767] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > [ 1.639312] 7fe0: 00000000 00000000 00000000 00000000 00000013 00000000 10d18100 04440800 > [ 1.647888] [<c032f358>] (nand_read_byte16+0x30/0x64) from [<c033194c>] (nand_command+0x174/0x1ec) > [ 1.657287] [<c033194c>] (nand_command+0x174/0x1ec) from [<c03320bc>] (nand_get_flash_type+0x4c/0x5b8) > [ 1.667053] [<c03320bc>] (nand_get_flash_type+0x4c/0x5b8) from [<c0332674>] (nand_scan_ident+0x4c/0x1a8) > [ 1.676971] [<c0332674>] (nand_scan_ident+0x4c/0x1a8) from [<c0336300>] (omap_nand_probe+0x2dc/0x6dc) > [ 1.686614] [<c0336300>] (omap_nand_probe+0x2dc/0x6dc) from [<c02ef658>] (platform_drv_probe+0x18/0x1c) > [ 1.696502] [<c02ef658>] (platform_drv_probe+0x18/0x1c) from [<c02ee32c>] (really_probe+0x70/0x1f8) > [ 1.705963] [<c02ee32c>] (really_probe+0x70/0x1f8) from [<c02ee4e4>] (driver_probe_device+0x30/0x48) > [ 1.715545] [<c02ee4e4>] (driver_probe_device+0x30/0x48) from [<c02ee590>] (__driver_attach+0x94/0x98) > [ 1.725341] [<c02ee590>] (__driver_attach+0x94/0x98) from [<c02ecc5c>] (bus_for_each_dev+0x74/0x98) > [ 1.734832] [<c02ecc5c>] (bus_for_each_dev+0x74/0x98) from [<c02ed504>] (bus_add_driver+0x1c8/0x234) > [ 1.744445] [<c02ed504>] (bus_add_driver+0x1c8/0x234) from [<c02eeb80>] (driver_register+0x78/0x140) > [ 1.754058] [<c02eeb80>] (driver_register+0x78/0x140) from [<c000874c>] (do_one_initcall+0xc0/0x134) > [ 1.763702] [<c000874c>] (do_one_initcall+0xc0/0x134) from [<c06aa2b0>] (do_basic_setup+0x84/0xc4) > [ 1.773132] [<c06aa2b0>] (do_basic_setup+0x84/0xc4) from [<c06aa350>] (kernel_init_freeable+0x60/0xf8) > [ 1.782958] [<c06aa350>] (kernel_init_freeable+0x60/0xf8) from [<c04eb518>] (kernel_init+0x8/0xe4) > [ 1.792419] [<c04eb518>] (kernel_init+0x8/0xe4) from [<c0009ec8>] (ret_from_fork+0x14/0x2c) > [ 1.801239] Code: e3a020a6 e5963000 eb06f2ce e5962000 (e1d230b0) > [ 1.807708] ---[ end trace 8c2fb2c3b59ab3aa ]--- > [ 1.812591] ------------[ cut here ]------------ > [ 1.817443] Kernel BUG at c0287f84 [verbose debug info unavailable] > [ 1.824035] Internal error: Oops - BUG: 0 [#2] PREEMPT ARM > [ 1.829772] Modules linked in: > [ 1.833007] CPU: 0 Tainted: G D (3.9.0-rc7-next-20130417-00036-ga693803-dirty #373) > [ 1.842285] PC is at omap3_l3_app_irq+0xa4/0x128 > [ 1.847137] LR is at handle_irq_event_percpu+0x50/0x1b4 > [ 1.852630] pc : [<c0287f84>] lr : [<c0082600>] psr: 20000193 > [ 1.852630] sp : c7057bc8 ip : c7057bf8 fp : c073bc1e > [ 1.864624] r10: c70055b8 r9 : 3ccf0000 r8 : 0b6db6c3 > [ 1.870117] r7 : 00000000 r6 : 00000000 r5 : 00020000 r4 : 00000000 > [ 1.876953] r3 : 00020000 r2 : 00000004 r1 : f8000000 r0 : 00020000 > [ 1.883789] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user > [ 1.891387] Control: 10c5387d Table: 80004019 DAC: 00000015 > [ 1.897399] Process swapper (pid: 1, stack limit = 0xc7056238) > [ 1.903503] Stack: (0xc7057bc8 to 0xc7058000) > [ 1.908081] 7bc0: 00000000 60000193 00000001 c7097a00 c7005590 00000000 > [ 1.916656] 7be0: 00000000 0000001a c7005540 c70055b8 c073bc1e c0082600 c7056000 00000000 > [ 1.925231] 7c00: 60000193 c7005540 c7005590 c7097a00 c073c814 ffffffff c7057e48 c7057e4c > [ 1.933807] 7c20: 00000000 c00827a0 c7005540 c7005590 00000000 c0084cec 0000001a 0000001a > [ 1.942382] 7c40: 00000000 c00825a0 c071c5c4 c000a69c fa200000 0000001a c7057c78 c0008538 > [ 1.950958] 7c60: c04efa78 60000113 ffffffff c7057cac ffffffff c00099c4 00000001 00000001 > [ 1.959533] 7c80: c7055440 00000000 c06e803c c7056000 0000000b 00000001 ffffffff c7057e48 > [ 1.968078] 7ca0: c7057e4c 00000000 c7057c98 c7057cc0 c04efa70 c04efa78 60000113 ffffffff > [ 1.976684] 7cc0: c7055440 c0034090 60000193 c06e8540 0000000b c7057d90 ffffffff c000d3b0 > [ 1.985260] 7ce0: 00001008 c06e8fc4 c8852000 c00084c4 00000000 00000000 00000007 00000000 > [ 1.993835] 7d00: 00000000 c8852000 ffffffff c00099e8 00000001 00000001 00000000 c7055440 > [ 2.002410] 7d20: 00000000 00000000 00000021 c073d288 00000000 60000113 00000000 00000000 > [ 2.010986] 7d40: c7055440 c7057d58 c006af80 c0030cfc 20000113 ffffffff 00000000 00000000 > [ 2.019561] 7d60: 00000000 00000000 c073dbba 00000021 20000193 c0708248 00000000 c032f358 > [ 2.028137] 7d80: 20000113 ffffffff c7057dc4 c000995c 00000021 00000001 c8852000 c7055440 > [ 2.036743] 7da0: c051c270 c05f9bb8 c72ce370 c72ce370 ffffffff c7057e48 c7057e4c 00000000 > [ 2.045318] 7dc0: c7055440 c7057dd8 c032f354 c032f358 20000113 ffffffff c72ce050 000000ff > [ 2.053894] 7de0: ffffffff c033194c 00000000 c72ce370 c72ce050 00000000 c7057e18 c03320bc > [ 2.062469] 7e00: 00000001 00000000 c72c7b80 c72ce000 c72ce050 00000002 00000000 c0c74054 > [ 2.071044] 7e20: c72ce370 c72ce050 00000000 00000001 00000002 0000008e c0702a20 c0332674 > [ 2.079620] 7e40: c7057e48 00000000 c0637790 00000008 00000000 c72ce000 c72ce050 c700a690 > [ 2.088195] 7e60: 00000000 c0c74054 0000008e c0336300 00000000 c72c7f50 c7120ef0 00000000 > [ 2.096771] 7e80: 00000000 c0702a20 c0702a28 c0c73628 c072a57c c0702a20 00000000 c072a57c > [ 2.105346] 7ea0: c06d12fc c02ef658 c0c73628 c02ee32c c0702a20 c072a57c c0702a54 00000000 > [ 2.113952] 7ec0: c06c709c c02ee4e4 c0702a20 c072a57c c0702a54 c02ee590 c072a57c c02ee4fc > [ 2.122528] 7ee0: c7057ee8 c02ecc5c c704b2a8 c7115690 c704b2d8 c072a57c c0723888 c72ba640 > [ 2.131103] 7f00: 00000000 c02ed504 c05fed1c c072a57c c073bd40 c06d12f4 c072a57c c073bd40 > [ 2.139709] 7f20: 00000000 c02eeb80 c06d12f4 c06db898 c073bd40 00000000 c06c709c c000874c > [ 2.148254] 7f40: 00000000 c06d12f4 00000006 c073bd40 c06d12f4 c06db898 c073bd40 00000007 > [ 2.156829] 7f60: c06aa3e8 c06aa2b0 00000006 00000006 c06aa3e8 00000000 c06db460 c06db460 > [ 2.165405] 7f80: 00000000 00000000 00000000 00000000 00000000 c06aa350 00000000 c04eb510 > [ 2.173980] 7fa0: 00000000 c04eb518 00000000 c0009ec8 00000000 00000000 00000000 00000000 > [ 2.182525] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > [ 2.191101] 7fe0: 00000000 00000000 00000000 00000000 00000013 00000000 10d18100 04440800 > [ 2.199676] [<c0287f84>] (omap3_l3_app_irq+0xa4/0x128) from [<c0082600>] (handle_irq_event_percpu+0x50/0x1b4) > [ 2.210083] [<c0082600>] (handle_irq_event_percpu+0x50/0x1b4) from [<c00827a0>] (handle_irq_event+0x3c/0x5c) > [ 2.220428] [<c00827a0>] (handle_irq_event+0x3c/0x5c) from [<c0084cec>] (handle_level_irq+0x8c/0x118) > [ 2.230102] [<c0084cec>] (handle_level_irq+0x8c/0x118) from [<c00825a0>] (generic_handle_irq+0x28/0x30) > [ 2.239959] [<c00825a0>] (generic_handle_irq+0x28/0x30) from [<c000a69c>] (handle_IRQ+0x30/0x84) > [ 2.249176] [<c000a69c>] (handle_IRQ+0x30/0x84) from [<c0008538>] (omap3_intc_handle_irq+0x64/0x74) > [ 2.258636] [<c0008538>] (omap3_intc_handle_irq+0x64/0x74) from [<c00099c4>] (__irq_svc+0x44/0x78) > [ 2.268005] Exception stack(0xc7057c78 to 0xc7057cc0) > [ 2.273315] 7c60: 00000001 00000001 > [ 2.281890] 7c80: c7055440 00000000 c06e803c c7056000 0000000b 00000001 ffffffff c7057e48 > [ 2.290466] 7ca0: c7057e4c 00000000 c7057c98 c7057cc0 c04efa70 c04efa78 60000113 ffffffff > [ 2.299041] [<c00099c4>] (__irq_svc+0x44/0x78) from [<c04efa78>] (_raw_spin_unlock_irq+0x2c/0x50) > [ 2.308349] [<c04efa78>] (_raw_spin_unlock_irq+0x2c/0x50) from [<c0034090>] (do_exit+0x268/0x358) > [ 2.317687] [<c0034090>] (do_exit+0x268/0x358) from [<c000d3b0>] (oops_end+0xb8/0xe8) > [ 2.325897] [<c000d3b0>] (oops_end+0xb8/0xe8) from [<c00084c4>] (do_DataAbort+0x88/0x98) > [ 2.334381] [<c00084c4>] (do_DataAbort+0x88/0x98) from [<c000995c>] (__dabt_svc+0x3c/0x60) > [ 2.343048] Exception stack(0xc7057d90 to 0xc7057dd8) > [ 2.348358] 7d80: 00000021 00000001 c8852000 c7055440 > [ 2.356964] 7da0: c051c270 c05f9bb8 c72ce370 c72ce370 ffffffff c7057e48 c7057e4c 00000000 > [ 2.365539] 7dc0: c7055440 c7057dd8 c032f354 c032f358 20000113 ffffffff > [ 2.372497] [<c000995c>] (__dabt_svc+0x3c/0x60) from [<c032f358>] (nand_read_byte16+0x30/0x64) > [ 2.381530] [<c032f358>] (nand_read_byte16+0x30/0x64) from [<c033194c>] (nand_command+0x174/0x1ec) > [ 2.390960] [<c033194c>] (nand_command+0x174/0x1ec) from [<c03320bc>] (nand_get_flash_type+0x4c/0x5b8) > [ 2.400756] [<c03320bc>] (nand_get_flash_type+0x4c/0x5b8) from [<c0332674>] (nand_scan_ident+0x4c/0x1a8) > [ 2.410736] [<c0332674>] (nand_scan_ident+0x4c/0x1a8) from [<c0336300>] (omap_nand_probe+0x2dc/0x6dc) > [ 2.420440] [<c0336300>] (omap_nand_probe+0x2dc/0x6dc) from [<c02ef658>] (platform_drv_probe+0x18/0x1c) > [ 2.430297] [<c02ef658>] (platform_drv_probe+0x18/0x1c) from [<c02ee32c>] (really_probe+0x70/0x1f8) > [ 2.439819] [<c02ee32c>] (really_probe+0x70/0x1f8) from [<c02ee4e4>] (driver_probe_device+0x30/0x48) > [ 2.449401] [<c02ee4e4>] (driver_probe_device+0x30/0x48) from [<c02ee590>] (__driver_attach+0x94/0x98) > [ 2.459167] [<c02ee590>] (__driver_attach+0x94/0x98) from [<c02ecc5c>] (bus_for_each_dev+0x74/0x98) > [ 2.468658] [<c02ecc5c>] (bus_for_each_dev+0x74/0x98) from [<c02ed504>] (bus_add_driver+0x1c8/0x234) > [ 2.478271] [<c02ed504>] (bus_add_driver+0x1c8/0x234) from [<c02eeb80>] (driver_register+0x78/0x140) > [ 2.487854] [<c02eeb80>] (driver_register+0x78/0x140) from [<c000874c>] (do_one_initcall+0xc0/0x134) > [ 2.497436] [<c000874c>] (do_one_initcall+0xc0/0x134) from [<c06aa2b0>] (do_basic_setup+0x84/0xc4) > [ 2.506835] [<c06aa2b0>] (do_basic_setup+0x84/0xc4) from [<c06aa350>] (kernel_init_freeable+0x60/0xf8) > [ 2.516601] [<c06aa350>] (kernel_init_freeable+0x60/0xf8) from [<c04eb518>] (kernel_init+0x8/0xe4) > [ 2.526031] [<c04eb518>] (kernel_init+0x8/0xe4) from [<c0009ec8>] (ret_from_fork+0x14/0x2c) > [ 2.534759] Code: e5911008 e2813e53 e1c320d0 eaffffe8 (e7f001f2) > [ 2.541168] ---[ end trace 8c2fb2c3b59ab3ab ]--- > [ 2.545989] Kernel panic - not syncing: Fatal exception in interrupt > > Any hints? Can you include the complete boot log? I am wondering if there were any errors seen during the gpmc probe. You can view my nand binding for the omap3430 sdp here [1]. Cheers Jon [1] https://github.com/jonhunter/linux/blob/platform-3.8-jhunter-dt/arch/arm/boot/dts/omap3430-sdp.dts ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-18 19:39 ` Jon Hunter @ 2013-04-18 20:23 ` Christoph Fritz 2013-04-18 22:28 ` Jon Hunter 0 siblings, 1 reply; 19+ messages in thread From: Christoph Fritz @ 2013-04-18 20:23 UTC (permalink / raw) To: Jon Hunter; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap Hi Jon On Thu, 2013-04-18 at 14:39 -0500, Jon Hunter wrote: > On 04/18/2013 02:03 PM, Christoph Fritz wrote: > I had put the complete size in here so ... > > + reg = <0 0 0x1000000>; Thanks. > > > + nand-bus-width = <16>; > > + ti,nand-ecc-opt = "bch8"; > > + /* no elm on omap3 */ > > + > > + gpmc,time-para-granularity = <0>; > > This is a boolean parameter so you don't need the "= <0>". When I want to disable this boolean I thought I need to add the "<0>" (or not defining at all) otherwise a single "gpmc,time-para-granularity" would be interpreted as enabled. > > > + gpmc,mux-add-data = <0>; > > This should be either 1 or 2. In arch/arm/mach-omap2/gpmc.h it gets set by this: #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) but the TRM for AM/DM37x as well as the TRM for Omap35x says: |9 MUXADDDATA Enables the Address and data multiplexed protocol (Reset RW 0x- | value is CS0MUXDEVICE input pin sampled at IC reset for | CS0 and 0 for CS1-7) | 0x0: Non Multiplexed attached device | 0x1: Address and data multiplexed attached device >From u-boot I got 0x00001800 for register GPMC_CONFIG1. So Bit 9 is 0. Why should I set it here to non zero? > > + gpmc,device-nand = <1>; > > This is a boolean parameter so you don't need the "= <0>". The nand here is attached by 16 lines. So I'm pretty sure I need the <1> or at least "gpmc,device-nand;" don't I? > > + > > + #address-cells = <1>; /* <- ? not sure about that */ > > + #size-cells = <1>; /* <- ? not sure about that */ > > This is just needed in case you wish to list partition info. Seeing as > you don't you can omit. Thanks. > > Can you include the complete boot log? I am wondering if there were any > errors seen during the gpmc probe. U-Boot SPL 2013.04-rc2-08894-g33f264f-dirty (Apr 17 2013 - 23:00:59) U-Boot 2013.04-rc2-08894-g33f264f-dirty (Apr 17 2013 - 23:00:59) OMAP36XX/37XX-GP ES1.2, CPU-OPP2, L3-165MHz, Max CPU Clock 1 Ghz OMAP3 EVM board + LPDDR/NAND I2C: ready DRAM: 128 MiB NAND: 256 MiB MMC: OMAP SD/MMC: 0 In: serial Out: serial Err: serial Read back SMSC id 0x92210000 Die ID #017200029e38000001683b051201102a Net: smc911x-0 Hit any key to stop autoboot: 0 OMAP3_EVM # md 0x6E000060 7 6e000060: 00001800 00141400 00141400 0f010f01 ................ 6e000070: 010c1414 1f0f0a80 00000870 ........p... OMAP3_EVM # boot smc911x: detected LAN9221 controller smc911x: phy initialized smc911x: MAC 00:50:c2:0d:6a:63 BOOTP broadcast 1 BOOTP broadcast 2 DHCP client bound to address 172.16.21.17 Using smc911x-0 device TFTP from server 172.16.21.1; our IP address is 172.16.21.17 Filename 'uImage-lil'. Load address: 0x82000000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# #################################### 2.8 MiB/s done Bytes transferred = 3841635 (3a9e63 hex) ## Booting kernel from Legacy Image at 82000000 ... Image Name: next-20130417-38-g03de9e2 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3841571 Bytes = 3.7 MiB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 3.9.0-rc7-next-20130417-00038-g03de9e2 (honschu@mars) (gcc version 4.4.5 (Debian 4.4.5-8) ) #374 PREEMPT Thu Apr 18 22:18:15 CEST 2013 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine: Generic OMAP3 (Flattened Device Tree), model: INCOstartec LILLY-DBB056 (DM3730) [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] CPU: All CPU(s) started in SVC mode. [ 0.000000] OMAP3630 ES1.2 (l2cache iva neon isp 192mhz_clk ) [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256 [ 0.000000] Kernel command line: console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0 root=/dev/nfs ip=dhcp [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Memory: 127MB = 127MB total [ 0.000000] Memory: 116040k/116040k available, 15032k reserved, 0K highmem [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB) [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc06a9f90 (6792 kB) [ 0.000000] .init : 0xc06aa000 - 0xc06db9ec ( 199 kB) [ 0.000000] .data : 0xc06dc000 - 0xc073bd20 ( 384 kB) [ 0.000000] .bss : 0xc073bd20 - 0xc0c7e414 (5386 kB) [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts [ 0.000000] Total of 96 interrupts on 1 active controller [ 0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz [ 0.000000] OMAP clockevent source: timer1 at 32768 Hz [ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms [ 0.000000] OMAP clocksource: 32k_counter at 32768 Hz [ 0.000000] Console: colour dummy device 80x30 [ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8 [ 0.000000] ... MAX_LOCK_DEPTH: 48 [ 0.000000] ... MAX_LOCKDEP_KEYS: 8191 [ 0.000000] ... CLASSHASH_SIZE: 4096 [ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384 [ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768 [ 0.000000] ... CHAINHASH_SIZE: 16384 [ 0.000000] memory used by lock dependency info: 3695 kB [ 0.000000] per task-struct memory footprint: 1152 bytes [ 0.001129] Calibrating delay loop... 398.13 BogoMIPS (lpj=1990656) [ 0.119659] pid_max: default: 4096 minimum: 301 [ 0.120025] Security Framework initialized [ 0.120147] Mount-cache hash table entries: 512 [ 0.136932] CPU: Testing write buffer coherency: ok [ 0.138458] Setting up static identity map for 0xc04efb68 - 0xc04efbc0 [ 0.143096] devtmpfs: initialized [ 0.199432] pinctrl core: initialized pinctrl subsystem [ 0.202819] regulator-dummy: no parameters [ 0.204528] NET: Registered protocol family 16 [ 0.205261] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.213256] Reprogramming SDRC clock to 400000000 Hz [ 0.231018] pinctrl-single 48002030.pinmux: 742 pins at pa fa002030 size 1484 [ 0.232818] pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92 [ 0.236236] OMAP GPIO hardware version 2.5 [ 0.254028] platform 49022000.mcbsp: alias fck already exists [ 0.254913] platform 49024000.mcbsp: alias fck already exists [ 0.263214] omap-gpmc 6e000000.gpmc: GPMC revision 5.0 [ 0.270019] No ATAGs? [ 0.270050] hw-breakpoint: debug architecture 0x4 unsupported. [ 0.272705] OMAP DMA hardware revision 5.0 [ 0.286834] bio: create slab <bio-0> at 0 [ 0.289367] VCC3: 3300 mV [ 0.292266] SCSI subsystem initialized [ 0.292877] usbcore: registered new interface driver usbfs [ 0.293029] usbcore: registered new interface driver hub [ 0.293518] usbcore: registered new device driver usb [ 0.295989] omap_i2c i2c.8: bus 0 rev4.4 at 2600 kHz [ 0.307556] twl 0-0048: PIH (irq 23) chaining IRQs 338..346 [ 0.308135] twl 0-0048: power (irq 343) chaining IRQs 346..353 [ 0.311401] VDD1: 600 <--> 1450 mV at 1200 mV [ 0.313507] VDAC: 1800 mV [ 0.315582] VPLL2: 1800 mV [ 0.317657] VMMC1: 1850 <--> 3150 mV at 3000 mV [ 0.319427] VUSB1V5: failed to apply 1500000uV constraint [ 0.322174] twl_reg regulator-vusb1v5.24: can't register VUSB1V5, -22 [ 0.322235] twl_reg: probe of regulator-vusb1v5.24 failed with error -22 [ 0.323425] VUSB1V8: failed to apply 1800000uV constraint [ 0.323852] twl_reg regulator-vusb1v8.25: can't register VUSB1V8, -22 [ 0.323913] twl_reg: probe of regulator-vusb1v8.25 failed with error -22 [ 0.325103] VUSB3V1: failed to apply 3100000uV constraint [ 0.325531] twl_reg regulator-vusb3v1.26: can't register VUSB3V1, -22 [ 0.325592] twl_reg: probe of regulator-vusb3v1.26 failed with error -22 [ 0.326690] VSIM: 1800 <--> 3000 mV at 1800 mV [ 0.329071] twl4030_gpio gpio.28: gpio (irq 338) chaining IRQs 354..371 [ 0.333251] VIO: 1800 mV [ 0.335571] VAUX2_4030: 2800 mV [ 0.337371] VDD2: at 1200 mV [ 0.339508] omap_i2c i2c.9: bus 1 rev4.4 at 2600 kHz [ 0.340820] omap_i2c i2c.10: bus 2 rev4.4 at 2600 kHz [ 0.341369] pps_core: LinuxPPS API ver. 1 registered [ 0.341400] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 0.341491] PTP clock support registered [ 0.345855] cfg80211: Calling CRDA to update world regulatory domain [ 0.346649] Switching to clocksource 32k_counter [ 0.374969] NET: Registered protocol family 2 [ 0.377319] TCP established hash table entries: 1024 (order: 1, 8192 bytes) [ 0.377532] TCP bind hash table entries: 1024 (order: 3, 36864 bytes) [ 0.378112] TCP: Hash tables configured (established 1024 bind 1024) [ 0.378326] TCP: reno registered [ 0.378356] UDP hash table entries: 128 (order: 1, 10240 bytes) [ 0.378540] UDP-Lite hash table entries: 128 (order: 1, 10240 bytes) [ 0.379547] NET: Registered protocol family 1 [ 0.381042] RPC: Registered named UNIX socket transport module. [ 0.381072] RPC: Registered udp transport module. [ 0.381103] RPC: Registered tcp transport module. [ 0.381103] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.381927] hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available [ 0.391540] VFS: Disk quotas dquot_6.5.2 [ 0.391632] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 0.394287] NFS: Registering the id_resolver key type [ 0.394866] Key type id_resolver registered [ 0.394897] Key type id_legacy registered [ 0.395050] fuse init (API version 7.21) [ 0.396270] msgmni has been set to 226 [ 0.401031] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250) [ 0.401184] io scheduler noop registered [ 0.401184] io scheduler deadline registered [ 0.401245] io scheduler cfq registered (default) [ 0.403167] OMAP DSS rev 2.0 [ 0.405731] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.412078] serial.5: ttyO0 at MMIO 0x4806a000 (irq = 88) is a OMAP UART0 [ 1.136993] console [ttyO0] enabled [ 1.142608] serial.6: ttyO1 at MMIO 0x4806c000 (irq = 89) is a OMAP UART1 [ 1.151550] serial.7: ttyO2 at MMIO 0x49020000 (irq = 90) is a OMAP UART2 [ 1.177642] brd: module loaded [ 1.191802] loop: module loaded [ 1.196746] mtdoops: mtd device (mtddev=name/number) must be supplied [ 1.204925] Missing elm_id property, fall back to Software BCH [ 1.213653] enabling NAND BCH ecc with 8-bit correction [ 1.224304] Unhandled fault: external abort on non-linefetch (0x1008) at 0xc8852000 [ 1.232360] Internal error: : 1008 [#1] PREEMPT ARM [ 1.237457] Modules linked in: [ 1.240661] CPU: 0 Not tainted (3.9.0-rc7-next-20130417-00038-g03de9e2 #374) [ 1.248443] PC is at nand_read_byte16+0x8/0x1c [ 1.253112] LR is at nand_command+0x174/0x1ec [ 1.257659] pc : [<c032d9a0>] lr : [<c0331704>] psr: 60000113 [ 1.257659] sp : c7057de8 ip : c0331590 fp : 00000000 [ 1.269714] r10: c7057e4c r9 : c7057e48 r8 : ffffffff [ 1.275177] r7 : c72ce370 r6 : ffffffff r5 : 000000ff r4 : c72ce050 [ 1.282043] r3 : c8852000 r2 : 00000081 r1 : ffffffff r0 : c72ce050 [ 1.288879] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel [ 1.296539] Control: 10c5387d Table: 80004019 DAC: 00000015 [ 1.302581] Process swapper (pid: 1, stack limit = 0xc7056238) [ 1.308685] Stack: (0xc7057de8 to 0xc7058000) [ 1.313262] 7de0: 00000000 c72ce370 c72ce050 00000000 c7057e18 c0331e74 [ 1.321807] 7e00: 00000001 00000000 c72c7b80 c72ce000 c72ce050 00000002 00000000 c0c74054 [ 1.330383] 7e20: c72ce370 c72ce050 00000000 00000001 00000002 0000008e c0702a20 c033242c [ 1.338989] 7e40: c7057e48 00000000 c0637598 00000008 00000000 c72ce000 c72ce050 c700a690 [ 1.347564] 7e60: 00000000 c0c74054 0000008e c03360b8 00000000 c72c7f50 c7120ef0 00000000 [ 1.356140] 7e80: 00000000 c0702a20 c0702a28 c0c73628 c072a57c c0702a20 00000000 c072a57c [ 1.364685] 7ea0: c06d12fc c02ef458 c0c73628 c02ee12c c0702a20 c072a57c c0702a54 00000000 [ 1.373260] 7ec0: c06c709c c02ee2e4 c0702a20 c072a57c c0702a54 c02ee390 c072a57c c02ee2fc [ 1.381835] 7ee0: c7057ee8 c02eca5c c704b2a8 c7115690 c704b2d8 c072a57c c0723888 c72ba640 [ 1.390411] 7f00: 00000000 c02ed304 c05feb28 c072a57c c073bd40 c06d12f4 c072a57c c073bd40 [ 1.398986] 7f20: 00000000 c02ee980 c06d12f4 c06db898 c073bd40 00000000 c06c709c c000874c [ 1.407562] 7f40: 00000000 c06d12f4 00000006 c073bd40 c06d12f4 c06db898 c073bd40 00000007 [ 1.416137] 7f60: c06aa3e8 c06aa2b0 00000006 00000006 c06aa3e8 00000000 c06db460 c06db460 [ 1.424713] 7f80: 00000000 00000000 00000000 00000000 00000000 c06aa350 00000000 c04eb2c8 [ 1.433288] 7fa0: 00000000 c04eb2d0 00000000 c0009ec8 00000000 00000000 00000000 00000000 [ 1.441833] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 1.450408] 7fe0: 00000000 00000000 00000000 00000000 00000013 00000000 1051a000 04440800 [ 1.458984] [<c032d9a0>] (nand_read_byte16+0x8/0x1c) from [<c0331704>] (nand_command+0x174/0x1ec) [ 1.468292] [<c0331704>] (nand_command+0x174/0x1ec) from [<c0331e74>] (nand_get_flash_type+0x4c/0x5b8) [ 1.478057] [<c0331e74>] (nand_get_flash_type+0x4c/0x5b8) from [<c033242c>] (nand_scan_ident+0x4c/0x1a8) [ 1.488006] [<c033242c>] (nand_scan_ident+0x4c/0x1a8) from [<c03360b8>] (omap_nand_probe+0x2dc/0x6dc) [ 1.497680] [<c03360b8>] (omap_nand_probe+0x2dc/0x6dc) from [<c02ef458>] (platform_drv_probe+0x18/0x1c) [ 1.507537] [<c02ef458>] (platform_drv_probe+0x18/0x1c) from [<c02ee12c>] (really_probe+0x70/0x1f8) [ 1.517028] [<c02ee12c>] (really_probe+0x70/0x1f8) from [<c02ee2e4>] (driver_probe_device+0x30/0x48) [ 1.526641] [<c02ee2e4>] (driver_probe_device+0x30/0x48) from [<c02ee390>] (__driver_attach+0x94/0x98) [ 1.536407] [<c02ee390>] (__driver_attach+0x94/0x98) from [<c02eca5c>] (bus_for_each_dev+0x74/0x98) [ 1.545898] [<c02eca5c>] (bus_for_each_dev+0x74/0x98) from [<c02ed304>] (bus_add_driver+0x1c8/0x234) [ 1.555480] [<c02ed304>] (bus_add_driver+0x1c8/0x234) from [<c02ee980>] (driver_register+0x78/0x140) [ 1.565063] [<c02ee980>] (driver_register+0x78/0x140) from [<c000874c>] (do_one_initcall+0xc0/0x134) [ 1.574615] [<c000874c>] (do_one_initcall+0xc0/0x134) from [<c06aa2b0>] (do_basic_setup+0x84/0xc4) [ 1.584014] [<c06aa2b0>] (do_basic_setup+0x84/0xc4) from [<c06aa350>] (kernel_init_freeable+0x60/0xf8) [ 1.593780] [<c06aa350>] (kernel_init_freeable+0x60/0xf8) from [<c04eb2d0>] (kernel_init+0x8/0xe4) [ 1.603179] [<c04eb2d0>] (kernel_init+0x8/0xe4) from [<c0009ec8>] (ret_from_fork+0x14/0x2c) [ 1.611938] Code: f57ff04f e12fff1e e59030dc e5933000 (e1d300b0) [ 1.618377] ---[ end trace 7ab5f8dfed0385fd ]--- [ 1.623229] ------------[ cut here ]------------ [ 1.628082] Kernel BUG at c0287d84 [verbose debug info unavailable] [ 1.634643] Internal error: Oops - BUG: 0 [#2] PREEMPT ARM [ 1.640380] Modules linked in: [ 1.643585] CPU: 0 Tainted: G D (3.9.0-rc7-next-20130417-00038-g03de9e2 #374) [ 1.652313] PC is at omap3_l3_app_irq+0xa4/0x128 [ 1.657165] LR is at handle_irq_event_percpu+0x50/0x1b4 [ 1.662628] pc : [<c0287d84>] lr : [<c0082400>] psr: 20000193 [ 1.662628] sp : c7057bd8 ip : c7057c08 fp : c073bc1e [ 1.674652] r10: c70055b8 r9 : 3ccf0000 r8 : 0b6db6c3 [ 1.680114] r7 : 00000000 r6 : 00000000 r5 : 00020000 r4 : 00000000 [ 1.686950] r3 : 00020000 r2 : 00000004 r1 : f8000000 r0 : 00020000 [ 1.693786] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user [ 1.701354] Control: 10c5387d Table: 80004019 DAC: 00000015 [ 1.707366] Process swapper (pid: 1, stack limit = 0xc7056238) [ 1.713470] Stack: (0xc7057bd8 to 0xc7058000) [ 1.718048] 7bc0: 00000000 60000193 [ 1.726593] 7be0: 00000001 c7097a00 c7005590 00000000 00000000 0000001a c7005540 c70055b8 [ 1.735168] 7c00: c073bc1e c0082400 c7056000 00000000 60000193 c7005540 c7005590 c7097a00 [ 1.743713] 7c20: c073c814 ffffffff c7057e48 c7057e4c 00000000 c00825a0 c7005540 c7005590 [ 1.752288] 7c40: 00000000 c0084aec 0000001a 0000001a 00000000 c00823a0 c071c5c4 c000a69c [ 1.760864] 7c60: fa200000 0000001a c7057c88 c0008538 c04ef830 60000113 ffffffff c7057cbc [ 1.769439] 7c80: ffffffff c00099c4 00000001 00000001 c7055440 00000000 c06e803c c7056000 [ 1.778015] 7ca0: 0000000b 00000001 ffffffff c7057e48 c7057e4c 00000000 c7057ca8 c7057cd0 [ 1.786590] 7cc0: c04ef828 c04ef830 60000113 ffffffff c7055440 c0033e90 60000193 c06e8540 [ 1.795166] 7ce0: 0000000b c7057da0 ffffffff c000d3b0 00001008 c06e8fc4 c8852000 c00084c4 [ 1.803741] 7d00: 00000000 c006ad30 00000007 00000000 00000000 c8852000 00000001 c0035abc [ 1.812286] 7d20: c7006a90 00000001 00000000 00000004 ffff8b4a 00200140 60000193 c7056000 [ 1.820861] 7d40: 00000035 00000000 01400000 c0087bd8 c071c5c4 00000006 00000000 c00099e8 [ 1.829437] 7d60: c7055440 00000001 c7057dc4 00000000 c7056000 00000000 00000000 c006ad80 [ 1.838043] 7d80: c0030afc 20000113 ffffffff c032d9a0 60000113 ffffffff c7057dd4 c000995c [ 1.846588] 7da0: c72ce050 ffffffff 00000081 c8852000 c72ce050 000000ff ffffffff c72ce370 [ 1.855163] 7dc0: ffffffff c7057e48 c7057e4c 00000000 c0331590 c7057de8 c0331704 c032d9a0 [ 1.863739] 7de0: 60000113 ffffffff 00000000 c72ce370 c72ce050 00000000 c7057e18 c0331e74 [ 1.872314] 7e00: 00000001 00000000 c72c7b80 c72ce000 c72ce050 00000002 00000000 c0c74054 [ 1.880889] 7e20: c72ce370 c72ce050 00000000 00000001 00000002 0000008e c0702a20 c033242c [ 1.889465] 7e40: c7057e48 00000000 c0637598 00000008 00000000 c72ce000 c72ce050 c700a690 [ 1.898040] 7e60: 00000000 c0c74054 0000008e c03360b8 00000000 c72c7f50 c7120ef0 00000000 [ 1.906646] 7e80: 00000000 c0702a20 c0702a28 c0c73628 c072a57c c0702a20 00000000 c072a57c [ 1.915222] 7ea0: c06d12fc c02ef458 c0c73628 c02ee12c c0702a20 c072a57c c0702a54 00000000 [ 1.923797] 7ec0: c06c709c c02ee2e4 c0702a20 c072a57c c0702a54 c02ee390 c072a57c c02ee2fc [ 1.932373] 7ee0: c7057ee8 c02eca5c c704b2a8 c7115690 c704b2d8 c072a57c c0723888 c72ba640 [ 1.940948] 7f00: 00000000 c02ed304 c05feb28 c072a57c c073bd40 c06d12f4 c072a57c c073bd40 [ 1.949523] 7f20: 00000000 c02ee980 c06d12f4 c06db898 c073bd40 00000000 c06c709c c000874c [ 1.958068] 7f40: 00000000 c06d12f4 00000006 c073bd40 c06d12f4 c06db898 c073bd40 00000007 [ 1.966644] 7f60: c06aa3e8 c06aa2b0 00000006 00000006 c06aa3e8 00000000 c06db460 c06db460 [ 1.975219] 7f80: 00000000 00000000 00000000 00000000 00000000 c06aa350 00000000 c04eb2c8 [ 1.983795] 7fa0: 00000000 c04eb2d0 00000000 c0009ec8 00000000 00000000 00000000 00000000 [ 1.992370] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 2.000946] 7fe0: 00000000 00000000 00000000 00000000 00000013 00000000 1051a000 04440800 [ 2.009521] [<c0287d84>] (omap3_l3_app_irq+0xa4/0x128) from [<c0082400>] (handle_irq_event_percpu+0x50/0x1b4) [ 2.019897] [<c0082400>] (handle_irq_event_percpu+0x50/0x1b4) from [<c00825a0>] (handle_irq_event+0x3c/0x5c) [ 2.030212] [<c00825a0>] (handle_irq_event+0x3c/0x5c) from [<c0084aec>] (handle_level_irq+0x8c/0x118) [ 2.039886] [<c0084aec>] (handle_level_irq+0x8c/0x118) from [<c00823a0>] (generic_handle_irq+0x28/0x30) [ 2.049713] [<c00823a0>] (generic_handle_irq+0x28/0x30) from [<c000a69c>] (handle_IRQ+0x30/0x84) [ 2.058898] [<c000a69c>] (handle_IRQ+0x30/0x84) from [<c0008538>] (omap3_intc_handle_irq+0x64/0x74) [ 2.068389] [<c0008538>] (omap3_intc_handle_irq+0x64/0x74) from [<c00099c4>] (__irq_svc+0x44/0x78) [ 2.077758] Exception stack(0xc7057c88 to 0xc7057cd0) [ 2.083038] 7c80: 00000001 00000001 c7055440 00000000 c06e803c c7056000 [ 2.091613] 7ca0: 0000000b 00000001 ffffffff c7057e48 c7057e4c 00000000 c7057ca8 c7057cd0 [ 2.100189] 7cc0: c04ef828 c04ef830 60000113 ffffffff [ 2.105468] [<c00099c4>] (__irq_svc+0x44/0x78) from [<c04ef830>] (_raw_spin_unlock_irq+0x2c/0x50) [ 2.114776] [<c04ef830>] (_raw_spin_unlock_irq+0x2c/0x50) from [<c0033e90>] (do_exit+0x268/0x358) [ 2.124084] [<c0033e90>] (do_exit+0x268/0x358) from [<c000d3b0>] (oops_end+0xb8/0xe8) [ 2.132293] [<c000d3b0>] (oops_end+0xb8/0xe8) from [<c00084c4>] (do_DataAbort+0x88/0x98) [ 2.140777] [<c00084c4>] (do_DataAbort+0x88/0x98) from [<c000995c>] (__dabt_svc+0x3c/0x60) [ 2.149414] Exception stack(0xc7057da0 to 0xc7057de8) [ 2.154693] 7da0: c72ce050 ffffffff 00000081 c8852000 c72ce050 000000ff ffffffff c72ce370 [ 2.163269] 7dc0: ffffffff c7057e48 c7057e4c 00000000 c0331590 c7057de8 c0331704 c032d9a0 [ 2.171844] 7de0: 60000113 ffffffff [ 2.175506] [<c000995c>] (__dabt_svc+0x3c/0x60) from [<c032d9a0>] (nand_read_byte16+0x8/0x1c) [ 2.184417] [<c032d9a0>] (nand_read_byte16+0x8/0x1c) from [<c0331704>] (nand_command+0x174/0x1ec) [ 2.193725] [<c0331704>] (nand_command+0x174/0x1ec) from [<c0331e74>] (nand_get_flash_type+0x4c/0x5b8) [ 2.203460] [<c0331e74>] (nand_get_flash_type+0x4c/0x5b8) from [<c033242c>] (nand_scan_ident+0x4c/0x1a8) [ 2.213378] [<c033242c>] (nand_scan_ident+0x4c/0x1a8) from [<c03360b8>] (omap_nand_probe+0x2dc/0x6dc) [ 2.223052] [<c03360b8>] (omap_nand_probe+0x2dc/0x6dc) from [<c02ef458>] (platform_drv_probe+0x18/0x1c) [ 2.232879] [<c02ef458>] (platform_drv_probe+0x18/0x1c) from [<c02ee12c>] (really_probe+0x70/0x1f8) [ 2.242370] [<c02ee12c>] (really_probe+0x70/0x1f8) from [<c02ee2e4>] (driver_probe_device+0x30/0x48) [ 2.251953] [<c02ee2e4>] (driver_probe_device+0x30/0x48) from [<c02ee390>] (__driver_attach+0x94/0x98) [ 2.261718] [<c02ee390>] (__driver_attach+0x94/0x98) from [<c02eca5c>] (bus_for_each_dev+0x74/0x98) [ 2.271179] [<c02eca5c>] (bus_for_each_dev+0x74/0x98) from [<c02ed304>] (bus_add_driver+0x1c8/0x234) [ 2.280761] [<c02ed304>] (bus_add_driver+0x1c8/0x234) from [<c02ee980>] (driver_register+0x78/0x140) [ 2.290344] [<c02ee980>] (driver_register+0x78/0x140) from [<c000874c>] (do_one_initcall+0xc0/0x134) [ 2.299926] [<c000874c>] (do_one_initcall+0xc0/0x134) from [<c06aa2b0>] (do_basic_setup+0x84/0xc4) [ 2.309295] [<c06aa2b0>] (do_basic_setup+0x84/0xc4) from [<c06aa350>] (kernel_init_freeable+0x60/0xf8) [ 2.319061] [<c06aa350>] (kernel_init_freeable+0x60/0xf8) from [<c04eb2d0>] (kernel_init+0x8/0xe4) [ 2.328460] [<c04eb2d0>] (kernel_init+0x8/0xe4) from [<c0009ec8>] (ret_from_fork+0x14/0x2c) [ 2.337219] Code: e5911008 e2813e53 e1c320d0 eaffffe8 (e7f001f2) [ 2.343597] ---[ end trace 7ab5f8dfed0385fe ]--- [ 2.348419] Kernel panic - not syncing: Fatal exception in interrupt ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-18 20:23 ` Christoph Fritz @ 2013-04-18 22:28 ` Jon Hunter 2013-04-18 22:48 ` Christoph Fritz 0 siblings, 1 reply; 19+ messages in thread From: Jon Hunter @ 2013-04-18 22:28 UTC (permalink / raw) To: Christoph Fritz; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On 04/18/2013 03:23 PM, Christoph Fritz wrote: > Hi Jon > > On Thu, 2013-04-18 at 14:39 -0500, Jon Hunter wrote: >> On 04/18/2013 02:03 PM, Christoph Fritz wrote: > >> I had put the complete size in here so ... >> >> + reg = <0 0 0x1000000>; > > Thanks. > >> >>> + nand-bus-width = <16>; >>> + ti,nand-ecc-opt = "bch8"; >>> + /* no elm on omap3 */ >>> + >>> + gpmc,time-para-granularity = <0>; >> >> This is a boolean parameter so you don't need the "= <0>". > > When I want to disable this boolean I thought I need to add the > "<0>" (or not defining at all) otherwise a single > "gpmc,time-para-granularity" would be interpreted as enabled. If you don't want to enable it, just don't define it at all. The code just checks for the presence of this property, so defining it as zero means you will enable it. >> >>> + gpmc,mux-add-data = <0>; >> >> This should be either 1 or 2. > > In arch/arm/mach-omap2/gpmc.h it gets set by this: > #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) > > but the TRM for AM/DM37x as well as the TRM for Omap35x says: > > |9 MUXADDDATA Enables the Address and data multiplexed protocol (Reset RW 0x- > | value is CS0MUXDEVICE input pin sampled at IC reset for > | CS0 and 0 for CS1-7) > | 0x0: Non Multiplexed attached device > | 0x1: Address and data multiplexed attached device > > From u-boot I got 0x00001800 for register GPMC_CONFIG1. So Bit 9 is 0. > Why should I set it here to non zero? It should be either 1 or 2, or you should not define it. So if the bit is zero from the u-boot configuration, just leave it out this property. Setting to 0 is probably ok if you don't want to have address-data multiplexing, but it is also pointless. >>> + gpmc,device-nand = <1>; >> >> This is a boolean parameter so you don't need the "= <0>". > > The nand here is attached by 16 lines. So I'm pretty sure I need the <1> > or at least "gpmc,device-nand;" don't I? This is a boolean property. You should just have "gpmc,device-nand". >>> + >>> + #address-cells = <1>; /* <- ? not sure about that */ >>> + #size-cells = <1>; /* <- ? not sure about that */ >> >> This is just needed in case you wish to list partition info. Seeing as >> you don't you can omit. > > Thanks. > >> >> Can you include the complete boot log? I am wondering if there were any >> errors seen during the gpmc probe. > > U-Boot SPL 2013.04-rc2-08894-g33f264f-dirty (Apr 17 2013 - 23:00:59) > > > U-Boot 2013.04-rc2-08894-g33f264f-dirty (Apr 17 2013 - 23:00:59) > > OMAP36XX/37XX-GP ES1.2, CPU-OPP2, L3-165MHz, Max CPU Clock 1 Ghz > OMAP3 EVM board + LPDDR/NAND > I2C: ready > DRAM: 128 MiB > NAND: 256 MiB > MMC: OMAP SD/MMC: 0 > In: serial > Out: serial > Err: serial > Read back SMSC id 0x92210000 > Die ID #017200029e38000001683b051201102a > Net: smc911x-0 > Hit any key to stop autoboot: 0 > OMAP3_EVM # md 0x6E000060 7 > 6e000060: 00001800 00141400 00141400 0f010f01 ................ > 6e000070: 010c1414 1f0f0a80 00000870 ........p... > OMAP3_EVM # boot > smc911x: detected LAN9221 controller > smc911x: phy initialized > smc911x: MAC 00:50:c2:0d:6a:63 > BOOTP broadcast 1 > BOOTP broadcast 2 > DHCP client bound to address 172.16.21.17 > Using smc911x-0 device > TFTP from server 172.16.21.1; our IP address is 172.16.21.17 > Filename 'uImage-lil'. > Load address: 0x82000000 > Loading: ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > #################################### > 2.8 MiB/s > done > Bytes transferred = 3841635 (3a9e63 hex) > ## Booting kernel from Legacy Image at 82000000 ... > Image Name: next-20130417-38-g03de9e2 > Image Type: ARM Linux Kernel Image (uncompressed) > Data Size: 3841571 Bytes = 3.7 MiB > Load Address: 80008000 > Entry Point: 80008000 > Verifying Checksum ... OK > Loading Kernel Image ... OK > OK > > Starting kernel ... > > [ 0.000000] Booting Linux on physical CPU 0x0 > [ 0.000000] Linux version 3.9.0-rc7-next-20130417-00038-g03de9e2 (honschu@mars) (gcc version 4.4.5 (Debian 4.4.5-8) ) #374 PREEMPT Thu Apr 18 22:18:15 CEST 2013 > [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d > [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache > [ 0.000000] Machine: Generic OMAP3 (Flattened Device Tree), model: INCOstartec LILLY-DBB056 (DM3730) > [ 0.000000] Memory policy: ECC disabled, Data cache writeback > [ 0.000000] CPU: All CPU(s) started in SVC mode. > [ 0.000000] OMAP3630 ES1.2 (l2cache iva neon isp 192mhz_clk ) > [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256 > [ 0.000000] Kernel command line: console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0 root=/dev/nfs ip=dhcp > [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) > [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) > [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) > [ 0.000000] Memory: 127MB = 127MB total > [ 0.000000] Memory: 116040k/116040k available, 15032k reserved, 0K highmem > [ 0.000000] Virtual kernel memory layout: > [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) > [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) > [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB) > [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) > [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) > [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) > [ 0.000000] .text : 0xc0008000 - 0xc06a9f90 (6792 kB) > [ 0.000000] .init : 0xc06aa000 - 0xc06db9ec ( 199 kB) > [ 0.000000] .data : 0xc06dc000 - 0xc073bd20 ( 384 kB) > [ 0.000000] .bss : 0xc073bd20 - 0xc0c7e414 (5386 kB) > [ 0.000000] NR_IRQS:16 nr_irqs:16 16 > [ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts > [ 0.000000] Total of 96 interrupts on 1 active controller > [ 0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz > [ 0.000000] OMAP clockevent source: timer1 at 32768 Hz > [ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms > [ 0.000000] OMAP clocksource: 32k_counter at 32768 Hz > [ 0.000000] Console: colour dummy device 80x30 > [ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar > [ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8 > [ 0.000000] ... MAX_LOCK_DEPTH: 48 > [ 0.000000] ... MAX_LOCKDEP_KEYS: 8191 > [ 0.000000] ... CLASSHASH_SIZE: 4096 > [ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384 > [ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768 > [ 0.000000] ... CHAINHASH_SIZE: 16384 > [ 0.000000] memory used by lock dependency info: 3695 kB > [ 0.000000] per task-struct memory footprint: 1152 bytes > [ 0.001129] Calibrating delay loop... 398.13 BogoMIPS (lpj=1990656) > [ 0.119659] pid_max: default: 4096 minimum: 301 > [ 0.120025] Security Framework initialized > [ 0.120147] Mount-cache hash table entries: 512 > [ 0.136932] CPU: Testing write buffer coherency: ok > [ 0.138458] Setting up static identity map for 0xc04efb68 - 0xc04efbc0 > [ 0.143096] devtmpfs: initialized > [ 0.199432] pinctrl core: initialized pinctrl subsystem > [ 0.202819] regulator-dummy: no parameters > [ 0.204528] NET: Registered protocol family 16 > [ 0.205261] DMA: preallocated 256 KiB pool for atomic coherent allocations > [ 0.213256] Reprogramming SDRC clock to 400000000 Hz > [ 0.231018] pinctrl-single 48002030.pinmux: 742 pins at pa fa002030 size 1484 > [ 0.232818] pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92 > [ 0.236236] OMAP GPIO hardware version 2.5 > [ 0.254028] platform 49022000.mcbsp: alias fck already exists > [ 0.254913] platform 49024000.mcbsp: alias fck already exists > [ 0.263214] omap-gpmc 6e000000.gpmc: GPMC revision 5.0 > [ 0.270019] No ATAGs? > [ 0.270050] hw-breakpoint: debug architecture 0x4 unsupported. > [ 0.272705] OMAP DMA hardware revision 5.0 > [ 0.286834] bio: create slab <bio-0> at 0 > [ 0.289367] VCC3: 3300 mV > [ 0.292266] SCSI subsystem initialized > [ 0.292877] usbcore: registered new interface driver usbfs > [ 0.293029] usbcore: registered new interface driver hub > [ 0.293518] usbcore: registered new device driver usb > [ 0.295989] omap_i2c i2c.8: bus 0 rev4.4 at 2600 kHz > [ 0.307556] twl 0-0048: PIH (irq 23) chaining IRQs 338..346 > [ 0.308135] twl 0-0048: power (irq 343) chaining IRQs 346..353 > [ 0.311401] VDD1: 600 <--> 1450 mV at 1200 mV > [ 0.313507] VDAC: 1800 mV > [ 0.315582] VPLL2: 1800 mV > [ 0.317657] VMMC1: 1850 <--> 3150 mV at 3000 mV > [ 0.319427] VUSB1V5: failed to apply 1500000uV constraint > [ 0.322174] twl_reg regulator-vusb1v5.24: can't register VUSB1V5, -22 > [ 0.322235] twl_reg: probe of regulator-vusb1v5.24 failed with error -22 > [ 0.323425] VUSB1V8: failed to apply 1800000uV constraint > [ 0.323852] twl_reg regulator-vusb1v8.25: can't register VUSB1V8, -22 > [ 0.323913] twl_reg: probe of regulator-vusb1v8.25 failed with error -22 > [ 0.325103] VUSB3V1: failed to apply 3100000uV constraint > [ 0.325531] twl_reg regulator-vusb3v1.26: can't register VUSB3V1, -22 > [ 0.325592] twl_reg: probe of regulator-vusb3v1.26 failed with error -22 > [ 0.326690] VSIM: 1800 <--> 3000 mV at 1800 mV > [ 0.329071] twl4030_gpio gpio.28: gpio (irq 338) chaining IRQs 354..371 > [ 0.333251] VIO: 1800 mV > [ 0.335571] VAUX2_4030: 2800 mV > [ 0.337371] VDD2: at 1200 mV > [ 0.339508] omap_i2c i2c.9: bus 1 rev4.4 at 2600 kHz > [ 0.340820] omap_i2c i2c.10: bus 2 rev4.4 at 2600 kHz > [ 0.341369] pps_core: LinuxPPS API ver. 1 registered > [ 0.341400] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> > [ 0.341491] PTP clock support registered > [ 0.345855] cfg80211: Calling CRDA to update world regulatory domain > [ 0.346649] Switching to clocksource 32k_counter > [ 0.374969] NET: Registered protocol family 2 > [ 0.377319] TCP established hash table entries: 1024 (order: 1, 8192 bytes) > [ 0.377532] TCP bind hash table entries: 1024 (order: 3, 36864 bytes) > [ 0.378112] TCP: Hash tables configured (established 1024 bind 1024) > [ 0.378326] TCP: reno registered > [ 0.378356] UDP hash table entries: 128 (order: 1, 10240 bytes) > [ 0.378540] UDP-Lite hash table entries: 128 (order: 1, 10240 bytes) > [ 0.379547] NET: Registered protocol family 1 > [ 0.381042] RPC: Registered named UNIX socket transport module. > [ 0.381072] RPC: Registered udp transport module. > [ 0.381103] RPC: Registered tcp transport module. > [ 0.381103] RPC: Registered tcp NFSv4.1 backchannel transport module. > [ 0.381927] hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available > [ 0.391540] VFS: Disk quotas dquot_6.5.2 > [ 0.391632] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) > [ 0.394287] NFS: Registering the id_resolver key type > [ 0.394866] Key type id_resolver registered > [ 0.394897] Key type id_legacy registered > [ 0.395050] fuse init (API version 7.21) > [ 0.396270] msgmni has been set to 226 > [ 0.401031] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250) > [ 0.401184] io scheduler noop registered > [ 0.401184] io scheduler deadline registered > [ 0.401245] io scheduler cfq registered (default) > [ 0.403167] OMAP DSS rev 2.0 > [ 0.405731] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled > [ 0.412078] serial.5: ttyO0 at MMIO 0x4806a000 (irq = 88) is a OMAP UART0 > [ 1.136993] console [ttyO0] enabled > [ 1.142608] serial.6: ttyO1 at MMIO 0x4806c000 (irq = 89) is a OMAP UART1 > [ 1.151550] serial.7: ttyO2 at MMIO 0x49020000 (irq = 90) is a OMAP UART2 > [ 1.177642] brd: module loaded > [ 1.191802] loop: module loaded > [ 1.196746] mtdoops: mtd device (mtddev=name/number) must be supplied > [ 1.204925] Missing elm_id property, fall back to Software BCH > [ 1.213653] enabling NAND BCH ecc with 8-bit correction > [ 1.224304] Unhandled fault: external abort on non-linefetch (0x1008) at 0xc8852000 > [ 1.232360] Internal error: : 1008 [#1] PREEMPT ARM > [ 1.237457] Modules linked in: > [ 1.240661] CPU: 0 Not tainted (3.9.0-rc7-next-20130417-00038-g03de9e2 #374) > [ 1.248443] PC is at nand_read_byte16+0x8/0x1c > [ 1.253112] LR is at nand_command+0x174/0x1ec > [ 1.257659] pc : [<c032d9a0>] lr : [<c0331704>] psr: 60000113 > [ 1.257659] sp : c7057de8 ip : c0331590 fp : 00000000 > [ 1.269714] r10: c7057e4c r9 : c7057e48 r8 : ffffffff > [ 1.275177] r7 : c72ce370 r6 : ffffffff r5 : 000000ff r4 : c72ce050 > [ 1.282043] r3 : c8852000 r2 : 00000081 r1 : ffffffff r0 : c72ce050 > [ 1.288879] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel > [ 1.296539] Control: 10c5387d Table: 80004019 DAC: 00000015 > [ 1.302581] Process swapper (pid: 1, stack limit = 0xc7056238) > [ 1.308685] Stack: (0xc7057de8 to 0xc7058000) > [ 1.313262] 7de0: 00000000 c72ce370 c72ce050 00000000 c7057e18 c0331e74 > [ 1.321807] 7e00: 00000001 00000000 c72c7b80 c72ce000 c72ce050 00000002 00000000 c0c74054 > [ 1.330383] 7e20: c72ce370 c72ce050 00000000 00000001 00000002 0000008e c0702a20 c033242c > [ 1.338989] 7e40: c7057e48 00000000 c0637598 00000008 00000000 c72ce000 c72ce050 c700a690 > [ 1.347564] 7e60: 00000000 c0c74054 0000008e c03360b8 00000000 c72c7f50 c7120ef0 00000000 > [ 1.356140] 7e80: 00000000 c0702a20 c0702a28 c0c73628 c072a57c c0702a20 00000000 c072a57c > [ 1.364685] 7ea0: c06d12fc c02ef458 c0c73628 c02ee12c c0702a20 c072a57c c0702a54 00000000 > [ 1.373260] 7ec0: c06c709c c02ee2e4 c0702a20 c072a57c c0702a54 c02ee390 c072a57c c02ee2fc > [ 1.381835] 7ee0: c7057ee8 c02eca5c c704b2a8 c7115690 c704b2d8 c072a57c c0723888 c72ba640 > [ 1.390411] 7f00: 00000000 c02ed304 c05feb28 c072a57c c073bd40 c06d12f4 c072a57c c073bd40 > [ 1.398986] 7f20: 00000000 c02ee980 c06d12f4 c06db898 c073bd40 00000000 c06c709c c000874c > [ 1.407562] 7f40: 00000000 c06d12f4 00000006 c073bd40 c06d12f4 c06db898 c073bd40 00000007 > [ 1.416137] 7f60: c06aa3e8 c06aa2b0 00000006 00000006 c06aa3e8 00000000 c06db460 c06db460 > [ 1.424713] 7f80: 00000000 00000000 00000000 00000000 00000000 c06aa350 00000000 c04eb2c8 > [ 1.433288] 7fa0: 00000000 c04eb2d0 00000000 c0009ec8 00000000 00000000 00000000 00000000 > [ 1.441833] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > [ 1.450408] 7fe0: 00000000 00000000 00000000 00000000 00000013 00000000 1051a000 04440800 > [ 1.458984] [<c032d9a0>] (nand_read_byte16+0x8/0x1c) from [<c0331704>] (nand_command+0x174/0x1ec) > [ 1.468292] [<c0331704>] (nand_command+0x174/0x1ec) from [<c0331e74>] (nand_get_flash_type+0x4c/0x5b8) > [ 1.478057] [<c0331e74>] (nand_get_flash_type+0x4c/0x5b8) from [<c033242c>] (nand_scan_ident+0x4c/0x1a8) > [ 1.488006] [<c033242c>] (nand_scan_ident+0x4c/0x1a8) from [<c03360b8>] (omap_nand_probe+0x2dc/0x6dc) > [ 1.497680] [<c03360b8>] (omap_nand_probe+0x2dc/0x6dc) from [<c02ef458>] (platform_drv_probe+0x18/0x1c) > [ 1.507537] [<c02ef458>] (platform_drv_probe+0x18/0x1c) from [<c02ee12c>] (really_probe+0x70/0x1f8) > [ 1.517028] [<c02ee12c>] (really_probe+0x70/0x1f8) from [<c02ee2e4>] (driver_probe_device+0x30/0x48) > [ 1.526641] [<c02ee2e4>] (driver_probe_device+0x30/0x48) from [<c02ee390>] (__driver_attach+0x94/0x98) > [ 1.536407] [<c02ee390>] (__driver_attach+0x94/0x98) from [<c02eca5c>] (bus_for_each_dev+0x74/0x98) > [ 1.545898] [<c02eca5c>] (bus_for_each_dev+0x74/0x98) from [<c02ed304>] (bus_add_driver+0x1c8/0x234) > [ 1.555480] [<c02ed304>] (bus_add_driver+0x1c8/0x234) from [<c02ee980>] (driver_register+0x78/0x140) > [ 1.565063] [<c02ee980>] (driver_register+0x78/0x140) from [<c000874c>] (do_one_initcall+0xc0/0x134) > [ 1.574615] [<c000874c>] (do_one_initcall+0xc0/0x134) from [<c06aa2b0>] (do_basic_setup+0x84/0xc4) > [ 1.584014] [<c06aa2b0>] (do_basic_setup+0x84/0xc4) from [<c06aa350>] (kernel_init_freeable+0x60/0xf8) > [ 1.593780] [<c06aa350>] (kernel_init_freeable+0x60/0xf8) from [<c04eb2d0>] (kernel_init+0x8/0xe4) > [ 1.603179] [<c04eb2d0>] (kernel_init+0x8/0xe4) from [<c0009ec8>] (ret_from_fork+0x14/0x2c) > [ 1.611938] Code: f57ff04f e12fff1e e59030dc e5933000 (e1d300b0) > [ 1.618377] ---[ end trace 7ab5f8dfed0385fd ]--- > [ 1.623229] ------------[ cut here ]------------ > [ 1.628082] Kernel BUG at c0287d84 [verbose debug info unavailable] > [ 1.634643] Internal error: Oops - BUG: 0 [#2] PREEMPT ARM > [ 1.640380] Modules linked in: > [ 1.643585] CPU: 0 Tainted: G D (3.9.0-rc7-next-20130417-00038-g03de9e2 #374) > [ 1.652313] PC is at omap3_l3_app_irq+0xa4/0x128 > [ 1.657165] LR is at handle_irq_event_percpu+0x50/0x1b4 > [ 1.662628] pc : [<c0287d84>] lr : [<c0082400>] psr: 20000193 > [ 1.662628] sp : c7057bd8 ip : c7057c08 fp : c073bc1e > [ 1.674652] r10: c70055b8 r9 : 3ccf0000 r8 : 0b6db6c3 > [ 1.680114] r7 : 00000000 r6 : 00000000 r5 : 00020000 r4 : 00000000 > [ 1.686950] r3 : 00020000 r2 : 00000004 r1 : f8000000 r0 : 00020000 > [ 1.693786] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user > [ 1.701354] Control: 10c5387d Table: 80004019 DAC: 00000015 > [ 1.707366] Process swapper (pid: 1, stack limit = 0xc7056238) > [ 1.713470] Stack: (0xc7057bd8 to 0xc7058000) > [ 1.718048] 7bc0: 00000000 60000193 > [ 1.726593] 7be0: 00000001 c7097a00 c7005590 00000000 00000000 0000001a c7005540 c70055b8 > [ 1.735168] 7c00: c073bc1e c0082400 c7056000 00000000 60000193 c7005540 c7005590 c7097a00 > [ 1.743713] 7c20: c073c814 ffffffff c7057e48 c7057e4c 00000000 c00825a0 c7005540 c7005590 > [ 1.752288] 7c40: 00000000 c0084aec 0000001a 0000001a 00000000 c00823a0 c071c5c4 c000a69c > [ 1.760864] 7c60: fa200000 0000001a c7057c88 c0008538 c04ef830 60000113 ffffffff c7057cbc > [ 1.769439] 7c80: ffffffff c00099c4 00000001 00000001 c7055440 00000000 c06e803c c7056000 > [ 1.778015] 7ca0: 0000000b 00000001 ffffffff c7057e48 c7057e4c 00000000 c7057ca8 c7057cd0 > [ 1.786590] 7cc0: c04ef828 c04ef830 60000113 ffffffff c7055440 c0033e90 60000193 c06e8540 > [ 1.795166] 7ce0: 0000000b c7057da0 ffffffff c000d3b0 00001008 c06e8fc4 c8852000 c00084c4 > [ 1.803741] 7d00: 00000000 c006ad30 00000007 00000000 00000000 c8852000 00000001 c0035abc > [ 1.812286] 7d20: c7006a90 00000001 00000000 00000004 ffff8b4a 00200140 60000193 c7056000 > [ 1.820861] 7d40: 00000035 00000000 01400000 c0087bd8 c071c5c4 00000006 00000000 c00099e8 > [ 1.829437] 7d60: c7055440 00000001 c7057dc4 00000000 c7056000 00000000 00000000 c006ad80 > [ 1.838043] 7d80: c0030afc 20000113 ffffffff c032d9a0 60000113 ffffffff c7057dd4 c000995c > [ 1.846588] 7da0: c72ce050 ffffffff 00000081 c8852000 c72ce050 000000ff ffffffff c72ce370 > [ 1.855163] 7dc0: ffffffff c7057e48 c7057e4c 00000000 c0331590 c7057de8 c0331704 c032d9a0 > [ 1.863739] 7de0: 60000113 ffffffff 00000000 c72ce370 c72ce050 00000000 c7057e18 c0331e74 > [ 1.872314] 7e00: 00000001 00000000 c72c7b80 c72ce000 c72ce050 00000002 00000000 c0c74054 > [ 1.880889] 7e20: c72ce370 c72ce050 00000000 00000001 00000002 0000008e c0702a20 c033242c > [ 1.889465] 7e40: c7057e48 00000000 c0637598 00000008 00000000 c72ce000 c72ce050 c700a690 > [ 1.898040] 7e60: 00000000 c0c74054 0000008e c03360b8 00000000 c72c7f50 c7120ef0 00000000 > [ 1.906646] 7e80: 00000000 c0702a20 c0702a28 c0c73628 c072a57c c0702a20 00000000 c072a57c > [ 1.915222] 7ea0: c06d12fc c02ef458 c0c73628 c02ee12c c0702a20 c072a57c c0702a54 00000000 > [ 1.923797] 7ec0: c06c709c c02ee2e4 c0702a20 c072a57c c0702a54 c02ee390 c072a57c c02ee2fc > [ 1.932373] 7ee0: c7057ee8 c02eca5c c704b2a8 c7115690 c704b2d8 c072a57c c0723888 c72ba640 > [ 1.940948] 7f00: 00000000 c02ed304 c05feb28 c072a57c c073bd40 c06d12f4 c072a57c c073bd40 > [ 1.949523] 7f20: 00000000 c02ee980 c06d12f4 c06db898 c073bd40 00000000 c06c709c c000874c > [ 1.958068] 7f40: 00000000 c06d12f4 00000006 c073bd40 c06d12f4 c06db898 c073bd40 00000007 > [ 1.966644] 7f60: c06aa3e8 c06aa2b0 00000006 00000006 c06aa3e8 00000000 c06db460 c06db460 > [ 1.975219] 7f80: 00000000 00000000 00000000 00000000 00000000 c06aa350 00000000 c04eb2c8 > [ 1.983795] 7fa0: 00000000 c04eb2d0 00000000 c0009ec8 00000000 00000000 00000000 00000000 > [ 1.992370] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > [ 2.000946] 7fe0: 00000000 00000000 00000000 00000000 00000013 00000000 1051a000 04440800 > [ 2.009521] [<c0287d84>] (omap3_l3_app_irq+0xa4/0x128) from [<c0082400>] (handle_irq_event_percpu+0x50/0x1b4) > [ 2.019897] [<c0082400>] (handle_irq_event_percpu+0x50/0x1b4) from [<c00825a0>] (handle_irq_event+0x3c/0x5c) > [ 2.030212] [<c00825a0>] (handle_irq_event+0x3c/0x5c) from [<c0084aec>] (handle_level_irq+0x8c/0x118) > [ 2.039886] [<c0084aec>] (handle_level_irq+0x8c/0x118) from [<c00823a0>] (generic_handle_irq+0x28/0x30) > [ 2.049713] [<c00823a0>] (generic_handle_irq+0x28/0x30) from [<c000a69c>] (handle_IRQ+0x30/0x84) > [ 2.058898] [<c000a69c>] (handle_IRQ+0x30/0x84) from [<c0008538>] (omap3_intc_handle_irq+0x64/0x74) > [ 2.068389] [<c0008538>] (omap3_intc_handle_irq+0x64/0x74) from [<c00099c4>] (__irq_svc+0x44/0x78) > [ 2.077758] Exception stack(0xc7057c88 to 0xc7057cd0) > [ 2.083038] 7c80: 00000001 00000001 c7055440 00000000 c06e803c c7056000 > [ 2.091613] 7ca0: 0000000b 00000001 ffffffff c7057e48 c7057e4c 00000000 c7057ca8 c7057cd0 > [ 2.100189] 7cc0: c04ef828 c04ef830 60000113 ffffffff > [ 2.105468] [<c00099c4>] (__irq_svc+0x44/0x78) from [<c04ef830>] (_raw_spin_unlock_irq+0x2c/0x50) > [ 2.114776] [<c04ef830>] (_raw_spin_unlock_irq+0x2c/0x50) from [<c0033e90>] (do_exit+0x268/0x358) > [ 2.124084] [<c0033e90>] (do_exit+0x268/0x358) from [<c000d3b0>] (oops_end+0xb8/0xe8) > [ 2.132293] [<c000d3b0>] (oops_end+0xb8/0xe8) from [<c00084c4>] (do_DataAbort+0x88/0x98) > [ 2.140777] [<c00084c4>] (do_DataAbort+0x88/0x98) from [<c000995c>] (__dabt_svc+0x3c/0x60) > [ 2.149414] Exception stack(0xc7057da0 to 0xc7057de8) > [ 2.154693] 7da0: c72ce050 ffffffff 00000081 c8852000 c72ce050 000000ff ffffffff c72ce370 > [ 2.163269] 7dc0: ffffffff c7057e48 c7057e4c 00000000 c0331590 c7057de8 c0331704 c032d9a0 > [ 2.171844] 7de0: 60000113 ffffffff > [ 2.175506] [<c000995c>] (__dabt_svc+0x3c/0x60) from [<c032d9a0>] (nand_read_byte16+0x8/0x1c) > [ 2.184417] [<c032d9a0>] (nand_read_byte16+0x8/0x1c) from [<c0331704>] (nand_command+0x174/0x1ec) > [ 2.193725] [<c0331704>] (nand_command+0x174/0x1ec) from [<c0331e74>] (nand_get_flash_type+0x4c/0x5b8) > [ 2.203460] [<c0331e74>] (nand_get_flash_type+0x4c/0x5b8) from [<c033242c>] (nand_scan_ident+0x4c/0x1a8) > [ 2.213378] [<c033242c>] (nand_scan_ident+0x4c/0x1a8) from [<c03360b8>] (omap_nand_probe+0x2dc/0x6dc) > [ 2.223052] [<c03360b8>] (omap_nand_probe+0x2dc/0x6dc) from [<c02ef458>] (platform_drv_probe+0x18/0x1c) > [ 2.232879] [<c02ef458>] (platform_drv_probe+0x18/0x1c) from [<c02ee12c>] (really_probe+0x70/0x1f8) > [ 2.242370] [<c02ee12c>] (really_probe+0x70/0x1f8) from [<c02ee2e4>] (driver_probe_device+0x30/0x48) > [ 2.251953] [<c02ee2e4>] (driver_probe_device+0x30/0x48) from [<c02ee390>] (__driver_attach+0x94/0x98) > [ 2.261718] [<c02ee390>] (__driver_attach+0x94/0x98) from [<c02eca5c>] (bus_for_each_dev+0x74/0x98) > [ 2.271179] [<c02eca5c>] (bus_for_each_dev+0x74/0x98) from [<c02ed304>] (bus_add_driver+0x1c8/0x234) > [ 2.280761] [<c02ed304>] (bus_add_driver+0x1c8/0x234) from [<c02ee980>] (driver_register+0x78/0x140) > [ 2.290344] [<c02ee980>] (driver_register+0x78/0x140) from [<c000874c>] (do_one_initcall+0xc0/0x134) > [ 2.299926] [<c000874c>] (do_one_initcall+0xc0/0x134) from [<c06aa2b0>] (do_basic_setup+0x84/0xc4) > [ 2.309295] [<c06aa2b0>] (do_basic_setup+0x84/0xc4) from [<c06aa350>] (kernel_init_freeable+0x60/0xf8) > [ 2.319061] [<c06aa350>] (kernel_init_freeable+0x60/0xf8) from [<c04eb2d0>] (kernel_init+0x8/0xe4) > [ 2.328460] [<c04eb2d0>] (kernel_init+0x8/0xe4) from [<c0009ec8>] (ret_from_fork+0x14/0x2c) > [ 2.337219] Code: e5911008 e2813e53 e1c320d0 eaffffe8 (e7f001f2) > [ 2.343597] ---[ end trace 7ab5f8dfed0385fe ]--- > [ 2.348419] Kernel panic - not syncing: Fatal exception in interrupt I don't see any other errors in the log. So I am wondering if the chip-select mapping is setup correctly. Can you share a dump of the gpmc registers from u-boot? Cheers Jon ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-18 22:28 ` Jon Hunter @ 2013-04-18 22:48 ` Christoph Fritz 2013-04-18 23:24 ` Jon Hunter 0 siblings, 1 reply; 19+ messages in thread From: Christoph Fritz @ 2013-04-18 22:48 UTC (permalink / raw) To: Jon Hunter; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On Thu, 2013-04-18 at 17:28 -0500, Jon Hunter wrote: > On 04/18/2013 03:23 PM, Christoph Fritz wrote: > > OMAP3_EVM # md 0x6E000060 7 > > 6e000060: 00001800 00141400 00141400 0f010f01 ................ > > 6e000070: 010c1414 1f0f0a80 00000870 ........p... > > I don't see any other errors in the log. So I am wondering if the > chip-select mapping is setup correctly. Can you share a dump of the gpmc > registers from u-boot? I already did, please see the "md 0x6E000060 7" from above. Below is my work-sheet how I configured the values: --- To get the values right for dt-GPMC-NAND-Config, here are the GPMC config registers for chip-select 0, they are taken from u-boot by doing "md 0x6E000060 7" on the u-boot shell: GPMC_CONFIG1: 0x6e000060: 0x00001800 GPMC_CONFIG2: 0x6e000064: 0x00141400 GPMC_CONFIG3: 0x6e000068: 0x00141400 GPMC_CONFIG4: 0x6e00006c: 0x0F010F01 GPMC_CONFIG5: 0x6e000070: 0x010C1414 GPMC_CONFIG6: 0x6e000074: 0x1F0F0A80 GPMC_CONFIG7: 0x6e000078: 0x00000870 and analyzed by datasheet (TRM page 2210): GPMC_CONFIG7 0x00000870: |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | 1| 0| 0| 0| 0| 1| 1| 1| 0| 0| 0| 0| 5:0 BASEADDR: 0x4 (reg addr: 0x30000000) dT: not supported CSi base address 6 CSVALID: 1 dT: not supported CS enable 11:8 MASKADDRESS: 0x1000: Chip-select size of 128 Mbytes dT: not supported CS mask address GPMC_CONFIG6 0x1F0F0A80: |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| | 0| 0| 0| 1| 1| 1| 1| 1| 0| 0| 0| 0| 1| 1| 1| 1| |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | 0| 0| 0| 0| 1| 0| 1| 0| 1| 0| 0| 0| 0| 0| 0| 0| 28:24 WRACCESSTIME: 0x1F: 31 GPMC_FCLK cycles dT: "gpmc,wr-access-ns = <0x1F>;" (0x0 to 0x1F) used by the attached memory for the first data capture 19:16 WRDATAONADMUXBUS: 0xF dT: "gpmc,wr-data-mux-bus-ns = <0xF>;" (0x0 to 0xF) Specifies on which GPMC_FCLK rising edge the first data is driven in the add/data mux bus 11:8 CYCLE2CYCLEDELAY: 0xA GPMC_FCLK cycles dT: "gpmc,cycle2cycle-delay-ns = <0xA>;" (0x0 to 0xF) Chip-select high pulse delay between successive accesses 7 CYCLE2CYCLESAMECSEN: 0x1: Add CYCLE2CYCLEDELAY dT: "gpmc,cycle2cycle-samecsen = <0x1>;" (bool) Add CYCLE2CYCLEDELAY between successive accesses to the same CS (any access type) 6 CYCLE2CYCLEDIFFCSEN: 0x0: No delay between the two accesses dT: "gpmc,cycle2cycle-diffcsen = <0x0>;" (bool) Add CYCLE2CYCLEDELAY between successive accesses to a different CS (any access type) 3:0 BUSTURNAROUND: 0x0: 0 GPMC_FCLK cycle dT: "gpmc,bus-turnaround-ns = <0x0>;" (0x0 to 0xF) Bus turn around latency between successive accesses to the same CS (read to write) or to a different CS (read to read and read to write) GPMC_CONFIG5 0x010C1414: |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| | 0| 0| 0| 0| 0| 0| 0| 1| 0| 0| 0| 0| 1| 1| 0| 0| |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | 0| 0| 0| 1| 0| 1| 0| 0| 0| 0| 0| 1| 0| 1| 0| 0| 27:24 PAGEBURSTACCESSTIME: 0x1: 1 GPMC_FCLK cycle dT: "gpmc,page-burst-access-ns = <0x1>;" (0x0 to 0xF) Delay between successive words in a multiple access 20:16 RDACCESSTIME: 0xC: 12 GPMC_FCLK cycles dT: "gpmc,access-ns = <0xC>;" (0x0 to 0x1F) Delay between start cycle time and first data valid 12:8 WRCYCLETIME: 0x14: 20 GPMC_FCLK cycles dT: "gpmc,wr-cycle-ns = <0x14>;" (0x0 to 0x1F) Total write cycle time 4:0 RDCYCLETIME: 0x14: 20 GPMC_FCLK cycles dT: "gpmc,rd-cycle-ns = <0x14>;" (0x0 to 0x1F) Total read cycle time GPMC_CONFIG4 0x0F010F01: |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| | 0| 0| 0| 0| 1| 1| 1| 1| 0| 0| 0| 0| 0| 0| 0| 1| |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | 0| 0| 0| 0| 1| 1| 1| 1| 0| 0| 0| 0| 0| 0| 0| 1| 28:24 WEOFFTIME: 0xF: 16 GPMC_FCLK cycle dT: "gpmc,we-off-ns = <0xF>;" (0x0 to 0x1F) nWE de-assertion time from start cycle time 23 WEEXTRADELAY: 0x0: nWE Timing control signal is not delayed dT: "gpmc,we-extra-delay = <0>;" (bool) nWE Add Extra Half GPMC_FCLK cycle 19:16 WEONTIME: 0x1: 1 GPMC_FCLK cycle dT: "gpmc,we-on-ns = <0x1>;" (0x0 to 0x1F) nWE assertion time from start cycle time 12:8 OEOFFTIME: 0xF: 15 GPMC_FCLK cycles dT: "gpmc,oe-off-ns = <0xF>;" (0x0 to 0x1F) nOE de-assertion time from start cycle time 7 OEEXTRADELAY: 0x0: nOE Timing control signal is not delayed dT: "gpmc,oe-extra-delay = <0>;" (bool) nOE Add Extra Half GPMC_FCLK cycle 3:0 OEONTIME: 0x1: 1 GPMC_FCLK cycle dT: "gpmc,oe-on-ns = <0x1>;" (0x0 to 0x1F) nOE assertion time from start cycle time GPMC_CONFIG3 0x00141400: |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| | 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 1| 0| 1| 0| 0| |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | 0| 0| 0| 1| 0| 1| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 20:16 ADVWROFFTIME: 0x14: 20 GPMC_FCLK cycles dT: "gpmc,adv-wr-off-ns = <0x14>;" (0x0 to 0x1F) nADV de-assertion time from start cycle time for write accesses 12:8 ADVRDOFFTIME: 0x14: 20 GPMC_FCLK cycles dT: "gpmc,adv-rd-off-ns = <0x14>;" (0x0 to 0x1F) nADV de-assertion time from start cycle time for read accesses 7 ADVEXTRADELAY: 0x0: nADV Timing control signal is not delayed dT: "gpmc,adv-extra-delay = <0>;" (bool) nADV Add Extra Half GPMC_FCLK cycle 3:0 ADVONTIME: 0x0: 0 GPMC_FCLK cycle dT: "gpmc,adv-on-ns = <0>;" (0x0 to 0xF) nADV assertion time from start cycle time GPMC_CONFIG2 0x00141400: |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| | 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 1| 0| 1| 0| 0| |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | 0| 0| 0| 1| 0| 1| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 20:16 CSWROFFTIME: 0x14: 20 GPMC_FCLK cycles dT: "gpmc,cs-wr-off-ns = <0x14>;" (0x0 to 0x1F) CS i de-assertion time from start cycle time for write accesses 12:8 CSRDOFFTIME: 0x14: 20 GPMC_FCLK cycles dT: "gpmc,cs-rd-off-ns = <0x14>;" (0x0 to 0x1F) CS i de-assertion time from start cycle time for read accesses 7 CSEXTRADELAY: 0x0: CS i Timing control signal is not delayed dT: "gpmc,cs-extra-delay = <0>;" (bool) CS i Add Extra Half GPMC_FCLK cycle 3:0 CSONTIME: 0x0: 0 GPMC_FCLK cycle dT: "gpmc,cs-on-ns = <0>;" (0x0 to 0xF) CS i assertion time from start cycle time GPMC_CONFIG1 0x00001800: |12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| | 1| 1| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 31 WRAPBURST: 0x0: Synchronous wrapping burst not supported dT: "gpmc,burst-wrap = <0>;" (bool) Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst 30 READMULTIPLE: 0x0: Single access dT: "gpmc,burst-read = <0>;" (bool) Selects the read single or multiple access 29 READTYPE: 0x0: Read Asynchronous dT: "gpmc,sync-read = <0>;" (bool) Selects the read mode operation 28 WRITEMULTIPLE: 0x0: Single access dT: "gpmc,burst-write = <0>;" (bool) Selects the write single or multiple access 27 WRITETYPE: 0x0: Write Asynchronous dT: "gpmc,sync-write = <0>;" (bool) Selects the write mode operation 26:25 CLKACTIVATIONTIME: 0x0: First rising edge of GPMC_CLK at start access time dT: not supported Output GPMC_CLK activation time 24:23 ATTACHEDDEVICEPAGE LENGTH: 0x0: 4 Words dT: "gpmc,burst-length= <4>;" (4, 8 or 16) Specifies the attached device page (burst) length 22 WAITREADMONITORING: 0x0: Wait pin is not monitored for read accesses dT: "gpmc,wait-on-read = <0>;" (bool) Selects the Wait monitoring configuration for Read accesses (Reset value is BOOTWAITEN input pin sampled at IC reset) 21 WAITWRITEMONITORING: 0x0: Wait pin is not monitored for write accesses dT: "gpmc,wait-on-write = <0>;" (bool) Selects the Wait monitoring configuration for Write accesses 19:18 WAITMONITORINGTIME: 0x0: Wait pin is monitored with valid data dT: not supported Selects input pin Wait monitoring time 17:16 WAITPINSELECT: 0x0: Wait input pin is WAIT0 dT: "gpmc,wait-pin = <0>;" (0 to 3) Selects the input WAIT pin for this chip-select (Reset value is BOOTWAITSELECT input pin sampled at IC reset for CS0 and 0 for CS1-7) 13:12 DEVICESIZE: 0x1: 16 bit dT: "gpmc,device-width = <2>;" (1 or 2) Selects the device size attached (Reset value is BOOTDEVICESIZE input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) 11:10 DEVICETYPE: 0x2: NAND Flash like devices, stream mode dT: "gpmc,device-nand = <1>;" (bool) Selects the attached device type 9 MUXADDDATA: 0x0: Non Multiplexed attached device dT: "gpmc,mux-add-data = <0>;" (0 or 1 or 2) Enables the Address and data multiplexed protocol (Reset value is CS0MUXDEVICE input pin sampled at IC reset for CS0 and 0 for CS1-7) 4 TIMEPARAGRANULARITY: 0x0: x1 latencies dT: "gpmc,time-para-granularity = <0>;" (bool) Signals timing latencies scalar factor (Rd/WrCycleTime, Rd/WrAccessTime, PageBurstAccessTime, CSOnTime, CSRd/WrOffTime, ADVOnTime, ADVRd/WrOffTime, OEOnTime, OEOffTime, WEOnTime, WEOffTime, Cycle2CycleDelay, BusTurnAround, TimeOutStartValue) 1:0 GPMCFCLKDIVIDER: 0x0: GPMC_CLK frequency = GPMC_FCLK frequency dT: not supported Divides the GPMC_FCLK clock ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-18 22:48 ` Christoph Fritz @ 2013-04-18 23:24 ` Jon Hunter 2013-04-18 23:26 ` Jon Hunter 0 siblings, 1 reply; 19+ messages in thread From: Jon Hunter @ 2013-04-18 23:24 UTC (permalink / raw) To: Christoph Fritz; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On 04/18/2013 05:48 PM, Christoph Fritz wrote: > On Thu, 2013-04-18 at 17:28 -0500, Jon Hunter wrote: >> On 04/18/2013 03:23 PM, Christoph Fritz wrote: > > >>> OMAP3_EVM # md 0x6E000060 7 >>> 6e000060: 00001800 00141400 00141400 0f010f01 ................ >>> 6e000070: 010c1414 1f0f0a80 00000870 ........p... > >> >> I don't see any other errors in the log. So I am wondering if the >> chip-select mapping is setup correctly. Can you share a dump of the gpmc >> registers from u-boot? > > I already did, please see the "md 0x6E000060 7" from above. Below is my > work-sheet how I configured the values: Sorry I missed that. > --- > > To get the values right for dt-GPMC-NAND-Config, here are the GPMC > config registers for chip-select 0, they are taken from u-boot > by doing "md 0x6E000060 7" on the u-boot shell: > > GPMC_CONFIG1: 0x6e000060: 0x00001800 > GPMC_CONFIG2: 0x6e000064: 0x00141400 > GPMC_CONFIG3: 0x6e000068: 0x00141400 > GPMC_CONFIG4: 0x6e00006c: 0x0F010F01 > GPMC_CONFIG5: 0x6e000070: 0x010C1414 > GPMC_CONFIG6: 0x6e000074: 0x1F0F0A80 > GPMC_CONFIG7: 0x6e000078: 0x00000870 > > and analyzed by datasheet (TRM page 2210): > > GPMC_CONFIG7 0x00000870: > |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| > | 1| 0| 0| 0| 0| 1| 1| 1| 0| 0| 0| 0| > > 5:0 BASEADDR: 0x4 (reg addr: 0x30000000) Base address looks fine. > dT: not supported > CSi base address > 6 CSVALID: 1 > dT: not supported > CS enable > 11:8 MASKADDRESS: 0x1000: Chip-select size of 128 Mbytes > dT: not supported > CS mask address > > GPMC_CONFIG6 0x1F0F0A80: > |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| > | 0| 0| 0| 1| 1| 1| 1| 1| 0| 0| 0| 0| 1| 1| 1| 1| > > |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| > | 0| 0| 0| 0| 1| 0| 1| 0| 1| 0| 0| 0| 0| 0| 0| 0| > > 28:24 WRACCESSTIME: 0x1F: 31 GPMC_FCLK cycles > dT: "gpmc,wr-access-ns = <0x1F>;" (0x0 to 0x1F) > used by the attached memory for the first data capture > > 19:16 WRDATAONADMUXBUS: 0xF > dT: "gpmc,wr-data-mux-bus-ns = <0xF>;" (0x0 to 0xF) > Specifies on which GPMC_FCLK rising edge the first data is > driven in the add/data mux bus > > 11:8 CYCLE2CYCLEDELAY: 0xA GPMC_FCLK cycles > dT: "gpmc,cycle2cycle-delay-ns = <0xA>;" (0x0 to 0xF) > Chip-select high pulse delay between successive accesses > > 7 CYCLE2CYCLESAMECSEN: 0x1: Add CYCLE2CYCLEDELAY > dT: "gpmc,cycle2cycle-samecsen = <0x1>;" (bool) > Add CYCLE2CYCLEDELAY between successive accesses > to the same CS (any access type) > > 6 CYCLE2CYCLEDIFFCSEN: 0x0: No delay between the two accesses > dT: "gpmc,cycle2cycle-diffcsen = <0x0>;" (bool) > Add CYCLE2CYCLEDELAY between successive accesses > to a different CS (any access type) > > 3:0 BUSTURNAROUND: 0x0: 0 GPMC_FCLK cycle > dT: "gpmc,bus-turnaround-ns = <0x0>;" (0x0 to 0xF) > Bus turn around latency between successive accesses to > the same CS (read to write) or to a different CS (read to > read and read to write) > > GPMC_CONFIG5 0x010C1414: > |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| > | 0| 0| 0| 0| 0| 0| 0| 1| 0| 0| 0| 0| 1| 1| 0| 0| > > |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| > | 0| 0| 0| 1| 0| 1| 0| 0| 0| 0| 0| 1| 0| 1| 0| 0| > > 27:24 PAGEBURSTACCESSTIME: 0x1: 1 GPMC_FCLK cycle > dT: "gpmc,page-burst-access-ns = <0x1>;" (0x0 to 0xF) > Delay between successive words in a multiple access > > 20:16 RDACCESSTIME: 0xC: 12 GPMC_FCLK cycles > dT: "gpmc,access-ns = <0xC>;" (0x0 to 0x1F) > Delay between start cycle time and first data valid > > 12:8 WRCYCLETIME: 0x14: 20 GPMC_FCLK cycles > dT: "gpmc,wr-cycle-ns = <0x14>;" (0x0 to 0x1F) > Total write cycle time > > 4:0 RDCYCLETIME: 0x14: 20 GPMC_FCLK cycles > dT: "gpmc,rd-cycle-ns = <0x14>;" (0x0 to 0x1F) > Total read cycle time > > GPMC_CONFIG4 0x0F010F01: > |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| > | 0| 0| 0| 0| 1| 1| 1| 1| 0| 0| 0| 0| 0| 0| 0| 1| > > |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| > | 0| 0| 0| 0| 1| 1| 1| 1| 0| 0| 0| 0| 0| 0| 0| 1| > > 28:24 WEOFFTIME: 0xF: 16 GPMC_FCLK cycle > dT: "gpmc,we-off-ns = <0xF>;" (0x0 to 0x1F) > nWE de-assertion time from start cycle time > > 23 WEEXTRADELAY: 0x0: nWE Timing control signal is not delayed > dT: "gpmc,we-extra-delay = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > nWE Add Extra Half GPMC_FCLK cycle > > 19:16 WEONTIME: 0x1: 1 GPMC_FCLK cycle > dT: "gpmc,we-on-ns = <0x1>;" (0x0 to 0x1F) > nWE assertion time from start cycle time > > 12:8 OEOFFTIME: 0xF: 15 GPMC_FCLK cycles > dT: "gpmc,oe-off-ns = <0xF>;" (0x0 to 0x1F) > nOE de-assertion time from start cycle time > > 7 OEEXTRADELAY: 0x0: nOE Timing control signal is not delayed > dT: "gpmc,oe-extra-delay = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > nOE Add Extra Half GPMC_FCLK cycle > > 3:0 OEONTIME: 0x1: 1 GPMC_FCLK cycle > dT: "gpmc,oe-on-ns = <0x1>;" (0x0 to 0x1F) > nOE assertion time from start cycle time > > GPMC_CONFIG3 0x00141400: > |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| > | 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 1| 0| 1| 0| 0| > > |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| > | 0| 0| 0| 1| 0| 1| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| > > 20:16 ADVWROFFTIME: 0x14: 20 GPMC_FCLK cycles > dT: "gpmc,adv-wr-off-ns = <0x14>;" (0x0 to 0x1F) > nADV de-assertion time from start cycle time for write accesses > > 12:8 ADVRDOFFTIME: 0x14: 20 GPMC_FCLK cycles > dT: "gpmc,adv-rd-off-ns = <0x14>;" (0x0 to 0x1F) > nADV de-assertion time from start cycle time for read accesses > > 7 ADVEXTRADELAY: 0x0: nADV Timing control signal is not delayed > dT: "gpmc,adv-extra-delay = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > nADV Add Extra Half GPMC_FCLK cycle > > 3:0 ADVONTIME: 0x0: 0 GPMC_FCLK cycle > dT: "gpmc,adv-on-ns = <0>;" (0x0 to 0xF) > nADV assertion time from start cycle time > > GPMC_CONFIG2 0x00141400: > |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| > | 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 1| 0| 1| 0| 0| > > |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| > | 0| 0| 0| 1| 0| 1| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| > > 20:16 CSWROFFTIME: 0x14: 20 GPMC_FCLK cycles > dT: "gpmc,cs-wr-off-ns = <0x14>;" (0x0 to 0x1F) > CS i de-assertion time from start cycle time for write accesses > > 12:8 CSRDOFFTIME: 0x14: 20 GPMC_FCLK cycles > dT: "gpmc,cs-rd-off-ns = <0x14>;" (0x0 to 0x1F) > CS i de-assertion time from start cycle time for read accesses > > 7 CSEXTRADELAY: 0x0: CS i Timing control signal is not delayed > dT: "gpmc,cs-extra-delay = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > CS i Add Extra Half GPMC_FCLK cycle > > 3:0 CSONTIME: 0x0: 0 GPMC_FCLK cycle > dT: "gpmc,cs-on-ns = <0>;" (0x0 to 0xF) > CS i assertion time from start cycle time > > GPMC_CONFIG1 0x00001800: > |12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| > | 1| 1| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| > > 31 WRAPBURST: 0x0: Synchronous wrapping burst not supported > dT: "gpmc,burst-wrap = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > Enables the wrapping burst capability. Must be set if the > attached device is configured in wrapping burst > > 30 READMULTIPLE: 0x0: Single access > dT: "gpmc,burst-read = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > Selects the read single or multiple access > > 29 READTYPE: 0x0: Read Asynchronous > dT: "gpmc,sync-read = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > Selects the read mode operation > > 28 WRITEMULTIPLE: 0x0: Single access > dT: "gpmc,burst-write = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > Selects the write single or multiple access > > 27 WRITETYPE: 0x0: Write Asynchronous > dT: "gpmc,sync-write = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > Selects the write mode operation > > 26:25 CLKACTIVATIONTIME: 0x0: First rising edge of GPMC_CLK at start > access time > dT: not supported > Output GPMC_CLK activation time > > 24:23 ATTACHEDDEVICEPAGE LENGTH: 0x0: 4 Words > dT: "gpmc,burst-length= <4>;" (4, 8 or 16) > Specifies the attached device page (burst) length > > 22 WAITREADMONITORING: 0x0: Wait pin is not monitored for read accesses > dT: "gpmc,wait-on-read = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > Selects the Wait monitoring configuration for Read accesses > (Reset value is BOOTWAITEN input pin sampled at IC reset) > > 21 WAITWRITEMONITORING: 0x0: Wait pin is not monitored for write accesses > dT: "gpmc,wait-on-write = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > Selects the Wait monitoring configuration for Write accesses > > 19:18 WAITMONITORINGTIME: 0x0: Wait pin is monitored with valid data > dT: not supported > Selects input pin Wait monitoring time It is supported, see gpmc,wait-monitoring-ns. > > 17:16 WAITPINSELECT: 0x0: Wait input pin is WAIT0 > dT: "gpmc,wait-pin = <0>;" (0 to 3) > Selects the input WAIT pin for this chip-select (Reset value > is BOOTWAITSELECT input pin sampled at IC reset for > CS0 and 0 for CS1-7) > > 13:12 DEVICESIZE: 0x1: 16 bit > dT: "gpmc,device-width = <2>;" (1 or 2) > Selects the device size attached (Reset value is > BOOTDEVICESIZE input pin sampled at IC reset for CS0 > and 0x1 for CS1 to CS7) > > 11:10 DEVICETYPE: 0x2: NAND Flash like devices, stream mode > dT: "gpmc,device-nand = <1>;" (bool) > Selects the attached device type > > 9 MUXADDDATA: 0x0: Non Multiplexed attached device > dT: "gpmc,mux-add-data = <0>;" (0 or 1 or 2) > Enables the Address and data multiplexed protocol (Reset > value is CS0MUXDEVICE input pin sampled at IC reset for > CS0 and 0 for CS1-7) > > 4 TIMEPARAGRANULARITY: 0x0: x1 latencies > dT: "gpmc,time-para-granularity = <0>;" (bool) You should omit this property, the above will enable it as it is a boolean property. > Signals timing latencies scalar factor (Rd/WrCycleTime, > Rd/WrAccessTime, PageBurstAccessTime, CSOnTime, > CSRd/WrOffTime, ADVOnTime, ADVRd/WrOffTime, > OEOnTime, OEOffTime, WEOnTime, WEOffTime, > Cycle2CycleDelay, BusTurnAround, TimeOutStartValue) > > 1:0 GPMCFCLKDIVIDER: 0x0: GPMC_CLK frequency = GPMC_FCLK frequency > dT: not supported > Divides the GPMC_FCLK clock In general if a property is boolean and you do not want it enabled, leave it out completely. For boolean we just check for the presence of the property and not value it has been assigned (see of_property_read_bool()). The GPMC device-tree binding documentation (ti-gpmc.txt) states ... "Boolean timing parameters. If property is present parameter enabled and disabled if omitted". Cheers Jon ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-18 23:24 ` Jon Hunter @ 2013-04-18 23:26 ` Jon Hunter 2013-04-19 9:01 ` Christoph Fritz 0 siblings, 1 reply; 19+ messages in thread From: Jon Hunter @ 2013-04-18 23:26 UTC (permalink / raw) To: Christoph Fritz; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On 04/18/2013 06:24 PM, Jon Hunter wrote: > > On 04/18/2013 05:48 PM, Christoph Fritz wrote: >> On Thu, 2013-04-18 at 17:28 -0500, Jon Hunter wrote: >>> On 04/18/2013 03:23 PM, Christoph Fritz wrote: >> >> >>>> OMAP3_EVM # md 0x6E000060 7 >>>> 6e000060: 00001800 00141400 00141400 0f010f01 ................ >>>> 6e000070: 010c1414 1f0f0a80 00000870 ........p... >> >>> >>> I don't see any other errors in the log. So I am wondering if the >>> chip-select mapping is setup correctly. Can you share a dump of the gpmc >>> registers from u-boot? >> >> I already did, please see the "md 0x6E000060 7" from above. Below is my >> work-sheet how I configured the values: > > Sorry I missed that. > >> --- >> >> To get the values right for dt-GPMC-NAND-Config, here are the GPMC >> config registers for chip-select 0, they are taken from u-boot >> by doing "md 0x6E000060 7" on the u-boot shell: >> >> GPMC_CONFIG1: 0x6e000060: 0x00001800 >> GPMC_CONFIG2: 0x6e000064: 0x00141400 >> GPMC_CONFIG3: 0x6e000068: 0x00141400 >> GPMC_CONFIG4: 0x6e00006c: 0x0F010F01 >> GPMC_CONFIG5: 0x6e000070: 0x010C1414 >> GPMC_CONFIG6: 0x6e000074: 0x1F0F0A80 >> GPMC_CONFIG7: 0x6e000078: 0x00000870 I would advise you dump the gpmc registers at the end of the gpmc probe. I am sure you will see something completely different to the above based upon your dt configuration. Cheers Jon ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-18 23:26 ` Jon Hunter @ 2013-04-19 9:01 ` Christoph Fritz 2013-04-19 12:02 ` Christoph Fritz 2013-04-19 12:57 ` ARM: dts: omap3: NAND support - how? Jon Hunter 0 siblings, 2 replies; 19+ messages in thread From: Christoph Fritz @ 2013-04-19 9:01 UTC (permalink / raw) To: Jon Hunter; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On Thu, 2013-04-18 at 18:26 -0500, Jon Hunter wrote: > On 04/18/2013 06:24 PM, Jon Hunter wrote: > >> To get the values right for dt-GPMC-NAND-Config, here are the GPMC > >> config registers for chip-select 0, they are taken from u-boot > >> by doing "md 0x6E000060 7" on the u-boot shell: > >> > >> GPMC_CONFIG1: 0x6e000060: 0x00001800 > >> GPMC_CONFIG2: 0x6e000064: 0x00141400 > >> GPMC_CONFIG3: 0x6e000068: 0x00141400 > >> GPMC_CONFIG4: 0x6e00006c: 0x0F010F01 > >> GPMC_CONFIG5: 0x6e000070: 0x010C1414 > >> GPMC_CONFIG6: 0x6e000074: 0x1F0F0A80 > >> GPMC_CONFIG7: 0x6e000078: 0x00000870 > > > I would advise you dump the gpmc registers at the end of the gpmc probe. > I am sure you will see something completely different to the above based > upon your dt configuration. Thanks to your help this is my new gpmc dt config: &gpmc { ranges = <0 0 0x30000000 0x1000000>; nand@0,0 { reg = <0 0 0x1000000>; nand-bus-width = <16>; ti,nand-ecc-opt = "hw"; /* no elm on omap3 */ gpmc,mux-add-data = <0>; gpmc,device-nand; gpmc,device-width = <2>; gpmc,wait-pin = <0>; gpmc,wait-monitoring-ns = <0x0>; gpmc,burst-length= <4>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <0x14>; gpmc,cs-wr-off-ns = <0x14>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <0x14>; gpmc,adv-wr-off-ns = <0x14>; gpmc,oe-on-ns = <0x1>; gpmc,oe-off-ns = <0xf>; gpmc,we-on-ns = <0x1>; gpmc,we-off-ns = <0xf>; gpmc,rd-cycle-ns = <0x14>; gpmc,wr-cycle-ns = <0x14>; gpmc,access-ns = <0xc>; gpmc,page-burst-access-ns = <0x1>; gpmc,bus-turnaround-ns = <0x0>; gpmc,cycle2cycle-samecsen = <0x1>; gpmc,cycle2cycle-delay-ns = <0xa>; gpmc,wr-data-mux-bus-ns = <0xf>; gpmc,wr-access-ns = <0x1f>; }; }; As suggested I added some printks to kernel gpmc-subsystem to compare the gpmc config registers. [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine: Generic OMAP3 (Flattened Device Tree), model: INCOstartec LILLY-DBB056 (DM3730) [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] CPU: All CPU(s) started in SVC mode. [ 0.000000] OMAP3630 ES1.2 (l2cache iva neon isp 192mhz_clk ) [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256 [ 0.000000] Kernel command line: console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0 root=/dev/nfs ip=dhcp [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Memory: 127MB = 127MB total [ 0.000000] Memory: 116040k/116040k available, 15032k reserved, 0K highmem [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB) [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc06a9fa8 (6792 kB) [ 0.000000] .init : 0xc06aa000 - 0xc06db9ec ( 199 kB) [ 0.000000] .data : 0xc06dc000 - 0xc073bd20 ( 384 kB) [ 0.000000] .bss : 0xc073bd20 - 0xc0c7e414 (5386 kB) [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts [ 0.000000] Total of 96 interrupts on 1 active controller [ 0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz [ 0.000000] OMAP clockevent source: timer1 at 32768 Hz [ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms [ 0.000000] OMAP clocksource: 32k_counter at 32768 Hz [ 0.000000] Console: colour dummy device 80x30 [ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8 [ 0.000000] ... MAX_LOCK_DEPTH: 48 [ 0.000000] ... MAX_LOCKDEP_KEYS: 8191 [ 0.000000] ... CLASSHASH_SIZE: 4096 [ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384 [ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768 [ 0.000000] ... CHAINHASH_SIZE: 16384 [ 0.000000] memory used by lock dependency info: 3695 kB [ 0.000000] per task-struct memory footprint: 1152 bytes [ 0.001037] Calibrating delay loop... 398.13 BogoMIPS (lpj=1990656) [ 0.119659] pid_max: default: 4096 minimum: 301 [ 0.119964] Security Framework initialized [ 0.120086] Mount-cache hash table entries: 512 [ 0.135314] CPU: Testing write buffer coherency: ok [ 0.136810] Setting up static identity map for 0xc04efee8 - 0xc04eff40 [ 0.141418] devtmpfs: initialized [ 0.197814] pinctrl core: initialized pinctrl subsystem [ 0.201232] regulator-dummy: no parameters [ 0.202972] NET: Registered protocol family 16 [ 0.203704] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.211700] Reprogramming SDRC clock to 400000000 Hz [ 0.229248] pinctrl-single 48002030.pinmux: 742 pins at pa fa002030 size 1484 [ 0.231140] pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92 [ 0.234588] OMAP GPIO hardware version 2.5 [ 0.252685] platform 49022000.mcbsp: alias fck already exists [ 0.253540] platform 49024000.mcbsp: alias fck already exists [ 0.261749] omap-gpmc 6e000000.gpmc: GPMC revision 5.0 [ 0.262084] gpmc_write_reg(), 176, [ 0.262115] gpmc_ch_dump_reg, 1836, GPMC_CS_CONFIG1 0x00001800 [ 0.262115] gpmc_ch_dump_reg, 1838, GPMC_CS_CONFIG2 0x00141400 [ 0.262145] gpmc_ch_dump_reg, 1840, GPMC_CS_CONFIG3 0x00141400 [ 0.262145] gpmc_ch_dump_reg, 1842, GPMC_CS_CONFIG4 0x0f010f01 [ 0.262176] gpmc_ch_dump_reg, 1844, GPMC_CS_CONFIG5 0x010c1414 [ 0.262176] gpmc_ch_dump_reg, 1846, GPMC_CS_CONFIG6 0x1f0f0a80 [ 0.262207] gpmc_ch_dump_reg, 1848, GPMC_CS_CONFIG7 0x00000870 [ 0.262207] gpmc_write_reg(), 176, [ 0.262237] gpmc_ch_dump_reg, 1836, GPMC_CS_CONFIG1 0x00001800 [ 0.262237] gpmc_ch_dump_reg, 1838, GPMC_CS_CONFIG2 0x00141400 [ 0.262237] gpmc_ch_dump_reg, 1840, GPMC_CS_CONFIG3 0x00141400 [ 0.262268] gpmc_ch_dump_reg, 1842, GPMC_CS_CONFIG4 0x0f010f01 [ 0.262268] gpmc_ch_dump_reg, 1844, GPMC_CS_CONFIG5 0x010c1414 [ 0.262298] gpmc_ch_dump_reg, 1846, GPMC_CS_CONFIG6 0x1f0f0a80 [ 0.262298] gpmc_ch_dump_reg, 1848, GPMC_CS_CONFIG7 0x00000870 [ 0.262695] gpmc_cs_enable_mem(), 433, [ 0.262725] gpmc_ch_dump_reg, 1836, GPMC_CS_CONFIG1 0x00001800 [ 0.262756] gpmc_ch_dump_reg, 1838, GPMC_CS_CONFIG2 0x00141400 [ 0.262756] gpmc_ch_dump_reg, 1840, GPMC_CS_CONFIG3 0x00141400 [ 0.262786] gpmc_ch_dump_reg, 1842, GPMC_CS_CONFIG4 0x0f010f01 [ 0.262786] gpmc_ch_dump_reg, 1844, GPMC_CS_CONFIG5 0x010c1414 [ 0.262817] gpmc_ch_dump_reg, 1846, GPMC_CS_CONFIG6 0x1f0f0a80 [ 0.262817] gpmc_ch_dump_reg, 1848, GPMC_CS_CONFIG7 0x00000f70 [ 0.262878] GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.262908] GPMC CS0: cs_rd_off : 4 ticks, 20 ns (was 20 ticks) 20 ns [ 0.262939] GPMC CS0: cs_wr_off : 4 ticks, 20 ns (was 20 ticks) 20 ns [ 0.262939] GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.262969] GPMC CS0: adv_rd_off: 4 ticks, 20 ns (was 20 ticks) 20 ns [ 0.263000] GPMC CS0: adv_wr_off: 4 ticks, 20 ns (was 20 ticks) 20 ns [ 0.263031] GPMC CS0: oe_on : 0 ticks, 0 ns (was 1 ticks) 0 ns [ 0.263031] GPMC CS0: oe_off : 3 ticks, 15 ns (was 15 ticks) 15 ns [ 0.263061] GPMC CS0: we_on : 0 ticks, 0 ns (was 1 ticks) 0 ns [ 0.263092] GPMC CS0: we_off : 3 ticks, 15 ns (was 15 ticks) 15 ns [ 0.263122] GPMC CS0: rd_cycle : 4 ticks, 20 ns (was 20 ticks) 20 ns [ 0.263153] GPMC CS0: wr_cycle : 4 ticks, 20 ns (was 20 ticks) 20 ns [ 0.263183] GPMC CS0: access : 3 ticks, 15 ns (was 12 ticks) 12 ns [ 0.263183] GPMC CS0: page_burst_access: 0 ticks, 0 ns (was 1 ticks) 0 ns [ 0.263214] GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.263244] GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 10 ticks) 0 ns [ 0.263244] GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.263275] GPMC CS0: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.263305] GPMC CS0: wr_data_mux_bus: 3 ticks, 15 ns (was 15 ticks) 15 ns [ 0.263336] GPMC CS0: wr_access : 7 ticks, 35 ns (was 31 ticks) 31 ns [ 0.263366] gpmc_read_settings_dt: page/burst-length set but not used! [ 0.263397] gpmc_read_settings_dt: read/write wait monitoring not enabled! [ 0.263427] gpmc_write_reg, 176, [ 0.263427] gpmc_ch_dump_reg, 1836, GPMC_CS_CONFIG1 0x00001800 [ 0.263458] gpmc_ch_dump_reg, 1838, GPMC_CS_CONFIG2 0x00040400 [ 0.263458] gpmc_ch_dump_reg, 1840, GPMC_CS_CONFIG3 0x00040400 [ 0.263488] gpmc_ch_dump_reg, 1842, GPMC_CS_CONFIG4 0x03000300 [ 0.263488] gpmc_ch_dump_reg, 1844, GPMC_CS_CONFIG5 0x00030404 [ 0.263519] gpmc_ch_dump_reg, 1846, GPMC_CS_CONFIG6 0x07030000 [ 0.263519] gpmc_ch_dump_reg, 1848, GPMC_CS_CONFIG7 0x00000f70 [ 0.269592] No ATAGs? [ 0.269622] hw-breakpoint: debug architecture 0x4 unsupported. [ 0.272277] OMAP DMA hardware revision 5.0 [ 0.286621] bio: create slab <bio-0> at 0 [ 0.289093] VCC3: 3300 mV [ 0.292144] SCSI subsystem initialized [ 0.292755] usbcore: registered new interface driver usbfs [ 0.292907] usbcore: registered new interface driver hub [ 0.293395] usbcore: registered new device driver usb [ 0.295867] omap_i2c i2c.8: bus 0 rev4.4 at 2600 kHz [ 0.307403] twl 0-0048: PIH (irq 23) chaining IRQs 338..346 [ 0.307983] twl 0-0048: power (irq 343) chaining IRQs 346..353 [ 0.311218] VDD1: 600 <--> 1450 mV at 1200 mV [ 0.313323] VDAC: 1800 mV [ 0.315460] VPLL2: 1800 mV [ 0.317535] VMMC1: 1850 <--> 3150 mV at 3000 mV [ 0.319366] VUSB1V5: failed to apply 1500000uV constraint [ 0.322113] twl_reg regulator-vusb1v5.24: can't register VUSB1V5, -22 [ 0.322174] twl_reg: probe of regulator-vusb1v5.24 failed with error -22 [ 0.323333] VUSB1V8: failed to apply 1800000uV constraint [ 0.323791] twl_reg regulator-vusb1v8.25: can't register VUSB1V8, -22 [ 0.323852] twl_reg: probe of regulator-vusb1v8.25 failed with error -22 [ 0.324981] VUSB3V1: failed to apply 3100000uV constraint [ 0.325439] twl_reg regulator-vusb3v1.26: can't register VUSB3V1, -22 [ 0.325500] twl_reg: probe of regulator-vusb3v1.26 failed with error -22 [ 0.326690] VSIM: 1800 <--> 3000 mV at 1800 mV [ 0.329071] twl4030_gpio gpio.28: gpio (irq 338) chaining IRQs 354..371 [ 0.333282] VIO: 1800 mV [ 0.335662] VAUX2_4030: 2800 mV [ 0.337432] VDD2: at 1200 mV [ 0.339569] omap_i2c i2c.9: bus 1 rev4.4 at 2600 kHz [ 0.340850] omap_i2c i2c.10: bus 2 rev4.4 at 2600 kHz [ 0.341430] pps_core: LinuxPPS API ver. 1 registered [ 0.341430] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 0.341522] PTP clock support registered [ 0.345947] cfg80211: Calling CRDA to update world regulatory domain [ 0.346771] Switching to clocksource 32k_counter [ 0.375244] NET: Registered protocol family 2 [ 0.377655] TCP established hash table entries: 1024 (order: 1, 8192 bytes) [ 0.377868] TCP bind hash table entries: 1024 (order: 3, 36864 bytes) [ 0.378448] TCP: Hash tables configured (established 1024 bind 1024) [ 0.378631] TCP: reno registered [ 0.378662] UDP hash table entries: 128 (order: 1, 10240 bytes) [ 0.378845] UDP-Lite hash table entries: 128 (order: 1, 10240 bytes) [ 0.379852] NET: Registered protocol family 1 [ 0.381347] RPC: Registered named UNIX socket transport module. [ 0.381378] RPC: Registered udp transport module. [ 0.381408] RPC: Registered tcp transport module. [ 0.381408] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.382232] hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available [ 0.391906] VFS: Disk quotas dquot_6.5.2 [ 0.391998] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 0.394653] NFS: Registering the id_resolver key type [ 0.395172] Key type id_resolver registered [ 0.395202] Key type id_legacy registered [ 0.395355] fuse init (API version 7.21) [ 0.396606] msgmni has been set to 226 [ 0.401428] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250) [ 0.401550] io scheduler noop registered [ 0.401580] io scheduler deadline registered [ 0.401641] io scheduler cfq registered (default) [ 0.403564] OMAP DSS rev 2.0 [ 0.406097] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.412414] serial.5: ttyO0 at MMIO 0x4806a000 (irq = 88) is a OMAP UART0 [ 1.483978] console [ttyO0] enabled [ 1.489654] serial.6: ttyO1 at MMIO 0x4806c000 (irq = 89) is a OMAP UART1 [ 1.498626] serial.7: ttyO2 at MMIO 0x49020000 (irq = 90) is a OMAP UART2 [ 1.524688] brd: module loaded [ 1.538970] loop: module loaded [ 1.543914] mtdoops: mtd device (mtddev=name/number) must be supplied [ 1.552215] Trying ONFI probe in 16 bits mode, aborting ! [ 1.557952] No NAND device found [ 1.561553] No NAND device found This is how u-boot GPMC config differs from final kernel configuration: u-boot: GPMC_CONFIG1: 0x6e000060: 0x00001800 kernel: 0x00001800 u-boot: GPMC_CONFIG2: 0x6e000064: 0x00141400 kernel: 0x00040400 u-boot: GPMC_CONFIG3: 0x6e000068: 0x00141400 kernel: 0x00040400 u-boot: GPMC_CONFIG4: 0x6e00006c: 0x0f010f01 kernel: 0x03000300 u-boot: GPMC_CONFIG5: 0x6e000070: 0x010c1414 kernel: 0x00030404 u-boot: GPMC_CONFIG6: 0x6e000074: 0x1f0f0a80 kernel: 0x07030000 u-boot: GPMC_CONFIG7: 0x6e000078: 0x00000870 kernel: 0x00000f70 The weird thing is that after gpmc_cs_enable_mem() gpmc registers are configured correct: [ 0.262695] gpmc_cs_enable_mem(), 433, [ 0.262725] gpmc_ch_dump_reg, 1836, GPMC_CS_CONFIG1 0x00001800 [ 0.262756] gpmc_ch_dump_reg, 1838, GPMC_CS_CONFIG2 0x00141400 [ 0.262756] gpmc_ch_dump_reg, 1840, GPMC_CS_CONFIG3 0x00141400 [ 0.262786] gpmc_ch_dump_reg, 1842, GPMC_CS_CONFIG4 0x0f010f01 [ 0.262786] gpmc_ch_dump_reg, 1844, GPMC_CS_CONFIG5 0x010c1414 [ 0.262817] gpmc_ch_dump_reg, 1846, GPMC_CS_CONFIG6 0x1f0f0a80 [ 0.262817] gpmc_ch_dump_reg, 1848, GPMC_CS_CONFIG7 0x00000f70 Any ideas? -- Christoph ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 9:01 ` Christoph Fritz @ 2013-04-19 12:02 ` Christoph Fritz 2013-04-19 14:00 ` Jon Hunter 2013-04-19 12:57 ` ARM: dts: omap3: NAND support - how? Jon Hunter 1 sibling, 1 reply; 19+ messages in thread From: Christoph Fritz @ 2013-04-19 12:02 UTC (permalink / raw) To: Jon Hunter; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On Fri, 2013-04-19 at 11:01 +0200, Christoph Fritz wrote: > This is how u-boot GPMC config differs from final kernel configuration: > > > u-boot: GPMC_CONFIG1: 0x6e000060: 0x00001800 > kernel: 0x00001800 > > u-boot: GPMC_CONFIG2: 0x6e000064: 0x00141400 > kernel: 0x00040400 > > u-boot: GPMC_CONFIG3: 0x6e000068: 0x00141400 > kernel: 0x00040400 > > u-boot: GPMC_CONFIG4: 0x6e00006c: 0x0f010f01 > kernel: 0x03000300 > > u-boot: GPMC_CONFIG5: 0x6e000070: 0x010c1414 > kernel: 0x00030404 > > u-boot: GPMC_CONFIG6: 0x6e000074: 0x1f0f0a80 > kernel: 0x07030000 > > u-boot: GPMC_CONFIG7: 0x6e000078: 0x00000870 > kernel: 0x00000f70 This differs because of wrong timings in my dt, this is my current one: &gpmc { ranges = <0 0 0x30000000 0x1000000>; nand@0,0 { reg = <0 0 0x1000000>; nand-bus-width = <16>; ti,nand-ecc-opt = "hw"; /* <- here I'm not sure, in current u-boot it's just 'hw' */ /* no elm on omap3 */ gpmc,mux-add-data = <0>; gpmc,device-nand; gpmc,device-width = <2>; gpmc,wait-pin = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,burst-length= <4>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <100>; gpmc,cs-wr-off-ns = <100>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <100>; gpmc,adv-wr-off-ns = <100>; gpmc,oe-on-ns = <5>; gpmc,oe-off-ns = <75>; gpmc,we-on-ns = <5>; gpmc,we-off-ns = <75>; gpmc,rd-cycle-ns = <100>; gpmc,wr-cycle-ns = <100>; gpmc,access-ns = <60>; gpmc,page-burst-access-ns = <5>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-delay-ns = <50>; gpmc,wr-data-mux-bus-ns = <75>; gpmc,wr-access-ns = <155>; }; }; and now NAND gets detected: [ 0.267913] omap-gpmc 6e000000.gpmc: GPMC revision 5.0 [ 0.269012] GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.269134] GPMC CS0: cs_rd_off : 20 ticks, 100 ns (was 20 ticks) 100 ns [ 0.269256] GPMC CS0: cs_wr_off : 20 ticks, 100 ns (was 20 ticks) 100 ns [ 0.269287] GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.269317] GPMC CS0: adv_rd_off: 20 ticks, 100 ns (was 20 ticks) 100 ns [ 0.269378] GPMC CS0: adv_wr_off: 20 ticks, 100 ns (was 20 ticks) 100 ns [ 0.269409] GPMC CS0: oe_on : 0 ticks, 0 ns (was 1 ticks) 0 ns [ 0.269439] GPMC CS0: oe_off : 15 ticks, 75 ns (was 15 ticks) 75 ns [ 0.269439] GPMC CS0: we_on : 0 ticks, 0 ns (was 1 ticks) 0 ns [ 0.269470] GPMC CS0: we_off : 15 ticks, 75 ns (was 15 ticks) 75 ns [ 0.269500] GPMC CS0: rd_cycle : 20 ticks, 100 ns (was 20 ticks) 100 ns [ 0.269531] GPMC CS0: wr_cycle : 20 ticks, 100 ns (was 20 ticks) 100 ns [ 0.269531] GPMC CS0: access : 12 ticks, 60 ns (was 12 ticks) 60 ns [ 0.269561] GPMC CS0: page_burst_access: 0 ticks, 0 ns (was 1 ticks) 0 ns [ 0.269592] GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.269592] gpmc_cs_set_timings, 404, t->cycle2cycle_delay: 0x00000000 [ 0.269622] GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 10 ticks) 0 ns [ 0.269653] GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.269653] GPMC CS0: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns [ 0.269683] GPMC CS0: wr_data_mux_bus: 15 ticks, 75 ns (was 15 ticks) 75 ns [ 0.269714] GPMC CS0: wr_access : 31 ticks, 155 ns (was 31 ticks) 155 ns [ 0.270416] gpmc_read_settings_dt: page/burst-length set but not used! [ 0.270446] gpmc_read_settings_dt: read/write wait monitoring not enabled! [ 0.276519] No ATAGs? [ 0.276550] hw-breakpoint: debug architecture 0x4 unsupported. [ 0.279205] OMAP DMA hardware revision 5.0 <SNIP> [ 2.021575] mtdoops: mtd device (mtddev=name/number) must be supplied [ 2.029907] Trying ONFI probe in 16 bits mode, aborting ! [ 2.035644] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xba (Micron NAND 256MiB 1,8V 16-bit), 256MiB, page size: 2048, OOB size: 64 but kernel GPMC config still differs from u-boot gpmc config: u-boot: GPMC_CONFIG1: 0x6e000060: 0x00001800 kernel: 0x00001800 OK u-boot: GPMC_CONFIG2: 0x6e000064: 0x00141400 kernel: 0x00141400 OK u-boot: GPMC_CONFIG3: 0x6e000068: 0x00141400 kernel: 0x00141400 OK u-boot: GPMC_CONFIG4: 0x6e00006c: 0x0f010f01 kernel: 0x0f000f00 DIFF u-boot: GPMC_CONFIG5: 0x6e000070: 0x010c1414 kernel: 0x000c1414 DIFF u-boot: GPMC_CONFIG6: 0x6e000074: 0x1f0f0a80 kernel: 0x1f0f0000 DIFF u-boot: GPMC_CONFIG7: 0x6e000078: 0x00000870 kernel: 0x00000f70 doesn't harm so I hacked the missing values to omap2_nand_gpmc_retime(): >From 8868823925441a824fe0d3143614482f25fb379b Mon Sep 17 00:00:00 2001 From: Christoph Fritz <chf.fritz@googlemail.com> Date: Fri, 19 Apr 2013 12:41:11 +0200 Subject: [PATCH] [RFC] ARM: OMAP2+: nand: add missing gpmc timing values This patch adds missing gpmc timing values to omap2_nand_gpmc_retime(). --- arch/arm/mach-omap2/gpmc-nand.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index d9c2719..d8bb241 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -58,6 +58,9 @@ static int omap2_nand_gpmc_retime( /* Read */ t.adv_rd_off = gpmc_t->adv_rd_off; t.oe_on = t.adv_on; + if (cpu_is_omap34xx()) { + t.oe_on = gpmc_t->oe_on; + } t.access = gpmc_t->access; t.oe_off = gpmc_t->oe_off; t.cs_rd_off = gpmc_t->cs_rd_off; @@ -69,11 +72,18 @@ static int omap2_nand_gpmc_retime( if (cpu_is_omap34xx()) { t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; t.wr_access = gpmc_t->wr_access; + t.we_on = gpmc_t->we_on; } t.we_off = gpmc_t->we_off; t.cs_wr_off = gpmc_t->cs_wr_off; t.wr_cycle = gpmc_t->wr_cycle; + if (cpu_is_omap34xx()) { + t.bool_timings = gpmc_t->bool_timings; + t.cycle2cycle_delay = gpmc_t->cycle2cycle_delay; + t.page_burst_access = gpmc_t->page_burst_access; + } + err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); if (err) return err; -- 1.7.10.4 now the GPMC config is the same as in u-boot: u-boot: GPMC_CONFIG1: 0x6e000060: 0x00001800 kernel: 0x00001800 OK u-boot: GPMC_CONFIG2: 0x6e000064: 0x00141400 kernel: 0x00141400 OK u-boot: GPMC_CONFIG3: 0x6e000068: 0x00141400 kernel: 0x00141400 OK u-boot: GPMC_CONFIG4: 0x6e00006c: 0x0f010f01 kernel: 0x0f010f01 OK u-boot: GPMC_CONFIG5: 0x6e000070: 0x010c1414 kernel: 0x010c1414 OK u-boot: GPMC_CONFIG6: 0x6e000074: 0x1f0f0a80 kernel: 0x1f0f0a80 OK u-boot: GPMC_CONFIG7: 0x6e000078: 0x00000870 kernel: 0x00000f70 doesn't harm Thanks -- Christoph ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 12:02 ` Christoph Fritz @ 2013-04-19 14:00 ` Jon Hunter 2013-04-19 14:53 ` Christoph Fritz 0 siblings, 1 reply; 19+ messages in thread From: Jon Hunter @ 2013-04-19 14:00 UTC (permalink / raw) To: Christoph Fritz; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On 04/19/2013 07:02 AM, Christoph Fritz wrote: > On Fri, 2013-04-19 at 11:01 +0200, Christoph Fritz wrote: > >> This is how u-boot GPMC config differs from final kernel configuration: >> >> >> u-boot: GPMC_CONFIG1: 0x6e000060: 0x00001800 >> kernel: 0x00001800 >> >> u-boot: GPMC_CONFIG2: 0x6e000064: 0x00141400 >> kernel: 0x00040400 >> >> u-boot: GPMC_CONFIG3: 0x6e000068: 0x00141400 >> kernel: 0x00040400 >> >> u-boot: GPMC_CONFIG4: 0x6e00006c: 0x0f010f01 >> kernel: 0x03000300 >> >> u-boot: GPMC_CONFIG5: 0x6e000070: 0x010c1414 >> kernel: 0x00030404 >> >> u-boot: GPMC_CONFIG6: 0x6e000074: 0x1f0f0a80 >> kernel: 0x07030000 >> >> u-boot: GPMC_CONFIG7: 0x6e000078: 0x00000870 >> kernel: 0x00000f70 > > This differs because of wrong timings in my dt, this is my current one: > > &gpmc { > ranges = <0 0 0x30000000 0x1000000>; > nand@0,0 { > reg = <0 0 0x1000000>; > nand-bus-width = <16>; > ti,nand-ecc-opt = "hw"; /* <- here I'm not sure, in current u-boot it's just 'hw' */ > /* no elm on omap3 */ > > gpmc,mux-add-data = <0>; > gpmc,device-nand; > gpmc,device-width = <2>; > gpmc,wait-pin = <0>; > gpmc,wait-monitoring-ns = <0>; > gpmc,burst-length= <4>; > gpmc,cs-on-ns = <0>; > gpmc,cs-rd-off-ns = <100>; > gpmc,cs-wr-off-ns = <100>; > gpmc,adv-on-ns = <0>; > gpmc,adv-rd-off-ns = <100>; > gpmc,adv-wr-off-ns = <100>; > gpmc,oe-on-ns = <5>; > gpmc,oe-off-ns = <75>; > gpmc,we-on-ns = <5>; > gpmc,we-off-ns = <75>; > gpmc,rd-cycle-ns = <100>; > gpmc,wr-cycle-ns = <100>; > gpmc,access-ns = <60>; > gpmc,page-burst-access-ns = <5>; > gpmc,bus-turnaround-ns = <0>; > gpmc,cycle2cycle-samecsen; > gpmc,cycle2cycle-delay-ns = <50>; > gpmc,wr-data-mux-bus-ns = <75>; > gpmc,wr-access-ns = <155>; > }; > }; > > and now NAND gets detected: > > [ 0.267913] omap-gpmc 6e000000.gpmc: GPMC revision 5.0 > [ 0.269012] GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.269134] GPMC CS0: cs_rd_off : 20 ticks, 100 ns (was 20 ticks) 100 ns > > [ 0.269256] GPMC CS0: cs_wr_off : 20 ticks, 100 ns (was 20 ticks) 100 ns > [ 0.269287] GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.269317] GPMC CS0: adv_rd_off: 20 ticks, 100 ns (was 20 ticks) 100 ns > [ 0.269378] GPMC CS0: adv_wr_off: 20 ticks, 100 ns (was 20 ticks) 100 ns > [ 0.269409] GPMC CS0: oe_on : 0 ticks, 0 ns (was 1 ticks) 0 ns > [ 0.269439] GPMC CS0: oe_off : 15 ticks, 75 ns (was 15 ticks) 75 ns > [ 0.269439] GPMC CS0: we_on : 0 ticks, 0 ns (was 1 ticks) 0 ns > [ 0.269470] GPMC CS0: we_off : 15 ticks, 75 ns (was 15 ticks) 75 ns > [ 0.269500] GPMC CS0: rd_cycle : 20 ticks, 100 ns (was 20 ticks) 100 ns > [ 0.269531] GPMC CS0: wr_cycle : 20 ticks, 100 ns (was 20 ticks) 100 ns > [ 0.269531] GPMC CS0: access : 12 ticks, 60 ns (was 12 ticks) 60 ns > [ 0.269561] GPMC CS0: page_burst_access: 0 ticks, 0 ns (was 1 ticks) 0 ns > [ 0.269592] GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.269592] gpmc_cs_set_timings, 404, t->cycle2cycle_delay: 0x00000000 > [ 0.269622] GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 10 ticks) 0 ns > [ 0.269653] GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.269653] GPMC CS0: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.269683] GPMC CS0: wr_data_mux_bus: 15 ticks, 75 ns (was 15 ticks) 75 ns > [ 0.269714] GPMC CS0: wr_access : 31 ticks, 155 ns (was 31 ticks) 155 ns > [ 0.270416] gpmc_read_settings_dt: page/burst-length set but not used! > [ 0.270446] gpmc_read_settings_dt: read/write wait monitoring not enabled! > [ 0.276519] No ATAGs? > [ 0.276550] hw-breakpoint: debug architecture 0x4 unsupported. > [ 0.279205] OMAP DMA hardware revision 5.0 > <SNIP> > [ 2.021575] mtdoops: mtd device (mtddev=name/number) must be supplied > [ 2.029907] Trying ONFI probe in 16 bits mode, aborting ! > [ 2.035644] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xba (Micron NAND 256MiB 1,8V 16-bit), 256MiB, page size: 2048, OOB size: 64 > > > but kernel GPMC config still differs from u-boot gpmc config: > > > u-boot: GPMC_CONFIG1: 0x6e000060: 0x00001800 > kernel: 0x00001800 OK > u-boot: GPMC_CONFIG2: 0x6e000064: 0x00141400 > kernel: 0x00141400 OK > u-boot: GPMC_CONFIG3: 0x6e000068: 0x00141400 > kernel: 0x00141400 OK > u-boot: GPMC_CONFIG4: 0x6e00006c: 0x0f010f01 > kernel: 0x0f000f00 DIFF > u-boot: GPMC_CONFIG5: 0x6e000070: 0x010c1414 > kernel: 0x000c1414 DIFF > u-boot: GPMC_CONFIG6: 0x6e000074: 0x1f0f0a80 > kernel: 0x1f0f0000 DIFF > u-boot: GPMC_CONFIG7: 0x6e000078: 0x00000870 > kernel: 0x00000f70 doesn't harm > > so I hacked the missing values to omap2_nand_gpmc_retime(): > > From 8868823925441a824fe0d3143614482f25fb379b Mon Sep 17 00:00:00 2001 > From: Christoph Fritz <chf.fritz@googlemail.com> > Date: Fri, 19 Apr 2013 12:41:11 +0200 > Subject: [PATCH] [RFC] ARM: OMAP2+: nand: add missing gpmc timing values > > This patch adds missing gpmc timing values to omap2_nand_gpmc_retime(). > --- > arch/arm/mach-omap2/gpmc-nand.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c > index d9c2719..d8bb241 100644 > --- a/arch/arm/mach-omap2/gpmc-nand.c > +++ b/arch/arm/mach-omap2/gpmc-nand.c > @@ -58,6 +58,9 @@ static int omap2_nand_gpmc_retime( > /* Read */ > t.adv_rd_off = gpmc_t->adv_rd_off; > t.oe_on = t.adv_on; > + if (cpu_is_omap34xx()) { > + t.oe_on = gpmc_t->oe_on; > + } How about just setting gpmc,adv-on-ns, then you don't need the above. > t.access = gpmc_t->access; > t.oe_off = gpmc_t->oe_off; > t.cs_rd_off = gpmc_t->cs_rd_off; > @@ -69,11 +72,18 @@ static int omap2_nand_gpmc_retime( > if (cpu_is_omap34xx()) { We should get rid of cpu_is_omap34xx() here as this is handled by gpmc_cs_set_timings(). > t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; > t.wr_access = gpmc_t->wr_access; > + t.we_on = gpmc_t->we_on; How about just setting gpmc,adv-on-ns, then you don't need the above. > } > t.we_off = gpmc_t->we_off; > t.cs_wr_off = gpmc_t->cs_wr_off; > t.wr_cycle = gpmc_t->wr_cycle; > > + if (cpu_is_omap34xx()) { > + t.bool_timings = gpmc_t->bool_timings; > + t.cycle2cycle_delay = gpmc_t->cycle2cycle_delay; > + t.page_burst_access = gpmc_t->page_burst_access; > + } The above timings are applicable to all gpmc versions and so you should not need to make this dependent on cpu_is_omap34xx(). So would be worthwhile spending a patch to add the above timings to this function. Cheers Jon ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 14:00 ` Jon Hunter @ 2013-04-19 14:53 ` Christoph Fritz 2013-04-19 15:36 ` Jon Hunter 0 siblings, 1 reply; 19+ messages in thread From: Christoph Fritz @ 2013-04-19 14:53 UTC (permalink / raw) To: Jon Hunter; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On Fri, 2013-04-19 at 09:00 -0500, Jon Hunter wrote: > On 04/19/2013 07:02 AM, Christoph Fritz wrote: > > so I hacked the missing values to omap2_nand_gpmc_retime(): > > > > From 8868823925441a824fe0d3143614482f25fb379b Mon Sep 17 00:00:00 2001 > > From: Christoph Fritz <chf.fritz@googlemail.com> > > Date: Fri, 19 Apr 2013 12:41:11 +0200 > > Subject: [PATCH] [RFC] ARM: OMAP2+: nand: add missing gpmc timing values > > > > This patch adds missing gpmc timing values to omap2_nand_gpmc_retime(). > > --- > > arch/arm/mach-omap2/gpmc-nand.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c > > index d9c2719..d8bb241 100644 > > --- a/arch/arm/mach-omap2/gpmc-nand.c > > +++ b/arch/arm/mach-omap2/gpmc-nand.c > > @@ -58,6 +58,9 @@ static int omap2_nand_gpmc_retime( > > /* Read */ > > t.adv_rd_off = gpmc_t->adv_rd_off; > > t.oe_on = t.adv_on; > > + if (cpu_is_omap34xx()) { > > + t.oe_on = gpmc_t->oe_on; > > + } > > How about just setting gpmc,adv-on-ns, then you don't need the above. > > > t.access = gpmc_t->access; > > t.oe_off = gpmc_t->oe_off; > > t.cs_rd_off = gpmc_t->cs_rd_off; > > @@ -69,11 +72,18 @@ static int omap2_nand_gpmc_retime( > > if (cpu_is_omap34xx()) { > > We should get rid of cpu_is_omap34xx() here as this is handled by > gpmc_cs_set_timings(). > > > t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; > > t.wr_access = gpmc_t->wr_access; > > + t.we_on = gpmc_t->we_on; > > How about just setting gpmc,adv-on-ns, then you don't need the above. > > > } > > t.we_off = gpmc_t->we_off; > > t.cs_wr_off = gpmc_t->cs_wr_off; > > t.wr_cycle = gpmc_t->wr_cycle; > > > > + if (cpu_is_omap34xx()) { > > + t.bool_timings = gpmc_t->bool_timings; > > + t.cycle2cycle_delay = gpmc_t->cycle2cycle_delay; > > + t.page_burst_access = gpmc_t->page_burst_access; > > + } > > The above timings are applicable to all gpmc versions and so you should > not need to make this dependent on cpu_is_omap34xx(). So would be > worthwhile spending a patch to add the above timings to this function. Before sending this patch, I'd like to get your opinion on this approach: >From 015f1e8006f8f85818b6bbd5ba00dc6b4ae48b65 Mon Sep 17 00:00:00 2001 From: Christoph Fritz <chf.fritz@googlemail.com> Date: Fri, 19 Apr 2013 12:41:11 +0200 Subject: [RFC][PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values This patch removes omap2_nand_gpmc_retime() which was used to quirk some timing values before gpmc_cs_set_timings(). Due to recent changes, gpmc_cs_set_timings() has evolved so that there is no more need for omap2_nand_gpmc_retime(). Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> --- arch/arm/mach-omap2/gpmc-nand.c | 40 +-------------------------------------- 1 file changed, 1 insertion(+), 39 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index d9c2719..c8044b0 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = { .resource = gpmc_nand_resource, }; -static int omap2_nand_gpmc_retime( - struct omap_nand_platform_data *gpmc_nand_data, - struct gpmc_timings *gpmc_t) -{ - struct gpmc_timings t; - int err; - - memset(&t, 0, sizeof(t)); - t.sync_clk = gpmc_t->sync_clk; - t.cs_on = gpmc_t->cs_on; - t.adv_on = gpmc_t->adv_on; - - /* Read */ - t.adv_rd_off = gpmc_t->adv_rd_off; - t.oe_on = t.adv_on; - t.access = gpmc_t->access; - t.oe_off = gpmc_t->oe_off; - t.cs_rd_off = gpmc_t->cs_rd_off; - t.rd_cycle = gpmc_t->rd_cycle; - - /* Write */ - t.adv_wr_off = gpmc_t->adv_wr_off; - t.we_on = t.oe_on; - if (cpu_is_omap34xx()) { - t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; - t.wr_access = gpmc_t->wr_access; - } - t.we_off = gpmc_t->we_off; - t.cs_wr_off = gpmc_t->cs_wr_off; - t.wr_cycle = gpmc_t->wr_cycle; - - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); - if (err) - return err; - - return 0; -} - static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* support only OMAP3 class */ @@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); if (gpmc_t) { - err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); if (err < 0) { dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 14:53 ` Christoph Fritz @ 2013-04-19 15:36 ` Jon Hunter 2013-04-19 15:48 ` Tony Lindgren 2013-04-19 16:29 ` [PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values Christoph Fritz 0 siblings, 2 replies; 19+ messages in thread From: Jon Hunter @ 2013-04-19 15:36 UTC (permalink / raw) To: Christoph Fritz; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On 04/19/2013 09:53 AM, Christoph Fritz wrote: > On Fri, 2013-04-19 at 09:00 -0500, Jon Hunter wrote: >> On 04/19/2013 07:02 AM, Christoph Fritz wrote: >>> so I hacked the missing values to omap2_nand_gpmc_retime(): >>> >>> From 8868823925441a824fe0d3143614482f25fb379b Mon Sep 17 00:00:00 2001 >>> From: Christoph Fritz <chf.fritz@googlemail.com> >>> Date: Fri, 19 Apr 2013 12:41:11 +0200 >>> Subject: [PATCH] [RFC] ARM: OMAP2+: nand: add missing gpmc timing values >>> >>> This patch adds missing gpmc timing values to omap2_nand_gpmc_retime(). >>> --- >>> arch/arm/mach-omap2/gpmc-nand.c | 10 ++++++++++ >>> 1 file changed, 10 insertions(+) >>> >>> diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c >>> index d9c2719..d8bb241 100644 >>> --- a/arch/arm/mach-omap2/gpmc-nand.c >>> +++ b/arch/arm/mach-omap2/gpmc-nand.c >>> @@ -58,6 +58,9 @@ static int omap2_nand_gpmc_retime( >>> /* Read */ >>> t.adv_rd_off = gpmc_t->adv_rd_off; >>> t.oe_on = t.adv_on; >>> + if (cpu_is_omap34xx()) { >>> + t.oe_on = gpmc_t->oe_on; >>> + } >> >> How about just setting gpmc,adv-on-ns, then you don't need the above. >> >>> t.access = gpmc_t->access; >>> t.oe_off = gpmc_t->oe_off; >>> t.cs_rd_off = gpmc_t->cs_rd_off; >>> @@ -69,11 +72,18 @@ static int omap2_nand_gpmc_retime( >>> if (cpu_is_omap34xx()) { >> >> We should get rid of cpu_is_omap34xx() here as this is handled by >> gpmc_cs_set_timings(). >> >>> t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; >>> t.wr_access = gpmc_t->wr_access; >>> + t.we_on = gpmc_t->we_on; >> >> How about just setting gpmc,adv-on-ns, then you don't need the above. >> >>> } >>> t.we_off = gpmc_t->we_off; >>> t.cs_wr_off = gpmc_t->cs_wr_off; >>> t.wr_cycle = gpmc_t->wr_cycle; >>> >>> + if (cpu_is_omap34xx()) { >>> + t.bool_timings = gpmc_t->bool_timings; >>> + t.cycle2cycle_delay = gpmc_t->cycle2cycle_delay; >>> + t.page_burst_access = gpmc_t->page_burst_access; >>> + } >> >> The above timings are applicable to all gpmc versions and so you should >> not need to make this dependent on cpu_is_omap34xx(). So would be >> worthwhile spending a patch to add the above timings to this function. > > Before sending this patch, I'd like to get your opinion on this > approach: > > From 015f1e8006f8f85818b6bbd5ba00dc6b4ae48b65 Mon Sep 17 00:00:00 2001 > From: Christoph Fritz <chf.fritz@googlemail.com> > Date: Fri, 19 Apr 2013 12:41:11 +0200 > Subject: [RFC][PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values > > This patch removes omap2_nand_gpmc_retime() which was used to quirk > some timing values before gpmc_cs_set_timings(). Due to recent changes, > gpmc_cs_set_timings() has evolved so that there is no more need for > omap2_nand_gpmc_retime(). > > Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> > --- > arch/arm/mach-omap2/gpmc-nand.c | 40 +-------------------------------------- > 1 file changed, 1 insertion(+), 39 deletions(-) > > diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c > index d9c2719..c8044b0 100644 > --- a/arch/arm/mach-omap2/gpmc-nand.c > +++ b/arch/arm/mach-omap2/gpmc-nand.c > @@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = { > .resource = gpmc_nand_resource, > }; > > -static int omap2_nand_gpmc_retime( > - struct omap_nand_platform_data *gpmc_nand_data, > - struct gpmc_timings *gpmc_t) > -{ > - struct gpmc_timings t; > - int err; > - > - memset(&t, 0, sizeof(t)); > - t.sync_clk = gpmc_t->sync_clk; > - t.cs_on = gpmc_t->cs_on; > - t.adv_on = gpmc_t->adv_on; > - > - /* Read */ > - t.adv_rd_off = gpmc_t->adv_rd_off; > - t.oe_on = t.adv_on; > - t.access = gpmc_t->access; > - t.oe_off = gpmc_t->oe_off; > - t.cs_rd_off = gpmc_t->cs_rd_off; > - t.rd_cycle = gpmc_t->rd_cycle; > - > - /* Write */ > - t.adv_wr_off = gpmc_t->adv_wr_off; > - t.we_on = t.oe_on; > - if (cpu_is_omap34xx()) { > - t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; > - t.wr_access = gpmc_t->wr_access; > - } > - t.we_off = gpmc_t->we_off; > - t.cs_wr_off = gpmc_t->cs_wr_off; > - t.wr_cycle = gpmc_t->wr_cycle; > - > - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); > - if (err) > - return err; > - > - return 0; > -} > - > static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) > { > /* support only OMAP3 class */ > @@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, > gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); > > if (gpmc_t) { > - err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); > + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); > if (err < 0) { > dev_err(dev, "Unable to set gpmc timings: %d\n", err); > return err; > Thanks for sending this. I would agree with this approach. The retime function seems very redundant looking at what it does. Grep'ing through the source, the only place I see a board file call gpmc_nand_init() and pass timings is in arch/arm/mach-omap2/board-flash.c. To keep the gpmc configuration consistent, I would also suggest making the following change so that oe_on and we_on are programmed as they would be by the current retime function. diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index c33adea..946a7516 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -116,6 +116,8 @@ struct gpmc_timings nand_default_timings[1] = { .adv_rd_off = 24, .adv_wr_off = 36, + .we_on = 6, + .oe_on = 6, .we_off = 30, .oe_off = 48, Cheers Jon ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 15:36 ` Jon Hunter @ 2013-04-19 15:48 ` Tony Lindgren 2013-04-19 15:56 ` Jon Hunter 2013-04-19 16:29 ` [PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values Christoph Fritz 1 sibling, 1 reply; 19+ messages in thread From: Tony Lindgren @ 2013-04-19 15:48 UTC (permalink / raw) To: Jon Hunter Cc: Christoph Fritz, Javier Martinez Canillas, Daniel Mack, linux-omap * Jon Hunter <jon-hunter@ti.com> [130419 08:41]: > On 04/19/2013 09:53 AM, Christoph Fritz wrote: > > -static int omap2_nand_gpmc_retime( > > - struct omap_nand_platform_data *gpmc_nand_data, > > - struct gpmc_timings *gpmc_t) > > -{ > > - struct gpmc_timings t; > > - int err; > > - > > - memset(&t, 0, sizeof(t)); > > - t.sync_clk = gpmc_t->sync_clk; > > - t.cs_on = gpmc_t->cs_on; > > - t.adv_on = gpmc_t->adv_on; > > - > > - /* Read */ > > - t.adv_rd_off = gpmc_t->adv_rd_off; > > - t.oe_on = t.adv_on; > > - t.access = gpmc_t->access; > > - t.oe_off = gpmc_t->oe_off; > > - t.cs_rd_off = gpmc_t->cs_rd_off; > > - t.rd_cycle = gpmc_t->rd_cycle; > > - > > - /* Write */ > > - t.adv_wr_off = gpmc_t->adv_wr_off; > > - t.we_on = t.oe_on; > > - if (cpu_is_omap34xx()) { > > - t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; > > - t.wr_access = gpmc_t->wr_access; > > - } > > - t.we_off = gpmc_t->we_off; > > - t.cs_wr_off = gpmc_t->cs_wr_off; > > - t.wr_cycle = gpmc_t->wr_cycle; > > - > > - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); > > - if (err) > > - return err; > > - > > - return 0; > > -} > > - > > static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) > > { > > /* support only OMAP3 class */ > > @@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, > > gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); > > > > if (gpmc_t) { > > - err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); > > + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); > > if (err < 0) { > > dev_err(dev, "Unable to set gpmc timings: %d\n", err); > > return err; > > > > Thanks for sending this. I would agree with this approach. The retime > function seems very redundant looking at what it does. > > Grep'ing through the source, the only place I see a board file call > gpmc_nand_init() and pass timings is in > arch/arm/mach-omap2/board-flash.c. To keep the gpmc configuration > consistent, I would also suggest making the following change so that > oe_on and we_on are programmed as they would be by the current retime > function. What about DVFS though? The L3 clock can get rescaled with DVFS, and after that the retime function needs to get called. We are not doing it in the mainline tree, but at least n8x0 - n900 vendor trees were doing it. > diff --git a/arch/arm/mach-omap2/board-flash.c > b/arch/arm/mach-omap2/board-flash.c > index c33adea..946a7516 100644 > --- a/arch/arm/mach-omap2/board-flash.c > +++ b/arch/arm/mach-omap2/board-flash.c > @@ -116,6 +116,8 @@ struct gpmc_timings nand_default_timings[1] = { > .adv_rd_off = 24, > .adv_wr_off = 36, > > + .we_on = 6, > + .oe_on = 6, > .we_off = 30, > .oe_off = 48, > Regards, Tony ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 15:48 ` Tony Lindgren @ 2013-04-19 15:56 ` Jon Hunter 2013-04-19 16:15 ` Tony Lindgren 0 siblings, 1 reply; 19+ messages in thread From: Jon Hunter @ 2013-04-19 15:56 UTC (permalink / raw) To: Tony Lindgren Cc: Christoph Fritz, Javier Martinez Canillas, Daniel Mack, linux-omap On 04/19/2013 10:48 AM, Tony Lindgren wrote: > * Jon Hunter <jon-hunter@ti.com> [130419 08:41]: >> On 04/19/2013 09:53 AM, Christoph Fritz wrote: >>> -static int omap2_nand_gpmc_retime( >>> - struct omap_nand_platform_data *gpmc_nand_data, >>> - struct gpmc_timings *gpmc_t) >>> -{ >>> - struct gpmc_timings t; >>> - int err; >>> - >>> - memset(&t, 0, sizeof(t)); >>> - t.sync_clk = gpmc_t->sync_clk; >>> - t.cs_on = gpmc_t->cs_on; >>> - t.adv_on = gpmc_t->adv_on; >>> - >>> - /* Read */ >>> - t.adv_rd_off = gpmc_t->adv_rd_off; >>> - t.oe_on = t.adv_on; >>> - t.access = gpmc_t->access; >>> - t.oe_off = gpmc_t->oe_off; >>> - t.cs_rd_off = gpmc_t->cs_rd_off; >>> - t.rd_cycle = gpmc_t->rd_cycle; >>> - >>> - /* Write */ >>> - t.adv_wr_off = gpmc_t->adv_wr_off; >>> - t.we_on = t.oe_on; >>> - if (cpu_is_omap34xx()) { >>> - t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; >>> - t.wr_access = gpmc_t->wr_access; >>> - } >>> - t.we_off = gpmc_t->we_off; >>> - t.cs_wr_off = gpmc_t->cs_wr_off; >>> - t.wr_cycle = gpmc_t->wr_cycle; >>> - >>> - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); >>> - if (err) >>> - return err; >>> - >>> - return 0; >>> -} >>> - >>> static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) >>> { >>> /* support only OMAP3 class */ >>> @@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, >>> gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); >>> >>> if (gpmc_t) { >>> - err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); >>> + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); >>> if (err < 0) { >>> dev_err(dev, "Unable to set gpmc timings: %d\n", err); >>> return err; >>> >> >> Thanks for sending this. I would agree with this approach. The retime >> function seems very redundant looking at what it does. >> >> Grep'ing through the source, the only place I see a board file call >> gpmc_nand_init() and pass timings is in >> arch/arm/mach-omap2/board-flash.c. To keep the gpmc configuration >> consistent, I would also suggest making the following change so that >> oe_on and we_on are programmed as they would be by the current retime >> function. > > What about DVFS though? The L3 clock can get rescaled with DVFS, > and after that the retime function needs to get called. We are > not doing it in the mainline tree, but at least n8x0 - n900 vendor > trees were doing it. I wondered if you would mention that ;-) If you look at the implementation of the omap2_nand_gpmc_retime(), it does not actually perform any retiming base upon frequency whatsoever (unlike smc91c96_gpmc_retime). So right now omap2_nand_gpmc_retime is a basic wrapper around gpmc_cs_set_timings() really adding no value. Hence, I agree with Christoph's patch to remove it. Cheers Jon ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 15:56 ` Jon Hunter @ 2013-04-19 16:15 ` Tony Lindgren 0 siblings, 0 replies; 19+ messages in thread From: Tony Lindgren @ 2013-04-19 16:15 UTC (permalink / raw) To: Jon Hunter Cc: Christoph Fritz, Javier Martinez Canillas, Daniel Mack, linux-omap * Jon Hunter <jon-hunter@ti.com> [130419 09:01]: > On 04/19/2013 10:48 AM, Tony Lindgren wrote: > > > > What about DVFS though? The L3 clock can get rescaled with DVFS, > > and after that the retime function needs to get called. We are > > not doing it in the mainline tree, but at least n8x0 - n900 vendor > > trees were doing it. > > I wondered if you would mention that ;-) > > If you look at the implementation of the omap2_nand_gpmc_retime(), it > does not actually perform any retiming base upon frequency whatsoever > (unlike smc91c96_gpmc_retime). So right now omap2_nand_gpmc_retime is a > basic wrapper around gpmc_cs_set_timings() really adding no value. > Hence, I agree with Christoph's patch to remove it. OK thanks fine with me then. Tony ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values 2013-04-19 15:36 ` Jon Hunter 2013-04-19 15:48 ` Tony Lindgren @ 2013-04-19 16:29 ` Christoph Fritz 2013-05-16 15:49 ` Tony Lindgren 1 sibling, 1 reply; 19+ messages in thread From: Christoph Fritz @ 2013-04-19 16:29 UTC (permalink / raw) To: Jon Hunter, Tony Lindgren Cc: Javier Martinez Canillas, Daniel Mack, linux-omap, linux-arm-kernel This patch removes omap2_nand_gpmc_retime() which was used to quirk some timing values before gpmc_cs_set_timings(). Due to recent changes, gpmc_cs_set_timings() has evolved so that there is no more need for a retime function. To keep the gpmc configuration consistent for legacy board files, this patch also adds oe_on and we_on to nand_default_timings[] as they would be by the retime function. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> --- arch/arm/mach-omap2/board-flash.c | 3 +++ arch/arm/mach-omap2/gpmc-nand.c | 40 +------------------------------------ 2 files changed, 4 insertions(+), 39 deletions(-) diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index c33adea..fc20a61 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = { .cs_rd_off = 36, .cs_wr_off = 36, + .we_on = 6, + .oe_on = 6, + .adv_on = 6, .adv_rd_off = 24, .adv_wr_off = 36, diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index d9c2719..c8044b0 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = { .resource = gpmc_nand_resource, }; -static int omap2_nand_gpmc_retime( - struct omap_nand_platform_data *gpmc_nand_data, - struct gpmc_timings *gpmc_t) -{ - struct gpmc_timings t; - int err; - - memset(&t, 0, sizeof(t)); - t.sync_clk = gpmc_t->sync_clk; - t.cs_on = gpmc_t->cs_on; - t.adv_on = gpmc_t->adv_on; - - /* Read */ - t.adv_rd_off = gpmc_t->adv_rd_off; - t.oe_on = t.adv_on; - t.access = gpmc_t->access; - t.oe_off = gpmc_t->oe_off; - t.cs_rd_off = gpmc_t->cs_rd_off; - t.rd_cycle = gpmc_t->rd_cycle; - - /* Write */ - t.adv_wr_off = gpmc_t->adv_wr_off; - t.we_on = t.oe_on; - if (cpu_is_omap34xx()) { - t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; - t.wr_access = gpmc_t->wr_access; - } - t.we_off = gpmc_t->we_off; - t.cs_wr_off = gpmc_t->cs_wr_off; - t.wr_cycle = gpmc_t->wr_cycle; - - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); - if (err) - return err; - - return 0; -} - static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* support only OMAP3 class */ @@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); if (gpmc_t) { - err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); if (err < 0) { dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values 2013-04-19 16:29 ` [PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values Christoph Fritz @ 2013-05-16 15:49 ` Tony Lindgren 0 siblings, 0 replies; 19+ messages in thread From: Tony Lindgren @ 2013-05-16 15:49 UTC (permalink / raw) To: Christoph Fritz Cc: Jon Hunter, Javier Martinez Canillas, Daniel Mack, linux-omap, linux-arm-kernel * Christoph Fritz <chf.fritz@googlemail.com> [130419 09:34]: > This patch removes omap2_nand_gpmc_retime() which was used to quirk > some timing values before gpmc_cs_set_timings(). Due to recent changes, > gpmc_cs_set_timings() has evolved so that there is no more need for a > retime function. > > To keep the gpmc configuration consistent for legacy board files, this > patch also adds oe_on and we_on to nand_default_timings[] as they > would be by the retime function. > > Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Thanks looks safe to me so applying into omap-for-v3.11/gpmc. Regards, Tony > --- > arch/arm/mach-omap2/board-flash.c | 3 +++ > arch/arm/mach-omap2/gpmc-nand.c | 40 +------------------------------------ > 2 files changed, 4 insertions(+), 39 deletions(-) > > diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c > index c33adea..fc20a61 100644 > --- a/arch/arm/mach-omap2/board-flash.c > +++ b/arch/arm/mach-omap2/board-flash.c > @@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = { > .cs_rd_off = 36, > .cs_wr_off = 36, > > + .we_on = 6, > + .oe_on = 6, > + > .adv_on = 6, > .adv_rd_off = 24, > .adv_wr_off = 36, > diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c > index d9c2719..c8044b0 100644 > --- a/arch/arm/mach-omap2/gpmc-nand.c > +++ b/arch/arm/mach-omap2/gpmc-nand.c > @@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = { > .resource = gpmc_nand_resource, > }; > > -static int omap2_nand_gpmc_retime( > - struct omap_nand_platform_data *gpmc_nand_data, > - struct gpmc_timings *gpmc_t) > -{ > - struct gpmc_timings t; > - int err; > - > - memset(&t, 0, sizeof(t)); > - t.sync_clk = gpmc_t->sync_clk; > - t.cs_on = gpmc_t->cs_on; > - t.adv_on = gpmc_t->adv_on; > - > - /* Read */ > - t.adv_rd_off = gpmc_t->adv_rd_off; > - t.oe_on = t.adv_on; > - t.access = gpmc_t->access; > - t.oe_off = gpmc_t->oe_off; > - t.cs_rd_off = gpmc_t->cs_rd_off; > - t.rd_cycle = gpmc_t->rd_cycle; > - > - /* Write */ > - t.adv_wr_off = gpmc_t->adv_wr_off; > - t.we_on = t.oe_on; > - if (cpu_is_omap34xx()) { > - t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; > - t.wr_access = gpmc_t->wr_access; > - } > - t.we_off = gpmc_t->we_off; > - t.cs_wr_off = gpmc_t->cs_wr_off; > - t.wr_cycle = gpmc_t->wr_cycle; > - > - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); > - if (err) > - return err; > - > - return 0; > -} > - > static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) > { > /* support only OMAP3 class */ > @@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, > gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); > > if (gpmc_t) { > - err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); > + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); > if (err < 0) { > dev_err(dev, "Unable to set gpmc timings: %d\n", err); > return err; > -- > 1.7.10.4 > > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 9:01 ` Christoph Fritz 2013-04-19 12:02 ` Christoph Fritz @ 2013-04-19 12:57 ` Jon Hunter 2013-04-19 13:06 ` Christoph Fritz 1 sibling, 1 reply; 19+ messages in thread From: Jon Hunter @ 2013-04-19 12:57 UTC (permalink / raw) To: Christoph Fritz; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On 04/19/2013 04:01 AM, Christoph Fritz wrote: > On Thu, 2013-04-18 at 18:26 -0500, Jon Hunter wrote: >> On 04/18/2013 06:24 PM, Jon Hunter wrote: > >>>> To get the values right for dt-GPMC-NAND-Config, here are the GPMC >>>> config registers for chip-select 0, they are taken from u-boot >>>> by doing "md 0x6E000060 7" on the u-boot shell: >>>> >>>> GPMC_CONFIG1: 0x6e000060: 0x00001800 >>>> GPMC_CONFIG2: 0x6e000064: 0x00141400 >>>> GPMC_CONFIG3: 0x6e000068: 0x00141400 >>>> GPMC_CONFIG4: 0x6e00006c: 0x0F010F01 >>>> GPMC_CONFIG5: 0x6e000070: 0x010C1414 >>>> GPMC_CONFIG6: 0x6e000074: 0x1F0F0A80 >>>> GPMC_CONFIG7: 0x6e000078: 0x00000870 >> >> >> I would advise you dump the gpmc registers at the end of the gpmc probe. >> I am sure you will see something completely different to the above based >> upon your dt configuration. > > Thanks to your help this is my new gpmc dt config: > > &gpmc { > ranges = <0 0 0x30000000 0x1000000>; > nand@0,0 { > reg = <0 0 0x1000000>; > nand-bus-width = <16>; > ti,nand-ecc-opt = "hw"; > /* no elm on omap3 */ > > gpmc,mux-add-data = <0>; > gpmc,device-nand; > gpmc,device-width = <2>; > gpmc,wait-pin = <0>; > gpmc,wait-monitoring-ns = <0x0>; > gpmc,burst-length= <4>; > gpmc,cs-on-ns = <0>; > gpmc,cs-rd-off-ns = <0x14>; > gpmc,cs-wr-off-ns = <0x14>; > gpmc,adv-on-ns = <0>; > gpmc,adv-rd-off-ns = <0x14>; > gpmc,adv-wr-off-ns = <0x14>; > gpmc,oe-on-ns = <0x1>; > gpmc,oe-off-ns = <0xf>; > gpmc,we-on-ns = <0x1>; > gpmc,we-off-ns = <0xf>; > gpmc,rd-cycle-ns = <0x14>; > gpmc,wr-cycle-ns = <0x14>; > gpmc,access-ns = <0xc>; > gpmc,page-burst-access-ns = <0x1>; > gpmc,bus-turnaround-ns = <0x0>; > gpmc,cycle2cycle-samecsen = <0x1>; > gpmc,cycle2cycle-delay-ns = <0xa>; > gpmc,wr-data-mux-bus-ns = <0xf>; > gpmc,wr-access-ns = <0x1f>; Please note that the above timings are in ns and the registers settings are in gpmc_fclk ticks. So you need to convert to ns. > }; > }; > > As suggested I added some printks to kernel gpmc-subsystem to compare > the gpmc config registers. > > [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d > [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache > [ 0.000000] Machine: Generic OMAP3 (Flattened Device Tree), model: INCOstartec LILLY-DBB056 (DM3730) > [ 0.000000] Memory policy: ECC disabled, Data cache writeback > [ 0.000000] CPU: All CPU(s) started in SVC mode. > [ 0.000000] OMAP3630 ES1.2 (l2cache iva neon isp 192mhz_clk ) > [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256 > [ 0.000000] Kernel command line: console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0 root=/dev/nfs ip=dhcp > [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) > [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) > [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) > [ 0.000000] Memory: 127MB = 127MB total > [ 0.000000] Memory: 116040k/116040k available, 15032k reserved, 0K highmem > [ 0.000000] Virtual kernel memory layout: > [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) > [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) > [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB) > [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) > [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) > [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) > [ 0.000000] .text : 0xc0008000 - 0xc06a9fa8 (6792 kB) > [ 0.000000] .init : 0xc06aa000 - 0xc06db9ec ( 199 kB) > [ 0.000000] .data : 0xc06dc000 - 0xc073bd20 ( 384 kB) > [ 0.000000] .bss : 0xc073bd20 - 0xc0c7e414 (5386 kB) > [ 0.000000] NR_IRQS:16 nr_irqs:16 16 > [ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts > [ 0.000000] Total of 96 interrupts on 1 active controller > [ 0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz > [ 0.000000] OMAP clockevent source: timer1 at 32768 Hz > [ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms > [ 0.000000] OMAP clocksource: 32k_counter at 32768 Hz > [ 0.000000] Console: colour dummy device 80x30 > [ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar > [ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8 > [ 0.000000] ... MAX_LOCK_DEPTH: 48 > [ 0.000000] ... MAX_LOCKDEP_KEYS: 8191 > [ 0.000000] ... CLASSHASH_SIZE: 4096 > [ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384 > [ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768 > [ 0.000000] ... CHAINHASH_SIZE: 16384 > [ 0.000000] memory used by lock dependency info: 3695 kB > [ 0.000000] per task-struct memory footprint: 1152 bytes > [ 0.001037] Calibrating delay loop... 398.13 BogoMIPS (lpj=1990656) > [ 0.119659] pid_max: default: 4096 minimum: 301 > [ 0.119964] Security Framework initialized > [ 0.120086] Mount-cache hash table entries: 512 > [ 0.135314] CPU: Testing write buffer coherency: ok > [ 0.136810] Setting up static identity map for 0xc04efee8 - 0xc04eff40 > [ 0.141418] devtmpfs: initialized > [ 0.197814] pinctrl core: initialized pinctrl subsystem > [ 0.201232] regulator-dummy: no parameters > [ 0.202972] NET: Registered protocol family 16 > [ 0.203704] DMA: preallocated 256 KiB pool for atomic coherent allocations > [ 0.211700] Reprogramming SDRC clock to 400000000 Hz > [ 0.229248] pinctrl-single 48002030.pinmux: 742 pins at pa fa002030 size 1484 > [ 0.231140] pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92 > [ 0.234588] OMAP GPIO hardware version 2.5 > [ 0.252685] platform 49022000.mcbsp: alias fck already exists > [ 0.253540] platform 49024000.mcbsp: alias fck already exists > [ 0.261749] omap-gpmc 6e000000.gpmc: GPMC revision 5.0 > [ 0.262084] gpmc_write_reg(), 176, > [ 0.262115] gpmc_ch_dump_reg, 1836, GPMC_CS_CONFIG1 0x00001800 > [ 0.262115] gpmc_ch_dump_reg, 1838, GPMC_CS_CONFIG2 0x00141400 > [ 0.262145] gpmc_ch_dump_reg, 1840, GPMC_CS_CONFIG3 0x00141400 > [ 0.262145] gpmc_ch_dump_reg, 1842, GPMC_CS_CONFIG4 0x0f010f01 > [ 0.262176] gpmc_ch_dump_reg, 1844, GPMC_CS_CONFIG5 0x010c1414 > [ 0.262176] gpmc_ch_dump_reg, 1846, GPMC_CS_CONFIG6 0x1f0f0a80 > [ 0.262207] gpmc_ch_dump_reg, 1848, GPMC_CS_CONFIG7 0x00000870 > [ 0.262207] gpmc_write_reg(), 176, > [ 0.262237] gpmc_ch_dump_reg, 1836, GPMC_CS_CONFIG1 0x00001800 > [ 0.262237] gpmc_ch_dump_reg, 1838, GPMC_CS_CONFIG2 0x00141400 > [ 0.262237] gpmc_ch_dump_reg, 1840, GPMC_CS_CONFIG3 0x00141400 > [ 0.262268] gpmc_ch_dump_reg, 1842, GPMC_CS_CONFIG4 0x0f010f01 > [ 0.262268] gpmc_ch_dump_reg, 1844, GPMC_CS_CONFIG5 0x010c1414 > [ 0.262298] gpmc_ch_dump_reg, 1846, GPMC_CS_CONFIG6 0x1f0f0a80 > [ 0.262298] gpmc_ch_dump_reg, 1848, GPMC_CS_CONFIG7 0x00000870 > [ 0.262695] gpmc_cs_enable_mem(), 433, > [ 0.262725] gpmc_ch_dump_reg, 1836, GPMC_CS_CONFIG1 0x00001800 > [ 0.262756] gpmc_ch_dump_reg, 1838, GPMC_CS_CONFIG2 0x00141400 > [ 0.262756] gpmc_ch_dump_reg, 1840, GPMC_CS_CONFIG3 0x00141400 > [ 0.262786] gpmc_ch_dump_reg, 1842, GPMC_CS_CONFIG4 0x0f010f01 > [ 0.262786] gpmc_ch_dump_reg, 1844, GPMC_CS_CONFIG5 0x010c1414 > [ 0.262817] gpmc_ch_dump_reg, 1846, GPMC_CS_CONFIG6 0x1f0f0a80 > [ 0.262817] gpmc_ch_dump_reg, 1848, GPMC_CS_CONFIG7 0x00000f70 > [ 0.262878] GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.262908] GPMC CS0: cs_rd_off : 4 ticks, 20 ns (was 20 ticks) 20 ns > [ 0.262939] GPMC CS0: cs_wr_off : 4 ticks, 20 ns (was 20 ticks) 20 ns > [ 0.262939] GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.262969] GPMC CS0: adv_rd_off: 4 ticks, 20 ns (was 20 ticks) 20 ns > [ 0.263000] GPMC CS0: adv_wr_off: 4 ticks, 20 ns (was 20 ticks) 20 ns > [ 0.263031] GPMC CS0: oe_on : 0 ticks, 0 ns (was 1 ticks) 0 ns > [ 0.263031] GPMC CS0: oe_off : 3 ticks, 15 ns (was 15 ticks) 15 ns > [ 0.263061] GPMC CS0: we_on : 0 ticks, 0 ns (was 1 ticks) 0 ns > [ 0.263092] GPMC CS0: we_off : 3 ticks, 15 ns (was 15 ticks) 15 ns > [ 0.263122] GPMC CS0: rd_cycle : 4 ticks, 20 ns (was 20 ticks) 20 ns > [ 0.263153] GPMC CS0: wr_cycle : 4 ticks, 20 ns (was 20 ticks) 20 ns > [ 0.263183] GPMC CS0: access : 3 ticks, 15 ns (was 12 ticks) 12 ns > [ 0.263183] GPMC CS0: page_burst_access: 0 ticks, 0 ns (was 1 ticks) 0 ns > [ 0.263214] GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.263244] GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 10 ticks) 0 ns > [ 0.263244] GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.263275] GPMC CS0: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns > [ 0.263305] GPMC CS0: wr_data_mux_bus: 3 ticks, 15 ns (was 15 ticks) 15 ns > [ 0.263336] GPMC CS0: wr_access : 7 ticks, 35 ns (was 31 ticks) 31 ns I think you need to convert the register settings to ns and put those values in the dts file. Cheers Jon ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: ARM: dts: omap3: NAND support - how? 2013-04-19 12:57 ` ARM: dts: omap3: NAND support - how? Jon Hunter @ 2013-04-19 13:06 ` Christoph Fritz 0 siblings, 0 replies; 19+ messages in thread From: Christoph Fritz @ 2013-04-19 13:06 UTC (permalink / raw) To: Jon Hunter; +Cc: Javier Martinez Canillas, Daniel Mack, linux-omap On Fri, 2013-04-19 at 07:57 -0500, Jon Hunter wrote: > On 04/19/2013 04:01 AM, Christoph Fritz wrote: > > I think you need to convert the register settings to ns and put those > values in the dts file. yes, I already did so. Please see my last mail. ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2013-05-16 15:49 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-04-18 19:03 ARM: dts: omap3: NAND support - how? Christoph Fritz 2013-04-18 19:39 ` Jon Hunter 2013-04-18 20:23 ` Christoph Fritz 2013-04-18 22:28 ` Jon Hunter 2013-04-18 22:48 ` Christoph Fritz 2013-04-18 23:24 ` Jon Hunter 2013-04-18 23:26 ` Jon Hunter 2013-04-19 9:01 ` Christoph Fritz 2013-04-19 12:02 ` Christoph Fritz 2013-04-19 14:00 ` Jon Hunter 2013-04-19 14:53 ` Christoph Fritz 2013-04-19 15:36 ` Jon Hunter 2013-04-19 15:48 ` Tony Lindgren 2013-04-19 15:56 ` Jon Hunter 2013-04-19 16:15 ` Tony Lindgren 2013-04-19 16:29 ` [PATCH] ARM: OMAP2+: nand: reorganize gpmc timing values Christoph Fritz 2013-05-16 15:49 ` Tony Lindgren 2013-04-19 12:57 ` ARM: dts: omap3: NAND support - how? Jon Hunter 2013-04-19 13:06 ` Christoph Fritz
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