3.9 regression : CAM_XCLKA wrong frequency setting.

3.9 regression : CAM_XCLKA wrong frequency setting.

[jean-philippe francois]

[-- Attachment #1: Type: text/plain, Size: 1524 bytes --]

Hi,

Laurent, you are on the recipient list because the symptom is visible
throug your driver. I found the other name looking in the clock
related files. Please apologize if you are not concerned by this mail.

Symptom :
External clock CAM_XCLKA frequency is wrong with 3.9, it was ok until
3.6. Everything else is working fine, except the fps are higher, and
the image quality sucks because the input clock is out of spec.
Oscilloscope measured freq is around 30 MHz instead of the 24 MHz the
sensor is asking for.

Hardware :
dm3730, with 19.2 MHz crystal, running at OPP100

The register frequency settings seems to be ok, and they are the same
as in 3.6.11 :
CM_CLKSEL2_PLL : 0x04816807
        19, 2 * 360 / 8 = 864 MHz
         this value is already set when I look at it in u-boot

CM_CLKSEL_CAM : 0x5
        864 / 5 = 172,8 MHz
        this value is set through the clock framework by the omap3isp
driver code

ISP.TCTRL_CTRL : 0x7
        172,8 / 7 = 24,685... MHz
         this value is set by the omap3isp driver code

However, as stated before, the actual output frequency is NOT 24 MHz
but around 30.

If dpll4 frequency is wrong, what other clock would be affected ?
What can I do to debug this ?
Laurent, I believe you have a camera add-on board for the beagle xm,
could you test and report wether you can reproduce this bug ?

Attached is the boot log with 3.9, with some debugging messages activated.

Thank you for your help,
Regards,

Jean-Philippe François

[-- Attachment #2: 3.9dmesg --]
[-- Type: application/octet-stream, Size: 28444 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.9.0 (cynove@jp) (gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-57) ) #5 PREEMPT Fri May 17 10:59:52 CEST 2013
[    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine: Cynove CYDM3730
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] On node 0 totalpages: 46592
[    0.000000] free_area_init_node: node 0, pgdat c054e01c, node_mem_map c056e000
[    0.000000]   Normal zone: 512 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 46592 pages, LIFO batch:15
[    0.000000] CPU: All CPU(s) started in SVC mode.
[    0.000000] OMAP3630 ES1.2 (l2cache iva sgx neon isp 192mhz_clk )
[    0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[    0.000000] pcpu-alloc: [0] 0 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 46080
[    0.000000] Kernel command line: console=ttyO2,115200n8 initrd=0x83000000,1664k mtdparts=omap2-nand.0:1024k(bootloaders),3072k(linux),1664k(ramfs),-(usr) ubi.mtd=3,2048 mem=55M@0x80000000 mem=128M@0x88000000 nohlt
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] __ex_table already sorted, skipping sort
[    0.000000] Memory: 55MB 127MB = 182MB total
[    0.000000] Memory: 177428k/177428k available, 9964k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xd0800000 - 0xff000000   ( 744 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .text : 0xc0008000 - 0xc04e8074   (4993 kB)
[    0.000000]       .init : 0xc04e9000 - 0xc05151f4   ( 177 kB)
[    0.000000]       .data : 0xc0516000 - 0xc05574a0   ( 262 kB)
[    0.000000]        .bss : 0xc05574a0 - 0xc056d9d0   (  90 kB)
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts
[    0.000000] Total of 96 interrupts on 1 active controller
[    0.000000] clock: associated clk dpll1_ck to clkdm dpll1_clkdm
[    0.000000] clock: associated clk dpll2_ck to clkdm dpll2_clkdm
[    0.000000] clock: associated clk dpll3_ck to clkdm dpll3_clkdm
[    0.000000] clock: associated clk dpll3_m3x2_ck to clkdm dpll3_clkdm
[    0.000000] clock: associated clk emu_core_alwon_ck to clkdm dpll3_clkdm
[    0.000000] clock: associated clk dpll4_ck to clkdm dpll4_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd omap_96m_alwon_fck's rate to 96000000 (div 0)
[    0.000000] omap2_clksel_recalc: recalc'd omap_48m_fck's rate to 48000000 (div 2)
[    0.000000] clock: associated clk dpll4_m2x2_ck to clkdm dpll4_clkdm
[    0.000000] clock: associated clk dpll4_m3x2_ck to clkdm dpll4_clkdm
[    0.000000] clock: associated clk dpll4_m4x2_ck to clkdm dpll4_clkdm
[    0.000000] clock: associated clk dpll4_m5x2_ck to clkdm dpll4_clkdm
[    0.000000] clock: associated clk dpll4_m6x2_ck to clkdm dpll4_clkdm
[    0.000000] clock: associated clk emu_per_alwon_ck to clkdm dpll4_clkdm
[    0.000000] clock: associated clk dpll5_ck to clkdm dpll5_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd clkout2_src_ck's rate to 54000000 (div 1)
[    0.000000] clock: could not associate clk clkout2_src_ck to clkdm core_clkdm
[    0.000000] clock: associated clk mpu_ck to clkdm mpu_clkdm
[    0.000000] clock: associated clk iva2_ck to clkdm iva2_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd sgx_fck's rate to 200000000 (div 2)
[    0.000000] clock: associated clk sgx_fck to clkdm sgx_clkdm
[    0.000000] clock: associated clk sgx_ick to clkdm sgx_clkdm
[    0.000000] clock: associated clk modem_fck to clkdm d2d_clkdm
[    0.000000] clock: associated clk sad2d_ick to clkdm d2d_clkdm
[    0.000000] clock: associated clk mad2d_ick to clkdm d2d_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt10_fck's rate to 32768 (div 1)
[    0.000000] clock: associated clk gpt10_fck to clkdm core_l4_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt11_fck's rate to 32768 (div 1)
[    0.000000] clock: associated clk gpt11_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk cpefuse_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk ts_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk usbtll_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk core_96m_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mmchs3_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mmchs2_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mspro_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mmchs1_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk i2c3_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk i2c2_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk i2c1_fck to clkdm core_l4_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd mcbsp5_fck's rate to 96000000 (div 1)
[    0.000000] clock: associated clk mcbsp5_fck to clkdm core_l4_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd mcbsp1_fck's rate to 96000000 (div 1)
[    0.000000] clock: associated clk mcbsp1_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk core_48m_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcspi4_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcspi3_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcspi2_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcspi1_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk uart2_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk uart1_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk core_12m_fck to clkdm core_l4_clkdm
[    0.000000] clock: associated clk hdq_fck to clkdm core_l4_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd ssi_ssr_fck_3430es2's rate to 266666666 (div 3)
[    0.000000] clock: associated clk ssi_ssr_fck_3430es2 to clkdm core_l4_clkdm
[    0.000000] clock: associated clk core_l3_ick to clkdm core_l3_clkdm
[    0.000000] clock: associated clk hsotgusb_ick_3430es2 to clkdm core_l3_clkdm
[    0.000000] clock: associated clk sdrc_ick to clkdm core_l3_clkdm
[    0.000000] clock: associated clk gpmc_fck to clkdm core_l3_clkdm
[    0.000000] clock: associated clk core_l4_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk usbtll_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mmchs3_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk icr_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk aes2_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk sha12_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk des2_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mmchs2_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mmchs1_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mspro_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk hdq_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcspi4_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcspi3_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcspi2_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcspi1_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk i2c3_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk i2c2_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk i2c1_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk uart2_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk uart1_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk gpt11_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk gpt10_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcbsp5_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mcbsp1_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk mailboxes_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk omapctrl_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk ssi_l4_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk ssi_ick_3430es2 to clkdm core_l4_clkdm
[    0.000000] clock: associated clk dss1_alwon_fck_3430es2 to clkdm dss_clkdm
[    0.000000] clock: associated clk dss_tv_fck to clkdm dss_clkdm
[    0.000000] clock: associated clk dss_96m_fck to clkdm dss_clkdm
[    0.000000] clock: associated clk dss2_alwon_fck to clkdm dss_clkdm
[    0.000000] clock: associated clk dss_ick_3430es2 to clkdm dss_clkdm
[    0.000000] clock: associated clk cam_mclk to clkdm cam_clkdm
[    0.000000] clock: associated clk cam_ick to clkdm cam_clkdm
[    0.000000] clock: associated clk csi2_96m_fck to clkdm cam_clkdm
[    0.000000] clock: associated clk usbhost_120m_fck to clkdm usbhost_clkdm
[    0.000000] clock: associated clk usbhost_48m_fck to clkdm usbhost_clkdm
[    0.000000] clock: associated clk usbhost_ick to clkdm usbhost_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd usim_fck's rate to 9600000 (div 2)
[    0.000000] omap2_clksel_recalc: recalc'd gpt1_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt1_fck to clkdm wkup_clkdm
[    0.000000] clock: associated clk wkup_32k_fck to clkdm wkup_clkdm
[    0.000000] clock: associated clk gpio1_dbck to clkdm wkup_clkdm
[    0.000000] clock: associated clk wdt2_fck to clkdm wkup_clkdm
[    0.000000] clock: associated clk wkup_l4_ick to clkdm wkup_clkdm
[    0.000000] clock: associated clk usim_ick to clkdm wkup_clkdm
[    0.000000] clock: associated clk wdt2_ick to clkdm wkup_clkdm
[    0.000000] clock: associated clk wdt1_ick to clkdm wkup_clkdm
[    0.000000] clock: associated clk gpio1_ick to clkdm wkup_clkdm
[    0.000000] clock: associated clk omap_32ksync_ick to clkdm wkup_clkdm
[    0.000000] clock: associated clk gpt12_ick to clkdm wkup_clkdm
[    0.000000] clock: associated clk gpt1_ick to clkdm wkup_clkdm
[    0.000000] clock: associated clk per_96m_fck to clkdm per_clkdm
[    0.000000] clock: associated clk per_48m_fck to clkdm per_clkdm
[    0.000000] clock: associated clk uart3_fck to clkdm per_clkdm
[    0.000000] clock: associated clk uart4_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt2_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt2_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt3_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt3_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt4_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt4_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt5_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt5_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt6_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt6_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt7_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt7_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt8_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt8_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd gpt9_fck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk gpt9_fck to clkdm per_clkdm
[    0.000000] clock: associated clk per_32k_alwon_fck to clkdm per_clkdm
[    0.000000] clock: associated clk gpio6_dbck to clkdm per_clkdm
[    0.000000] clock: associated clk gpio5_dbck to clkdm per_clkdm
[    0.000000] clock: associated clk gpio4_dbck to clkdm per_clkdm
[    0.000000] clock: associated clk gpio3_dbck to clkdm per_clkdm
[    0.000000] clock: associated clk gpio2_dbck to clkdm per_clkdm
[    0.000000] clock: associated clk wdt3_fck to clkdm per_clkdm
[    0.000000] clock: associated clk per_l4_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpio6_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpio5_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpio4_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpio3_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpio2_ick to clkdm per_clkdm
[    0.000000] clock: associated clk wdt3_ick to clkdm per_clkdm
[    0.000000] clock: associated clk uart3_ick to clkdm per_clkdm
[    0.000000] clock: associated clk uart4_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpt9_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpt8_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpt7_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpt6_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpt5_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpt4_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpt3_ick to clkdm per_clkdm
[    0.000000] clock: associated clk gpt2_ick to clkdm per_clkdm
[    0.000000] clock: associated clk mcbsp2_ick to clkdm per_clkdm
[    0.000000] clock: associated clk mcbsp3_ick to clkdm per_clkdm
[    0.000000] clock: associated clk mcbsp4_ick to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd mcbsp2_fck's rate to 96000000 (div 1)
[    0.000000] clock: associated clk mcbsp2_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd mcbsp3_fck's rate to 96000000 (div 1)
[    0.000000] clock: associated clk mcbsp3_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd mcbsp4_fck's rate to 96000000 (div 1)
[    0.000000] clock: associated clk mcbsp4_fck to clkdm per_clkdm
[    0.000000] omap2_clksel_recalc: recalc'd emu_src_ck's rate to 19200000 (div 1)
[    0.000000] clock: associated clk emu_src_ck to clkdm emu_clkdm
[    0.000000] clock: associated clk sr1_fck to clkdm wkup_clkdm
[    0.000000] clock: associated clk sr2_fck to clkdm wkup_clkdm
[    0.000000] clock: associated clk sr_l4_ick to clkdm core_l4_clkdm
[    0.000000] clock: associated clk gpt12_fck to clkdm wkup_clkdm
[    0.000000] clock: associated clk wdt1_fck to clkdm wkup_clkdm
[    0.000000] Clocking rate (Crystal/Core/MPU): 19.2/400/800 MHz
[    0.000000] clock: dpll5_ck: starting DPLL round_rate, target rate 120000000
[    0.000000] clock: dpll5_ck: m = 6: n = 1: new_rate = 115200000
[    0.000000] clock: dpll5_ck: m = 12: n = 2: new_rate = 115200000
[    0.000000] clock: dpll5_ck: m = 18: n = 3: new_rate = 115200000
[    0.000000] clock: dpll5_ck: m = 25: n = 4: new_rate = 120000000
[    0.000000] omap3_noncore_dpll_set_rate: dpll5_ck: set rate: locking rate to 120000000.
[    0.000000] clock: locking DPLL dpll5_ck
[    0.000000] clock: dpll5_ck transition to 'locked' in 205 loops
[    0.000000] clock: locking DPLL dpll5_ck
[    0.000000] clock: stopping DPLL dpll5_ck
[    0.000000] omap2_clksel_recalc: recalc'd gpt1_fck's rate to 32768 (div 1)
[    0.000000] clock: locking DPLL dpll1_ck
[    0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms
[    0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000000] Console: colour dummy device 80x30
[    0.000183] Calibrating delay loop... 531.66 BogoMIPS (lpj=2658304)
[    0.049957] pid_max: default: 32768 minimum: 301
[    0.050079] Mount-cache hash table entries: 512
[    0.050628] CPU: Testing write buffer coherency: ok
[    0.050872] Setting up static identity map for 0xc0376db8 - 0xc0376e28
[    0.053253] devtmpfs: initialized
[    0.055297] clock: locking DPLL dpll4_ck
[    0.055328] clock: stopping DPLL dpll4_ck
[    0.055328] clock: locking DPLL dpll4_ck
[    0.055358] clock: dpll4_ck transition to 'locked' in 7 loops
[    0.055389] clock: stopping DPLL dpll4_ck
[    0.055389] clock: locking DPLL dpll4_ck
[    0.055419] clock: dpll4_ck transition to 'locked' in 8 loops
[    0.055419] clock: stopping DPLL dpll4_ck
[    0.055450] clock: locking DPLL dpll4_ck
[    0.055480] clock: dpll4_ck transition to 'locked' in 8 loops
[    0.085723] omap_hwmod: mcbsp2: cannot be enabled for reset (3)
[    0.085968] clock: locking DPLL dpll5_ck
[    0.085998] clock: dpll5_ck transition to 'locked' in 4 loops
[    0.085998] clock: stopping DPLL dpll5_ck
[    0.099456] pinctrl core: initialized pinctrl subsystem
[    0.100341] regulator-dummy: no parameters
[    0.100738] NET: Registered protocol family 16
[    0.101226] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.101776] omap-gpmc omap-gpmc: GPMC revision 5.0
[    0.104736] OMAP GPIO hardware version 2.5
[    0.109283] omap_mux_get_by_name: Could not find signal uart1_rx.uart1_rx
[    0.109527] omap_mux_get_by_name: Could not find signal uart2_rx.uart2_rx
[    0.109771] omap_mux_get_by_name: Could not find signal uart3_rx_irrx.uart3_rx_irrx
[    0.110260] omap_mux_get_by_name: Could not find signal uart4_rx.uart4_rx
[    0.110473] omap_mux_init: Add partition: #1: core, flags: 4
[    0.118438] Reprogramming SDRC clock to 400000000 Hz
[    0.118469] GPMC CS4: cs_on     :   2 ticks,  10 ns (was   1 ticks)  10 ns
[    0.118469] GPMC CS4: cs_rd_off :  12 ticks,  60 ns (was  16 ticks)  60 ns
[    0.118499] GPMC CS4: cs_wr_off :  12 ticks,  60 ns (was  16 ticks)  60 ns
[    0.118499] GPMC CS4: adv_on    :   0 ticks,   0 ns (was   1 ticks)   0 ns
[    0.118499] GPMC CS4: adv_rd_off:   0 ticks,   0 ns (was   2 ticks)   0 ns
[    0.118530] GPMC CS4: adv_wr_off:   0 ticks,   0 ns (was   2 ticks)   0 ns
[    0.118530] GPMC CS4: oe_on     :   2 ticks,  10 ns (was   3 ticks)  10 ns
[    0.118530] GPMC CS4: oe_off    :  12 ticks,  60 ns (was  16 ticks)  60 ns
[    0.118560] GPMC CS4: we_on     :   2 ticks,  10 ns (was   3 ticks)  10 ns
[    0.118560] GPMC CS4: we_off    :  12 ticks,  60 ns (was  16 ticks)  60 ns
[    0.118560] GPMC CS4: rd_cycle  :  14 ticks,  70 ns (was  17 ticks)  70 ns
[    0.118591] GPMC CS4: wr_cycle  :  14 ticks,  70 ns (was  17 ticks)  70 ns
[    0.118591] GPMC CS4: access    :  12 ticks,  60 ns (was  15 ticks)  60 ns
[    0.118591] GPMC CS4: page_burst_access:   0 ticks,   0 ns (was   1 ticks)   0 ns
[    0.118621] GPMC CS4: bus_turnaround:   0 ticks,   0 ns (was   0 ticks)   0 ns
[    0.118621] GPMC CS4: cycle2cycle_delay:   0 ticks,   0 ns (was   0 ticks)   0 ns
[    0.118621] GPMC CS4: wait_monitoring:   0 ticks,   0 ns (was   0 ticks)   0 ns
[    0.118652] GPMC CS4: clk_activation:   0 ticks,   0 ns (was   0 ticks)   0 ns
[    0.118652] GPMC CS4: wr_data_mux_bus:   0 ticks,   0 ns (was   3 ticks)   0 ns
[    0.118682] GPMC CS4: wr_access :   2 ticks,  10 ns (was  15 ticks)  10 ns
[    0.133575] OMAP DMA hardware revision 5.0
[    0.145385] bio: create slab <bio-0> at 0
[    0.170501] omap-dma-engine omap-dma-engine: OMAP DMA engine driver
[    0.170989] v33: 3300 mV 
[    0.171295] v18: 1800 mV 
[    0.172546] SCSI subsystem initialized
[    0.173309] usbcore: registered new interface driver usbfs
[    0.173492] usbcore: registered new interface driver hub
[    0.173706] usbcore: registered new device driver usb
[    0.175231] omap_i2c omap_i2c.1: bus 1 rev4.4 at 100 kHz
[    0.175445] media: Linux media interface: v0.10
[    0.175598] Linux video capture interface: v2.00
[    0.176483] omap-iommu omap-iommu.0: mmu_isp registered
[    0.177947] cfg80211: Calling CRDA to update world regulatory domain
[    0.178222] Switching to clocksource 32k_counter
[    0.195922] NET: Registered protocol family 2
[    0.196472] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[    0.196533] TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
[    0.196563] TCP: Hash tables configured (established 2048 bind 2048)
[    0.196624] TCP: reno registered
[    0.196624] UDP hash table entries: 256 (order: 0, 4096 bytes)
[    0.196655] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[    0.196868] NET: Registered protocol family 1
[    0.197448] Trying to unpack rootfs image as initramfs...
[    0.320953] Freeing initrd memory: 1664K
[    0.324371] msgmni has been set to 349
[    0.325561] io scheduler noop registered
[    0.325561] io scheduler deadline registered
[    0.325592] io scheduler cfq registered (default)
[    0.326232] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 88) is a OMAP UART0
[    0.326721] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 89) is a OMAP UART1
[    0.327209] omap_uart.2: ttyO2 at MMIO 0x49020000 (irq = 90) is a OMAP UART2
[    0.978637] console [ttyO2] enabled
[    0.982818] omap_uart.3: ttyO3 at MMIO 0x49042000 (irq = 96) is a OMAP UART3
[    0.990814] Initialising atsha204 module
[    0.995147] entering sha204p_wakeup
[    1.007629] atsha204 SN : 1235ad73743fc42ee
[    1.012054] atsha204 successfully probed
[    1.025238] brd: module loaded
[    1.033294] loop: module loaded
[    1.038177] Missing elm_id property, fall back to Software BCH
[    1.046508] enabling NAND BCH ecc with 4-bit correction
[    1.052368] ONFI param page 0 valid
[    1.056030] ONFI flash detected
[    1.059387] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xac (Micron MT29F4G08ABBDAHC), 512MiB, page size: 2048, OOB size: 64
[    1.071380] 4 cmdlinepart partitions found on MTD device omap2-nand.0
[    1.078186] Creating 4 MTD partitions on "omap2-nand.0":
[    1.083831] 0x000000000000-0x000000100000 : "bootloaders"
[    1.091735] 0x000000100000-0x000000400000 : "linux"
[    1.100616] 0x000000400000-0x0000005a0000 : "ramfs"
[    1.108154] 0x0000005a0000-0x000020000000 : "usr"
[    1.530761] ks8851_mll ks8851_mll (unregistered net_device): message enable is 0
[    1.538635] ks8851_mll ks8851_mll (unregistered net_device): the selftest passes
[    1.558105] ks8851_mll ks8851_mll eth0: Mac address is: b8:ba:72:02:00:00
[    1.565307] ks8851_mll ks8851_mll eth0: Found chip, family: 0x88, id: 0x7, rev: 0x1
[    1.573699] usbcore: registered new interface driver ax88179_178a
[    1.580291] usbcore: registered new interface driver cdc_ether
[    1.586608] usbcore: registered new interface driver smsc95xx
[    1.592681] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    1.600250] mousedev: PS/2 mouse device common for all mice
[    1.610565] rtc-s35390a 1-0030: rtc core: registered rtc-s35390a as rtc0
[    1.617767] i2c /dev entries driver
[    1.623565] tmp102 1-0048: initialized
[    1.629211] tmp102 1-0049: initialized
[    1.634185] omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
[    1.642211] omap-dma-engine omap-dma-engine: allocating channel for 62
[    1.649169] omap-dma-engine omap-dma-engine: allocating channel for 61
[    1.656127] omap_hsmmc.0 supply vmmc_aux not found, using dummy regulator
[    2.028686] omap-dma-engine omap-dma-engine: allocating channel for 48
[    2.035614] omap-dma-engine omap-dma-engine: allocating channel for 47
[    2.043579] omap_hsmmc.1 supply vmmc_aux not found, using dummy regulator
[    2.089202] usbcore: registered new interface driver usbhid
[    2.095062] usbhid: USB HID core driver
[    2.099395] TCP: cubic registered
[    2.102874] NET: Registered protocol family 17
[    2.107604] NET: Registered protocol family 15
[    2.112274] lib80211: common routines for IEEE802.11 drivers
[    2.118225] lib80211_crypt: registered algorithm 'NULL'
[    2.118225] lib80211_crypt: registered algorithm 'WEP'
[    2.118225] lib80211_crypt: registered algorithm 'CCMP'
[    2.118255] lib80211_crypt: registered algorithm 'TKIP'
[    2.118316] Key type dns_resolver registered
[    2.122894] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
[    2.131988] omap_vc_init_channel: No PMIC info for vdd_core
[    2.137847] omap_vp_init: No PMIC info for vdd_core
[    2.143005] omap_vc_init_channel: No PMIC info for vdd_mpu_iva
[    2.149139] omap_vp_init: No PMIC info for vdd_mpu_iva
[    2.154541] omap2_set_init_voltage: unable to find boot up OPP for vdd_mpu_iva
[    2.163208] omap2_set_init_voltage: unable to set vdd_mpu_iva
[    2.169311] omap_vc_pre_scale: Insufficient pmic info to scale the vdd_core
[    2.182037] UBI: attaching mtd3 to ubi0
[    2.194793] mmc1: new high speed SDIO card at address 0001
[    5.688049] UBI: scanning is finished
[    5.705413] UBI warning: print_rsvd_warning: cannot reserve enough PEBs for bad PEB handling, reserved 40, need 80
[    5.718597] UBI: attached mtd3 (name "usr", size 506 MiB) to ubi0
[    5.725006] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
[    5.732177] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 512
[    5.739135] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
[    5.746337] UBI: good PEBs: 4051, bad PEBs: 0, corrupted PEBs: 0
[    5.752655] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128
[    5.760131] UBI: max/mean erase counter: 3/2, WL threshold: 4096, image sequence number: 834340315
[    5.769561] UBI: available PEBs: 0, total reserved PEBs: 4051, PEBs reserved for bad PEB handling: 40
[    5.779266] UBI: background thread "ubi_bgt0d" started, PID 584
[    5.786468] rtc-s35390a 1-0030: setting system clock to 2013-05-17 11:07:25 UTC (1368788845)
[    5.796081] Freeing init memory: 176K
[    5.848510] UBIFS: background thread "ubifs_bgt0_0" started, PID 596
[    5.959777] UBIFS: mounted UBI device 0, volume 0, name "user"(null)
[    5.966461] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
[    5.976074] UBIFS: FS size: 506761216 bytes (483 MiB, 3991 LEBs), journal size 25395200 bytes (24 MiB, 200 LEBs)
[    5.986755] UBIFS: reserved for root: 4952683 bytes (4836 KiB)
[    5.992889] UBIFS: media format: w4/r0 (latest is w4/r0), UUID DF59BB01-CE71-4F87-A0B9-E0FE6685730F, small LPT model
[    8.344299] atsha204 1-0064: sha204p_send_command : xfer failed, err = -121
[    8.351959] entering sha204p_wakeup
[    8.993225] CMEMK module: built on May 16 2013 at 11:10:10
[    9.004211]   Reference Linux version 3.9.0
[    9.009216]   File /home/cynove/src/ARM_ptxdist/dm3730/platform-CYDM3730/build-target/dvsdk_dm3730_4_03/linuxutils_2_26_02_05/packages/ti/sdo/linuxutils/cmem/src/module/cmemk.c
[    9.030059] CMEM Range Overlaps Kernel Physical - allowing overlap
[    9.036560] CMEM phys_start (0x83700000) overlaps kernel (0x80000000 -> 0x8b600000)
[    9.050201] allocated heap buffer 0xd1000000 of size 0x2200000
[    9.056335] heap fallback enabled - will try heap if pool buffer is not available
[    9.068267] cmemk initialized
[    9.108978] <1>DSPLINK Module (1.65.01.05_eng) created on Date: May 16 2013 Time: 11:10:39
[    9.156280] SDMAK module: built on May 16 2013 at 11:10:11
[    9.165588]   Reference Linux version 3.9.0
[    9.171844]   File /home/cynove/src/ARM_ptxdist/dm3730/platform-CYDM3730/build-target/dvsdk_dm3730_4_03/linuxutils_2_26_02_05/packages/ti/sdo/linuxutils/sdma/src/module/sdmak.c
[   35.215332] omap3isp supply VDD_CSIPHY1 not found, using dummy regulator
[   35.226135] omap3isp supply VDD_CSIPHY2 not found, using dummy regulator
[   35.233703] omap3isp omap3isp: Revision 15.0 found
[   35.238922] omap3isp omap3isp: entering isp_enable_clocks
[   35.239105] omap-iommu omap-iommu.0: mmu_isp: version 1.1
[   35.244934] omap3isp omap3isp: hist: DMA channel = 4
[   35.281005] ov10x33 1-0010: ov10x33_registered
[   35.285675] Entering cam_set_xclk
[   35.292755] omap3isp omap3isp: isp_set_xclk(): cam_xclka set to 24685714 Hz
[   35.294342] ov10x33 1-0010: sensor id : 0xa630
[   36.464813] Entering cam_set_xclk
[   36.468292] omap3isp omap3isp: isp_set_xclk(): cam_xclka set to 0 Hz
[   36.561126] Entering cam_set_xclk
[   36.564636] omap3isp omap3isp: entering isp_enable_clocks
[   36.565185] omap3isp omap3isp: isp_set_xclk(): cam_xclka set to 24685714 Hz
[   36.571014] omap3isp omap3isp: resizer_set_selection: L=106,T=0,W=1072,H=800,which=1
[   36.571044] omap3isp omap3isp: resizer_set_selection: input=1280x800, output=1280x800

Re: 3.9 regression : CAM_XCLKA wrong frequency setting.

[jean-philippe francois]

2013/5/17 jean-philippe francois <jp.francois@cynove.com>:
> Hi,
>
> Laurent, you are on the recipient list because the symptom is visible
> throug your driver. I found the other name looking in the clock
> related files. Please apologize if you are not concerned by this mail.
>
> Symptom :
> External clock CAM_XCLKA frequency is wrong with 3.9, it was ok until
> 3.6. Everything else is working fine, except the fps are higher, and
> the image quality sucks because the input clock is out of spec.
> Oscilloscope measured freq is around 30 MHz instead of the 24 MHz the
> sensor is asking for.
>
> Hardware :
> dm3730, with 19.2 MHz crystal, running at OPP100
>
> The register frequency settings seems to be ok, and they are the same
> as in 3.6.11 :
> CM_CLKSEL2_PLL : 0x04816807
>         19, 2 * 360 / 8 = 864 MHz
>          this value is already set when I look at it in u-boot
>
> CM_CLKSEL_CAM : 0x5
>         864 / 5 = 172,8 MHz
>         this value is set through the clock framework by the omap3isp
> driver code
>
> ISP.TCTRL_CTRL : 0x7
>         172,8 / 7 = 24,685... MHz
>          this value is set by the omap3isp driver code
>
> However, as stated before, the actual output frequency is NOT 24 MHz
> but around 30.
>
> If dpll4 frequency is wrong, what other clock would be affected ?

As usual, writing a mail brings up new idea. Sorry to use the lists
as rubber duck debug partner, but I still need your help.

Obviously, dpll4 frequency is correct, because it sources the 96 and
48 MHz clock.
I can check it measuring bit time on uart3tx : 8.6usec for 115200 => Ok

30 MHz is 1.25 * 24 MHz
CM_CLKSEL_CAM reset value is 4, programmed value is 5,
So I did the following, while looking at CAM_XCLKA on scope :

# devmem 0x48004f40
0x00000005
# devmem 0x48004f40 32 5  -> freq = 30 MHz
# devmem 0x48004f40 32 4  -> freq = 30 MHz
# devmem 0x48004f40 32 5  -> freq = 24 MHz

So there is something nasty in the setup sequence of cam_mclk and dpll4_m5ckx2
that prevents the new divisor value to be used by the hardware.
I will dive into the code to see where things went wrong, but I am a
bit lost here.

> What can I do to debug this ?
> Laurent, I believe you have a camera add-on board for the beagle xm,
> could you test and report wether you can reproduce this bug ?
>
> Attached is the boot log with 3.9, with some debugging messages activated.
>
> Thank you for your help,
> Regards,
>
> Jean-Philippe François
--
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[PATCH] ARM : omap3 : fix wrong container_of in clock36xx.c

[Jean-Philippe Francois]

omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock
to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock
have parent defined as clk_divider.
Fix the function to use clk_divider. 
Tested with  3.9 on dm3730.

Signed-off-by: Jean-Philippe François <jp.francois@cynove.com>

Index: b/arch/arm/mach-omap2/clock36xx.c
===================================================================
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -20,11 +20,12 @@
 
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 
 #include "clock.h"
 #include "clock36xx.h"
-
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 /**
  * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@
  */
 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 {
-	struct clk_hw_omap *parent;
+	struct clk_divider *parent;
 	struct clk_hw *parent_hw;
-	u32 dummy_v, orig_v, clksel_shift;
+	u32 dummy_v, orig_v;
 	int ret;
 
 	/* Clear PWRDN bit of HSDIVIDER */
 	ret = omap2_dflt_clk_enable(clk);
 
 	parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
-	parent = to_clk_hw_omap(parent_hw);
+	parent = to_clk_divider(parent_hw);
 
 	/* Restore the dividers */
 	if (!ret) {
-		clksel_shift = __ffs(parent->clksel_mask);
-		orig_v = __raw_readl(parent->clksel_reg);
+		orig_v = __raw_readl(parent->reg);
 		dummy_v = orig_v;
 
 		/* Write any other value different from the Read value */
-		dummy_v ^= (1 << clksel_shift);
-		__raw_writel(dummy_v, parent->clksel_reg);
+		dummy_v ^= (1 << parent->shift);
+		__raw_writel(dummy_v, parent->reg);
 
 		/* Write the original divider */
-		__raw_writel(orig_v, parent->clksel_reg);
+		__raw_writel(orig_v, parent->reg);
 	}
 
 	return ret;
--
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Re: [PATCH] ARM : omap3 : fix wrong container_of in clock36xx.c

[Mike Turquette]

Quoting Jean-Philippe Francois (2013-05-17 08:51:26)
> omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock
> to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock
> have parent defined as clk_divider.
> Fix the function to use clk_divider. 
> Tested with  3.9 on dm3730.
> 
> Signed-off-by: Jean-Philippe Fran��ois <jp.francois@cynove.com>
> 
> Index: b/arch/arm/mach-omap2/clock36xx.c
> ===================================================================
> --- a/arch/arm/mach-omap2/clock36xx.c
> +++ b/arch/arm/mach-omap2/clock36xx.c
> @@ -20,11 +20,12 @@
>  
>  #include <linux/kernel.h>
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>  #include <linux/io.h>
>  
>  #include "clock.h"
>  #include "clock36xx.h"
> -
> +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
>  
>  /**
>   * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
> @@ -39,29 +40,28 @@
>   */
>  int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
>  {
> -       struct clk_hw_omap *parent;
> +       struct clk_divider *parent;
>         struct clk_hw *parent_hw;
> -       u32 dummy_v, orig_v, clksel_shift;
> +       u32 dummy_v, orig_v;
>         int ret;
>  
>         /* Clear PWRDN bit of HSDIVIDER */
>         ret = omap2_dflt_clk_enable(clk);
>  
>         parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
> -       parent = to_clk_hw_omap(parent_hw);
> +       parent = to_clk_divider(parent_hw);

Peaking inside of clock structures was OK back in the legacy clock days,
and even if the clocks are the same type (clk_hw_omap), but having omap
code dig into clk-divider structures is pretty gross.

How about reentrantly calling clk_set_rate here to achieve the same
effect?

	/* kick parent's clksel register after toggling PWRDN bit */
	struct clk *parent = clk_get_parent(clk->clk);
	unsigned long parent_rate = clk_get_rate(parent);
	clk_set_rate(parent, parent_rate/2);
	clk_set_rate(parent, parent_rate);

Regards,
Mike

>  
>         /* Restore the dividers */
>         if (!ret) {
> -               clksel_shift = __ffs(parent->clksel_mask);
> -               orig_v = __raw_readl(parent->clksel_reg);
> +               orig_v = __raw_readl(parent->reg);
>                 dummy_v = orig_v;
>  
>                 /* Write any other value different from the Read value */
> -               dummy_v ^= (1 << clksel_shift);
> -               __raw_writel(dummy_v, parent->clksel_reg);
> +               dummy_v ^= (1 << parent->shift);
> +               __raw_writel(dummy_v, parent->reg);
>  
>                 /* Write the original divider */
> -               __raw_writel(orig_v, parent->clksel_reg);
> +               __raw_writel(orig_v, parent->reg);
>         }
>  
>         return ret;
--
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