* [RFC 01/23] gpio/omap: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-19 9:29 ` Linus Walleij
2013-11-19 18:21 ` Santosh Shilimkar
2013-11-16 0:01 ` [RFC 02/23] watchdog: omap_wdt: " Taras Kondratiuk
` (20 subsequent siblings)
21 siblings, 2 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Santosh Shilimkar,
Kevin Hilman, Linus Walleij, linux-gpio, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/gpio/gpio-omap.c | 188 +++++++++++++++++++++++-----------------------
1 file changed, 94 insertions(+), 94 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 89675f8..8f4ad0f 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -108,12 +108,12 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
u32 l;
reg += bank->regs->direction;
- l = __raw_readl(reg);
+ l = readl_relaxed(reg);
if (is_input)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- __raw_writel(l, reg);
+ writel_relaxed(l, reg);
bank->context.oe = l;
}
@@ -132,7 +132,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
bank->context.dataout &= ~l;
}
- __raw_writel(l, reg);
+ writel_relaxed(l, reg);
}
/* set data out value using mask register */
@@ -142,12 +142,12 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
u32 gpio_bit = GPIO_BIT(bank, gpio);
u32 l;
- l = __raw_readl(reg);
+ l = readl_relaxed(reg);
if (enable)
l |= gpio_bit;
else
l &= ~gpio_bit;
- __raw_writel(l, reg);
+ writel_relaxed(l, reg);
bank->context.dataout = l;
}
@@ -155,26 +155,26 @@ static int _get_gpio_datain(struct gpio_bank *bank, int offset)
{
void __iomem *reg = bank->base + bank->regs->datain;
- return (__raw_readl(reg) & (1 << offset)) != 0;
+ return (readl_relaxed(reg) & (1 << offset)) != 0;
}
static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
{
void __iomem *reg = bank->base + bank->regs->dataout;
- return (__raw_readl(reg) & (1 << offset)) != 0;
+ return (readl_relaxed(reg) & (1 << offset)) != 0;
}
static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
{
- int l = __raw_readl(base + reg);
+ int l = readl_relaxed(base + reg);
if (set)
l |= mask;
else
l &= ~mask;
- __raw_writel(l, base + reg);
+ writel_relaxed(l, base + reg);
}
static inline void _gpio_dbck_enable(struct gpio_bank *bank)
@@ -183,7 +183,7 @@ static inline void _gpio_dbck_enable(struct gpio_bank *bank)
clk_enable(bank->dbck);
bank->dbck_enabled = true;
- __raw_writel(bank->dbck_enable_mask,
+ writel_relaxed(bank->dbck_enable_mask,
bank->base + bank->regs->debounce_en);
}
}
@@ -196,7 +196,7 @@ static inline void _gpio_dbck_disable(struct gpio_bank *bank)
* enabled but the clock is not, GPIO module seems to be unable
* to detect events and generate interrupts at least on OMAP3.
*/
- __raw_writel(0, bank->base + bank->regs->debounce_en);
+ writel_relaxed(0, bank->base + bank->regs->debounce_en);
clk_disable(bank->dbck);
bank->dbck_enabled = false;
@@ -233,10 +233,10 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
clk_enable(bank->dbck);
reg = bank->base + bank->regs->debounce;
- __raw_writel(debounce, reg);
+ writel_relaxed(debounce, reg);
reg = bank->base + bank->regs->debounce_en;
- val = __raw_readl(reg);
+ val = readl_relaxed(reg);
if (debounce)
val |= l;
@@ -244,7 +244,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
val &= ~l;
bank->dbck_enable_mask = val;
- __raw_writel(val, reg);
+ writel_relaxed(val, reg);
clk_disable(bank->dbck);
/*
* Enable debounce clock per module.
@@ -283,12 +283,12 @@ static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
bank->dbck_enable_mask &= ~gpio_bit;
bank->context.debounce_en &= ~gpio_bit;
- __raw_writel(bank->context.debounce_en,
+ writel_relaxed(bank->context.debounce_en,
bank->base + bank->regs->debounce_en);
if (!bank->dbck_enable_mask) {
bank->context.debounce = 0;
- __raw_writel(bank->context.debounce, bank->base +
+ writel_relaxed(bank->context.debounce, bank->base +
bank->regs->debounce);
clk_disable(bank->dbck);
bank->dbck_enabled = false;
@@ -311,18 +311,18 @@ static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
trigger & IRQ_TYPE_EDGE_FALLING);
bank->context.leveldetect0 =
- __raw_readl(bank->base + bank->regs->leveldetect0);
+ readl_relaxed(bank->base + bank->regs->leveldetect0);
bank->context.leveldetect1 =
- __raw_readl(bank->base + bank->regs->leveldetect1);
+ readl_relaxed(bank->base + bank->regs->leveldetect1);
bank->context.risingdetect =
- __raw_readl(bank->base + bank->regs->risingdetect);
+ readl_relaxed(bank->base + bank->regs->risingdetect);
bank->context.fallingdetect =
- __raw_readl(bank->base + bank->regs->fallingdetect);
+ readl_relaxed(bank->base + bank->regs->fallingdetect);
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
bank->context.wake_en =
- __raw_readl(bank->base + bank->regs->wkup_en);
+ readl_relaxed(bank->base + bank->regs->wkup_en);
}
/* This part needs to be executed always for OMAP{34xx, 44xx} */
@@ -347,8 +347,8 @@ static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
exit:
bank->level_mask =
- __raw_readl(bank->base + bank->regs->leveldetect0) |
- __raw_readl(bank->base + bank->regs->leveldetect1);
+ readl_relaxed(bank->base + bank->regs->leveldetect0) |
+ readl_relaxed(bank->base + bank->regs->leveldetect1);
}
#ifdef CONFIG_ARCH_OMAP1
@@ -366,13 +366,13 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
reg += bank->regs->irqctrl;
- l = __raw_readl(reg);
+ l = readl_relaxed(reg);
if ((l >> gpio) & 1)
l &= ~(1 << gpio);
else
l |= 1 << gpio;
- __raw_writel(l, reg);
+ writel_relaxed(l, reg);
}
#else
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
@@ -390,7 +390,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
} else if (bank->regs->irqctrl) {
reg += bank->regs->irqctrl;
- l = __raw_readl(reg);
+ l = readl_relaxed(reg);
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
bank->toggle_mask |= 1 << gpio;
if (trigger & IRQ_TYPE_EDGE_RISING)
@@ -400,7 +400,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
else
return -EINVAL;
- __raw_writel(l, reg);
+ writel_relaxed(l, reg);
} else if (bank->regs->edgectrl1) {
if (gpio & 0x08)
reg += bank->regs->edgectrl2;
@@ -408,7 +408,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
reg += bank->regs->edgectrl1;
gpio &= 0x07;
- l = __raw_readl(reg);
+ l = readl_relaxed(reg);
l &= ~(3 << (gpio << 1));
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 2 << (gpio << 1);
@@ -418,8 +418,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
/* Enable wake-up during idle for dynamic tick */
_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
bank->context.wake_en =
- __raw_readl(bank->base + bank->regs->wkup_en);
- __raw_writel(l, reg);
+ readl_relaxed(bank->base + bank->regs->wkup_en);
+ writel_relaxed(l, reg);
}
return 0;
}
@@ -430,17 +430,17 @@ static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset)
void __iomem *reg = bank->base + bank->regs->pinctrl;
/* Claim the pin for MPU */
- __raw_writel(__raw_readl(reg) | (1 << offset), reg);
+ writel_relaxed(readl_relaxed(reg) | (1 << offset), reg);
}
if (bank->regs->ctrl && !BANK_USED(bank)) {
void __iomem *reg = bank->base + bank->regs->ctrl;
u32 ctrl;
- ctrl = __raw_readl(reg);
+ ctrl = readl_relaxed(reg);
/* Module is enabled, clocks are not gated */
ctrl &= ~GPIO_MOD_CTRL_BIT;
- __raw_writel(ctrl, reg);
+ writel_relaxed(ctrl, reg);
bank->context.ctrl = ctrl;
}
}
@@ -455,17 +455,17 @@ static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset)
/* Disable wake-up during idle for dynamic tick */
_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
bank->context.wake_en =
- __raw_readl(bank->base + bank->regs->wkup_en);
+ readl_relaxed(bank->base + bank->regs->wkup_en);
}
if (bank->regs->ctrl && !BANK_USED(bank)) {
void __iomem *reg = bank->base + bank->regs->ctrl;
u32 ctrl;
- ctrl = __raw_readl(reg);
+ ctrl = readl_relaxed(reg);
/* Module is disabled, clocks are gated */
ctrl |= GPIO_MOD_CTRL_BIT;
- __raw_writel(ctrl, reg);
+ writel_relaxed(ctrl, reg);
bank->context.ctrl = ctrl;
}
}
@@ -474,7 +474,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
{
void __iomem *reg = bank->base + bank->regs->direction;
- return __raw_readl(reg) & mask;
+ return readl_relaxed(reg) & mask;
}
static int gpio_irq_type(struct irq_data *d, unsigned type)
@@ -530,16 +530,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
void __iomem *reg = bank->base;
reg += bank->regs->irqstatus;
- __raw_writel(gpio_mask, reg);
+ writel_relaxed(gpio_mask, reg);
/* Workaround for clearing DSP GPIO interrupts to allow retention */
if (bank->regs->irqstatus2) {
reg = bank->base + bank->regs->irqstatus2;
- __raw_writel(gpio_mask, reg);
+ writel_relaxed(gpio_mask, reg);
}
/* Flush posted write for the irq status to avoid spurious interrupts */
- __raw_readl(reg);
+ readl_relaxed(reg);
}
static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -554,7 +554,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
u32 mask = (1 << bank->width) - 1;
reg += bank->regs->irqenable;
- l = __raw_readl(reg);
+ l = readl_relaxed(reg);
if (bank->regs->irqenable_inv)
l = ~l;
l &= mask;
@@ -572,7 +572,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
bank->context.irqenable1 |= gpio_mask;
} else {
reg += bank->regs->irqenable;
- l = __raw_readl(reg);
+ l = readl_relaxed(reg);
if (bank->regs->irqenable_inv)
l &= ~gpio_mask;
else
@@ -580,7 +580,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
bank->context.irqenable1 = l;
}
- __raw_writel(l, reg);
+ writel_relaxed(l, reg);
}
static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -594,7 +594,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
bank->context.irqenable1 &= ~gpio_mask;
} else {
reg += bank->regs->irqenable;
- l = __raw_readl(reg);
+ l = readl_relaxed(reg);
if (bank->regs->irqenable_inv)
l |= gpio_mask;
else
@@ -602,7 +602,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
bank->context.irqenable1 = l;
}
- __raw_writel(l, reg);
+ writel_relaxed(l, reg);
}
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
@@ -638,7 +638,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
else
bank->context.wake_en &= ~gpio_bit;
- __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
+ writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
@@ -740,7 +740,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
u32 enabled;
enabled = _get_gpio_irqbank_mask(bank);
- isr_saved = isr = __raw_readl(isr_reg) & enabled;
+ isr_saved = isr = readl_relaxed(isr_reg) & enabled;
if (bank->level_mask)
level_mask = bank->level_mask & enabled;
@@ -874,7 +874,7 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
- __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
+ writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
@@ -889,7 +889,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
- __raw_writel(bank->context.wake_en, mask_reg);
+ writel_relaxed(bank->context.wake_en, mask_reg);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
@@ -1011,7 +1011,7 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
if (called || bank->regs->revision == USHRT_MAX)
return;
- rev = __raw_readw(bank->base + bank->regs->revision);
+ rev = readw_relaxed(bank->base + bank->regs->revision);
pr_info("OMAP GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
@@ -1032,20 +1032,20 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
l = 0xffff;
if (bank->is_mpuio) {
- __raw_writel(l, bank->base + bank->regs->irqenable);
+ writel_relaxed(l, bank->base + bank->regs->irqenable);
return;
}
_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
_gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
if (bank->regs->debounce_en)
- __raw_writel(0, base + bank->regs->debounce_en);
+ writel_relaxed(0, base + bank->regs->debounce_en);
/* Save OE default value (0xffffffff) in the context */
- bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
+ bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
/* Initialize interface clk ungated, module enabled */
if (bank->regs->ctrl)
- __raw_writel(0, base + bank->regs->ctrl);
+ writel_relaxed(0, base + bank->regs->ctrl);
bank->dbck = clk_get(bank->dev, "dbclk");
if (IS_ERR(bank->dbck))
@@ -1282,11 +1282,11 @@ static int omap_gpio_runtime_suspend(struct device *dev)
*/
wake_low = bank->context.leveldetect0 & bank->context.wake_en;
if (wake_low)
- __raw_writel(wake_low | bank->context.fallingdetect,
+ writel_relaxed(wake_low | bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect);
wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
if (wake_hi)
- __raw_writel(wake_hi | bank->context.risingdetect,
+ writel_relaxed(wake_hi | bank->context.risingdetect,
bank->base + bank->regs->risingdetect);
if (!bank->enabled_non_wakeup_gpios)
@@ -1301,7 +1301,7 @@ static int omap_gpio_runtime_suspend(struct device *dev)
* non-wakeup GPIOs. Otherwise spurious IRQs will be
* generated. See OMAP2420 Errata item 1.101.
*/
- bank->saved_datain = __raw_readl(bank->base +
+ bank->saved_datain = readl_relaxed(bank->base +
bank->regs->datain);
l1 = bank->context.fallingdetect;
l2 = bank->context.risingdetect;
@@ -1309,8 +1309,8 @@ static int omap_gpio_runtime_suspend(struct device *dev)
l1 &= ~bank->enabled_non_wakeup_gpios;
l2 &= ~bank->enabled_non_wakeup_gpios;
- __raw_writel(l1, bank->base + bank->regs->fallingdetect);
- __raw_writel(l2, bank->base + bank->regs->risingdetect);
+ writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
+ writel_relaxed(l2, bank->base + bank->regs->risingdetect);
bank->workaround_enabled = true;
@@ -1358,9 +1358,9 @@ static int omap_gpio_runtime_resume(struct device *dev)
* generate a PRCM wakeup. Here we restore the
* pre-runtime_suspend() values for edge triggering.
*/
- __raw_writel(bank->context.fallingdetect,
+ writel_relaxed(bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect);
- __raw_writel(bank->context.risingdetect,
+ writel_relaxed(bank->context.risingdetect,
bank->base + bank->regs->risingdetect);
if (bank->loses_context) {
@@ -1382,7 +1382,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
return 0;
}
- l = __raw_readl(bank->base + bank->regs->datain);
+ l = readl_relaxed(bank->base + bank->regs->datain);
/*
* Check if any of the non-wakeup interrupt GPIOs have changed
@@ -1412,24 +1412,24 @@ static int omap_gpio_runtime_resume(struct device *dev)
if (gen) {
u32 old0, old1;
- old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
- old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
+ old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
+ old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
if (!bank->regs->irqstatus_raw0) {
- __raw_writel(old0 | gen, bank->base +
+ writel_relaxed(old0 | gen, bank->base +
bank->regs->leveldetect0);
- __raw_writel(old1 | gen, bank->base +
+ writel_relaxed(old1 | gen, bank->base +
bank->regs->leveldetect1);
}
if (bank->regs->irqstatus_raw0) {
- __raw_writel(old0 | l, bank->base +
+ writel_relaxed(old0 | l, bank->base +
bank->regs->leveldetect0);
- __raw_writel(old1 | l, bank->base +
+ writel_relaxed(old1 | l, bank->base +
bank->regs->leveldetect1);
}
- __raw_writel(old0, bank->base + bank->regs->leveldetect0);
- __raw_writel(old1, bank->base + bank->regs->leveldetect1);
+ writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
+ writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
}
bank->workaround_enabled = false;
@@ -1471,55 +1471,55 @@ static void omap_gpio_init_context(struct gpio_bank *p)
struct omap_gpio_reg_offs *regs = p->regs;
void __iomem *base = p->base;
- p->context.ctrl = __raw_readl(base + regs->ctrl);
- p->context.oe = __raw_readl(base + regs->direction);
- p->context.wake_en = __raw_readl(base + regs->wkup_en);
- p->context.leveldetect0 = __raw_readl(base + regs->leveldetect0);
- p->context.leveldetect1 = __raw_readl(base + regs->leveldetect1);
- p->context.risingdetect = __raw_readl(base + regs->risingdetect);
- p->context.fallingdetect = __raw_readl(base + regs->fallingdetect);
- p->context.irqenable1 = __raw_readl(base + regs->irqenable);
- p->context.irqenable2 = __raw_readl(base + regs->irqenable2);
+ p->context.ctrl = readl_relaxed(base + regs->ctrl);
+ p->context.oe = readl_relaxed(base + regs->direction);
+ p->context.wake_en = readl_relaxed(base + regs->wkup_en);
+ p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
+ p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
+ p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
+ p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
+ p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
+ p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
if (regs->set_dataout && p->regs->clr_dataout)
- p->context.dataout = __raw_readl(base + regs->set_dataout);
+ p->context.dataout = readl_relaxed(base + regs->set_dataout);
else
- p->context.dataout = __raw_readl(base + regs->dataout);
+ p->context.dataout = readl_relaxed(base + regs->dataout);
p->context_valid = true;
}
static void omap_gpio_restore_context(struct gpio_bank *bank)
{
- __raw_writel(bank->context.wake_en,
+ writel_relaxed(bank->context.wake_en,
bank->base + bank->regs->wkup_en);
- __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
- __raw_writel(bank->context.leveldetect0,
+ writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
+ writel_relaxed(bank->context.leveldetect0,
bank->base + bank->regs->leveldetect0);
- __raw_writel(bank->context.leveldetect1,
+ writel_relaxed(bank->context.leveldetect1,
bank->base + bank->regs->leveldetect1);
- __raw_writel(bank->context.risingdetect,
+ writel_relaxed(bank->context.risingdetect,
bank->base + bank->regs->risingdetect);
- __raw_writel(bank->context.fallingdetect,
+ writel_relaxed(bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect);
if (bank->regs->set_dataout && bank->regs->clr_dataout)
- __raw_writel(bank->context.dataout,
+ writel_relaxed(bank->context.dataout,
bank->base + bank->regs->set_dataout);
else
- __raw_writel(bank->context.dataout,
+ writel_relaxed(bank->context.dataout,
bank->base + bank->regs->dataout);
- __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
+ writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
if (bank->dbck_enable_mask) {
- __raw_writel(bank->context.debounce, bank->base +
+ writel_relaxed(bank->context.debounce, bank->base +
bank->regs->debounce);
- __raw_writel(bank->context.debounce_en,
+ writel_relaxed(bank->context.debounce_en,
bank->base + bank->regs->debounce_en);
}
- __raw_writel(bank->context.irqenable1,
+ writel_relaxed(bank->context.irqenable1,
bank->base + bank->regs->irqenable);
- __raw_writel(bank->context.irqenable2,
+ writel_relaxed(bank->context.irqenable2,
bank->base + bank->regs->irqenable2);
}
#endif /* CONFIG_PM_RUNTIME */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC 01/23] gpio/omap: raw read and write endian fix
2013-11-16 0:01 ` [RFC 01/23] gpio/omap: raw read and write endian fix Taras Kondratiuk
@ 2013-11-19 9:29 ` Linus Walleij
2013-11-19 15:43 ` Tony Lindgren
` (2 more replies)
2013-11-19 18:21 ` Santosh Shilimkar
1 sibling, 3 replies; 44+ messages in thread
From: Linus Walleij @ 2013-11-19 9:29 UTC (permalink / raw)
To: Taras Kondratiuk, ext Tony Lindgren, Javier Martinez Canillas
Cc: Linux-OMAP, linaro-networking, Victor Kamensky, Santosh Shilimkar,
Kevin Hilman, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
On Sat, Nov 16, 2013 at 1:01 AM, Taras Kondratiuk
<taras.kondratiuk@linaro.org> wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Since I generally just dislike __raw accessors I went and applied
this. If it collides with any of Tony's fixup work I might need to
take the patch out again, no big deal.
Some ACKs would be nice, but unless there are major objections
this stays merged.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [RFC 01/23] gpio/omap: raw read and write endian fix
2013-11-19 9:29 ` Linus Walleij
@ 2013-11-19 15:43 ` Tony Lindgren
2013-11-19 16:51 ` Javier Martinez Canillas
2013-11-19 18:12 ` Kevin Hilman
2 siblings, 0 replies; 44+ messages in thread
From: Tony Lindgren @ 2013-11-19 15:43 UTC (permalink / raw)
To: Linus Walleij
Cc: Taras Kondratiuk, Javier Martinez Canillas, Linux-OMAP,
linaro-networking, Victor Kamensky, Santosh Shilimkar,
Kevin Hilman, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
* Linus Walleij <linus.walleij@linaro.org> [131119 01:29]:
> On Sat, Nov 16, 2013 at 1:01 AM, Taras Kondratiuk
> <taras.kondratiuk@linaro.org> wrote:
>
> > From: Victor Kamensky <victor.kamensky@linaro.org>
> >
> > All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> > Need to use endian neutral functions to read/write h/w registers.
> > I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> > need to use read[lw]_relaxed and write[lw]_relaxed functions.
> > If the first simply reads/writes register, the second will byteswap
> > it if host operates in BE mode.
> >
> > Changes are trivial sed like replacement of __raw_xxx functions
> > with xxx_relaxed variant.
> >
> > Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> > Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
>
> Since I generally just dislike __raw accessors I went and applied
> this. If it collides with any of Tony's fixup work I might need to
> take the patch out again, no big deal.
Thanks, this should not conflict with what I have. I just had few
fixes for the twl4030-gpio for older omaps and I doubt that I have
further driver dependencies beyond that for my clean-up work.
> Some ACKs would be nice, but unless there are major objections
> this stays merged.
Acked-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC 01/23] gpio/omap: raw read and write endian fix
2013-11-19 9:29 ` Linus Walleij
2013-11-19 15:43 ` Tony Lindgren
@ 2013-11-19 16:51 ` Javier Martinez Canillas
2013-11-19 18:12 ` Kevin Hilman
2 siblings, 0 replies; 44+ messages in thread
From: Javier Martinez Canillas @ 2013-11-19 16:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Taras Kondratiuk, ext Tony Lindgren, Linux-OMAP,
linaro-networking, Victor Kamensky, Santosh Shilimkar,
Kevin Hilman, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
On 11/19/2013 10:29 AM, Linus Walleij wrote:
> On Sat, Nov 16, 2013 at 1:01 AM, Taras Kondratiuk
> <taras.kondratiuk@linaro.org> wrote:
>
>> From: Victor Kamensky <victor.kamensky@linaro.org>
>>
>> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
>> Need to use endian neutral functions to read/write h/w registers.
>> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
>> need to use read[lw]_relaxed and write[lw]_relaxed functions.
>> If the first simply reads/writes register, the second will byteswap
>> it if host operates in BE mode.
>>
>> Changes are trivial sed like replacement of __raw_xxx functions
>> with xxx_relaxed variant.
>>
>> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
>> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
>
> Since I generally just dislike __raw accessors I went and applied
> this. If it collides with any of Tony's fixup work I might need to
> take the patch out again, no big deal.
>
> Some ACKs would be nice, but unless there are major objections
> this stays merged.
Looks good to me and also I've tested this patch on a TI DM3730 (Cortex A-8)
board in LE mode and found no regressions on devices using a GPIO.
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>
> Yours,
> Linus Walleij
>
Thanks a lot and best regards,
Javier
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC 01/23] gpio/omap: raw read and write endian fix
2013-11-19 9:29 ` Linus Walleij
2013-11-19 15:43 ` Tony Lindgren
2013-11-19 16:51 ` Javier Martinez Canillas
@ 2013-11-19 18:12 ` Kevin Hilman
2 siblings, 0 replies; 44+ messages in thread
From: Kevin Hilman @ 2013-11-19 18:12 UTC (permalink / raw)
To: Linus Walleij
Cc: Taras Kondratiuk, ext Tony Lindgren, Javier Martinez Canillas,
Linux-OMAP, linaro-networking, Victor Kamensky, Santosh Shilimkar,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Linus Walleij <linus.walleij@linaro.org> writes:
> On Sat, Nov 16, 2013 at 1:01 AM, Taras Kondratiuk
> <taras.kondratiuk@linaro.org> wrote:
>
>> From: Victor Kamensky <victor.kamensky@linaro.org>
>>
>> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
>> Need to use endian neutral functions to read/write h/w registers.
>> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
>> need to use read[lw]_relaxed and write[lw]_relaxed functions.
>> If the first simply reads/writes register, the second will byteswap
>> it if host operates in BE mode.
>>
>> Changes are trivial sed like replacement of __raw_xxx functions
>> with xxx_relaxed variant.
>>
>> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
>> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
>
> Since I generally just dislike __raw accessors I went and applied
> this. If it collides with any of Tony's fixup work I might need to
> take the patch out again, no big deal.
>
> Some ACKs would be nice, but unless there are major objections
> this stays merged.
Acked-by: Kevin Hilman <khilman@linaro.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC 01/23] gpio/omap: raw read and write endian fix
2013-11-16 0:01 ` [RFC 01/23] gpio/omap: raw read and write endian fix Taras Kondratiuk
2013-11-19 9:29 ` Linus Walleij
@ 2013-11-19 18:21 ` Santosh Shilimkar
1 sibling, 0 replies; 44+ messages in thread
From: Santosh Shilimkar @ 2013-11-19 18:21 UTC (permalink / raw)
To: Taras Kondratiuk
Cc: linux-omap, linaro-networking, Victor Kamensky, Kevin Hilman,
Linus Walleij, linux-gpio, linux-kernel
On Friday 15 November 2013 07:01 PM, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC 02/23] watchdog: omap_wdt: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
2013-11-16 0:01 ` [RFC 01/23] gpio/omap: raw read and write endian fix Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 6:27 ` Guenter Roeck
2013-11-17 19:09 ` Wim Van Sebroeck
2013-11-16 0:01 ` [RFC 03/23] OMAPDSS: " Taras Kondratiuk
` (19 subsequent siblings)
21 siblings, 2 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Wim Van Sebroeck,
linux-watchdog, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/watchdog/omap_wdt.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index af88ffd..2ff7bff 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -68,14 +68,14 @@ static void omap_wdt_reload(struct omap_wdt_dev *wdev)
void __iomem *base = wdev->base;
/* wait for posted write to complete */
- while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
+ while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
cpu_relax();
wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
- __raw_writel(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
+ writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
/* wait for posted write to complete */
- while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
+ while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
cpu_relax();
/* reloaded WCRR from WLDR */
}
@@ -85,12 +85,12 @@ static void omap_wdt_enable(struct omap_wdt_dev *wdev)
void __iomem *base = wdev->base;
/* Sequence to enable the watchdog */
- __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
- while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
+ writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
+ while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
cpu_relax();
- __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
- while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
+ writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
+ while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
cpu_relax();
}
@@ -99,12 +99,12 @@ static void omap_wdt_disable(struct omap_wdt_dev *wdev)
void __iomem *base = wdev->base;
/* sequence required to disable watchdog */
- __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
- while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
+ writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
+ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
cpu_relax();
- __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
- while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
+ writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
+ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
cpu_relax();
}
@@ -115,11 +115,11 @@ static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
void __iomem *base = wdev->base;
/* just count up at 32 KHz */
- while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
+ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
cpu_relax();
- __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
- while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
+ writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
+ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
cpu_relax();
}
@@ -135,11 +135,11 @@ static int omap_wdt_start(struct watchdog_device *wdog)
pm_runtime_get_sync(wdev->dev);
/* initialize prescaler */
- while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
+ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
cpu_relax();
- __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
- while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
+ writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
+ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
cpu_relax();
omap_wdt_set_timer(wdev, wdog->timeout);
@@ -275,7 +275,7 @@ static int omap_wdt_probe(struct platform_device *pdev)
}
pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
- __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
+ readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
omap_wdt->timeout);
pm_runtime_put_sync(wdev->dev);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC 02/23] watchdog: omap_wdt: raw read and write endian fix
2013-11-16 0:01 ` [RFC 02/23] watchdog: omap_wdt: " Taras Kondratiuk
@ 2013-11-16 6:27 ` Guenter Roeck
2013-11-17 19:09 ` Wim Van Sebroeck
1 sibling, 0 replies; 44+ messages in thread
From: Guenter Roeck @ 2013-11-16 6:27 UTC (permalink / raw)
To: Taras Kondratiuk, linux-omap
Cc: linaro-networking, Victor Kamensky, Wim Van Sebroeck,
linux-watchdog, linux-kernel
On 11/15/2013 04:01 PM, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC 02/23] watchdog: omap_wdt: raw read and write endian fix
2013-11-16 0:01 ` [RFC 02/23] watchdog: omap_wdt: " Taras Kondratiuk
2013-11-16 6:27 ` Guenter Roeck
@ 2013-11-17 19:09 ` Wim Van Sebroeck
1 sibling, 0 replies; 44+ messages in thread
From: Wim Van Sebroeck @ 2013-11-17 19:09 UTC (permalink / raw)
To: Taras Kondratiuk
Cc: linux-omap, linaro-networking, Victor Kamensky, linux-watchdog,
linux-kernel
Hi Victor, Taras,
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
This was added to linux-watchdog-next.
Kind regards,
Wim.
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC 03/23] OMAPDSS: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
2013-11-16 0:01 ` [RFC 01/23] gpio/omap: raw read and write endian fix Taras Kondratiuk
2013-11-16 0:01 ` [RFC 02/23] watchdog: omap_wdt: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-18 13:13 ` Tomi Valkeinen
2013-11-16 0:01 ` [RFC 04/23] mmc: omap: " Taras Kondratiuk
` (18 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Tomi Valkeinen,
Jean-Christophe Plagniol-Villard, linux-fbdev, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/video/omap2/dss/dispc.c | 4 ++--
drivers/video/omap2/dss/dsi.c | 4 ++--
drivers/video/omap2/dss/dss.c | 4 ++--
drivers/video/omap2/dss/rfbi.c | 16 ++++++++--------
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 4 ++--
drivers/video/omap2/dss/venc.c | 4 ++--
drivers/video/omap2/omapfb/omapfb-main.c | 10 +++++-----
drivers/video/omap2/vrfb.c | 6 +++---
8 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 4779750..87a3682 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -228,12 +228,12 @@ static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
static inline void dispc_write_reg(const u16 idx, u32 val)
{
- __raw_writel(val, dispc.base + idx);
+ writel_relaxed(val, dispc.base + idx);
}
static inline u32 dispc_read_reg(const u16 idx)
{
- return __raw_readl(dispc.base + idx);
+ return readl_relaxed(dispc.base + idx);
}
static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index a598b58..c5af3fa 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -414,7 +414,7 @@ static inline void dsi_write_reg(struct platform_device *dsidev,
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
- __raw_writel(val, dsi->base + idx.idx);
+ writel_relaxed(val, dsi->base + idx.idx);
}
static inline u32 dsi_read_reg(struct platform_device *dsidev,
@@ -422,7 +422,7 @@ static inline u32 dsi_read_reg(struct platform_device *dsidev,
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
- return __raw_readl(dsi->base + idx.idx);
+ return readl_relaxed(dsi->base + idx.idx);
}
static void dsi_bus_lock(struct omap_dss_device *dssdev)
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index bd01608..e53f663 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -104,12 +104,12 @@ static const char * const dss_generic_clk_source_names[] = {
static inline void dss_write_reg(const struct dss_reg idx, u32 val)
{
- __raw_writel(val, dss.base + idx.idx);
+ writel_relaxed(val, dss.base + idx.idx);
}
static inline u32 dss_read_reg(const struct dss_reg idx)
{
- return __raw_readl(dss.base + idx.idx);
+ return readl_relaxed(dss.base + idx.idx);
}
#define SR(reg) \
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index c8a81a2..7772e33 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -122,12 +122,12 @@ static struct {
static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
{
- __raw_writel(val, rfbi.base + idx.idx);
+ writel_relaxed(val, rfbi.base + idx.idx);
}
static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
{
- return __raw_readl(rfbi.base + idx.idx);
+ return readl_relaxed(rfbi.base + idx.idx);
}
static int rfbi_runtime_get(void)
@@ -263,8 +263,8 @@ static void rfbi_write_pixels(const void __iomem *buf, int scr_width,
for (; h; --h) {
for (i = 0; i < w; ++i) {
const u8 __iomem *b = (const u8 __iomem *)pd;
- rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
- rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
+ rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+1));
+ rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+0));
++pd;
}
pd += horiz_offset;
@@ -277,9 +277,9 @@ static void rfbi_write_pixels(const void __iomem *buf, int scr_width,
for (; h; --h) {
for (i = 0; i < w; ++i) {
const u8 __iomem *b = (const u8 __iomem *)pd;
- rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
- rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
- rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
+ rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+2));
+ rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+1));
+ rfbi_write_reg(RFBI_PARAM, readb_relaxed(b+0));
++pd;
}
pd += horiz_offset;
@@ -291,7 +291,7 @@ static void rfbi_write_pixels(const void __iomem *buf, int scr_width,
for (; h; --h) {
for (i = 0; i < w; ++i) {
- rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
+ rfbi_write_reg(RFBI_PARAM, readw_relaxed(pd));
++pd;
}
pd += horiz_offset;
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index 3dfe009..59936fa 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -43,13 +43,13 @@
static inline void hdmi_write_reg(void __iomem *base_addr,
const u16 idx, u32 val)
{
- __raw_writel(val, base_addr + idx);
+ writel_relaxed(val, base_addr + idx);
}
static inline u32 hdmi_read_reg(void __iomem *base_addr,
const u16 idx)
{
- return __raw_readl(base_addr + idx);
+ return readl_relaxed(base_addr + idx);
}
static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index 5f88ac4..74e6973 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -309,12 +309,12 @@ static struct {
static inline void venc_write_reg(int idx, u32 val)
{
- __raw_writel(val, venc.base + idx);
+ writel_relaxed(val, venc.base + idx);
}
static inline u32 venc_read_reg(int idx)
{
- u32 l = __raw_readl(venc.base + idx);
+ u32 l = readl_relaxed(venc.base + idx);
return l;
}
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index 27d6905..f7a347c 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -82,18 +82,18 @@ static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color)
g = g * 64 / 256;
b = b * 32 / 256;
- __raw_writew((r << 11) | (g << 5) | (b << 0), p);
+ writew_relaxed((r << 11) | (g << 5) | (b << 0), p);
} else if (var->bits_per_pixel == 24) {
u8 __iomem *p = (u8 __iomem *)addr;
p += (y * line_len + x) * 3;
- __raw_writeb(b, p + 0);
- __raw_writeb(g, p + 1);
- __raw_writeb(r, p + 2);
+ writeb_relaxed(b, p + 0);
+ writeb_relaxed(g, p + 1);
+ writeb_relaxed(r, p + 2);
} else if (var->bits_per_pixel == 32) {
u32 __iomem *p = (u32 __iomem *)addr;
p += y * line_len + x;
- __raw_writel(color, p);
+ writel_relaxed(color, p);
}
}
diff --git a/drivers/video/omap2/vrfb.c b/drivers/video/omap2/vrfb.c
index f346b02..0324690 100644
--- a/drivers/video/omap2/vrfb.c
+++ b/drivers/video/omap2/vrfb.c
@@ -82,17 +82,17 @@ static bool vrfb_loaded;
static void omap2_sms_write_rot_control(u32 val, unsigned ctx)
{
- __raw_writel(val, vrfb_base + SMS_ROT_CONTROL(ctx));
+ writel_relaxed(val, vrfb_base + SMS_ROT_CONTROL(ctx));
}
static void omap2_sms_write_rot_size(u32 val, unsigned ctx)
{
- __raw_writel(val, vrfb_base + SMS_ROT_SIZE(ctx));
+ writel_relaxed(val, vrfb_base + SMS_ROT_SIZE(ctx));
}
static void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
{
- __raw_writel(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx));
+ writel_relaxed(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx));
}
static inline void restore_hw_context(int ctx)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC 03/23] OMAPDSS: raw read and write endian fix
2013-11-16 0:01 ` [RFC 03/23] OMAPDSS: " Taras Kondratiuk
@ 2013-11-18 13:13 ` Tomi Valkeinen
0 siblings, 0 replies; 44+ messages in thread
From: Tomi Valkeinen @ 2013-11-18 13:13 UTC (permalink / raw)
To: Taras Kondratiuk, linux-omap
Cc: linaro-networking, Victor Kamensky,
Jean-Christophe Plagniol-Villard, linux-fbdev, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 709 bytes --]
On 2013-11-16 02:01, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
Looks fine to me. Quick test with o4 panda works fine.
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tomi
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 901 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC 04/23] mmc: omap: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (2 preceding siblings ...)
2013-11-16 0:01 ` [RFC 03/23] OMAPDSS: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 06/23] drivers: bus: omap_l3: " Taras Kondratiuk
` (17 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Jarkko Lavinen, Chris Ball,
Balaji T K, linux-mmc, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/mmc/host/omap.c | 4 ++--
drivers/mmc/host/omap_hsmmc.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index b94f38e..ef2d088 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -79,8 +79,8 @@
#define mmc_omap2() (!mmc_omap1())
#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
-#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
-#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
+#define OMAP_MMC_READ(host, reg) readw_relaxed((host)->virt_base + OMAP_MMC_REG(host, reg))
+#define OMAP_MMC_WRITE(host, reg, val) writew_relaxed((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
/*
* Command types
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 6ac63df..fbbbfc0 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -135,10 +135,10 @@
* MMC Host controller read/write API's
*/
#define OMAP_HSMMC_READ(base, reg) \
- __raw_readl((base) + OMAP_HSMMC_##reg)
+ readl_relaxed((base) + OMAP_HSMMC_##reg)
#define OMAP_HSMMC_WRITE(base, reg, val) \
- __raw_writel((val), (base) + OMAP_HSMMC_##reg)
+ writel_relaxed((val), (base) + OMAP_HSMMC_##reg)
struct omap_hsmmc_next {
unsigned int dma_len;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 06/23] drivers: bus: omap_l3: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (3 preceding siblings ...)
2013-11-16 0:01 ` [RFC 04/23] mmc: omap: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 07/23] hwrng: omap - " Taras Kondratiuk
` (16 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap; +Cc: linaro-networking, Victor Kamensky, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/bus/omap_l3_noc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index feeecae..82de7a5 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -72,7 +72,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
* to determine the source
*/
base = l3->l3_base[i];
- err_reg = __raw_readl(base + l3_flagmux[i] +
+ err_reg = readl_relaxed(base + l3_flagmux[i] +
+ L3_FLAGMUX_REGERR0 + (inttype << 3));
/* Get the corresponding error and analyse */
@@ -82,9 +82,9 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
/* Read the stderrlog_main_source from clk domain */
l3_targ_base = base + *(l3_targ[i] + err_src);
- std_err_main = __raw_readl(l3_targ_base +
+ std_err_main = readl_relaxed(l3_targ_base +
L3_TARG_STDERRLOG_MAIN);
- masterid = __raw_readl(l3_targ_base +
+ masterid = readl_relaxed(l3_targ_base +
L3_TARG_STDERRLOG_MSTADDR);
switch (std_err_main & CUSTOM_ERROR) {
@@ -93,7 +93,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
l3_targ_inst_name[i][err_src];
WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
target_name,
- __raw_readl(l3_targ_base +
+ readl_relaxed(l3_targ_base +
L3_TARG_STDERRLOG_SLVOFSLSB));
/* clear the std error log*/
clear = std_err_main | CLEAR_STDERR_LOG;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 07/23] hwrng: omap - raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (4 preceding siblings ...)
2013-11-16 0:01 ` [RFC 06/23] drivers: bus: omap_l3: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 08/23] crypto: omap-aes " Taras Kondratiuk
` (15 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Deepak Saxena, Matt Mackall,
Herbert Xu, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/char/hw_random/omap-rng.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index 9b89ff4..d68cf8a 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -131,13 +131,13 @@ struct omap_rng_dev {
static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
{
- return __raw_readl(priv->base + priv->pdata->regs[reg]);
+ return readl_relaxed(priv->base + priv->pdata->regs[reg]);
}
static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
u32 val)
{
- __raw_writel(val, priv->base + priv->pdata->regs[reg]);
+ writel_relaxed(val, priv->base + priv->pdata->regs[reg]);
}
static int omap_rng_data_present(struct hwrng *rng, int wait)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 08/23] crypto: omap-aes - raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (5 preceding siblings ...)
2013-11-16 0:01 ` [RFC 07/23] hwrng: omap - " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 09/23] crypto: omap-sham " Taras Kondratiuk
` (14 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Herbert Xu, David S. Miller,
linux-crypto, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/crypto/omap-aes.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c
index ce791c2..777ae0a 100644
--- a/drivers/crypto/omap-aes.c
+++ b/drivers/crypto/omap-aes.c
@@ -195,7 +195,7 @@ static DEFINE_SPINLOCK(list_lock);
#define omap_aes_read(dd, offset) \
({ \
int _read_ret; \
- _read_ret = __raw_readl(dd->io_base + offset); \
+ _read_ret = readl_relaxed(dd->io_base + offset); \
pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
offset, _read_ret); \
_read_ret; \
@@ -203,7 +203,7 @@ static DEFINE_SPINLOCK(list_lock);
#else
static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
{
- return __raw_readl(dd->io_base + offset);
+ return readl_relaxed(dd->io_base + offset);
}
#endif
@@ -212,13 +212,13 @@ static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
do { \
pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
offset, value); \
- __raw_writel(value, dd->io_base + offset); \
+ writel_relaxed(value, dd->io_base + offset); \
} while (0)
#else
static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
u32 value)
{
- __raw_writel(value, dd->io_base + offset);
+ writel_relaxed(value, dd->io_base + offset);
}
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 09/23] crypto: omap-sham - raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (6 preceding siblings ...)
2013-11-16 0:01 ` [RFC 08/23] crypto: omap-aes " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 10/23] Input: omap-keypad " Taras Kondratiuk
` (13 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Herbert Xu, David S. Miller,
linux-crypto, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/crypto/omap-sham.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index 8bdde57..b011b97 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -244,13 +244,13 @@ static struct omap_sham_drv sham = {
static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
{
- return __raw_readl(dd->io_base + offset);
+ return readl_relaxed(dd->io_base + offset);
}
static inline void omap_sham_write(struct omap_sham_dev *dd,
u32 offset, u32 value)
{
- __raw_writel(value, dd->io_base + offset);
+ writel_relaxed(value, dd->io_base + offset);
}
static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 10/23] Input: omap-keypad - raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (7 preceding siblings ...)
2013-11-16 0:01 ` [RFC 09/23] crypto: omap-sham " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 11/23] mfd: omap-usb-host: " Taras Kondratiuk
` (12 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Dmitry Torokhov, linux-input,
linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/input/keyboard/omap4-keypad.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c
index 30acfd4..952a2eb 100644
--- a/drivers/input/keyboard/omap4-keypad.c
+++ b/drivers/input/keyboard/omap4-keypad.c
@@ -89,26 +89,26 @@ struct omap4_keypad {
static int kbd_readl(struct omap4_keypad *keypad_data, u32 offset)
{
- return __raw_readl(keypad_data->base +
+ return readl_relaxed(keypad_data->base +
keypad_data->reg_offset + offset);
}
static void kbd_writel(struct omap4_keypad *keypad_data, u32 offset, u32 value)
{
- __raw_writel(value,
+ writel_relaxed(value,
keypad_data->base + keypad_data->reg_offset + offset);
}
static int kbd_read_irqreg(struct omap4_keypad *keypad_data, u32 offset)
{
- return __raw_readl(keypad_data->base +
+ return readl_relaxed(keypad_data->base +
keypad_data->irqreg_offset + offset);
}
static void kbd_write_irqreg(struct omap4_keypad *keypad_data,
u32 offset, u32 value)
{
- __raw_writel(value,
+ writel_relaxed(value,
keypad_data->base + keypad_data->irqreg_offset + offset);
}
@@ -312,7 +312,7 @@ static int omap4_keypad_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
goto err_unmap;
}
- rev = __raw_readl(keypad_data->base + OMAP4_KBD_REVISION);
+ rev = readl_relaxed(keypad_data->base + OMAP4_KBD_REVISION);
rev &= 0x03 << 30;
rev >>= 30;
switch (rev) {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 11/23] mfd: omap-usb-host: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (8 preceding siblings ...)
2013-11-16 0:01 ` [RFC 10/23] Input: omap-keypad " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-18 10:35 ` Lee Jones
2013-11-16 0:01 ` [RFC 12/23] mfd: omap-usb-tll: " Taras Kondratiuk
` (11 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Samuel Ortiz, Lee Jones,
linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/mfd/omap-usb-host.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index 29ee54d..3b34de1 100644
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -121,22 +121,22 @@ static u64 usbhs_dmamask = DMA_BIT_MASK(32);
static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
{
- __raw_writel(val, base + reg);
+ writel_relaxed(val, base + reg);
}
static inline u32 usbhs_read(void __iomem *base, u32 reg)
{
- return __raw_readl(base + reg);
+ return readl_relaxed(base + reg);
}
static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
{
- __raw_writeb(val, base + reg);
+ writeb_relaxed(val, base + reg);
}
static inline u8 usbhs_readb(void __iomem *base, u8 reg)
{
- return __raw_readb(base + reg);
+ return readb_relaxed(base + reg);
}
/*-------------------------------------------------------------------------*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC 11/23] mfd: omap-usb-host: raw read and write endian fix
2013-11-16 0:01 ` [RFC 11/23] mfd: omap-usb-host: " Taras Kondratiuk
@ 2013-11-18 10:35 ` Lee Jones
0 siblings, 0 replies; 44+ messages in thread
From: Lee Jones @ 2013-11-18 10:35 UTC (permalink / raw)
To: Taras Kondratiuk
Cc: linux-omap, linaro-networking, Victor Kamensky, Samuel Ortiz,
linux-kernel
On Sat, 16 Nov 2013, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
> ---
> drivers/mfd/omap-usb-host.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Applied, thanks.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC 12/23] mfd: omap-usb-tll: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (9 preceding siblings ...)
2013-11-16 0:01 ` [RFC 11/23] mfd: omap-usb-host: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-18 10:35 ` Lee Jones
2013-11-16 0:01 ` [RFC 13/23] spi: omap2-mcspi: " Taras Kondratiuk
` (10 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Samuel Ortiz, Lee Jones,
linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/mfd/omap-usb-tll.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mfd/omap-usb-tll.c b/drivers/mfd/omap-usb-tll.c
index e59ac4c..15bcd93 100644
--- a/drivers/mfd/omap-usb-tll.c
+++ b/drivers/mfd/omap-usb-tll.c
@@ -121,22 +121,22 @@ static DEFINE_SPINLOCK(tll_lock); /* serialize access to tll_dev */
static inline void usbtll_write(void __iomem *base, u32 reg, u32 val)
{
- __raw_writel(val, base + reg);
+ writel_relaxed(val, base + reg);
}
static inline u32 usbtll_read(void __iomem *base, u32 reg)
{
- return __raw_readl(base + reg);
+ return readl_relaxed(base + reg);
}
static inline void usbtll_writeb(void __iomem *base, u8 reg, u8 val)
{
- __raw_writeb(val, base + reg);
+ writeb_relaxed(val, base + reg);
}
static inline u8 usbtll_readb(void __iomem *base, u8 reg)
{
- return __raw_readb(base + reg);
+ return readb_relaxed(base + reg);
}
/*-------------------------------------------------------------------------*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC 12/23] mfd: omap-usb-tll: raw read and write endian fix
2013-11-16 0:01 ` [RFC 12/23] mfd: omap-usb-tll: " Taras Kondratiuk
@ 2013-11-18 10:35 ` Lee Jones
0 siblings, 0 replies; 44+ messages in thread
From: Lee Jones @ 2013-11-18 10:35 UTC (permalink / raw)
To: Taras Kondratiuk
Cc: linux-omap, linaro-networking, Victor Kamensky, Samuel Ortiz,
linux-kernel
On Sat, 16 Nov 2013, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
> ---
> drivers/mfd/omap-usb-tll.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Applied, thanks.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC 13/23] spi: omap2-mcspi: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (10 preceding siblings ...)
2013-11-16 0:01 ` [RFC 12/23] mfd: omap-usb-tll: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
[not found] ` <1384560086-11994-14-git-send-email-taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2013-11-16 0:01 ` [RFC 14/23] USB: ehci-omap: " Taras Kondratiuk
` (9 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Mark Brown, linux-spi,
linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/spi/spi-omap2-mcspi.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index ed4af47..c9471b7 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -157,14 +157,14 @@ static inline void mcspi_write_reg(struct spi_master *master,
{
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
- __raw_writel(val, mcspi->base + idx);
+ writel_relaxed(val, mcspi->base + idx);
}
static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
{
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
- return __raw_readl(mcspi->base + idx);
+ return readl_relaxed(mcspi->base + idx);
}
static inline void mcspi_write_cs_reg(const struct spi_device *spi,
@@ -172,14 +172,14 @@ static inline void mcspi_write_cs_reg(const struct spi_device *spi,
{
struct omap2_mcspi_cs *cs = spi->controller_state;
- __raw_writel(val, cs->base + idx);
+ writel_relaxed(val, cs->base + idx);
}
static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
{
struct omap2_mcspi_cs *cs = spi->controller_state;
- return __raw_readl(cs->base + idx);
+ return readl_relaxed(cs->base + idx);
}
static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
@@ -332,7 +332,7 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
list_for_each_entry(cs, &ctx->cs, node)
- __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
+ writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
}
static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
@@ -340,9 +340,9 @@ static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
unsigned long timeout;
timeout = jiffies + msecs_to_jiffies(1000);
- while (!(__raw_readl(reg) & bit)) {
+ while (!(readl_relaxed(reg) & bit)) {
if (time_after(jiffies, timeout)) {
- if (!(__raw_readl(reg) & bit))
+ if (!(readl_relaxed(reg) & bit))
return -ETIMEDOUT;
else
return 0;
@@ -669,7 +669,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
}
dev_vdbg(&spi->dev, "write-%d %02x\n",
word_len, *tx);
- __raw_writel(*tx++, tx_reg);
+ writel_relaxed(*tx++, tx_reg);
}
if (rx != NULL) {
if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -681,7 +681,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
if (c == 1 && tx == NULL &&
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
omap2_mcspi_set_enable(spi, 0);
- *rx++ = __raw_readl(rx_reg);
+ *rx++ = readl_relaxed(rx_reg);
dev_vdbg(&spi->dev, "read-%d %02x\n",
word_len, *(rx - 1));
if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -695,7 +695,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
omap2_mcspi_set_enable(spi, 0);
}
- *rx++ = __raw_readl(rx_reg);
+ *rx++ = readl_relaxed(rx_reg);
dev_vdbg(&spi->dev, "read-%d %02x\n",
word_len, *(rx - 1));
}
@@ -716,7 +716,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
}
dev_vdbg(&spi->dev, "write-%d %04x\n",
word_len, *tx);
- __raw_writel(*tx++, tx_reg);
+ writel_relaxed(*tx++, tx_reg);
}
if (rx != NULL) {
if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -728,7 +728,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
if (c == 2 && tx == NULL &&
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
omap2_mcspi_set_enable(spi, 0);
- *rx++ = __raw_readl(rx_reg);
+ *rx++ = readl_relaxed(rx_reg);
dev_vdbg(&spi->dev, "read-%d %04x\n",
word_len, *(rx - 1));
if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -742,7 +742,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
omap2_mcspi_set_enable(spi, 0);
}
- *rx++ = __raw_readl(rx_reg);
+ *rx++ = readl_relaxed(rx_reg);
dev_vdbg(&spi->dev, "read-%d %04x\n",
word_len, *(rx - 1));
}
@@ -763,7 +763,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
}
dev_vdbg(&spi->dev, "write-%d %08x\n",
word_len, *tx);
- __raw_writel(*tx++, tx_reg);
+ writel_relaxed(*tx++, tx_reg);
}
if (rx != NULL) {
if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -775,7 +775,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
if (c == 4 && tx == NULL &&
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
omap2_mcspi_set_enable(spi, 0);
- *rx++ = __raw_readl(rx_reg);
+ *rx++ = readl_relaxed(rx_reg);
dev_vdbg(&spi->dev, "read-%d %08x\n",
word_len, *(rx - 1));
if (mcspi_wait_for_reg_bit(chstat_reg,
@@ -789,7 +789,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
omap2_mcspi_set_enable(spi, 0);
}
- *rx++ = __raw_readl(rx_reg);
+ *rx++ = readl_relaxed(rx_reg);
dev_vdbg(&spi->dev, "read-%d %08x\n",
word_len, *(rx - 1));
}
@@ -1101,7 +1101,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
/* RX_ONLY mode needs dummy data in TX reg */
if (t->tx_buf == NULL)
- __raw_writel(0, cs->base
+ writel_relaxed(0, cs->base
+ OMAP2_MCSPI_TX0);
if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
@@ -1465,9 +1465,9 @@ static int omap2_mcspi_resume(struct device *dev)
* change in account.
*/
cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
- __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
+ writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
- __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
+ writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
}
}
pm_runtime_mark_last_busy(mcspi->dev);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 14/23] USB: ehci-omap: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (11 preceding siblings ...)
2013-11-16 0:01 ` [RFC 13/23] spi: omap2-mcspi: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
[not found] ` <1384560086-11994-15-git-send-email-taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
[not found] ` <1384560086-11994-1-git-send-email-taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
` (8 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Felipe Balbi, Alan Stern,
Greg Kroah-Hartman, linux-usb, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
drivers/usb/host/ehci-omap.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index 6fa82d6..803e706 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -73,12 +73,12 @@ struct omap_hcd {
static inline void ehci_write(void __iomem *base, u32 reg, u32 val)
{
- __raw_writel(val, base + reg);
+ writel_relaxed(val, base + reg);
}
static inline u32 ehci_read(void __iomem *base, u32 reg)
{
- return __raw_readl(base + reg);
+ return readl_relaxed(base + reg);
}
/* configure so an HC device and id are always provided */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread[parent not found: <1384560086-11994-1-git-send-email-taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>]
* [RFC 05/23] i2c: omap: raw read and write endian fix
[not found] ` <1384560086-11994-1-git-send-email-taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2013-11-16 0:01 ` Taras Kondratiuk
[not found] ` <1384560086-11994-6-git-send-email-taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2013-11-16 0:01 ` [RFC 15/23] usb: musb: " Taras Kondratiuk
1 sibling, 1 reply; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linaro-networking-QSEj5FYQhm4dnm+yROfE0A, Victor Kamensky,
Tony Lindgren, Wolfram Sang, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
From: Victor Kamensky <victor.kamensky-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
drivers/i2c/busses/i2c-omap.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 9967a6f..d69826e 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -266,13 +266,13 @@ static const u8 reg_map_ip_v2[] = {
static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
int reg, u16 val)
{
- __raw_writew(val, i2c_dev->base +
+ writew_relaxed(val, i2c_dev->base +
(i2c_dev->regs[reg] << i2c_dev->reg_shift));
}
static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
{
- return __raw_readw(i2c_dev->base +
+ return readw_relaxed(i2c_dev->base +
(i2c_dev->regs[reg] << i2c_dev->reg_shift));
}
@@ -1142,7 +1142,7 @@ omap_i2c_probe(struct platform_device *pdev)
* Also since the omap_i2c_read_reg uses reg_map_ip_* a
* raw_readw is done.
*/
- rev = __raw_readw(dev->base + 0x04);
+ rev = readw_relaxed(dev->base + 0x04);
dev->scheme = OMAP_I2C_SCHEME(rev);
switch (dev->scheme) {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 15/23] usb: musb: raw read and write endian fix
[not found] ` <1384560086-11994-1-git-send-email-taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2013-11-16 0:01 ` [RFC 05/23] i2c: omap: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-25 22:07 ` Felipe Balbi
1 sibling, 1 reply; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap-u79uwXL29TY76Z2rM5mHXA
Cc: linaro-networking-QSEj5FYQhm4dnm+yROfE0A, Victor Kamensky,
Felipe Balbi, Greg Kroah-Hartman,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
From: Victor Kamensky <victor.kamensky-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
drivers/usb/musb/musb_io.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
index eebeed7..76f4d2a 100644
--- a/drivers/usb/musb/musb_io.h
+++ b/drivers/usb/musb/musb_io.h
@@ -42,17 +42,17 @@
/* NOTE: these offsets are all in bytes */
static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
- { return __raw_readw(addr + offset); }
+ { return readw_relaxed(addr + offset); }
static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
- { return __raw_readl(addr + offset); }
+ { return readl_relaxed(addr + offset); }
static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
- { __raw_writew(data, addr + offset); }
+ { writew_relaxed(data, addr + offset); }
static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
- { __raw_writel(data, addr + offset); }
+ { writel_relaxed(data, addr + offset); }
#if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
@@ -65,7 +65,7 @@ static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
u16 tmp;
u8 val;
- tmp = __raw_readw(addr + (offset & ~1));
+ tmp = readw_relaxed(addr + (offset & ~1));
if (offset & 1)
val = (tmp >> 8);
else
@@ -78,22 +78,22 @@ static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
{
u16 tmp;
- tmp = __raw_readw(addr + (offset & ~1));
+ tmp = readw_relaxed(addr + (offset & ~1));
if (offset & 1)
tmp = (data << 8) | (tmp & 0xff);
else
tmp = (tmp & 0xff00) | data;
- __raw_writew(tmp, addr + (offset & ~1));
+ writew_relaxed(tmp, addr + (offset & ~1));
}
#else
static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
- { return __raw_readb(addr + offset); }
+ { return readb_relaxed(addr + offset); }
static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- { __raw_writeb(data, addr + offset); }
+ { writeb_relaxed(data, addr + offset); }
#endif /* CONFIG_USB_MUSB_TUSB6010 */
--
1.7.9.5
--
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^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC 15/23] usb: musb: raw read and write endian fix
2013-11-16 0:01 ` [RFC 15/23] usb: musb: " Taras Kondratiuk
@ 2013-11-25 22:07 ` Felipe Balbi
2013-11-25 22:13 ` Felipe Balbi
0 siblings, 1 reply; 44+ messages in thread
From: Felipe Balbi @ 2013-11-25 22:07 UTC (permalink / raw)
To: Taras Kondratiuk
Cc: linux-omap, linaro-networking, Victor Kamensky, Felipe Balbi,
Greg Kroah-Hartman, linux-usb, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1384 bytes --]
On Sat, Nov 16, 2013 at 02:01:18AM +0200, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
> ---
> drivers/usb/musb/musb_io.h | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
> index eebeed7..76f4d2a 100644
> --- a/drivers/usb/musb/musb_io.h
> +++ b/drivers/usb/musb/musb_io.h
> @@ -42,17 +42,17 @@
> /* NOTE: these offsets are all in bytes */
>
> static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
> - { return __raw_readw(addr + offset); }
> + { return readw_relaxed(addr + offset); }
x86 doesn't provide any of the write?_relaxed methods so this breaks
build on x86 at least.
--
balbi
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^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [RFC 15/23] usb: musb: raw read and write endian fix
2013-11-25 22:07 ` Felipe Balbi
@ 2013-11-25 22:13 ` Felipe Balbi
0 siblings, 0 replies; 44+ messages in thread
From: Felipe Balbi @ 2013-11-25 22:13 UTC (permalink / raw)
To: Felipe Balbi
Cc: Taras Kondratiuk, linux-omap, linaro-networking, Victor Kamensky,
Greg Kroah-Hartman, linux-usb, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2590 bytes --]
Hi,
On Mon, Nov 25, 2013 at 04:07:49PM -0600, Felipe Balbi wrote:
> On Sat, Nov 16, 2013 at 02:01:18AM +0200, Taras Kondratiuk wrote:
> > From: Victor Kamensky <victor.kamensky@linaro.org>
> >
> > All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> > Need to use endian neutral functions to read/write h/w registers.
> > I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> > need to use read[lw]_relaxed and write[lw]_relaxed functions.
> > If the first simply reads/writes register, the second will byteswap
> > it if host operates in BE mode.
> >
> > Changes are trivial sed like replacement of __raw_xxx functions
> > with xxx_relaxed variant.
> >
> > Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> > Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
> > ---
> > drivers/usb/musb/musb_io.h | 18 +++++++++---------
> > 1 file changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
> > index eebeed7..76f4d2a 100644
> > --- a/drivers/usb/musb/musb_io.h
> > +++ b/drivers/usb/musb/musb_io.h
> > @@ -42,17 +42,17 @@
> > /* NOTE: these offsets are all in bytes */
> >
> > static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
> > - { return __raw_readw(addr + offset); }
> > + { return readw_relaxed(addr + offset); }
>
> x86 doesn't provide any of the write?_relaxed methods so this breaks
> build on x86 at least.
here's an untested patch which would "solve" the problem:
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 34f69cb..b6ad164 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -73,6 +73,9 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
#define __raw_readw __readw
#define __raw_readl __readl
+#define writeb_relaxed(d, a) __writeb(d, a)
+#define writew_relaxed(d, a) __writew(d, a)
+#define writel_relaxed(d, a) __writel(d, a)
#define __raw_writeb __writeb
#define __raw_writew __writew
#define __raw_writel __writel
@@ -85,6 +88,7 @@ build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
#define readq_relaxed(a) readq(a)
+#define writeq_relaxed(d, a) writeq(d, a)
#define __raw_readq(a) readq(a)
#define __raw_writeq(val, addr) writeq(val, addr)
I'm not sure if it's correct though. Someone would have to tell me if
it's correct or not. For now, I have dropped $subject from my
testing/next branch.
--
balbi
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^ permalink raw reply related [flat|nested] 44+ messages in thread
* [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (13 preceding siblings ...)
[not found] ` <1384560086-11994-1-git-send-email-taras.kondratiuk-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 16:09 ` Jarkko Nikula
` (2 more replies)
2013-11-16 0:01 ` [RFC 17/23] ARM: OMAP2+: " Taras Kondratiuk
` (6 subsequent siblings)
21 siblings, 3 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Peter Ujfalusi, Jarkko Nikula,
Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai,
alsa-devel, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
sound/soc/omap/mcbsp.c | 12 ++++++------
sound/soc/omap/omap-dmic.c | 4 ++--
sound/soc/omap/omap-mcpdm.c | 4 ++--
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index 83433fd..86c7538 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -36,10 +36,10 @@ static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
if (mcbsp->pdata->reg_size == 2) {
((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
- __raw_writew((u16)val, addr);
+ writew_relaxed((u16)val, addr);
} else {
((u32 *)mcbsp->reg_cache)[reg] = val;
- __raw_writel(val, addr);
+ writel_relaxed(val, addr);
}
}
@@ -48,22 +48,22 @@ static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
if (mcbsp->pdata->reg_size == 2) {
- return !from_cache ? __raw_readw(addr) :
+ return !from_cache ? readw_relaxed(addr) :
((u16 *)mcbsp->reg_cache)[reg];
} else {
- return !from_cache ? __raw_readl(addr) :
+ return !from_cache ? readl_relaxed(addr) :
((u32 *)mcbsp->reg_cache)[reg];
}
}
static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
{
- __raw_writel(val, mcbsp->st_data->io_base_st + reg);
+ writel_relaxed(val, mcbsp->st_data->io_base_st + reg);
}
static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
{
- return __raw_readl(mcbsp->st_data->io_base_st + reg);
+ return readl_relaxed(mcbsp->st_data->io_base_st + reg);
}
#define MCBSP_READ(mcbsp, reg) \
diff --git a/sound/soc/omap/omap-dmic.c b/sound/soc/omap/omap-dmic.c
index 12e566b..1bd531d 100644
--- a/sound/soc/omap/omap-dmic.c
+++ b/sound/soc/omap/omap-dmic.c
@@ -61,12 +61,12 @@ struct omap_dmic {
static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
{
- __raw_writel(val, dmic->io_base + reg);
+ writel_relaxed(val, dmic->io_base + reg);
}
static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
{
- return __raw_readl(dmic->io_base + reg);
+ return readl_relaxed(dmic->io_base + reg);
}
static inline void omap_dmic_start(struct omap_dmic *dmic)
diff --git a/sound/soc/omap/omap-mcpdm.c b/sound/soc/omap/omap-mcpdm.c
index 90d2a7c..653ba1c 100644
--- a/sound/soc/omap/omap-mcpdm.c
+++ b/sound/soc/omap/omap-mcpdm.c
@@ -74,12 +74,12 @@ struct omap_mcpdm {
static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
- __raw_writel(val, mcpdm->io_base + reg);
+ writel_relaxed(val, mcpdm->io_base + reg);
}
static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
- return __raw_readl(mcpdm->io_base + reg);
+ return readl_relaxed(mcpdm->io_base + reg);
}
#ifdef DEBUG
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: raw read and write endian fix
2013-11-16 0:01 ` [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: " Taras Kondratiuk
@ 2013-11-16 16:09 ` Jarkko Nikula
2013-11-16 17:23 ` Takashi Iwai
2013-11-18 10:30 ` Peter Ujfalusi
2013-11-18 11:15 ` Mark Brown
2 siblings, 1 reply; 44+ messages in thread
From: Jarkko Nikula @ 2013-11-16 16:09 UTC (permalink / raw)
To: Taras Kondratiuk
Cc: alsa-devel, Victor Kamensky, Takashi Iwai, linux-kernel,
Liam Girdwood, Peter Ujfalusi, Mark Brown, linaro-networking,
linux-omap
On 11/16/2013 02:01 AM, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
> ---
> sound/soc/omap/mcbsp.c | 12 ++++++------
> sound/soc/omap/omap-dmic.c | 4 ++--
> sound/soc/omap/omap-mcpdm.c | 4 ++--
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
Looks ok to me by looking at the _relaxed definitions in
arch/arm/include/asm/io.h.
Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: raw read and write endian fix
2013-11-16 16:09 ` Jarkko Nikula
@ 2013-11-16 17:23 ` Takashi Iwai
0 siblings, 0 replies; 44+ messages in thread
From: Takashi Iwai @ 2013-11-16 17:23 UTC (permalink / raw)
To: Jarkko Nikula
Cc: alsa-devel, Victor Kamensky, Taras Kondratiuk, Liam Girdwood,
Peter Ujfalusi, Mark Brown, linaro-networking, linux-omap,
linux-kernel
At Sat, 16 Nov 2013 18:09:51 +0200,
Jarkko Nikula wrote:
>
> On 11/16/2013 02:01 AM, Taras Kondratiuk wrote:
> > From: Victor Kamensky <victor.kamensky@linaro.org>
> >
> > All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> > Need to use endian neutral functions to read/write h/w registers.
> > I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> > need to use read[lw]_relaxed and write[lw]_relaxed functions.
> > If the first simply reads/writes register, the second will byteswap
> > it if host operates in BE mode.
> >
> > Changes are trivial sed like replacement of __raw_xxx functions
> > with xxx_relaxed variant.
> >
> > Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> > Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
> > ---
> > sound/soc/omap/mcbsp.c | 12 ++++++------
> > sound/soc/omap/omap-dmic.c | 4 ++--
> > sound/soc/omap/omap-mcpdm.c | 4 ++--
> > 3 files changed, 10 insertions(+), 10 deletions(-)
> >
> Looks ok to me by looking at the _relaxed definitions in
> arch/arm/include/asm/io.h.
>
> Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
>
What's the reason to use _relaxed version in all places?
I understand this patch is to fix the endianess, so this can be
applied as is, as long as the original code works. But, still in
general, I wonder how the concurrency is guaranteed by this driver
code...
thanks,
Takashi
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: raw read and write endian fix
2013-11-16 0:01 ` [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: " Taras Kondratiuk
2013-11-16 16:09 ` Jarkko Nikula
@ 2013-11-18 10:30 ` Peter Ujfalusi
2013-11-18 11:15 ` Mark Brown
2 siblings, 0 replies; 44+ messages in thread
From: Peter Ujfalusi @ 2013-11-18 10:30 UTC (permalink / raw)
To: Taras Kondratiuk, linux-omap
Cc: alsa-devel, Victor Kamensky, Takashi Iwai, linux-kernel,
Liam Girdwood, Mark Brown, linaro-networking, Jarkko Nikula
On 11/16/2013 02:01 AM, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
>
> Changes are trivial sed like replacement of __raw_xxx functions
> with xxx_relaxed variant.
>
> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
> sound/soc/omap/mcbsp.c | 12 ++++++------
> sound/soc/omap/omap-dmic.c | 4 ++--
> sound/soc/omap/omap-mcpdm.c | 4 ++--
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
> index 83433fd..86c7538 100644
> --- a/sound/soc/omap/mcbsp.c
> +++ b/sound/soc/omap/mcbsp.c
> @@ -36,10 +36,10 @@ static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
>
> if (mcbsp->pdata->reg_size == 2) {
> ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
> - __raw_writew((u16)val, addr);
> + writew_relaxed((u16)val, addr);
> } else {
> ((u32 *)mcbsp->reg_cache)[reg] = val;
> - __raw_writel(val, addr);
> + writel_relaxed(val, addr);
> }
> }
>
> @@ -48,22 +48,22 @@ static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
> void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
>
> if (mcbsp->pdata->reg_size == 2) {
> - return !from_cache ? __raw_readw(addr) :
> + return !from_cache ? readw_relaxed(addr) :
> ((u16 *)mcbsp->reg_cache)[reg];
> } else {
> - return !from_cache ? __raw_readl(addr) :
> + return !from_cache ? readl_relaxed(addr) :
> ((u32 *)mcbsp->reg_cache)[reg];
> }
> }
>
> static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
> {
> - __raw_writel(val, mcbsp->st_data->io_base_st + reg);
> + writel_relaxed(val, mcbsp->st_data->io_base_st + reg);
> }
>
> static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
> {
> - return __raw_readl(mcbsp->st_data->io_base_st + reg);
> + return readl_relaxed(mcbsp->st_data->io_base_st + reg);
> }
>
> #define MCBSP_READ(mcbsp, reg) \
> diff --git a/sound/soc/omap/omap-dmic.c b/sound/soc/omap/omap-dmic.c
> index 12e566b..1bd531d 100644
> --- a/sound/soc/omap/omap-dmic.c
> +++ b/sound/soc/omap/omap-dmic.c
> @@ -61,12 +61,12 @@ struct omap_dmic {
>
> static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
> {
> - __raw_writel(val, dmic->io_base + reg);
> + writel_relaxed(val, dmic->io_base + reg);
> }
>
> static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
> {
> - return __raw_readl(dmic->io_base + reg);
> + return readl_relaxed(dmic->io_base + reg);
> }
>
> static inline void omap_dmic_start(struct omap_dmic *dmic)
> diff --git a/sound/soc/omap/omap-mcpdm.c b/sound/soc/omap/omap-mcpdm.c
> index 90d2a7c..653ba1c 100644
> --- a/sound/soc/omap/omap-mcpdm.c
> +++ b/sound/soc/omap/omap-mcpdm.c
> @@ -74,12 +74,12 @@ struct omap_mcpdm {
>
> static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
> {
> - __raw_writel(val, mcpdm->io_base + reg);
> + writel_relaxed(val, mcpdm->io_base + reg);
> }
>
> static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
> {
> - return __raw_readl(mcpdm->io_base + reg);
> + return readl_relaxed(mcpdm->io_base + reg);
> }
>
> #ifdef DEBUG
>
--
Péter
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: raw read and write endian fix
2013-11-16 0:01 ` [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: " Taras Kondratiuk
2013-11-16 16:09 ` Jarkko Nikula
2013-11-18 10:30 ` Peter Ujfalusi
@ 2013-11-18 11:15 ` Mark Brown
2 siblings, 0 replies; 44+ messages in thread
From: Mark Brown @ 2013-11-18 11:15 UTC (permalink / raw)
To: Taras Kondratiuk
Cc: alsa-devel, Victor Kamensky, Takashi Iwai, linux-kernel,
Liam Girdwood, Peter Ujfalusi, linaro-networking, linux-omap,
Jarkko Nikula
[-- Attachment #1.1: Type: text/plain, Size: 523 bytes --]
On Sat, Nov 16, 2013 at 02:01:19AM +0200, Taras Kondratiuk wrote:
> From: Victor Kamensky <victor.kamensky@linaro.org>
>
> All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
> Need to use endian neutral functions to read/write h/w registers.
> I.e instead of __raw_read[lw] and __raw_write[lw] functions code
> need to use read[lw]_relaxed and write[lw]_relaxed functions.
> If the first simply reads/writes register, the second will byteswap
> it if host operates in BE mode.
Applied, thanks.
[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
[-- Attachment #2: Type: text/plain, Size: 0 bytes --]
^ permalink raw reply [flat|nested] 44+ messages in thread
* [RFC 17/23] ARM: OMAP2+: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (14 preceding siblings ...)
2013-11-16 0:01 ` [RFC 16/23] ASoC: omap: mcbsp, mcpdm, dmic: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 18/23] ARM: OMAP: dmtimer: " Taras Kondratiuk
` (5 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Tony Lindgren, Russell King,
Paul Walmsley, Kevin Hilman, Benoît Cousson, Rajendra Nayak,
linux-arm-kernel, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
arch/arm/mach-omap2/board-flash.c | 4 +--
arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 2 +-
arch/arm/mach-omap2/clkt2xxx_osc.c | 8 +++---
arch/arm/mach-omap2/clkt2xxx_sys.c | 2 +-
arch/arm/mach-omap2/clkt_clksel.c | 10 +++----
arch/arm/mach-omap2/clkt_dpll.c | 6 ++---
arch/arm/mach-omap2/clkt_iclk.c | 8 +++---
arch/arm/mach-omap2/clock.c | 16 +++++------
arch/arm/mach-omap2/clock36xx.c | 6 ++---
arch/arm/mach-omap2/cm2xxx_3xxx.h | 4 +--
arch/arm/mach-omap2/cm33xx.c | 4 +--
arch/arm/mach-omap2/cm3xxx.c | 8 +++---
arch/arm/mach-omap2/cm44xx.c | 8 +++---
arch/arm/mach-omap2/cminst44xx.c | 4 +--
arch/arm/mach-omap2/control.c | 20 +++++++-------
arch/arm/mach-omap2/dma.c | 4 +--
arch/arm/mach-omap2/dpll3xxx.c | 32 +++++++++++-----------
arch/arm/mach-omap2/dpll44xx.c | 12 ++++-----
arch/arm/mach-omap2/gpmc.c | 8 +++---
arch/arm/mach-omap2/id.c | 2 +-
arch/arm/mach-omap2/irq.c | 4 +--
arch/arm/mach-omap2/mux.c | 8 +++---
arch/arm/mach-omap2/omap-hotplug.c | 4 +--
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 18 ++++++-------
arch/arm/mach-omap2/omap-smp.c | 4 +--
arch/arm/mach-omap2/omap-wakeupgen.c | 42 ++++++++++++++---------------
arch/arm/mach-omap2/omap4-common.c | 16 +++++------
arch/arm/mach-omap2/omap_hwmod.c | 10 +++----
arch/arm/mach-omap2/omap_phy_internal.c | 6 ++---
arch/arm/mach-omap2/prcm_mpu44xx.c | 4 +--
arch/arm/mach-omap2/prm2xxx.h | 2 +-
arch/arm/mach-omap2/prm2xxx_3xxx.h | 4 +--
arch/arm/mach-omap2/prm33xx.c | 4 +--
arch/arm/mach-omap2/prm3xxx.h | 2 +-
arch/arm/mach-omap2/prm44xx.c | 4 +--
arch/arm/mach-omap2/prminst44xx.c | 4 +--
arch/arm/mach-omap2/sdrc.h | 8 +++---
arch/arm/mach-omap2/sdrc2xxx.c | 4 +--
arch/arm/mach-omap2/sr_device.c | 2 +-
arch/arm/mach-omap2/sram.c | 16 +++++------
arch/arm/mach-omap2/timer.c | 8 +++---
arch/arm/mach-omap2/vc.c | 4 +--
arch/arm/mach-omap2/wd_timer.c | 8 +++---
43 files changed, 177 insertions(+), 177 deletions(-)
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index fc20a61..17ecd8d 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -160,13 +160,13 @@ static u8 get_gpmc0_type(void)
if (!fpga_map_addr)
return -ENOMEM;
- if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
+ if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
/* we dont have an DEBUG FPGA??? */
/* Depend on #defines!! default to strata boot return param */
goto unmap;
/* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
- cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
+ cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
/* ES2.0 SDP's onwards 4 dip switches are provided for CS */
if (omap_rev() >= OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index d862010..83933df 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -141,7 +141,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
if (!dd)
return -EINVAL;
- tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+ tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg);
tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
dd->div1_mask);
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index 19f54d4..0717dff 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -39,9 +39,9 @@ int omap2_enable_osc_ck(struct clk_hw *clk)
{
u32 pcc;
- pcc = __raw_readl(prcm_clksrc_ctrl);
+ pcc = readl_relaxed(prcm_clksrc_ctrl);
- __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+ writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
return 0;
}
@@ -57,9 +57,9 @@ void omap2_disable_osc_ck(struct clk_hw *clk)
{
u32 pcc;
- pcc = __raw_readl(prcm_clksrc_ctrl);
+ pcc = readl_relaxed(prcm_clksrc_ctrl);
- __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+ writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
}
unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index f467d07..58dd3a9 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -33,7 +33,7 @@ u32 omap2xxx_get_sysclkdiv(void)
{
u32 div;
- div = __raw_readl(prcm_clksrc_ctrl);
+ div = readl_relaxed(prcm_clksrc_ctrl);
div &= OMAP_SYSCLKDIV_MASK;
div >>= OMAP_SYSCLKDIV_SHIFT;
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 0ec9f6f..7ac0050 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
{
u32 v;
- v = __raw_readl(clk->clksel_reg);
+ v = readl_relaxed(clk->clksel_reg);
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
- __raw_writel(v, clk->clksel_reg);
+ writel_relaxed(v, clk->clksel_reg);
- v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+ v = readl_relaxed(clk->clksel_reg); /* OCP barrier */
}
/**
@@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk)
if (!clk->clksel || !clk->clksel_mask)
return 0;
- v = __raw_readl(clk->clksel_reg);
+ v = readl_relaxed(clk->clksel_reg);
v &= clk->clksel_mask;
v >>= __ffs(clk->clksel_mask);
@@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
WARN((!clk->clksel || !clk->clksel_mask),
"clock: %s: attempt to call on a non-clksel clock", clk_name);
- r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+ r = readl_relaxed(clk->clksel_reg) & clk->clksel_mask;
r >>= __ffs(clk->clksel_mask);
for (clks = clk->clksel; clks->parent && !found; clks++) {
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230..934e8f0 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
if (!dd)
return -EINVAL;
- v = __raw_readl(dd->control_reg);
+ v = readl_relaxed(dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
@@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
return 0;
/* Return bypass rate if DPLL is bypassed */
- v = __raw_readl(dd->control_reg);
+ v = readl_relaxed(dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
return __clk_get_rate(dd->clk_bypass);
}
- v = __raw_readl(dd->mult_div1_reg);
+ v = readl_relaxed(dd->mult_div1_reg);
dpll_mult = v & dd->mult_mask;
dpll_mult >>= __ffs(dd->mult_mask);
dpll_div = v & dd->div1_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index f10eb03..70fe2c1 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -29,9 +29,9 @@ void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
- v = __raw_readl((__force void __iomem *)r);
+ v = readl_relaxed((__force void __iomem *)r);
v |= (1 << clk->enable_bit);
- __raw_writel(v, (__force void __iomem *)r);
+ writel_relaxed(v, (__force void __iomem *)r);
}
/* XXX */
@@ -41,9 +41,9 @@ void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
- v = __raw_readl((__force void __iomem *)r);
+ v = readl_relaxed((__force void __iomem *)r);
v &= ~(1 << clk->enable_bit);
- __raw_writel(v, (__force void __iomem *)r);
+ writel_relaxed(v, (__force void __iomem *)r);
}
/* Public data */
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..5e191be 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -105,7 +105,7 @@ static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
ena = (idlest) ? 0 : mask;
- omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+ omap_test_timeout(((readl_relaxed(reg) & mask) == ena),
MAX_MODULE_ENABLE_WAIT, i);
if (i < MAX_MODULE_ENABLE_WAIT)
@@ -138,7 +138,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
/* Not all modules have multiple clocks that their IDLEST depends on */
if (clk->ops->find_companion) {
clk->ops->find_companion(clk, &companion_reg, &other_bit);
- if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+ if (!(readl_relaxed(companion_reg) & (1 << other_bit)))
return;
}
@@ -309,13 +309,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
}
/* FIXME should not have INVERT_ENABLE bit here */
- v = __raw_readl(clk->enable_reg);
+ v = readl_relaxed(clk->enable_reg);
if (clk->flags & INVERT_ENABLE)
v &= ~(1 << clk->enable_bit);
else
v |= (1 << clk->enable_bit);
- __raw_writel(v, clk->enable_reg);
- v = __raw_readl(clk->enable_reg); /* OCP barrier */
+ writel_relaxed(v, clk->enable_reg);
+ v = readl_relaxed(clk->enable_reg); /* OCP barrier */
if (clk->ops && clk->ops->find_idlest)
_omap2_module_wait_ready(clk);
@@ -353,12 +353,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
return;
}
- v = __raw_readl(clk->enable_reg);
+ v = readl_relaxed(clk->enable_reg);
if (clk->flags & INVERT_ENABLE)
v |= (1 << clk->enable_bit);
else
v &= ~(1 << clk->enable_bit);
- __raw_writel(v, clk->enable_reg);
+ writel_relaxed(v, clk->enable_reg);
/* No OCP barrier needed here since it is a disable operation */
if (clkdm_control && clk->clkdm)
@@ -454,7 +454,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 v;
- v = __raw_readl(clk->enable_reg);
+ v = readl_relaxed(clk->enable_reg);
if (clk->flags & INVERT_ENABLE)
v ^= BIT(clk->enable_bit);
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index bbd6a3f..bdd228a 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -53,15 +53,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
/* Restore the dividers */
if (!ret) {
- orig_v = __raw_readl(parent->reg);
+ orig_v = readl_relaxed(parent->reg);
dummy_v = orig_v;
/* Write any other value different from the Read value */
dummy_v ^= (1 << parent->shift);
- __raw_writel(dummy_v, parent->reg);
+ writel_relaxed(dummy_v, parent->reg);
/* Write the original divider */
- __raw_writel(orig_v, parent->reg);
+ writel_relaxed(orig_v, parent->reg);
}
return ret;
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index bfbd16f..72928a3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -52,12 +52,12 @@
static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
{
- return __raw_readl(cm_base + module + idx);
+ return readl_relaxed(cm_base + module + idx);
}
static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
{
- __raw_writel(val, cm_base + module + idx);
+ writel_relaxed(val, cm_base + module + idx);
}
/* Read-modify-write a register in a CM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 325a515..74a0935 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -50,13 +50,13 @@
/* Read a register in a CM instance */
static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
{
- return __raw_readl(cm_base + inst + idx);
+ return readl_relaxed(cm_base + inst + idx);
}
/* Write into a register in a CM */
static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
{
- __raw_writel(val, cm_base + inst + idx);
+ writel_relaxed(val, cm_base + inst + idx);
}
/* Read-modify-write a register in CM */
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 9061c30..85d9842 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -388,7 +388,7 @@ void omap3_cm_save_context(void)
omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
cm_context.iva2_cm_clksel2 =
omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
- cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
+ cm_context.cm_sysconfig = readl_relaxed(OMAP3430_CM_SYSCONFIG);
cm_context.sgx_cm_clksel =
omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
cm_context.dss_cm_clksel =
@@ -418,7 +418,7 @@ void omap3_cm_save_context(void)
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
cm_context.pll_cm_clken2 =
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
- cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
+ cm_context.cm_polctrl = readl_relaxed(OMAP3430_CM_POLCTRL);
cm_context.iva2_cm_fclken =
omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
cm_context.iva2_cm_clken_pll =
@@ -519,7 +519,7 @@ void omap3_cm_restore_context(void)
CM_CLKSEL1);
omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
CM_CLKSEL2);
- __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
+ writel_relaxed(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
CM_CLKSEL);
omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
@@ -547,7 +547,7 @@ void omap3_cm_restore_context(void)
OMAP3430ES2_CM_CLKSEL5);
omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
OMAP3430ES2_CM_CLKEN2);
- __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
+ writel_relaxed(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
CM_FCLKEN);
omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 535d66e..30b6d97 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -30,23 +30,23 @@
/* Read a register in CM1 */
u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
{
- return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg));
+ return readl_relaxed(OMAP44XX_CM1_REGADDR(inst, reg));
}
/* Write into a register in CM1 */
void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
{
- __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg));
+ writel_relaxed(val, OMAP44XX_CM1_REGADDR(inst, reg));
}
/* Read a register in CM2 */
u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
{
- return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg));
+ return readl_relaxed(OMAP44XX_CM2_REGADDR(inst, reg));
}
/* Write into a register in CM2 */
void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
{
- __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg));
+ writel_relaxed(val, OMAP44XX_CM2_REGADDR(inst, reg));
}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index f0290f5..c026d3c 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -116,7 +116,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]);
- return __raw_readl(_cm_bases[part] + inst + idx);
+ return readl_relaxed(_cm_bases[part] + inst + idx);
}
/* Write into a register in a CM instance */
@@ -125,7 +125,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]);
- __raw_writel(val, _cm_bases[part] + inst + idx);
+ writel_relaxed(val, _cm_bases[part] + inst + idx);
}
/* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 31e0dfe..5d91945 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -161,32 +161,32 @@ void __iomem *omap_ctrl_base_get(void)
u8 omap_ctrl_readb(u16 offset)
{
- return __raw_readb(OMAP_CTRL_REGADDR(offset));
+ return readb_relaxed(OMAP_CTRL_REGADDR(offset));
}
u16 omap_ctrl_readw(u16 offset)
{
- return __raw_readw(OMAP_CTRL_REGADDR(offset));
+ return readw_relaxed(OMAP_CTRL_REGADDR(offset));
}
u32 omap_ctrl_readl(u16 offset)
{
- return __raw_readl(OMAP_CTRL_REGADDR(offset));
+ return readl_relaxed(OMAP_CTRL_REGADDR(offset));
}
void omap_ctrl_writeb(u8 val, u16 offset)
{
- __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
+ writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
}
void omap_ctrl_writew(u16 val, u16 offset)
{
- __raw_writew(val, OMAP_CTRL_REGADDR(offset));
+ writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
}
void omap_ctrl_writel(u32 val, u16 offset)
{
- __raw_writel(val, OMAP_CTRL_REGADDR(offset));
+ writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
}
/*
@@ -198,12 +198,12 @@ void omap_ctrl_writel(u32 val, u16 offset)
u32 omap4_ctrl_pad_readl(u16 offset)
{
- return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
+ return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
}
void omap4_ctrl_pad_writel(u32 val, u16 offset)
{
- __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
+ writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
}
#ifdef CONFIG_ARCH_OMAP3
@@ -232,7 +232,7 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
*
* XXX This should use some omap_ctrl_writel()-type function
*/
- __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
+ writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
}
#endif
@@ -295,7 +295,7 @@ void omap3_clear_scratchpad_contents(void)
if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
OMAP3430_GLOBAL_COLD_RST_MASK) {
for ( ; offset <= max_offset; offset += 0x4)
- __raw_writel(0x0, (v_addr + offset));
+ writel_relaxed(0x0, (v_addr + offset));
omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
OMAP3430_GR_MOD,
OMAP3_PRM_RSTST_OFFSET);
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 49fd0d5..2582ed2 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -98,7 +98,7 @@ static inline void dma_write(u32 val, int reg, int lch)
stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
offset = reg_map[reg] + (stride * lch);
- __raw_writel(val, dma_base + offset);
+ writel_relaxed(val, dma_base + offset);
}
static inline u32 dma_read(int reg, int lch)
@@ -108,7 +108,7 @@ static inline u32 dma_read(int reg, int lch)
stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
offset = reg_map[reg] + (stride * lch);
- val = __raw_readl(dma_base + offset);
+ val = readl_relaxed(dma_base + offset);
return val;
}
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3a0296c..d3fe570 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -50,10 +50,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
dd = clk->dpll_data;
- v = __raw_readl(dd->control_reg);
+ v = readl_relaxed(dd->control_reg);
v &= ~dd->enable_mask;
v |= clken_bits << __ffs(dd->enable_mask);
- __raw_writel(v, dd->control_reg);
+ writel_relaxed(v, dd->control_reg);
}
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -69,7 +69,7 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
state <<= __ffs(dd->idlest_mask);
- while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
+ while (((readl_relaxed(dd->idlest_reg) & dd->idlest_mask) != state) &&
i < MAX_DPLL_WAIT_TRIES) {
i++;
udelay(1);
@@ -147,7 +147,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
state <<= __ffs(dd->idlest_mask);
/* Check if already locked */
- if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
+ if ((readl_relaxed(dd->idlest_reg) & dd->idlest_mask) == state)
goto done;
ai = omap3_dpll_autoidle_read(clk);
@@ -311,14 +311,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
* only since freqsel field is no longer present on other devices.
*/
if (cpu_is_omap343x()) {
- v = __raw_readl(dd->control_reg);
+ v = readl_relaxed(dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
- __raw_writel(v, dd->control_reg);
+ writel_relaxed(v, dd->control_reg);
}
/* Set DPLL multiplier, divider */
- v = __raw_readl(dd->mult_div1_reg);
+ v = readl_relaxed(dd->mult_div1_reg);
v &= ~(dd->mult_mask | dd->div1_mask);
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
@@ -336,11 +336,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
v |= sd_div << __ffs(dd->sddiv_mask);
}
- __raw_writel(v, dd->mult_div1_reg);
+ writel_relaxed(v, dd->mult_div1_reg);
/* Set 4X multiplier and low-power mode */
if (dd->m4xen_mask || dd->lpmode_mask) {
- v = __raw_readl(dd->control_reg);
+ v = readl_relaxed(dd->control_reg);
if (dd->m4xen_mask) {
if (dd->last_rounded_m4xen)
@@ -356,7 +356,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
v &= ~dd->lpmode_mask;
}
- __raw_writel(v, dd->control_reg);
+ writel_relaxed(v, dd->control_reg);
}
/* We let the clock framework set the other output dividers later */
@@ -554,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
if (!dd->autoidle_reg)
return -EINVAL;
- v = __raw_readl(dd->autoidle_reg);
+ v = readl_relaxed(dd->autoidle_reg);
v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask);
@@ -588,10 +588,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
* by writing 0x5 instead of 0x1. Add some mechanism to
* optionally enter this mode.
*/
- v = __raw_readl(dd->autoidle_reg);
+ v = readl_relaxed(dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
- __raw_writel(v, dd->autoidle_reg);
+ writel_relaxed(v, dd->autoidle_reg);
}
@@ -614,10 +614,10 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
if (!dd->autoidle_reg)
return;
- v = __raw_readl(dd->autoidle_reg);
+ v = readl_relaxed(dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
- __raw_writel(v, dd->autoidle_reg);
+ writel_relaxed(v, dd->autoidle_reg);
}
@@ -660,7 +660,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
WARN_ON(!dd->enable_mask);
- v = __raw_readl(dd->control_reg) & dd->enable_mask;
+ v = readl_relaxed(dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
rate = parent_rate;
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index d28b0f7..9562383 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
- v = __raw_readl(clk->clksel_reg);
+ v = readl_relaxed(clk->clksel_reg);
v &= mask;
v >>= __ffs(mask);
@@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
- v = __raw_readl(clk->clksel_reg);
+ v = readl_relaxed(clk->clksel_reg);
/* Clear the bit to allow gatectrl */
v &= ~mask;
- __raw_writel(v, clk->clksel_reg);
+ writel_relaxed(v, clk->clksel_reg);
}
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
@@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
- v = __raw_readl(clk->clksel_reg);
+ v = readl_relaxed(clk->clksel_reg);
/* Set the bit to deny gatectrl */
v |= mask;
- __raw_writel(v, clk->clksel_reg);
+ writel_relaxed(v, clk->clksel_reg);
}
const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
@@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
rate = omap2_get_dpll_rate(clk);
/* regm4xen adds a multiplier of 4 to DPLL calculations */
- v = __raw_readl(dd->control_reg);
+ v = readl_relaxed(dd->control_reg);
if (v & OMAP4430_DPLL_REGM4XEN_MASK)
rate *= OMAP4430_REGM4XEN_MULT;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 579697a..55e381e 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -170,12 +170,12 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev);
static void gpmc_write_reg(int idx, u32 val)
{
- __raw_writel(val, gpmc_base + idx);
+ writel_relaxed(val, gpmc_base + idx);
}
static u32 gpmc_read_reg(int idx)
{
- return __raw_readl(gpmc_base + idx);
+ return readl_relaxed(gpmc_base + idx);
}
void gpmc_cs_write_reg(int cs, int idx, u32 val)
@@ -183,7 +183,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
void __iomem *reg_addr;
reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- __raw_writel(val, reg_addr);
+ writel_relaxed(val, reg_addr);
}
static u32 gpmc_cs_read_reg(int cs, int idx)
@@ -191,7 +191,7 @@ static u32 gpmc_cs_read_reg(int cs, int idx)
void __iomem *reg_addr;
reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- return __raw_readl(reg_addr);
+ return readl_relaxed(reg_addr);
}
/* TODO: Add support for gpmc_fck to clock framework and use it */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0289adc..5bf2dc7 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -93,7 +93,7 @@ EXPORT_SYMBOL(omap_type);
#define OMAP_TAP_DIE_ID_44XX_2 0x020c
#define OMAP_TAP_DIE_ID_44XX_3 0x0210
-#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
+#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
struct omap_id {
u16 hawkeye; /* Silicon type (Hawkeye id) */
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3926f37..411b197 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -83,12 +83,12 @@ struct omap3_intc_regs {
static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
{
- __raw_writel(val, bank->base_reg + reg);
+ writel_relaxed(val, bank->base_reg + reg);
}
static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
{
- return __raw_readl(bank->base_reg + reg);
+ return readl_relaxed(bank->base_reg + reg);
}
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index f82cf87..216f051 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -70,18 +70,18 @@ struct omap_mux_partition *omap_mux_get(const char *name)
u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
{
if (partition->flags & OMAP_MUX_REG_8BIT)
- return __raw_readb(partition->base + reg);
+ return readb_relaxed(partition->base + reg);
else
- return __raw_readw(partition->base + reg);
+ return readw_relaxed(partition->base + reg);
}
void omap_mux_write(struct omap_mux_partition *partition, u16 val,
u16 reg)
{
if (partition->flags & OMAP_MUX_REG_8BIT)
- __raw_writeb(val, partition->base + reg);
+ writeb_relaxed(val, partition->base + reg);
else
- __raw_writew(val, partition->base + reg);
+ writew_relaxed(val, partition->base + reg);
}
void omap_mux_write_array(struct omap_mux_partition *partition,
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 458f72f..971791f 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -39,7 +39,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
pr_err("Secure clear status failed\n");
} else {
- __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+ writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0);
}
@@ -53,7 +53,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
boot_cpu = omap_read_auxcoreboot0();
else
boot_cpu =
- __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
+ readl_relaxed(base + OMAP_AUX_CORE_BOOT_0) >> 5;
if (boot_cpu == smp_processor_id()) {
/*
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index f991016..6358257 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -116,7 +116,7 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
- __raw_writel(addr, pm_info->wkup_sar_addr);
+ writel_relaxed(addr, pm_info->wkup_sar_addr);
}
/*
@@ -141,7 +141,7 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
break;
}
- __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
+ writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
}
/* Helper functions for MPUSS OSWR */
@@ -179,7 +179,7 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
- __raw_writel(save_state, pm_info->l2x0_sar_addr);
+ writel_relaxed(save_state, pm_info->l2x0_sar_addr);
}
/*
@@ -192,10 +192,10 @@ static void save_l2x0_context(void)
u32 val;
void __iomem *l2x0_base = omap4_get_l2cache_base();
if (l2x0_base) {
- val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
- __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
- val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
- __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+ val = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+ writel_relaxed(val, sar_base + L2X0_AUXCTRL_OFFSET);
+ val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+ writel_relaxed(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
}
}
#else
@@ -383,9 +383,9 @@ int __init omap4_mpuss_init(void)
/* Save device type on scratchpad for low level code to use */
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
- __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
+ writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET);
else
- __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+ writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET);
save_l2x0_context();
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 8912110..0622542 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -94,7 +94,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
if (omap_secure_apis_support())
omap_modify_auxcoreboot0(0x200, 0xfffffdff);
else
- __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+ writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
if (!cpu1_clkdm && !cpu1_pwrdm) {
cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
@@ -224,7 +224,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
if (omap_secure_apis_support())
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
else
- __raw_writel(virt_to_phys(omap5_secondary_startup),
+ writel_relaxed(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);
}
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 813c615..6f5665a 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -56,19 +56,19 @@ static unsigned int omap_secure_apis;
*/
static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
{
- return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
+ return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
(cpu * CPU_ENA_OFFSET) + (idx * 4));
}
static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
{
- __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
+ writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
(cpu * CPU_ENA_OFFSET) + (idx * 4));
}
static inline void sar_writel(u32 val, u32 offset, u8 idx)
{
- __raw_writel(val, sar_base + offset + (idx * 4));
+ writel_relaxed(val, sar_base + offset + (idx * 4));
}
static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
@@ -227,21 +227,21 @@ static inline void omap4_irq_save_context(void)
}
/* Save AuxBoot* registers */
- val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
- __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
- val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
- __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+ val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+ writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
+ val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
+ writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
/* Save SyncReq generation logic */
- val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
- __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
- val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
- __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
+ val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
+ writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
+ val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
+ writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
/* Set the Backup Bit Mask status */
- val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+ val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
- __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+ writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
}
@@ -260,15 +260,15 @@ static inline void omap5_irq_save_context(void)
}
/* Save AuxBoot* registers */
- val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
- __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
- val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
- __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
+ val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+ writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
+ val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+ writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
/* Set the Backup Bit Mask status */
- val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+ val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
- __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+ writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
}
@@ -302,9 +302,9 @@ static void irq_sar_clear(void)
if (soc_is_omap54xx())
offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
- val = __raw_readl(sar_base + offset);
+ val = readl_relaxed(sar_base + offset);
val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
- __raw_writel(val, sar_base + offset);
+ writel_relaxed(val, sar_base + offset);
}
/*
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 5791143..2840d1e 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -125,19 +125,19 @@ void __init gic_init_irq(void)
void gic_dist_disable(void)
{
if (gic_dist_base_addr)
- __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
+ writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
}
bool gic_dist_disabled(void)
{
- return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
+ return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
}
void gic_timer_retrigger(void)
{
- u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
- u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
- u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
+ u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
+ u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
+ u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
/*
@@ -145,11 +145,11 @@ void gic_timer_retrigger(void)
* disabled. Ack the pending interrupt, and retrigger it.
*/
pr_warn("%s: lost localtimer interrupt\n", __func__);
- __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
+ writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
- __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
+ writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
- __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
+ writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
}
}
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d9ee0ff..645dc40 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -72,7 +72,7 @@
* | (../mach-omap2/omap_hwmod*) |
* +-------------------------------+
* | OMAP clock/PRCM/register fns |
- * | (__raw_{read,write}l, clk*) |
+ * | ({read,write}l_relaxed, clk*) |
* +-------------------------------+
*
* Device drivers should not contain any OMAP-specific code or data in
@@ -3114,17 +3114,17 @@ static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
{
if (oh->flags & HWMOD_16BIT_REG)
- return __raw_readw(oh->_mpu_rt_va + reg_offs);
+ return readw_relaxed(oh->_mpu_rt_va + reg_offs);
else
- return __raw_readl(oh->_mpu_rt_va + reg_offs);
+ return readl_relaxed(oh->_mpu_rt_va + reg_offs);
}
void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
{
if (oh->flags & HWMOD_16BIT_REG)
- __raw_writew(v, oh->_mpu_rt_va + reg_offs);
+ writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
else
- __raw_writel(v, oh->_mpu_rt_va + reg_offs);
+ writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
}
/**
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index eb8a25d..50640b3 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -57,7 +57,7 @@ static int __init omap4430_phy_power_down(void)
}
/* Power down the phy */
- __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+ writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
iounmap(ctrl_base);
@@ -162,7 +162,7 @@ void ti81xx_musb_phy_power(u8 on)
return;
}
- usbphycfg = __raw_readl(scm_base + USBCTRL0);
+ usbphycfg = readl_relaxed(scm_base + USBCTRL0);
if (on) {
if (cpu_is_ti816x()) {
@@ -181,7 +181,7 @@ void ti81xx_musb_phy_power(u8 on)
usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
}
- __raw_writel(usbphycfg, scm_base + USBCTRL0);
+ writel_relaxed(usbphycfg, scm_base + USBCTRL0);
iounmap(scm_base);
}
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index c30e44a..cdbee63 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -30,12 +30,12 @@ void __iomem *prcm_mpu_base;
u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
{
- return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+ return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
}
void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
{
- __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+ writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
}
u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 3194dd8..d2cb636 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -27,7 +27,7 @@
/*
* OMAP2-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
+ * Use {read,write}l_relaxed() with these registers.
*
* With a few exceptions, these are the register names beginning with
* PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 9624b40..1a3a963 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -55,12 +55,12 @@
/* Power/reset management domain register get/set */
static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{
- return __raw_readl(prm_base + module + idx);
+ return readl_relaxed(prm_base + module + idx);
}
static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
{
- __raw_writel(val, prm_base + module + idx);
+ writel_relaxed(val, prm_base + module + idx);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 7204407..93ba48a 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -27,13 +27,13 @@
/* Read a register in a PRM instance */
u32 am33xx_prm_read_reg(s16 inst, u16 idx)
{
- return __raw_readl(prm_base + inst + idx);
+ return readl_relaxed(prm_base + inst + idx);
}
/* Write into a register in a PRM instance */
void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
{
- __raw_writel(val, prm_base + inst + idx);
+ writel_relaxed(val, prm_base + inst + idx);
}
/* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 277f717..f20e5c9 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -26,7 +26,7 @@
/*
* OMAP3-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
+ * Use {read,write}l_relaxed() with these registers.
*
* With a few exceptions, these are the register names beginning with
* PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 03a6034..94a43b3 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
/* Read a register in a CM/PRM instance in the PRM module */
u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
{
- return __raw_readl(prm_base + inst + reg);
+ return readl_relaxed(prm_base + inst + reg);
}
/* Write into a register in a CM/PRM instance in the PRM module */
void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
{
- __raw_writel(val, prm_base + inst + reg);
+ writel_relaxed(val, prm_base + inst + reg);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 6334b96..0e08425 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -48,7 +48,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]);
- return __raw_readl(_prm_bases[part] + inst + idx);
+ return readl_relaxed(_prm_bases[part] + inst + idx);
}
/* Write into a register in a PRM instance */
@@ -57,7 +57,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]);
- __raw_writel(val, _prm_bases[part] + inst + idx);
+ writel_relaxed(val, _prm_bases[part] + inst + idx);
}
/* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 446aa13..645a2a4 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -31,24 +31,24 @@ extern void __iomem *omap2_sms_base;
static inline void sdrc_write_reg(u32 val, u16 reg)
{
- __raw_writel(val, OMAP_SDRC_REGADDR(reg));
+ writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
}
static inline u32 sdrc_read_reg(u16 reg)
{
- return __raw_readl(OMAP_SDRC_REGADDR(reg));
+ return readl_relaxed(OMAP_SDRC_REGADDR(reg));
}
/* SMS global register get/set */
static inline void sms_write_reg(u32 val, u16 reg)
{
- __raw_writel(val, OMAP_SMS_REGADDR(reg));
+ writel_relaxed(val, OMAP_SMS_REGADDR(reg));
}
static inline u32 sms_read_reg(u16 reg)
{
- return __raw_readl(OMAP_SMS_REGADDR(reg));
+ return readl_relaxed(OMAP_SMS_REGADDR(reg));
}
extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 9072917..ae3f155 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -103,9 +103,9 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
* prm2xxx.c function
*/
if (cpu_is_omap2420())
- __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
+ writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
else
- __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
+ writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
curr_perf_level = level;
local_irq_restore(flags);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d7bc33f..1b91ef0 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -57,7 +57,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
/*
* In OMAP4 the efuse registers are 24 bit aligned.
- * A __raw_readl will fail for non-32 bit aligned address
+ * A readl_relaxed will fail for non-32 bit aligned address
* and hence the 8-bit read and shift.
*/
if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 4bd0968..ddf1818 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -70,16 +70,16 @@ static int is_sram_locked(void)
if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
/* RAMFW: R/W access to all initiators for all qualifier sets */
if (cpu_is_omap242x()) {
- __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
- __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
- __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
+ writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
+ writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
+ writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
}
if (cpu_is_omap34xx()) {
- __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
- __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
- __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
- __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
- __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
+ writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+ writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
+ writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+ writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
+ writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
}
return 0;
} else
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index ead48fa..3a16ea0 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -532,15 +532,15 @@ static void __init realtime_counter_init(void)
}
/* Program numerator and denumerator registers */
- reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+ reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
NUMERATOR_DENUMERATOR_MASK;
reg |= num;
- __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+ writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
- reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
+ reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
NUMERATOR_DENUMERATOR_MASK;
reg |= den;
- __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+ writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
iounmap(base);
}
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 49ac797..267f204 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -462,7 +462,7 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
OMAP4_DOWNTIME_MASK);
- __raw_writel(val, OMAP4_SCRM_CLKSETUPTIME);
+ writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
}
/* OMAP4 specific voltage init functions */
@@ -584,7 +584,7 @@ static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
/* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
- __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
+ writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
/* HSSCLH can always be zero */
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index d15c7bb..97d6607 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -49,12 +49,12 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
}
/* sequence required to disable watchdog */
- __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
- while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+ writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
+ while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
cpu_relax();
- __raw_writel(0x5555, base + OMAP_WDT_SPR);
- while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+ writel_relaxed(0x5555, base + OMAP_WDT_SPR);
+ while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
cpu_relax();
return 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 18/23] ARM: OMAP: dmtimer: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (15 preceding siblings ...)
2013-11-16 0:01 ` [RFC 17/23] ARM: OMAP2+: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 19/23] ARM: OMAP: counter-32k: " Taras Kondratiuk
` (4 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Tony Lindgren, Russell King,
linux-arm-kernel, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
arch/arm/plat-omap/dmtimer.c | 8 ++++----
arch/arm/plat-omap/include/plat/dmtimer.h | 16 ++++++++--------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 869254c..db10169 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -103,7 +103,7 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
timer->context.tmar);
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
timer->context.tsicr);
- __raw_writel(timer->context.tier, timer->irq_ena);
+ writel_relaxed(timer->context.tier, timer->irq_ena);
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
timer->context.tclr);
}
@@ -699,9 +699,9 @@ int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
omap_dm_timer_enable(timer);
if (timer->revision == 1)
- l = __raw_readl(timer->irq_ena) & ~mask;
+ l = readl_relaxed(timer->irq_ena) & ~mask;
- __raw_writel(l, timer->irq_dis);
+ writel_relaxed(l, timer->irq_dis);
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
@@ -722,7 +722,7 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
return 0;
}
- l = __raw_readl(timer->irq_stat);
+ l = readl_relaxed(timer->irq_stat);
return l;
}
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index fb92abb..e5e46d6 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -280,20 +280,20 @@ static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
int posted)
{
if (posted)
- while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+ while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
cpu_relax();
- return __raw_readl(timer->func_base + (reg & 0xff));
+ return readl_relaxed(timer->func_base + (reg & 0xff));
}
static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
u32 reg, u32 val, int posted)
{
if (posted)
- while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+ while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
cpu_relax();
- __raw_writel(val, timer->func_base + (reg & 0xff));
+ writel_relaxed(val, timer->func_base + (reg & 0xff));
}
static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
@@ -301,7 +301,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
u32 tidr;
/* Assume v1 ip if bits [31:16] are zero */
- tidr = __raw_readl(timer->io_base);
+ tidr = readl_relaxed(timer->io_base);
if (!(tidr >> 16)) {
timer->revision = 1;
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
@@ -382,7 +382,7 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
}
/* Ack possibly pending interrupt */
- __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
+ writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
}
static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
@@ -396,7 +396,7 @@ static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
unsigned int value)
{
- __raw_writel(value, timer->irq_ena);
+ writel_relaxed(value, timer->irq_ena);
__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
}
@@ -409,7 +409,7 @@ __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
unsigned int value)
{
- __raw_writel(value, timer->irq_stat);
+ writel_relaxed(value, timer->irq_stat);
}
#endif /* __ASM_ARCH_DMTIMER_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 19/23] ARM: OMAP: counter-32k: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (16 preceding siblings ...)
2013-11-16 0:01 ` [RFC 18/23] ARM: OMAP: dmtimer: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 20/23] ARM: OMAP: debug-leds: " Taras Kondratiuk
` (3 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Tony Lindgren, Russell King,
linux-arm-kernel, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
arch/arm/plat-omap/counter_32k.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index d9bc98e..21ca329 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -40,7 +40,7 @@ static void __iomem *sync32k_cnt_reg;
static u32 notrace omap_32k_read_sched_clock(void)
{
- return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
+ return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
}
/**
@@ -64,7 +64,7 @@ static void omap_read_persistent_clock(struct timespec *ts)
spin_lock_irqsave(&read_persistent_clock_lock, flags);
last_cycles = cycles;
- cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
+ cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
nsecs = clocksource_cyc2ns(cycles - last_cycles,
persistent_mult, persistent_shift);
@@ -95,7 +95,7 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
* The 'SCHEME' bits(30-31) of the revision register is used
* to identify the version.
*/
- if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
+ if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
OMAP2_32KSYNCNT_REV_SCHEME)
sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
else
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 20/23] ARM: OMAP: debug-leds: raw read and write endian fix
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (17 preceding siblings ...)
2013-11-16 0:01 ` [RFC 19/23] ARM: OMAP: counter-32k: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 21/23] ARM: OMAP4: sleep: byteswap data for big-endian Taras Kondratiuk
` (2 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Tony Lindgren, Russell King,
linux-arm-kernel, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
arch/arm/plat-omap/debug-leds.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index aa7ebc6..48b69de 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -85,12 +85,12 @@ static void dbg_led_set(struct led_classdev *cdev,
struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
u16 reg;
- reg = __raw_readw(&fpga->leds);
+ reg = readw_relaxed(&fpga->leds);
if (b != LED_OFF)
reg |= led->mask;
else
reg &= ~led->mask;
- __raw_writew(reg, &fpga->leds);
+ writew_relaxed(reg, &fpga->leds);
}
static enum led_brightness dbg_led_get(struct led_classdev *cdev)
@@ -98,7 +98,7 @@ static enum led_brightness dbg_led_get(struct led_classdev *cdev)
struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
u16 reg;
- reg = __raw_readw(&fpga->leds);
+ reg = readw_relaxed(&fpga->leds);
return (reg & led->mask) ? LED_FULL : LED_OFF;
}
@@ -112,7 +112,7 @@ static int fpga_probe(struct platform_device *pdev)
return -ENODEV;
fpga = ioremap(iomem->start, resource_size(iomem));
- __raw_writew(0xff, &fpga->leds);
+ writew_relaxed(0xff, &fpga->leds);
for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
struct dbg_led *led;
@@ -138,15 +138,15 @@ static int fpga_probe(struct platform_device *pdev)
static int fpga_suspend_noirq(struct device *dev)
{
- fpga_led_state = __raw_readw(&fpga->leds);
- __raw_writew(0xff, &fpga->leds);
+ fpga_led_state = readw_relaxed(&fpga->leds);
+ writew_relaxed(0xff, &fpga->leds);
return 0;
}
static int fpga_resume_noirq(struct device *dev)
{
- __raw_writew(~fpga_led_state, &fpga->leds);
+ writew_relaxed(~fpga_led_state, &fpga->leds);
return 0;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 21/23] ARM: OMAP4: sleep: byteswap data for big-endian
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (18 preceding siblings ...)
2013-11-16 0:01 ` [RFC 20/23] ARM: OMAP: debug-leds: " Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 22/23] ARM: OMAP4: sleep/smp: switch CPU to BE if compiled for BE Taras Kondratiuk
2013-11-16 0:01 ` [RFC 23/23] ARM: OMAP4: enable big endian support Taras Kondratiuk
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Tony Lindgren, Russell King,
linux-arm-kernel, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
Assembler functions defined in sleep44xx.S need to byteswap values
after read / before write from h/w register if code compiled in big
endian mode. Simple change to do 'rev x, x' before str instruction
and after ldr instruction that deals with h/w registers.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
arch/arm/mach-omap2/sleep44xx.S | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 9086ce0..8017016 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -12,6 +12,7 @@
#include <linux/linkage.h>
#include <asm/smp_scu.h>
#include <asm/memory.h>
+#include <asm/assembler.h>
#include <asm/hardware/cache-l2x0.h>
#include "omap-secure.h"
@@ -74,6 +75,7 @@ ENTRY(omap4_finish_suspend)
*/
bl omap4_get_sar_ram_base
ldr r9, [r0, #OMAP_TYPE_OFFSET]
+ARM_BE8(rev r9, r9)
cmp r9, #0x1 @ Check for HS device
bne skip_secure_l1_clean
mov r0, #SCU_PM_NORMAL
@@ -113,12 +115,14 @@ skip_secure_l1_clean:
bl omap4_get_sar_ram_base
mov r8, r0
ldr r9, [r8, #OMAP_TYPE_OFFSET]
+ARM_BE8(rev r9, r9)
cmp r9, #0x1 @ Check for HS device
bne scu_gp_set
mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
ands r0, r0, #0x0f
ldreq r0, [r8, #SCU_OFFSET0]
ldrne r0, [r8, #SCU_OFFSET1]
+ARM_BE8(rev r0, r0)
mov r1, #0x00
stmfd r13!, {r4-r12, r14}
ldr r12, =OMAP4_MON_SCU_PWR_INDEX
@@ -130,6 +134,7 @@ scu_gp_set:
ands r0, r0, #0x0f
ldreq r1, [r8, #SCU_OFFSET0]
ldrne r1, [r8, #SCU_OFFSET1]
+ARM_BE8(rev r1, r1)
bl omap4_get_scu_base
bl scu_power_mode
skip_scu_gp_set:
@@ -157,6 +162,7 @@ skip_scu_gp_set:
ands r5, r5, #0x0f
ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory.
+ARM_BE8(rev r0, r0)
cmp r0, #3
bne do_WFI
#ifdef CONFIG_PL310_ERRATA_727915
@@ -167,9 +173,11 @@ skip_scu_gp_set:
bl omap4_get_l2cache_base
mov r2, r0
ldr r0, =0xffff
+ARM_BE8(rev r0, r0)
str r0, [r2, #L2X0_CLEAN_INV_WAY]
wait:
ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
+ARM_BE8(rev r0, r0)
ldr r1, =0xffff
ands r0, r0, r1
bne wait
@@ -182,9 +190,11 @@ l2x_sync:
bl omap4_get_l2cache_base
mov r2, r0
mov r0, #0x0
+ARM_BE8(rev r0, r0)
str r0, [r2, #L2X0_CACHE_SYNC]
sync:
ldr r0, [r2, #L2X0_CACHE_SYNC]
+ARM_BE8(rev r0, r0)
ands r0, r0, #0x1
bne sync
#endif
@@ -216,6 +226,7 @@ do_WFI:
bl omap4_get_sar_ram_base
mov r8, r0
ldr r9, [r8, #OMAP_TYPE_OFFSET]
+ARM_BE8(rev r9, r9)
cmp r9, #0x1 @ Check for HS device
bne scu_gp_clear
mov r0, #SCU_PM_NORMAL
@@ -258,6 +269,7 @@ ENTRY(omap4_cpu_resume)
*/
ldr r8, =OMAP44XX_SAR_RAM_BASE
ldr r9, [r8, #OMAP_TYPE_OFFSET]
+ARM_BE8(rev r9, r9)
cmp r9, #0x1 @ Skip if GP device
bne skip_ns_smp_enable
mrc p15, 0, r0, c0, c0, 5
@@ -292,16 +304,19 @@ skip_ns_smp_enable:
*/
ldr r2, =OMAP44XX_L2CACHE_BASE
ldr r0, [r2, #L2X0_CTRL]
+ARM_BE8(rev r0, r0)
and r0, #0x0f
cmp r0, #1
beq skip_l2en @ Skip if already enabled
ldr r3, =OMAP44XX_SAR_RAM_BASE
ldr r1, [r3, #OMAP_TYPE_OFFSET]
+ARM_BE8(rev r1, r1)
cmp r1, #0x1 @ Check for HS device
bne set_gp_por
ldr r0, =OMAP4_PPA_L2_POR_INDEX
ldr r1, =OMAP44XX_SAR_RAM_BASE
ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+ARM_BE8(rev r4, r4)
adr r3, ppa_por_params
str r4, [r3, #0x04]
mov r1, #0x0 @ Process ID
@@ -313,11 +328,13 @@ skip_ns_smp_enable:
set_gp_por:
ldr r1, =OMAP44XX_SAR_RAM_BASE
ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+ARM_BE8(rev r0, r0)
ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
DO_SMC
set_aux_ctrl:
ldr r1, =OMAP44XX_SAR_RAM_BASE
ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
+ARM_BE8(rev r0, r0)
ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
DO_SMC
mov r0, #0x1
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 22/23] ARM: OMAP4: sleep/smp: switch CPU to BE if compiled for BE
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (19 preceding siblings ...)
2013-11-16 0:01 ` [RFC 21/23] ARM: OMAP4: sleep: byteswap data for big-endian Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
2013-11-16 0:01 ` [RFC 23/23] ARM: OMAP4: enable big endian support Taras Kondratiuk
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Tony Lindgren, Russell King,
linux-arm-kernel, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
If kernel operates in BE mode on device that has LE bootloader/ROM code,
we need to switch CPU to operate in BE mode before it will start to
access BE data. Generic secondary_startup function that is called from
OMAP specific secondary startup code will do the switch, but we need
to do it earlier because OMAP's secondary_startup code works with BE data.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
arch/arm/mach-omap2/omap-headsmp.S | 13 +++++++++++++
arch/arm/mach-omap2/sleep44xx.S | 6 ++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 75e9295..75c98d4 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -17,6 +17,7 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
#include "omap44xx.h"
@@ -58,6 +59,12 @@ hold: ldr r12,=0x103
bne hold
/*
+ * ROM code operates in little endian mode, when we get control we
+ * need to switch it back to big endian mode.
+ */
+ARM_BE8(setend be)
+
+ /*
* we've been released from the wait loop,secondary_stack
* should now contain the SVC stack for this core
*/
@@ -75,6 +82,12 @@ hold_2: ldr r12,=0x103
bne hold_2
/*
+ * ROM code operates in little endian mode, when we get control we
+ * need to switch it back to big endian mode.
+ */
+ARM_BE8(setend be)
+
+ /*
* GIC distributor control register has changed between
* CortexA9 r1pX and r2pX. The Control Register secure
* banked version is now composed of 2 bits:
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 8017016..f509dc5 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -260,6 +260,12 @@ ENDPROC(omap4_finish_suspend)
*/
ENTRY(omap4_cpu_resume)
/*
+ * ROM code operates in little endian mode, when we get control we
+ * need to switch it back to big endian mode.
+ */
+ARM_BE8(setend be)
+
+ /*
* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
* OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
* init and for CPU1, a secure PPA API provided. CPU0 must be ON
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread* [RFC 23/23] ARM: OMAP4: enable big endian support
2013-11-16 0:01 [RFC 00/23] OMAP4: big endian support and fixes Taras Kondratiuk
` (20 preceding siblings ...)
2013-11-16 0:01 ` [RFC 22/23] ARM: OMAP4: sleep/smp: switch CPU to BE if compiled for BE Taras Kondratiuk
@ 2013-11-16 0:01 ` Taras Kondratiuk
21 siblings, 0 replies; 44+ messages in thread
From: Taras Kondratiuk @ 2013-11-16 0:01 UTC (permalink / raw)
To: linux-omap
Cc: linaro-networking, Victor Kamensky, Tony Lindgren, Russell King,
linux-arm-kernel, linux-kernel
From: Victor Kamensky <victor.kamensky@linaro.org>
Previous patches fixed big endian issues in OMAP4 code,
so mark it as one that supports big endian
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
---
arch/arm/mach-omap2/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b5fb5f7..b5b19a3 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -48,6 +48,7 @@ config ARCH_OMAP4
select COMMON_CLK
select ARM_ERRATA_754322
select ARM_ERRATA_775420
+ select ARCH_SUPPORTS_BIG_ENDIAN
config SOC_OMAP5
bool "TI OMAP5"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 44+ messages in thread