[PATCH v1 0/5] add parallel NAND support for TI's new OMAPx and AMxx platforms

[PATCH v1 0/5] add parallel NAND support for TI's new OMAPx and AMxx platforms

[Pekon Gupta]

This patch-set adds and updates parallel NAND support on following TI platforms
 - AM335x (am335x-evm)
 - DRA7xx (dra7-evm
 - AM43xx (am43X-epos-evm)

In addition, following OMAP2+/GPMC patch is also added in this series as
it add checks DRA7xx and AM43xxx platforms for non-DT kernels.
	ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms


Minal Shah (1):
  ARM: dts: dra7: add support for parallel NAND flash

Pekon Gupta (4):
  ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms
    and ECC schemes
  ARM: dts: am335x-evm: NAND: update MTD partition table
  ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt
  ARM: dts: am43xx: add support for parallel NAND flash

 arch/arm/boot/dts/am335x-evm.dts     |  51 +++++++--------
 arch/arm/boot/dts/am4372.dtsi        |  24 +++++++
 arch/arm/boot/dts/am43x-epos-evm.dts | 107 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7-evm.dts       | 117 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi          |  20 ++++++
 arch/arm/boot/dts/omap3430-sdp.dts   |   3 +-
 arch/arm/mach-omap2/gpmc-nand.c      |  31 ++++++----
 7 files changed, 315 insertions(+), 38 deletions(-)

-- 
1.8.5.1.163.gd7aced9

[PATCH v1 1/5] ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes

[Pekon Gupta]

This patch
 - refactors gpmc_hwecc_bch_capable()
 - add checks for new platforms like dra7xx, am43xx
 - add checks for OMAP3 SoC, w.r.t. new ECC schemes spawned in following commit:
    commit ac65caf514ec3e55e8d3d510ee37f80dd97418fe
    ARM: OMAP2+: cleaned-up DT support of various ECC schemes

Signed-off-by: Pekon Gupta <pekon@ti.com>
---
 arch/arm/mach-omap2/gpmc-nand.c | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 174caec..4349e82 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -45,24 +45,31 @@ static struct platform_device gpmc_nand_device = {
 
 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
-	/* support only OMAP3 class */
-	if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
-		pr_err("BCH ecc is not supported on this CPU\n");
+	/* platforms which support all ECC schemes */
+	if (soc_is_am33xx() || cpu_is_omap44xx() ||
+		 soc_is_omap54xx() || soc_is_dra7xx())
+		return 1;
+
+	/* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
+	 * which require H/W based ECC error detection */
+	if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
+	    ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
+		 (ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
 		return 0;
-	}
 
 	/*
 	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
 	 * and AM33xx derivates. Other chips may be added if confirmed to work.
 	 */
-	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
-	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
-	    (!soc_is_am33xx())) {
-		pr_err("BCH 4-bit mode is not supported on this CPU\n");
+	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) &&
+	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))
 		return 0;
-	}
 
-	return 1;
+	/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
+	if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
+		return 1;
+	else
+		return 0;
 }
 
 /* This function will go away once the device-tree convertion is complete */
@@ -133,8 +140,10 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
 
 	gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 
-	if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
+	if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
+		dev_err(dev, "Unsupported NAND ECC scheme selected\n");
 		return -EINVAL;
+	}
 
 	err = platform_device_register(&gpmc_nand_device);
 	if (err < 0) {
-- 
1.8.5.1.163.gd7aced9

[PATCH v1 2/5] ARM: dts: am335x-evm: NAND: update MTD partition table

[Pekon Gupta]

This patch has following updates, specific to MTD/NAND DT
 - update MTD NAND partition table to keep compatibility between
   different boards and mainline u-boot.
 - prefix 'NAND.' in names of NAND device MTD partitions to differentiate them
   from other MTD device partitions (like NOR and QSPI)
               Partition_Name            Partition_Size
    /dev/mtd0  NAND.SPL                  1 block-size*
    /dev/mtd1  NAND.SPL.backup1          1 block-size*
    /dev/mtd2  NAND.SPL.backup2          1 block-size*
    /dev/mtd3  NAND.SPL.backup3          1 block-size*
    /dev/mtd5  NAND.u-boot-spl-os        2 block-size* [for falcon boot]
    /dev/mtd4  NAND.u-boot               1 MB
    /dev/mtd6  NAND.u-boot-env           1 block-size*
    /dev/mtd7  NAND.u-boot-env.backup1   1 block-size*
    /dev/mtd8  NAND.kernel               till 0xA00000
    /dev/mtd9  NAND.file-system          till end of device

* am335x-evm uses NAND device with block-size=128KiB

Signed-off-by: Pekon Gupta <pekon@ti.com>
---
 arch/arm/boot/dts/am335x-evm.dts | 48 +++++++++++++++++++++-------------------
 1 file changed, 25 insertions(+), 23 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 7e6c64e..17c3cc0 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -460,50 +460,52 @@
 		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
 		elm_id = <&elm>;
-
 		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
 		partition@0 {
-			label = "SPL1";
+			label = "NAND.SPL";
 			reg = <0x00000000 0x000020000>;
 		};
-
 		partition@1 {
-			label = "SPL2";
+			label = "NAND.SPL.backup1";
 			reg = <0x00020000 0x00020000>;
 		};
-
 		partition@2 {
-			label = "SPL3";
+			label = "NAND.SPL.backup2";
 			reg = <0x00040000 0x00020000>;
 		};
-
 		partition@3 {
-			label = "SPL4";
+			label = "NAND.SPL.backup3";
 			reg = <0x00060000 0x00020000>;
 		};
-
 		partition@4 {
-			label = "U-boot";
-			reg = <0x00080000 0x001e0000>;
+			label = "NAND.u-boot-spl";
+			reg = <0x00080000 0x00040000>;
 		};
-
 		partition@5 {
-			label = "environment";
-			reg = <0x00260000 0x00020000>;
+			label = "NAND.u-boot";
+			reg = <0x000C0000 0x00100000>;
 		};
-
 		partition@6 {
-			label = "Kernel";
-			reg = <0x00280000 0x00500000>;
+			label = "NAND.u-boot-env";
+			reg = <0x001C0000 0x00020000>;
 		};
-
 		partition@7 {
-			label = "File-System";
-			reg = <0x00780000 0x0F880000>;
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x001E0000 0x00020000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00200000 0x00800000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00A00000 0x0F600000>;
 		};
 	};
 };
-- 
1.8.5.1.163.gd7aced9

[PATCH v1 3/5] ARM: dts: AM33xx: updated default ECC scheme in nand-ecc-opt

[Pekon Gupta]

This patch updated MTD/NAND DT node binding to replace deprecated bindings
as per following commit.
    commit ac65caf514ec3e55e8d3d510ee37f80dd97418fe
    ARM: OMAP2+: cleaned-up DT support of various ECC schemes
    Also Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt

Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
 arch/arm/boot/dts/am335x-evm.dts   | 5 ++---
 arch/arm/boot/dts/omap3430-sdp.dts | 3 +--
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 17c3cc0..07d61bb 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -434,9 +434,9 @@
 	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
 	nand@0,0 {
 		reg = <0 0 0>; /* CS0, offset 0 */
-		nand-bus-width = <8>;
 		ti,nand-ecc-opt = "bch8";
-		gpmc,device-nand = "true";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <8>;
 		gpmc,device-width = <1>;
 		gpmc,sync-clk-ps = <0>;
 		gpmc,cs-on-ns = <0>;
@@ -460,7 +460,6 @@
 		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
-		elm_id = <&elm>;
 		/* MTD partition table */
 		/* All SPL-* partitions are sized to minimal length
 		 * which can be independently programmable. For
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 281914e..d48c085 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -103,9 +103,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <1 0 0x08000000>;
+		ti,nand-ecc-opt = "ham1";
 		nand-bus-width = <8>;
-
-		ti,nand-ecc-opt = "sw";
 		gpmc,cs-on-ns = <0>;
 		gpmc,cs-rd-off-ns = <36>;
 		gpmc,cs-wr-off-ns = <36>;
-- 
1.8.5.1.163.gd7aced9

[PATCH v1 4/5] ARM: dts: dra7: add support for parallel NAND flash

[Pekon Gupta]

From: Minal Shah <minal.shah@ti.com>

DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
	On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
	So following board settings are required for NAND device detection:
	SW5.9 (GPMC_WPN) = LOW
	SW5.1 (NAND_BOOTn) = HIGH

Signed-off-by: Minal Shah <minal.shah@ti.com>
Signed-off-by: Pekon Gupta <pekon@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts | 117 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi    |  20 +++++++
 2 files changed, 137 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..81c5f7f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,37 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	nand_flash_x16: nand_flash_x16 {
+		/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+		 * So NAND flash requires following switch settings:
+		 * SW5.9 (GPMC_WPN) = LOW
+		 * SW5.1 (NAND_BOOTn) = HIGH */
+		pinctrl-single,pins = <
+			0x0 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad0	*/
+			0x4 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad1	*/
+			0x8 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad2	*/
+			0xc 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad3	*/
+			0x10 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad4	*/
+			0x14 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad5	*/
+			0x18 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad6	*/
+			0x1c 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad7	*/
+			0x20 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad8	*/
+			0x24 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad9	*/
+			0x28 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad10	*/
+			0x2c 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad11	*/
+			0x30 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad12	*/
+			0x34 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad13	*/
+			0x38 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad14	*/
+			0x3c 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad15	*/
+			0xD8 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_wait0	*/
+			0xCC 	0x0 	/* (PIN_OUTPUT	   | MUX_MODE0)	gpmc_wen	*/
+			0xB4 	0x0	/* (PIN_OUTPUT | MUX_MODE0)	gpmc_csn0	*/
+			0xC4 	0x0	/* (PIN_OUTPUT 	   | MUX_MODE0)	gpmc_advn_ale */
+			0xC8 	0x0	/* (PIN_OUTPUT	   | MUX_MODE0)	gpmc_oen_ren	 */
+			0xD0 	0x0	/* (PIN_OUTPUT 	   | MUX_MODE0)	gpmc_be0n_cle */
+		>;
+	};
 };
 
 &i2c1 {
@@ -273,3 +304,89 @@
 &cpu0 {
 	cpu0-supply = <&smps123_reg>;
 };
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_flash_x16>;
+	ranges = <0 0 0x08000000 0x10000000>;
+	nand@0,0 {
+		reg = <0 0 0>;
+		ti,nand-ecc-opt = "bch8";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <40>;
+		gpmc,cs-wr-off-ns = <40>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <30>;
+		gpmc,adv-wr-off-ns = <30>;
+		gpmc,we-on-ns = <5>;
+		gpmc,we-off-ns = <25>;
+		gpmc,oe-on-ns = <2>;
+		gpmc,oe-off-ns = <20>;
+		gpmc,access-ns = <20>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,rd-cycle-ns = <40>;
+		gpmc,wr-cycle-ns = <40>;
+		gpmc,wait-on-read = "true";
+		gpmc,wait-on-write = "true";
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x000020000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00020000 0x00020000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00040000 0x00020000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x00060000 0x00020000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot";
+			reg = <0x000C0000 0x00100000>;
+		};
+		partition@6 {
+			label = "NAND.u-boot-env";
+			reg = <0x001C0000 0x00020000>;
+		};
+		partition@7 {
+			label = "NAND.u-boot-env";
+			reg = <0x001E0000 0x00020000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00200000 0x00800000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00A00000 0x0F600000>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1fd75aa..5965bc3 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -621,6 +621,26 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		elm: elm@48078000 {
+			compatible = "ti,am3352-elm";
+			reg = <0x48078000 0x2000>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "elm";
+			status = "disabled";
+		};
+
+		gpmc: gpmc@50000000 {
+			compatible = "ti,am3352-gpmc";
+			ti,hwmods = "gpmc";
+			reg = <0x50000000 0x2000>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			gpmc,num-cs = <8>;
+			gpmc,num-waitpins = <2>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
 	};
 };
 
-- 
1.8.5.1.163.gd7aced9

[PATCH v1 5/5] ARM: dts: am43xx: add support for parallel NAND flash

[Pekon Gupta]

This patch:
 - enables GPMC h/w and ELM h/w engine for AM43xx devices (am4372.dtsi)
 - adds pinmux and DT node for Micron 4K-paged x8 NAND device (MT29F4G08AB)
   present on following boards:

   am43x-epos-evm:
	On this board, NAND Flash control lines are muxed with QSPI, Thus only
        one of the two can be used at a time. Selection is controlled by:
        (a) dynamically driving following GPIO pin from software
            GPMC_A0(GPIO) == 0 NAND is selected (default)
            GPMC_A0(GPIO) == 1 eMMC is selected

Signed-off-by: Pekon Gupta <pekon@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi        |  24 ++++++++
 arch/arm/boot/dts/am43x-epos-evm.dts | 107 +++++++++++++++++++++++++++++++++++
 2 files changed, 131 insertions(+)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c6bd4d9..489a4ab 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -689,6 +689,30 @@
 			       <&edma 11>;
 			dma-names = "tx", "rx";
 		};
+
+		elm: elm@48080000 {
+			compatible = "ti,am3352-elm";
+			reg = <0x48080000 0x2000>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "elm";
+			clocks = <&l4ls_gclk>;
+			clock-names = "fck";
+			status = "disabled";
+		};
+
+		gpmc: gpmc@50000000 {
+			compatible = "ti,am3352-gpmc";
+			ti,hwmods = "gpmc";
+			clocks = <&l3s_gclk>;
+			clock-names = "fck";
+			reg = <0x50000000 0x2000>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			gpmc,num-cs = <7>;
+			gpmc,num-waitpins = <2>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
 	};
 };
 
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c..15aa708 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -79,6 +79,27 @@
 				0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 			>;
 		};
+
+		nand_flash_x8: nand_flash_x8 {
+			pinctrl-single,pins = <
+				0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a0.SELQSPIorNAND/GPIO */
+				0x0  (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+				0x4  (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+				0x8  (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+				0xc  (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+				0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+				0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+				0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+				0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+				0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+				0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
+				0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+				0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+				0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+				0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+				0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+			>;
+		};
 	};
 
 	matrix_keypad: matrix_keypad@0 {
@@ -184,3 +205,89 @@
 &gpio3 {
 	status = "okay";
 };
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_flash_x8>;
+	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+	nand@0,0 {
+		reg = <0 0 0>; /* CS0, offset 0 */
+		ti,nand-ecc-opt = "bch8";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <8>;
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
+		gpmc,cs-wr-off-ns = <40>;
+		gpmc,adv-on-ns = <0>;  /* cs-on-ns */
+		gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
+		gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
+		gpmc,we-on-ns = <0>;   /* cs-on-ns */
+		gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
+		gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
+		gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
+		gpmc,access-ns = <30>; /* tCEA + 4*/
+		gpmc,rd-cycle-ns = <40>;
+		gpmc,wr-cycle-ns = <40>;
+		gpmc,wait-on-read = "true";
+		gpmc,wait-on-write = "true";
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x000C0000 0x00040000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00100000 0x00080000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot";
+			reg = <0x00180000 0x00100000>;
+		};
+		partition@6 {
+			label = "NAND.u-boot-env";
+			reg = <0x00280000 0x00040000>;
+		};
+		partition@7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x002C0000 0x00040000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00300000 0x00700000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00800000 0x1F600000>;
+		};
+	};
+};
-- 
1.8.5.1.163.gd7aced9

RE: [PATCH v1 0/5] add parallel NAND support for TI's new OMAPx and AMxx platforms

[Gupta, Pekon]

Hi Benoit, Tony,
 
>From: Gupta, Pekon
>
>This patch-set adds and updates parallel NAND support on following TI platforms
> - AM335x (am335x-evm)
> - DRA7xx (dra7-evm
> - AM43xx (am43X-epos-evm)
>
>In addition, following OMAP2+/GPMC patch is also added in this series as
>it add checks DRA7xx and AM43xxx platforms for non-DT kernels.
>	ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms
>
Please let me know, if this patch-set is in acceptable state,
Or should I rebase it against any specific branch at your side ?


with regards, pekon

Re: [PATCH v1 0/5] add parallel NAND support for TI's new OMAPx and AMxx platforms

[Tony Lindgren]

* Gupta, Pekon <pekon@ti.com> [140212 20:30]:
> Hi Benoit, Tony,
>  
> >From: Gupta, Pekon
> >
> >This patch-set adds and updates parallel NAND support on following TI platforms
> > - AM335x (am335x-evm)
> > - DRA7xx (dra7-evm
> > - AM43xx (am43X-epos-evm)
> >
> >In addition, following OMAP2+/GPMC patch is also added in this series as
> >it add checks DRA7xx and AM43xxx platforms for non-DT kernels.
> >	ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms
> >
> Please let me know, if this patch-set is in acceptable state,
> Or should I rebase it against any specific branch at your side ?

Thanks applying all except 4/5 into omap-for-v3.15/dt. Patch 4
should be just updated for the macros, I'll comment on that
separately.

Regards,

Tony

Re: [PATCH v1 4/5] ARM: dts: dra7: add support for parallel NAND flash

[Tony Lindgren]

* Pekon Gupta <pekon@ti.com> [140205 05:31]:
> From: Minal Shah <minal.shah@ti.com>
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -93,6 +93,37 @@
>  			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>  		>;
>  	};
> +
> +	nand_flash_x16: nand_flash_x16 {
> +		/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
> +		 * So NAND flash requires following switch settings:
> +		 * SW5.9 (GPMC_WPN) = LOW
> +		 * SW5.1 (NAND_BOOTn) = HIGH */
> +		pinctrl-single,pins = <
> +			0x0 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad0	*/
> +			0x4 	0x70000 /* (PIN_INPUT | MUX_MODE0)	gpmc_ad1	*/
...

Can you guys please update this one to use the macros in
arch/arm/boot/dts/include/dt-bindings/pinctrl/omap.h?

Preferrably the new DRA7XX_CORE_IOPAD and friends macros.
I've picked up the other patches in this series already.

Regards,

Tony