Re: [RFC PATCH] clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock

[Mike Turquette <mturquette@linaro.org>]

Quoting Tero Kristo (2014-06-17 01:23:31)
> On 06/17/2014 11:19 AM, Paul Walmsley wrote:
> > On Tue, 17 Jun 2014, Tero Kristo wrote:
> >
> >> I am fine with this approach, as it seems pretty much all the other mux-clock
> >> users are setting this flag also. The TI clocks have had this way of using mux
> >> clocks from the legacy times... might just be a design flaw.
> >
> > The non-CCF clock framework never automatically switched parents on rate
> > changes, AFAIK.
> 
> That might be true yea, so this must have been introduced with CCF.

Correct, which is why the flag exists.

> 
> > The only case that approached this was with PLLs.  PLLs would
> > automatically be placed into bypass if the PLL rate was set to the bypass
> > rate.
> 
> Someone could argue that this is rather strange approach also and would 
> be better to use some other API for the purpose.

I have always liked this feature. I had a hack patch on the list a long
time ago for testing bypass mode on the OMAP4 MPU when set to 400MHZ or
something like that (and chained from dpll_core I think...).

The point is to get the rate you ask for when you call clk_set_rate. The
method by which the PLL achieves that rate isn't really important, so
long as you have glitchless clocks (which OMAP's PRCM does).

Regards,
Mike

> 
> .Tero
>