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From: Nishanth Menon <nm@ti.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	Benoit Cousson <bcousson@baylibre.com>,
	Tony Lindgren <tony@atomide.com>,
	Santosh Shilimkar <ssantosh@kernel.org>,
	Shawn Guo <shawn.guo@linaro.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	Kukjin Kim <kgene.kim@samsung.com>,
	Simon Horman <horms@verge.net.au>,
	Magnus Damm <magnus.damm@gmail.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Michal Simek <michal.simek@xilinx.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, linux-omap@vger.kernel.org
Subject: Re: [PATCH v2 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains
Date: Thu, 8 Jan 2015 09:20:59 -0600	[thread overview]
Message-ID: <20150108152059.GB24705@kahuna> (raw)
In-Reply-To: <1420652576-22309-9-git-send-email-marc.zyngier@arm.com>

On 17:42-20150107, Marc Zyngier wrote:
a few more minor comments follow:

[..]
> --- a/drivers/irqchip/irq-crossbar.c
> +++ b/drivers/irqchip/irq-crossbar.c
[..]
> @@ -33,6 +34,7 @@
>   * @write: register write function pointer
>   */
>  struct crossbar_device {
> +	raw_spinlock_t lock;

^^ kernel doc missing.

[...]
> +static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
> +				 unsigned int nr_irqs, void *data)
>  {
> -	if (needs_crossbar_write(hw))
> -		cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
> +	struct of_phandle_args *args = data;
> +	irq_hw_number_t hwirq;
> +	int i;
> +
> +	if (args->args_count != 3)
> +		return -EINVAL;	/* Not GIC compliant */
> +	if (args->args[0] != 0)
> +		return -EINVAL;	/* No PPI should point to this domain */
> +
> +	hwirq = args->args[1];
> +	if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
> +		return -EINVAL;	/* Can't deal with this */
> +
> +	for (i = 0; i < nr_irqs; i++) {
> +		int err = allocate_gic_irq(d, virq + i, hwirq + i);

^^ add a blank line here?

> +		if (err)
> +			return err;
> +
> +		irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
> +					      &crossbar_chip, NULL);
> +	}
>  
>  	return 0;
>  }
>  
>  /**
> - * crossbar_domain_unmap - unmap a crossbar<->irq connection
> + * crossbar_domain_free - unmap/free a crossbar<->irq connection
>   * @d: domain of irq to unmap

      ^^ should be @domain?

> - * @irq: virq number
> + * @virq: virq number
> + * @nr_irqs: number of irqs to free
>   *
>   * We do not maintain a use count of total number of map/unmap
>   * calls for a particular irq to find out if a irq can be really
> @@ -117,14 +144,19 @@ static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
>   * after which irq is anyways unusable. So an explicit map has to be called
>   * after that.
>   */
> -static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
> +static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
> +				 unsigned int nr_irqs)
>  {
> -	irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
> +	int i;
>  
> -	if (needs_crossbar_write(hw)) {
> -		cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
> -		cb->write(hw - GIC_IRQ_START, cb->safe_map);
> +	raw_spin_lock(&cb->lock);
> +	for (i = 0; i < nr_irqs; i++) {
> +		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);

^^ Add a blank line here.

-- 
Regards,
Nishanth Menon

  parent reply	other threads:[~2015-01-08 15:22 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-07 17:42 [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 01/21] ARM: tegra: irq: nuke leftovers from non-DT support Marc Zyngier
2015-01-08  8:56   ` Thierry Reding
2015-01-07 17:42 ` [PATCH v2 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller Marc Zyngier
2015-01-08 10:13   ` Thierry Reding
2015-01-08 15:06   ` Nishanth Menon
2015-01-10 12:28     ` Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 03/21] ARM: tegra: skip gic_arch_extn setup if DT has a LIC node Marc Zyngier
2015-01-08 10:16   ` Thierry Reding
2015-01-07 17:42 ` [PATCH v2 04/21] ARM: tegra: update DTs to expose legacy interrupt controller Marc Zyngier
2015-01-08 10:41   ` Thierry Reding
2015-01-10 12:37     ` Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 05/21] DT: tegra: add binding for the " Marc Zyngier
2015-01-08 10:51   ` Thierry Reding
2015-01-08 15:12   ` Nishanth Menon
2015-01-07 17:42 ` [PATCH v2 06/21] ARM: tegra: remove old LIC support Marc Zyngier
2015-01-08 11:29   ` Thierry Reding
2015-01-10 12:43     ` Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 07/21] genirq: Add irqchip_set_wake_parent Marc Zyngier
2015-01-08 15:15   ` Nishanth Menon
2015-01-10 12:46     ` Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains Marc Zyngier
2015-01-08 14:39   ` Nishanth Menon
2015-01-10 12:59     ` Marc Zyngier
2015-01-08 15:20   ` Nishanth Menon [this message]
2015-01-07 17:42 ` [PATCH v2 09/21] DT: update ti,irq-crossbar binding Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 10/21] irqchip: GIC: get rid of routable domain Marc Zyngier
2015-01-08 16:13   ` Nishanth Menon
2015-01-07 17:42 ` [PATCH v2 11/21] DT: arm,gic: kill arm,routable-irqs Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 12/21] ARM: omap: convert wakeupgen to stacked domains Marc Zyngier
2015-01-08 16:44   ` Nishanth Menon
2015-01-10 13:17     ` Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 13/21] DT: omap4/5: add binding for the wake-up generator Marc Zyngier
2015-01-08 16:52   ` Nishanth Menon
2015-01-10 13:22     ` Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 14/21] ARM: imx6: convert GPC to stacked domains Marc Zyngier
2015-01-08 16:57   ` Nishanth Menon
2015-01-09 17:40   ` Stefan Agner
2015-01-10 13:34     ` Marc Zyngier
2015-01-10 14:16       ` Stefan Agner
2015-01-07 17:42 ` [PATCH v2 15/21] ARM: exynos4/5: convert pmu wakeup " Marc Zyngier
2015-01-08 16:58   ` Nishanth Menon
2015-01-07 17:42 ` [PATCH v2 16/21] DT: exynos: update PMU binding Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 17/21] irqchip: gic: add an entry point to set up irqchip flags Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 18/21] ARM: shmobile: remove use of gic_arch_extn.irq_set_wake Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 19/21] ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 20/21] ARM: zynq: " Marc Zyngier
2015-01-07 17:42 ` [PATCH v2 21/21] irqchip: gic: Drop support for gic_arch_extn Marc Zyngier
2015-01-07 18:45 ` [PATCH v2 00/21] irqchip: gic: killing gic_arch_extn and co, slowly santosh shilimkar
2015-01-08  3:31 ` Nishanth Menon
2015-01-10 13:45 ` Marc Zyngier
2015-01-12 14:14 ` Rob Herring
2015-01-12 15:39   ` Marc Zyngier

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