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From: Mike Turquette <mturquette@linaro.org>
To: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>,
	Tomeu Vizoso <tomeu.vizoso@collabora.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-kernel@vger.kernel.org, t-kristo@ti.com,
	linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v13 3/6] clk: Make clk API return per-user struct clk instances
Date: Mon, 02 Feb 2015 09:32:28 -0800	[thread overview]
Message-ID: <20150202173228.421.87108@quantum> (raw)
In-Reply-To: <20150202170458.GB9418@atomide.com>

Quoting Tony Lindgren (2015-02-02 09:04:59)
> * Mike Turquette <mturquette@linaro.org> [150201 13:27]:
> > Quoting Tomeu Vizoso (2015-01-23 03:03:30)
> > > Moves clock state to struct clk_core, but takes care to change as little API as
> > > possible.
> > > 
> > > struct clk_hw still has a pointer to a struct clk, which is the
> > > implementation's per-user clk instance, for backwards compatibility.
> > > 
> > > The struct clk that clk_get_parent() returns isn't owned by the caller, but by
> > > the clock implementation, so the former shouldn't call clk_put() on it.
> > > 
> > > Because some boards in mach-omap2 still register clocks statically, their clock
> > > registration had to be updated to take into account that the clock information
> > > is stored in struct clk_core now.
> > 
> > Tero, Paul & Tony,
> > 
> > Tomeu's patch unveils a problem with omap3_noncore_dpll_enable and
> > struct dpll_data, namely this snippet from
> > arch/arm/mach-omap2/dpll3xxx.c:
> > 
> >         parent = __clk_get_parent(hw->clk);
> > 
> >         if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
> >                 WARN(parent != dd->clk_bypass,
> >                                 "here0, parent name is %s, bypass name is %s\n",
> >                                 __clk_get_name(parent), __clk_get_name(dd->clk_bypass));
> >                 r = _omap3_noncore_dpll_bypass(clk);
> >         } else {
> >                 WARN(parent != dd->clk_ref,
> >                                 "here1, parent name is %s, ref name is %s\n",
> >                                 __clk_get_name(parent), __clk_get_name(dd->clk_ref));
> >                 r = _omap3_noncore_dpll_lock(clk);
> >         }
> > 
> > struct dpll_data has members clk_ref and clk_bypass which are struct clk
> > pointers. This was always a bit of a violation of the clk.h contract
> > since drivers are not supposed to deref struct clk pointers. Now that we
> > generate unique pointers for each call to clk_get (clk_ref & clk_bypass
> > are populated by of_clk_get in ti_clk_register_dpll) then the pointer
> > comparisons above will never be equal (even if they resolve down to the
> > same struct clk_core). I added the verbose traces to the WARNs above to
> > illustrate the point: the names are always the same but the pointers
> > differ.
> > 
> > AFAICT this doesn't break anything, but booting on OMAP3+ results in
> > noisy WARNs.
> 
> Also on at least omap4 like I posted.

Right, hence the + after OMAP3 ;-)

> So sounds like the check for
> WARN is wrong but harmless. Paul & Tero, what do you want to do
> about that?

I would be fine to simply silence the WARNs since we're so closed to the
merge window and then revisit it with a proper fix. Of course the ideal
solution would be to convert the pointer comparison scheme to one using
parent_index.

Regards,
Mike

>  
> > I think the correct fix is to replace clk_bypass and clk_ref pointers
> > with a simple integer parent_index. In fact we already have this index.
> > See how the pointers are populated in ti_clk_register_dpll:
> > 
> > 
> >         dd->clk_ref = of_clk_get(node, 0);
> >         dd->clk_bypass = of_clk_get(node, 1);
> > 
> > Tony, the same problem affects the FAPLL code which copy/pastes some of
> > the DPLL code.
> > 
> > Thoughts?
> 
> Not seeing these warnings with dm186x as fapll.c does not use
> dpll3xxx.c. This is because of the way the PLL's child synthesizers
> need to also access the PLL registers for power and bypass mode.
> 
> Not related to the $subject bug, but to me it seems that we could
> possibly have Linux generic PLL code if we add support for
> parent_in_bypass_mode in addition to the parent_rate. This is because
> the PLL can in theory generate the same rate both in bypass mode and
> regular mode so parent_rate is not enough to tell it to the child
> synthesizers. Not sure how the PLL registers enabling and disabling
> it's children should be handled, maybe regmap would work there.
> 
> Regards,
> 
> Tony

  reply	other threads:[~2015-02-02 17:32 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1422011024-32283-1-git-send-email-tomeu.vizoso@collabora.com>
2015-01-23 11:03 ` [PATCH v13 3/6] clk: Make clk API return per-user struct clk instances Tomeu Vizoso
2015-02-01 21:24   ` Mike Turquette
2015-02-02 17:04     ` Tony Lindgren
2015-02-02 17:32       ` Mike Turquette [this message]
2015-02-02 19:32     ` Tero Kristo
2015-02-02 20:44       ` Tony Lindgren
2015-02-02 22:48         ` Mike Turquette
2015-02-02 23:11           ` Tony Lindgren
2015-02-02 22:41       ` Mike Turquette
2015-02-02 22:52         ` Stephen Boyd
2015-02-03  7:03         ` Tomeu Vizoso
2015-02-03  8:46           ` Tero Kristo
2015-02-03 15:22             ` Tony Lindgren
2015-02-02 20:45     ` Stephen Boyd
2015-02-02 21:31       ` Julia Lawall
2015-02-02 22:35         ` Stephen Boyd
2015-02-02 22:50           ` Mike Turquette
2015-02-03 16:04             ` [Cocci] " Quentin Lambert
2015-02-04 23:26               ` Stephen Boyd
2015-02-05 15:45                 ` Quentin Lambert
2015-02-05 16:02                   ` Quentin Lambert
2015-02-06  1:49                     ` Stephen Boyd
2015-02-06  2:15                   ` Stephen Boyd
2015-02-06  9:01                     ` Quentin Lambert
2015-02-06  9:12                       ` Julia Lawall
2015-02-06 17:15                         ` Stephen Boyd
2015-02-17 22:01                     ` Stephen Boyd
2015-03-12 17:20                       ` Sebastian Andrzej Siewior
2015-03-12 19:43                         ` Stephen Boyd
2015-03-13  3:29                           ` Shawn Guo
2015-03-13  8:20                             ` Sebastian Andrzej Siewior
2015-03-13 13:42                               ` Shawn Guo
2015-03-13 17:42                             ` Stephen Boyd
2015-02-05 19:44   ` Sylwester Nawrocki
2015-02-05 20:06     ` Sylwester Nawrocki
2015-02-05 20:07     ` Stephen Boyd
2015-02-05 22:14       ` Stephen Boyd
2015-02-06  0:42         ` Russell King - ARM Linux
2015-02-06  1:35           ` Stephen Boyd
2015-02-06 13:39             ` Russell King - ARM Linux
2015-02-06 19:30               ` Stephen Boyd
2015-02-06 19:37                 ` Russell King - ARM Linux
2015-02-06 19:41                   ` Stephen Boyd
2015-02-19 21:32                 ` Mike Turquette
2015-02-24 14:08                   ` Russell King - ARM Linux
2015-02-25  2:18                     ` Mike Turquette
2015-01-23 11:03 ` [PATCH v13 4/6] clk: Add rate constraints to clocks Tomeu Vizoso
2015-01-29 13:31   ` Geert Uytterhoeven
2015-01-29 19:13     ` Stephen Boyd
2015-01-31  1:31       ` Stephen Boyd
2015-01-31 18:36         ` Tomeu Vizoso
2015-02-01 22:18           ` Mike Turquette
2015-02-02  7:59             ` Geert Uytterhoeven
2015-02-02 16:12               ` Tony Lindgren
2015-02-02 17:46                 ` Mike Turquette
2015-02-02 17:49                   ` Russell King - ARM Linux
2015-02-02 19:21                   ` Tony Lindgren
2015-02-02 20:47                     ` Tony Lindgren

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