Re: [PATCH v2 1/4] ARM: dts: dra7: Add dt node for the sycon pcie

[Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>]

* Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org> [151012 15:09]:
> Hi,
> 
> On Tuesday 13 October 2015 03:33 AM, Tony Lindgren wrote:
> > * Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org> [151012 14:50]:
> >> Hi Tony,
> >>
> >> On Tuesday 13 October 2015 02:51 AM, Tony Lindgren wrote:
> >>> * Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org> [150915 06:37]:
> >>>> Add new device tree node for the control module register space where
> >>>> PCIe registers are present.
> >>>>
> >>>> Signed-off-by: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> >>>> ---
> >>>>  arch/arm/boot/dts/dra7.dtsi |    5 +++++
> >>>>  1 file changed, 5 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> >>>> index 5d65db9..0769b5d 100644
> >>>> --- a/arch/arm/boot/dts/dra7.dtsi
> >>>> +++ b/arch/arm/boot/dts/dra7.dtsi
> >>>> @@ -154,6 +154,11 @@
> >>>>  					compatible = "syscon";
> >>>>  					reg = <0x1c04 0x0020>;
> >>>>  				};
> >>>> +
> >>>> +				scm_conf_pcie: tisyscon@1c24 {
> >>>> +					compatible = "syscon";
> >>>> +					reg = <0x1c24 0x0024>;
> >>>> +				};
> >>>>  			};
> >>>>  
> >>>>  			cm_core_aon: cm_core_aon@5000 {
> >>>
> >>>
> >>> Why don't you just extend the existing scm_conf1 area? This is not all pcie
> >>> specific for scm_conf_pcie, at least for PLLEN_CONTROL, RMII_CLK_SETTING
> >>> and MUXSEL_32K_CLKIN.
> >>
> >> scm_conf_pcie has only PCIe registers (it starts at 0x4A003C24).
> >> PLLEN_CONTROL and others are at 0x4A003C14 as per
> >> DRA75x_DRA74x_SR1.1_NDA_TRM_vW.
> > 
> > Oh sorry I guess I was looking at a wrong address then.
> > 
> >> Since PCIe itself has a bunch of registers for itself, thought of
> >> creating a separate dt node. But I can extend scm_conf1 area.
> > 
> > Why not just ioremap them then? Do these need to be shared with
> > some other driver?
> 
> yeah, some are used by PCIe controller driver and some are used by PCIe
> PHY driver.

OK makes sense to me then.

Thanks,

Tony
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