From: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
To: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>,
nm-l0cyMroinI0@public.gmane.org,
Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>
Subject: Re: [PATCH] ARM: dts: DRA7: change address-cells and size-cells
Date: Mon, 29 Feb 2016 15:01:46 -0800 [thread overview]
Message-ID: <20160229230146.GT13417@atomide.com> (raw)
In-Reply-To: <1456308664-28308-1-git-send-email-lokeshvutla-l0cyMroinI0@public.gmane.org>
* Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org> [160224 02:14]:
> DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
> represent this in memory dt node, the address-cells and size cells
> should be 2. So, changing the address-cells and size-cells to 2 and
> updating the memory nodes accordingly.
Applying into omap-for-v4.6/dt thanks.
Tony
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prev parent reply other threads:[~2016-02-29 23:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-24 10:11 [PATCH] ARM: dts: DRA7: change address-cells and size-cells Lokesh Vutla
[not found] ` <1456308664-28308-1-git-send-email-lokeshvutla-l0cyMroinI0@public.gmane.org>
2016-02-26 19:11 ` Tony Lindgren
[not found] ` <20160226191127.GE13417-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
2016-02-29 8:44 ` Lokesh Vutla
[not found] ` <56D40505.8020702-l0cyMroinI0@public.gmane.org>
2016-02-29 18:16 ` Tony Lindgren
[not found] ` <20160229181606.GM13417-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
2016-02-29 20:45 ` Arnd Bergmann
2016-02-29 21:32 ` Tony Lindgren
2016-02-29 23:01 ` Tony Lindgren [this message]
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