[PATCH 0/6] Init Clock frequences for accelerators

[PATCH 0/6] Init Clock frequences for accelerators

[Suman Anna]

Hi Tony,

The following series configures the initial frequencies for the required
DPLLs and corresponding output divider clocks used by various remoteproc
accelerators (DSP, IVAHD) on OMAP4, OMAP5 & DRA7xx/AM57xx SoCs and the
GPU on DRA7xx/AM57xx SoCs. All these devices require Adaptive Voltage
Scaling (AVS) to be programmed at all OPPs at boot time, which is
programmed in the bootloader. Furthermore, DVFS is not supported on
these domains implying a one-time OPP clock frequency setup.

IPUs (except for IPU1 on DRA7) being in CORE domain, are clocked by the
CORE DPLL and do not require any specific programming. The DPLLs clock
rates are configured for OPP_NOM rates which is what the bootloader
configures the corresponding voltage domains for by default. The design
follows the assigned-clock parents/rates rules for clock providers in
the generic clock bindings.

Newer U-boots of 2017.01 and later can also add/update these properties
if a different OPP is required. The default is OPP_NOM, and higher OPPs
can be supported through configuration of the bootloader. This series
sets up the DPLLs for OPP_NOM and be agnostic of the bootloaders w.r.t
the clock frequences (like when using older U-Boots).

MPU domain is not affected as it supports DVFS and different OPPs can
be supported through the appropriate kernel framework.

I have tested the patches using 4.12-rc4, but they can be applied on
the 4.12-rc1 base just fine.

regards
Suman

Subhajit Paul (1):
  ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks

Suman Anna (5):
  ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates
  ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates
  ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL
  ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates
  ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates

 arch/arm/boot/dts/dra7xx-clocks.dtsi   | 20 ++++++++++++++++++++
 arch/arm/boot/dts/omap44xx-clocks.dtsi |  6 ++++++
 arch/arm/boot/dts/omap54xx-clocks.dtsi |  6 ++++++
 3 files changed, 32 insertions(+)

-- 
2.12.0

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[PATCH 1/6] ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates

[Suman Anna]

The IVA DPLL is not an essential DPLL for the functionality of a
bootloader and is usually not configured (e.g. older u-boots configure
it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer
than 2014.01 do not even have an option), and this results in incorrect
operating frequencies when trying to use a DSP or IVAHD, whose root
clocks are derived from this DPLL. Use the DT standard properties
"assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock
rate and the rates for its derivative clocks at boot time to properly
initialize/lock this DPLL. The DPLL will automatically transition
into a low-power stop mode when the associated output clocks are
not utilized or gated automatically.

The reset values of the dividers M4 & M5 (functional clocks for DSP and
IVAHD respectively) are identical to each other, but are different at
each OPP. The reset values also do not match a specific OPP. So, the
derived output clocks from the IVA DPLL have to be initialized as well
to avoid initializing these divider outputs to incorrect frequencies.

The clock rates are chosen based on the OPP100 values as defined in the
OMAP4430 ES2.x Public TRM vAP, section "3.6.3.8.7 DPLL_IVA Preferred
Settings". The DPLL locked frequency is 1862.4 MHz (value for
DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of
this value.

Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37fbaa7..9cb205b87835 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -357,6 +357,8 @@
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
 		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+		assigned-clocks = <&dpll_iva_ck>;
+		assigned-clock-rates = <931200000>;
 	};
 
 	dpll_iva_x2_ck: dpll_iva_x2_ck {
@@ -374,6 +376,8 @@
 		reg = <0x01b8>;
 		ti,index-starts-at-one;
 		ti,invert-autoidle-bit;
+		assigned-clocks = <&dpll_iva_m4x2_ck>;
+		assigned-clock-rates = <465600000>;
 	};
 
 	dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
@@ -385,6 +389,8 @@
 		reg = <0x01bc>;
 		ti,index-starts-at-one;
 		ti,invert-autoidle-bit;
+		assigned-clocks = <&dpll_iva_m5x2_ck>;
+		assigned-clock-rates = <266100000>;
 	};
 
 	dpll_mpu_ck: dpll_mpu_ck@160 {
-- 
2.12.0

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[PATCH 3/6] ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL

[Suman Anna]

The IPU1 functional clock is actually the output of a mux clock,
ipu1_gfclk_mux. The mux clock is sourced by default from the
DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency
(361 MHz) for the IPU1 functional clock on platforms where ABE_DPLL
is configured properly. Reconfigure the mux clock to be sourced from
CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so that both the IPU1
and IPU2 are running from the same clock and clocked at the same
nominal frequency of 425 MHz.

This also ensures that IPU1 functional clock is always configured
properly and becomes independent of the state of the ABE DPLL on
all boards.

Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3330738e4c6e..cfaf27215901 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -791,6 +791,8 @@
 		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 		ti,bit-shift = <24>;
 		reg = <0x0520>;
+		assigned-clocks = <&ipu1_gfclk_mux>;
+		assigned-clock-parents = <&dpll_core_h22x2_ck>;
 	};
 
 	mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
-- 
2.12.0

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[PATCH 5/6] ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates

[Suman Anna]

The IVA DPLL in DRA7xx provides the output clocks for only the IVAHD
subsystem in DRA7xx as compared to previous OMAP generations when it
provided the clocks for both DSP and IVAHD subsystems. This DPLL is
currently not configured by older bootloaders. Use the DT standard
properties "assigned-clocks" and "assigned-clock-rates" to set the
IVA DPLL clock rate and the rates for its derivative clocks at boot
time to properly initialize/lock this DPLL and be independent of the
bootloader version. Newer u-boots (from 2017.01 onwards) reuse and
can update these properties to choose an appropriate one-time fixed
OPP configuration. The DPLL will automatically transition into a
low-power stop mode when the associated output clocks are not
utilized or gated automatically.

The reset value of the divider M2 (that supplies the IVA_GFLCK, the
functional clock for the IVAHD subsystem) does not match a specific
OPP. So, the derived output clock from this IVA DPLL has to be
initialized as well to avoid initializing these divider outputs to an
incorrect frequencies.

The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data
Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The
clock rates are chosen based on these OPP_NOM values and defined as per
a DRA7xx PLL spec document. The DPLL locked frequency is 2300 MHz, so
the dpll_iva_ck clock rate used is half of this value. The value for the
divider clock, dpll_iva_m2_ck, has to be set to 388.333334 MHz or more
for the divider clk logic to compute the appropriate divider value for
OPP_NOM.

Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 8a82490035d9..76e2b7478141 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -376,6 +376,8 @@
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+		assigned-clocks = <&dpll_iva_ck>;
+		assigned-clock-rates = <1165000000>;
 	};
 
 	dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
@@ -387,6 +389,8 @@
 		reg = <0x01b0>;
 		ti,index-starts-at-one;
 		ti,invert-autoidle-bit;
+		assigned-clocks = <&dpll_iva_m2_ck>;
+		assigned-clock-rates = <388333334>;
 	};
 
 	iva_dclk: iva_dclk {
-- 
2.12.0

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[PATCH 6/6] ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks

[Suman Anna]

From: Subhajit Paul <subhajit_paul-l0cyMroinI0@public.gmane.org>

The GPU has two functional clocks - GPU_CORE_GCLK and GPU_HYD_GCLK.
Both of these are mux clocks and are derived from the DPLL_CORE
H14 output clock CORE_GPU_CLK by default. These clocks can also be
be derived from DPLL_PER or DPLL_GPU.

The GPU DPLL provides the output clocks primarily for the GPU.
Configuring the GPU for different OPP clock frequencies is easier
to achieve when using the DPLL_GPU rather than the other two DPLLs
due to:
1. minimal affect on any other output clocks from these DPLLs
2. may require an impossible post-divider values on existing DPLLs
   without affecting other clocks.

So, switch the GPU functional clocks to be sourced from GPU DPLL by
default. This is done using the DT standard properties "assigned-clocks"
and "assigned-clock-parents". Newer u-boots (from 2017.01 onwards) reuse
and can update these properties to choose an appropriate one-time fixed
OPP configuration as all the required ABB/AVS setup is performed within
the bootloader. Note that there is no DVFS supported for any of the
non-MPU domains. The DPLL will automatically transition into a low-power
stop mode when the associated output clocks are not utilized or gated
automatically.

This patch also sets the initial values for the DPLL_GPU outputs.
These values are chosen based on the OPP_NOM values defined as per
recommendation from design team. The DPLL locked frequency is kept
at 1277 MHz, so that the value for the divider clock, dpll_gpu_m2_ck,
can be set to 425.67 MHz for OPP_NOM.

Signed-off-by: Subhajit Paul <subhajit_paul-l0cyMroinI0@public.gmane.org>
[s-anna-l0cyMroinI0@public.gmane.org: revise patch description]
Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 76e2b7478141..cf229dfabf61 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -414,6 +414,8 @@
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 		reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+		assigned-clocks = <&dpll_gpu_ck>;
+		assigned-clock-rates = <1277000000>;
 	};
 
 	dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
@@ -425,6 +427,8 @@
 		reg = <0x02e8>;
 		ti,index-starts-at-one;
 		ti,invert-autoidle-bit;
+		assigned-clocks = <&dpll_gpu_m2_ck>;
+		assigned-clock-rates = <425666667>;
 	};
 
 	dpll_core_m2_ck: dpll_core_m2_ck@130 {
@@ -1760,6 +1764,8 @@
 		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
 		ti,bit-shift = <24>;
 		reg = <0x1220>;
+		assigned-clocks = <&gpu_core_gclk_mux>;
+		assigned-clock-parents = <&dpll_gpu_m2_ck>;
 	};
 
 	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
@@ -1768,6 +1774,8 @@
 		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
 		ti,bit-shift = <26>;
 		reg = <0x1220>;
+		assigned-clocks = <&gpu_hyd_gclk_mux>;
+		assigned-clock-parents = <&dpll_gpu_m2_ck>;
 	};
 
 	l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
-- 
2.12.0

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Re: [PATCH 0/6] Init Clock frequences for accelerators

[Tony Lindgren]

* Suman Anna <s-anna-l0cyMroinI0@public.gmane.org> [170607 14:31]:
> Hi Tony,
> 
> The following series configures the initial frequencies for the required
> DPLLs and corresponding output divider clocks used by various remoteproc
> accelerators (DSP, IVAHD) on OMAP4, OMAP5 & DRA7xx/AM57xx SoCs and the
> GPU on DRA7xx/AM57xx SoCs. All these devices require Adaptive Voltage
> Scaling (AVS) to be programmed at all OPPs at boot time, which is
> programmed in the bootloader. Furthermore, DVFS is not supported on
> these domains implying a one-time OPP clock frequency setup.

Tero, care to comment or ack this series?

Regards,

Tony
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Re: [PATCH 0/6] Init Clock frequences for accelerators

[Tero Kristo]

On 12/06/17 10:36, Tony Lindgren wrote:
> * Suman Anna <s-anna@ti.com> [170607 14:31]:
>> Hi Tony,
>>
>> The following series configures the initial frequencies for the required
>> DPLLs and corresponding output divider clocks used by various remoteproc
>> accelerators (DSP, IVAHD) on OMAP4, OMAP5 & DRA7xx/AM57xx SoCs and the
>> GPU on DRA7xx/AM57xx SoCs. All these devices require Adaptive Voltage
>> Scaling (AVS) to be programmed at all OPPs at boot time, which is
>> programmed in the bootloader. Furthermore, DVFS is not supported on
>> these domains implying a one-time OPP clock frequency setup.
> 
> Tero, care to comment or ack this series?

These have been in use in TI releases for quite a while already, and 
look fine, thus:

Acked-by: Tero Kristo <t-kristo@ti.com>

(Didn't quite think my ack was needed for them so didn't respond 
earlier, sorry.)

Re: [PATCH 0/6] Init Clock frequences for accelerators

[Tony Lindgren]

* Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org> [170612 01:36]:
> On 12/06/17 10:36, Tony Lindgren wrote:
> > * Suman Anna <s-anna-l0cyMroinI0@public.gmane.org> [170607 14:31]:
> > > Hi Tony,
> > > 
> > > The following series configures the initial frequencies for the required
> > > DPLLs and corresponding output divider clocks used by various remoteproc
> > > accelerators (DSP, IVAHD) on OMAP4, OMAP5 & DRA7xx/AM57xx SoCs and the
> > > GPU on DRA7xx/AM57xx SoCs. All these devices require Adaptive Voltage
> > > Scaling (AVS) to be programmed at all OPPs at boot time, which is
> > > programmed in the bootloader. Furthermore, DVFS is not supported on
> > > these domains implying a one-time OPP clock frequency setup.
> > 
> > Tero, care to comment or ack this series?
> 
> These have been in use in TI releases for quite a while already, and look
> fine, thus:
> 
> Acked-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
> 
> (Didn't quite think my ack was needed for them so didn't respond earlier,
> sorry.)

OK thanks applying all into omap-for-v4.13/dt.

Regards,

Tony
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[PATCH 2/6] ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates

[Suman Anna]

The IVA DPLL is not an essential DPLL for the functionality of a
bootloader and is usually not configured (e.g. older u-boots configure
it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer
than 2014.01 do not even have an option), and this results in incorrect
operating frequencies when trying to use a DSP or IVAHD, whose root
clocks are derived from this DPLL. Use the DT standard properties
"assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock
rate and the rates for its derivative clocks at boot time to properly
initialize/lock this DPLL. The DPLL will automatically transition
into a low-power stop mode when the associated output clocks are
not utilized or gated automatically.

The reset values of the dividers H11 & H12 (functional clocks for DSP
and IVAHD respectively) are identical to each other, but are different
at each OPP. The reset values also do not match a specific OPP. So, the
derived output clocks from the IVA DPLL have to be initialized as well
to avoid initializing these divider outputs to incorrect frequencies.

The clock rates are chosen based on the OPP_NOM values as defined in
the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA
Preferred Settings". The recommended maximum DPLL locked frequency is
2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck
clock rate used is half of this value. The value 465.92 MHz is used
instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider
value can be calculated.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/boot/dts/omap54xx-clocks.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 4899c2359d0a..529193442620 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -315,6 +315,8 @@
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
 		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+		assigned-clocks = <&dpll_iva_ck>;
+		assigned-clock-rates = <1165000000>;
 	};
 
 	dpll_iva_x2_ck: dpll_iva_x2_ck {
@@ -330,6 +332,8 @@
 		ti,max-div = <63>;
 		reg = <0x01b8>;
 		ti,index-starts-at-one;
+		assigned-clocks = <&dpll_iva_h11x2_ck>;
+		assigned-clock-rates = <465920000>;
 	};
 
 	dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
@@ -339,6 +343,8 @@
 		ti,max-div = <63>;
 		reg = <0x01bc>;
 		ti,index-starts-at-one;
+		assigned-clocks = <&dpll_iva_h12x2_ck>;
+		assigned-clock-rates = <388300000>;
 	};
 
 	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
-- 
2.12.0

[PATCH 4/6] ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates

[Suman Anna]

The DSP DPLL is a new DPLL compared to previous OMAP generations and
supplies the root clocks for the DSP processors, as well as a mux
input source for EVE sub-system (on applicable SoCs). This DPLL is
currently not configured by older bootloaders. Use the DT standard
properties "assigned-clocks" and "assigned-clock-rates" to set the
DSP DPLL clock rate and the rates for its derivative clocks at boot
time to properly initialize/lock this DPLL and be independent of the
bootloader version. Newer u-boots (from 2017.01 onwards) reuse and
can update these properties to choose an appropriate one-time fixed
OPP configuration. The DPLL will automatically transition into a
low-power stop mode when the associated output clocks are not
utilized or gated automatically.

The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The
desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency),
and is currently auto set due to the desired M2 divider value being the
same as reset value for the locked frequency of 600 MHz. The EVE_GCLK
however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate
explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate
is also set explicitly to not rely on any implicit matching divider reset
values to the locked DPLL frequency.

The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data
Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The
clock rates are chosen based on these OPP_NOM values and defined as per
a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so
the dpll_dsp_ck clock rate used is half of this value.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index cfaf27215901..8a82490035d9 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -338,6 +338,8 @@
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 		reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+		assigned-clocks = <&dpll_dsp_ck>;
+		assigned-clock-rates = <600000000>;
 	};
 
 	dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
@@ -349,6 +351,8 @@
 		reg = <0x0244>;
 		ti,index-starts-at-one;
 		ti,invert-autoidle-bit;
+		assigned-clocks = <&dpll_dsp_m2_ck>;
+		assigned-clock-rates = <600000000>;
 	};
 
 	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
@@ -659,6 +663,8 @@
 		reg = <0x0248>;
 		ti,index-starts-at-one;
 		ti,invert-autoidle-bit;
+		assigned-clocks = <&dpll_dsp_m3x2_ck>;
+		assigned-clock-rates = <400000000>;
 	};
 
 	dpll_gmac_x2_ck: dpll_gmac_x2_ck {
-- 
2.12.0