From mboxrd@z Thu Jan 1 00:00:00 1970 From: Phong Tran Subject: [PATCH 13/15] ARM: mm: cleanup cppcheck shifting errors Date: Sun, 23 Jun 2019 22:13:11 +0700 Message-ID: <20190623151313.970-14-tranmanphong@gmail.com> References: <20190623151313.970-1-tranmanphong@gmail.com> Return-path: In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: mark.rutland@arm.com, kstewart@linuxfoundation.org, songliubraving@fb.com, andrew@lunn.ch, peterz@infradead.org, nsekhar@ti.com, ast@kernel.org, jolsa@redhat.com, netdev@vger.kernel.org, gerg@uclinux.org, lorenzo.pieralisi@arm.com, will@kernel.org, linux-samsung-soc@vger.kernel.org, daniel@iogearbox.net, tranmanphong@gmail.com, festevam@gmail.com, gregory.clement@bootlin.com, allison@lohutok.net, linux@armlinux.org.uk, krzk@kernel.org, haojian.zhuang@gmail.com, bgolaszewski@baylibre.com, tony@atomide.com, mingo@redhat.com, linux-imx@nxp.com, yhs@fb.com, sebastian.hesselbarth@gmail.com, illusionist.neo@gmail.com, jason@lakedaemon.net, liviu.dudau@arm.com, s.hauer@pengutronix.de, acme@kernel.org, lkundrak@v3.sk, robert.jarzmik@free.fr, dmg@turingmachine.org, swinslow@gmail.co List-Id: linux-omap@vger.kernel.org [arch/arm/mm/alignment.c:875]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour [arch/arm/mm/fault.c:556]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour [arch/arm/mm/fault.c:585]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour [arch/arm/mm/fault.c:219]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour Signed-off-by: Phong Tran --- arch/arm/mm/fault.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index c063708fa503..159c4e7bff09 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -5,9 +5,9 @@ /* * Fault status register encodings. We steal bit 31 for our own purposes. */ -#define FSR_LNX_PF (1 << 31) -#define FSR_WRITE (1 << 11) -#define FSR_FS4 (1 << 10) +#define FSR_LNX_PF (1U << 31) +#define FSR_WRITE (1U << 11) +#define FSR_FS4 (1U << 10) #define FSR_FS3_0 (15) #define FSR_FS5_0 (0x3f) -- 2.11.0