From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: SATA broken with LPAE Date: Wed, 26 Jun 2019 14:53:25 +0200 Message-ID: <20190626125325.GA4744@lst.de> References: <16f065ef-f4ac-46b4-de2a-6b5420ae873a@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <16f065ef-f4ac-46b4-de2a-6b5420ae873a-l0cyMroinI0@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Roger Quadros Cc: axboe-tSWWG44O7X1aa/9Udqfwiw@public.gmane.org, Vignesh Raghavendra , martin.petersen-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org, linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Tony Lindgren , jejb-tEXmvtCZX7AybS5Ee8rs3A@public.gmane.org, "Nori, Sekhar" , "hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org" , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, hch-jcswGhMUV9g@public.gmane.org List-Id: linux-omap@vger.kernel.org Hi Roger, it seems the arm dma direct mapping code isn't doing the right thing here. On other platforms that have > 4G memory we always use swiotlb for bounce buffering in case a device that can't DMA to all the memory. Arm is the odd one out and uses its own dmabounce framework instead, but it seems like it doesn't get used in this case. We need to make sure dmabounce (or swiotlb for that matter) is set up if > 32-bit addressing is supported. I'm not really an arm platform expert, but some of those on the Cc list are and might chime in on how to do that.