[PATCH] ARM: dts: ti/omap: dra7: Fix PCIe PHY divided clock generation

[Danny Baumann <dannybaumann@web.de>]

From: Danny Baumann <danny.baumann@legrand.com>

Commit d0bdd8bb7f35a2b4434a3ef665f9cfc3aba886c7 ("ARM: dts: ti/omap:
dra7: fix redundant clock divider definition") removed the ti,dividers
property in favor of the ti,max-div property. That particular divider is
'backwards', though (0 = 'divide by 2', 1 = 'do not divide, see AM574x
TRM, table 3-846 on page 939), so the removal of that property inverted
the driver behavior.
Restore previous behavior by restoring the ti,dividers property and fix
the redundancy by removing the ti,max-div property instead.

Fixes: d0bdd8bb7f35 ("ARM: dts: ti/omap: dra7: fix redundant clock divider definition")
Cc: Andreas Kemnade <andreas@kemnade.info>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: stable@vger.kernel.org # 6.13+
Signed-off-by: Danny Baumann <danny.baumann@legrand.com>
---
 arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
index 0de16ee262cf..615a8fb47776 100644
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -1376,8 +1376,8 @@ optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
 		clocks = <&apll_pcie_ck>;
 		#clock-cells = <0>;
 		reg = <0x021c>;
+		ti,dividers = <2>, <1>;
 		ti,bit-shift = <8>;
-		ti,max-div = <2>;
 	};
 
 	apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
-- 
2.52.0