[PATCH] ARM: OMAP: Add minimal OMAP2430 support V2

Komal Shah
2006-06-12T16:25:03Z

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Tony/Juha/Richard,

Attached patch is re-worked with PRCM and SDRC changes
to prcm/sdrc_read/write_reg fashion. I have tested it on OMAP2420
H4 EVM. I still need to test it on SDP2430.

- Moved prcm.c to clock.c.

Please review.

---
[PATCH] ARM: OMAP: Add Minimal OMAP2430 support and
added read/write_reg functions for PRCM and SDRC.

Signed-off-by: Komal Shah <komal_shah802003@yahoo.com>

--
http://www.fastmail.fm - Email service worth paying for. Try it for free

[-- Attachment #2: prcm-min2430-1206.patch --]
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diff --git a/arch/arm/configs/omap_sdp2430_2430_defconfig b/arch/arm/configs/omap_sdp2430_2430_defconfig
new file mode 100644
index 0000000..1dbe0f1
--- /dev/null
+++ b/arch/arm/configs/omap_sdp2430_2430_defconfig
@@ -0,0 +1,941 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.17-rc5-omap1
+# Tue Jun 13 03:22:38 2006
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_VECTORS_BASE=0xffff0000
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_UID16=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+CONFIG_OBSOLETE_INTERMODULE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+# CONFIG_BLK_DEV_IO_TRACE is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_AT91RM9200 is not set
+
+#
+# TI OMAP Implementations
+#
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+# CONFIG_OMAP_BOOT_REASON is not set
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_STI is not set
+CONFIG_OMAP_MPU_TIMER=y
+# CONFIG_OMAP_32K_TIMER is not set
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP Core Type
+#
+CONFIG_ARCH_OMAP24XX=y
+# CONFIG_ARCH_OMAP2420 is not set
+CONFIG_ARCH_OMAP2430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_H4 is not set
+# CONFIG_MACH_OMAP_APOLLON is not set
+CONFIG_MACH_OMAP_SDP2430=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+
+#
+# Bus support
+#
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+# CONFIG_APM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_ONENAND_SYNC_READ is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_OMAP_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+CONFIG_VIDEO_V4L2=y
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# Synchronous Serial Interfaces (SSI)
+#
+# CONFIG_OMAP_TSC2101 is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_QUOTA=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_UNWIND_INFO is not set
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+CONFIG_LIBCRC32C=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index ab144c3..d9d73be 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -9,6 +9,10 @@ config ARCH_OMAP2420
bool "OMAP2420 support"
depends on ARCH_OMAP24XX

+config ARCH_OMAP2430
+ bool "OMAP2430 support"
+ depends on ARCH_OMAP24XX
+
comment "OMAP Board Type"
depends on ARCH_OMAP2

@@ -24,3 +28,9 @@ config MACH_OMAP_H4
config MACH_OMAP_APOLLON
bool "OMAP 2420 Apollon board"
depends on ARCH_OMAP2 && ARCH_OMAP24XX
+
+config MACH_OMAP_SDP2430
+ bool "OMAP 2430 SDP2430 board"
+ depends on ARCH_OMAP2 && ARCH_OMAP24XX
+
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 111eaa6..302595c 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@ # Makefile for the linux kernel.
#

# Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o serial.o
+obj-y := irq.o id.o io.o sram-fn.o memory.o clock.o mux.o devices.o serial.o

obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o

@@ -14,4 +14,5 @@ # Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
+obj-$(CONFIG_MACH_OMAP_SDP2430) += board-sdp2430.o

diff --git a/arch/arm/mach-omap2/board-sdp2430.c b/arch/arm/mach-omap2/board-sdp2430.c
new file mode 100644
index 0000000..d2c2607
--- /dev/null
+++ b/arch/arm/mach-omap2/board-sdp2430.c
@@ -0,0 +1,180 @@
+/*
+ * linux/arch/arm/mach-omap2/board-sdp2430.c
+ *
+ * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
+ *
+ * Modified from mach-omap2/board-generic.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/delay.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/usb.h>
+#include <asm/arch/board.h>
+#include <asm/arch/common.h>
+#include "prcm-regs.h"
+
+#include <asm/io.h>
+#include <asm/delay.h>
+
+
+static struct omap_uart_config sdp2430_uart_config __initdata = {
+ .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
+};
+
+static struct omap_board_config_kernel sdp2430_config[] = {
+ { OMAP_TAG_UART, &sdp2430_uart_config },
+};
+
+static struct mtd_partition sdp2430_partitions[] = {
+ /* bootloader (U-Boot, etc) in first sector */
+ {
+ .name = "bootloader",
+ .offset = 0,
+ .size = SZ_256K,
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
+ /* bootloader params in the next sector */
+ {
+ .name = "params",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_128K,
+ .mask_flags = 0,
+ },
+ /* kernel */
+ {
+ .name = "kernel",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_2M,
+ .mask_flags = 0
+ },
+ /* file system */
+ {
+ .name = "filesystem",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ .mask_flags = 0
+ }
+};
+
+static struct flash_platform_data sdp2430_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+ .parts = sdp2430_partitions,
+ .nr_parts = ARRAY_SIZE(sdp2430_partitions),
+};
+
+static struct resource sdp2430_flash_resource = {
+ .start = SDP2430_CS0_BASE,
+ .end = SDP2430_CS0_BASE + SZ_64M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device sdp2430_flash_device = {
+ .name = "omapflash",
+ .id = 0,
+ .dev = {
+ .platform_data = &sdp2430_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &sdp2430_flash_resource,
+};
+
+static struct resource sdp2430_smc91x_resources[] = {
+ [0] = {
+ .start = OMAP24XX_ETHR_START, /* Physical */
+ .end = OMAP24XX_ETHR_START + 0xf,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
+ .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device sdp2430_smc91x_device = {
+ .name = "smc91x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(sdp2430_smc91x_resources),
+ .resource = sdp2430_smc91x_resources,
+};
+
+static struct platform_device *sdp2430_devices[] __initdata = {
+ &sdp2430_smc91x_device,
+ &sdp2430_flash_device,
+};
+
+static inline void __init sdp2430_init_smc91x(void)
+{
+ /* Make sure CS5 timings are correct */
+ GPMC_CONFIG1_5 = 0x00011200;
+ GPMC_CONFIG2_5 = 0x001f1f02;
+ GPMC_CONFIG3_5 = 0x00080804;
+ GPMC_CONFIG4_5 = 0x1c091c09;
+ GPMC_CONFIG5_5 = 0x041f1f1f;
+ GPMC_CONFIG6_5 = 0x000004c4;
+ GPMC_CONFIG7_5 = 0x00000f40 | (0x08000000 >> 24);
+ udelay(100);
+
+ /* FIXME: Add omap_cfg_reg(GPIO_149) here */
+ if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) {
+ printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
+ OMAP24XX_ETHR_GPIO_IRQ);
+ return;
+ }
+ omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
+}
+
+static void __init omap_sdp2430_init_irq(void)
+{
+ omap2_init_common_hw();
+ omap_init_irq();
+ omap_gpio_init();
+ sdp2430_init_smc91x();
+}
+
+static void __init omap_sdp2430_init(void)
+{
+ /*
+ * Make sure the serial ports are muxed on at this point.
+ * You have to mux them off in device drivers later on
+ * if not needed.
+ */
+ platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
+ omap_board_config = sdp2430_config;
+ omap_board_config_size = ARRAY_SIZE(sdp2430_config);
+ omap_serial_init();
+}
+
+static void __init omap_sdp2430_map_io(void)
+{
+ omap2_map_common_io();
+}
+
+MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
+ /* Maintainer: Komal Shah <komal_shah802003@yahoo.com> */
+ .phys_io = 0x48000000,
+ .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
+ .boot_params = 0x80000100,
+ .map_io = omap_sdp2430_map_io,
+ .init_irq = omap_sdp2430_init_irq,
+ .init_machine = omap_sdp2430_init,
+ .timer = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 72eb4bf..61f45d5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -38,6 +38,45 @@ #include "clock.h"
static struct prcm_config *curr_prcm_set;
static u32 curr_perf_level = PRCM_FULL_SPEED;

+static void __iomem *prcm_vbase;
+
+static inline u32 prcm_read_reg(int reg)
+{
+ return __raw_readl(prcm_vbase + (reg));
+}
+
+static inline void prcm_write_reg(int reg, u32 value)
+{
+ __raw_writel((value), prcm_vbase + (reg));
+}
+
+u32 omap_prcm_get_reset_sources(void)
+{
+ u32 reg;
+
+ reg = prcm_read_reg(RM_RSTST_WKUP);
+ reg &= 0x7f;
+
+ return reg;
+}
+EXPORT_SYMBOL(omap_prcm_get_reset_sources);
+
+/* Resets clock rates and reboots the system. Only called from system.h */
+void omap_prcm_arch_reset(char mode)
+{
+ u32 rate, reg;
+ struct clk *vclk, *sclk;
+
+ vclk = clk_get(NULL, "virt_prcm_set");
+ sclk = clk_get(NULL, "sys_ck");
+ rate = clk_get_rate(sclk);
+ clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
+
+ reg = prcm_read_reg(RM_RSTCTRL_WKUP);
+ reg |= RM_RST_GS;
+ prcm_write_reg(RM_RSTCTRL_WKUP, reg);
+}
+
/*-------------------------------------------------------------------------
* Omap2 specific clock functions
*-------------------------------------------------------------------------*/
@@ -45,7 +84,7 @@ static u32 curr_perf_level = PRCM_FULL_S
/* Recalculate SYST_CLK */
static void omap2_sys_clk_recalc(struct clk * clk)
{
- u32 div = PRCM_CLKSRC_CTRL;
+ u32 div = prcm_read_reg(PRCM_CLKSRC_CTRL);
div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
div >>= clk->rate_offset;
clk->rate = (clk->parent->rate / div);
@@ -57,11 +96,11 @@ static u32 omap2_get_dpll_rate(struct cl
long long dpll_clk;
int dpll_mult, dpll_div, amult;

- dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
- dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
+ dpll_mult = (prcm_read_reg(CM_CLKSEL1_PLL) >> 12) & 0x03ff;/* 10 bits */
+ dpll_div = (prcm_read_reg(CM_CLKSEL1_PLL) >> 8) & 0x0f; /* 4 bits */
dpll_clk = (long long)tclk->parent->rate * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
- amult = CM_CLKSEL2_PLL & 0x3;
+ amult = prcm_read_reg(CM_CLKSEL2_PLL) & 0x3;
dpll_clk *= amult;

return dpll_clk;
@@ -88,21 +127,21 @@ static void omap2_clk_fixed_enable(struc
if (clk->enable_bit == 0xff) /* Parent will do it */
return;

- cval = CM_CLKEN_PLL;
+ cval = prcm_read_reg(CM_CLKEN_PLL);

if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
return;

cval &= ~(0x3 << clk->enable_bit);
cval |= (0x3 << clk->enable_bit);
- CM_CLKEN_PLL = cval;
+ prcm_write_reg(CM_CLKEN_PLL, cval);

if (clk == &apll96_ck)
cval = (1 << 8);
else if (clk == &apll54_ck)
cval = (1 << 6);

- while (!CM_IDLEST_CKGEN & cval) { /* Wait for lock */
+ while (!prcm_read_reg(CM_IDLEST_CKGEN) & cval) {/* Wait for lock */
++i;
udelay(1);
if (i == 100000)
@@ -125,15 +164,14 @@ static int _omap2_clk_enable(struct clk
clk->name);
return 0;
}
-
- if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
+ if (clk->enable_reg == (void __iomem *)CM_CLKEN_PLL) {
omap2_clk_fixed_enable(clk);
return 0;
}

- regval32 = __raw_readl(clk->enable_reg);
+ regval32 = prcm_read_reg((u32)clk->enable_reg);
regval32 |= (1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
+ prcm_write_reg((u32)clk->enable_reg, regval32);

return 0;
}
@@ -146,9 +184,9 @@ static void omap2_clk_fixed_disable(stru
if(clk->enable_bit == 0xff) /* let parent off do it */
return;

- cval = CM_CLKEN_PLL;
+ cval = prcm_read_reg(CM_CLKEN_PLL);
cval &= ~(0x3 << clk->enable_bit);
- CM_CLKEN_PLL = cval;
+ prcm_write_reg(CM_CLKEN_PLL, cval);
}

/* Disables clock without considering parent dependencies or use count */
@@ -159,14 +197,14 @@ static void _omap2_clk_disable(struct cl
if (clk->enable_reg == 0)
return;

- if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
+ if (clk->enable_reg == (void __iomem *)CM_CLKEN_PLL) {
omap2_clk_fixed_disable(clk);
return;
}

- regval32 = __raw_readl(clk->enable_reg);
+ regval32 = prcm_read_reg((u32)clk->enable_reg);
regval32 &= ~(1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
+ prcm_write_reg((u32)clk->enable_reg, regval32);
}

static int omap2_clk_enable(struct clk *clk)
@@ -210,7 +248,7 @@ static u32 omap2_dpll_round_rate(unsigne
{
u32 high, low;

- if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */
+ if ((prcm_read_reg(CM_CLKSEL2_PLL) & 0x3) == 1) { /* DPLL clockout */
high = curr_prcm_set->dpll_speed * 2;
low = curr_prcm_set->dpll_speed;
} else { /* DPLL clockout x 2 */
@@ -251,7 +289,8 @@ static void omap2_clksel_recalc(struct c
fixed = 1;
}

- if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
+ if ((clk == &dss1_fck) &&
+ ((prcm_read_reg(CM_CLKSEL1_CORE) & (0x1f << 8)) == 0)) {
clk->rate = sys_ck.rate;
return;
}
@@ -373,20 +412,6 @@ static long omap2_clk_round_rate(struct
return clk->rate;
}

-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compenste for the shifted DLL value in unlock mode.
- */
-static u32 omap2_dll_force_needed(void)
-{
- u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */
-
- if ((dll_state & (1 << 2)) == (1 << 2))
- return 1;
- else
- return 0;
-}
-
static u32 omap2_reprogram_sdrc(u32 level, u32 force)
{
u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
@@ -401,7 +426,7 @@ static u32 omap2_reprogram_sdrc(u32 leve

if (level == PRCM_HALF_SPEED) {
local_irq_save(flags);
- PRCM_VOLTSETUP = 0xffff;
+ prcm_write_reg(PRCM_VOLTSETUP, 0xffff);
omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
slow_dll_ctrl, m_type);
curr_perf_level = PRCM_HALF_SPEED;
@@ -409,7 +434,7 @@ static u32 omap2_reprogram_sdrc(u32 leve
}
if (level == PRCM_FULL_SPEED) {
local_irq_save(flags);
- PRCM_VOLTSETUP = 0xffff;
+ prcm_write_reg(PRCM_VOLTSETUP, 0xffff);
omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
fast_dll_ctrl, m_type);
curr_perf_level = PRCM_FULL_SPEED;
@@ -428,7 +453,7 @@ static int omap2_reprogram_dpll(struct c

local_irq_save(flags);
cur_rate = omap2_get_dpll_rate(&dpll_ck);
- mult = CM_CLKSEL2_PLL & 0x3;
+ mult = prcm_read_reg(CM_CLKSEL2_PLL) & 0x3;

if ((rate == (cur_rate / 2)) && (mult == 2)) {
omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
@@ -439,15 +464,15 @@ static int omap2_reprogram_dpll(struct c
if (valid_rate != rate)
goto dpll_exit;

- if ((CM_CLKSEL2_PLL & 0x3) == 1)
+ if ((prcm_read_reg(CM_CLKSEL2_PLL) & 0x3) == 1)
low = curr_prcm_set->dpll_speed;
else
low = curr_prcm_set->dpll_speed / 2;

- tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
+ tmpset.cm_clksel1_pll = prcm_read_reg(CM_CLKSEL1_PLL);
tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
- tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
+ tmpset.cm_clksel2_pll = prcm_read_reg(CM_CLKSEL2_PLL);
tmpset.cm_clksel2_pll &= ~0x3;
if (rate > low) {
tmpset.cm_clksel2_pll |= 0x2;
@@ -554,11 +579,11 @@ static u32 omap2_get_clksel(u32 *div_sel

switch ((*div_sel & SRC_RATE_SEL_MASK)) {
case CM_MPU_SEL1:
- div_addr = (u32)&CM_CLKSEL_MPU;
+ div_addr = (u32)CM_CLKSEL_MPU;
mask = 0x1f;
break;
case CM_DSP_SEL1:
- div_addr = (u32)&CM_CLKSEL_DSP;
+ div_addr = (u32)CM_CLKSEL_DSP;
if (cpu_is_omap2420()) {
if ((div_off == 0) || (div_off == 8))
mask = 0x1f;
@@ -572,22 +597,22 @@ static u32 omap2_get_clksel(u32 *div_sel
}
break;
case CM_GFX_SEL1:
- div_addr = (u32)&CM_CLKSEL_GFX;
+ div_addr = (u32)CM_CLKSEL_GFX;
if (div_off == 0)
mask = 0x7;
break;
case CM_MODEM_SEL1:
- div_addr = (u32)&CM_CLKSEL_MDM;
+ div_addr = (u32)CM_CLKSEL_MDM;
if (div_off == 0)
mask = 0xf;
break;
case CM_SYSCLKOUT_SEL1:
- div_addr = (u32)&PRCM_CLKOUT_CTRL;
+ div_addr = (u32)PRCM_CLKOUT_CTRL;
if ((div_off == 3) || (div_off = 11))
mask= 0x3;
break;
case CM_CORE_SEL1:
- div_addr = (u32)&CM_CLKSEL1_CORE;
+ div_addr = (u32)CM_CLKSEL1_CORE;
switch (div_off) {
case 0: /* l3 */
case 8: /* dss1 */
@@ -614,7 +639,7 @@ static u32 omap2_get_clksel(u32 *div_sel
return ret;

/* Isolate field */
- reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
+ reg_val = prcm_read_reg(div_addr) & (mask << div_off);

/* Normalize back to divider value */
reg_val >>= div_off;
@@ -650,7 +675,6 @@ static int omap2_clk_set_rate(struct clk

{
int ret = -EINVAL;
- void __iomem * reg;
u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
u32 new_div = 0;

@@ -682,17 +706,15 @@ static int omap2_clk_set_rate(struct clk
else
field_val = new_div;

- reg = (void __iomem *)div_sel;
-
- reg_val = __raw_readl(reg);
+ reg_val = prcm_read_reg(div_sel);
reg_val &= ~(field_mask << div_off);
reg_val |= (field_val << div_off);

- __raw_writel(reg_val, reg);
+ prcm_write_reg(div_sel, reg_val);
clk->rate = clk->parent->rate / field_val;

if (clk->flags & DELAYED_APP)
- __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
+ prcm_write_reg(PRCM_CLKCFG_CTRL, 0x01);
ret = 0;
} else if (clk->set_rate != 0)
ret = clk->set_rate(clk, rate);
@@ -712,7 +734,7 @@ static u32 omap2_get_src_field(u32 *type
/* Find target control register.*/
switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
case CM_CORE_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL1_CORE;
+ src_reg_addr = (u32)CM_CLKSEL1_CORE;
if (reg_offset == 13) { /* DSS2_fclk */
mask = 0x1;
if (src_clk == &sys_ck)
@@ -734,7 +756,7 @@ static u32 omap2_get_src_field(u32 *type
}
break;
case CM_CORE_SEL2:
- src_reg_addr = (u32)&CM_CLKSEL2_CORE;
+ src_reg_addr = (u32)CM_CLKSEL2_CORE;
mask = 0x3;
if (src_clk == &func_32k_ck)
val = 0x0;
@@ -744,7 +766,7 @@ static u32 omap2_get_src_field(u32 *type
val = 0x2;
break;
case CM_WKUP_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL2_CORE;
+ src_reg_addr = (u32)CM_CLKSEL2_CORE;
mask = 0x3;
if (src_clk == &func_32k_ck)
val = 0x0;
@@ -754,7 +776,7 @@ static u32 omap2_get_src_field(u32 *type
val = 0x2;
break;
case CM_PLL_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL1_PLL;
+ src_reg_addr = (u32)CM_CLKSEL1_PLL;
mask = 0x1;
if (reg_offset == 0x3) {
if (src_clk == &apll96_ck)
@@ -770,7 +792,7 @@ static u32 omap2_get_src_field(u32 *type
}
break;
case CM_PLL_SEL2:
- src_reg_addr = (u32)&CM_CLKSEL2_PLL;
+ src_reg_addr = (u32)CM_CLKSEL2_PLL;
mask = 0x3;
if (src_clk == &func_32k_ck)
val = 0x0;
@@ -778,7 +800,7 @@ static u32 omap2_get_src_field(u32 *type
val = 0x2;
break;
case CM_SYSCLKOUT_SEL1:
- src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
+ src_reg_addr = (u32)PRCM_CLKOUT_CTRL;
mask = 0x3;
if (src_clk == &dpll_ck)
val = 0;
@@ -802,7 +824,6 @@ static u32 omap2_get_src_field(u32 *type

static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
{
- void __iomem * reg;
u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
int ret = -EINVAL;

@@ -819,18 +840,16 @@ static int omap2_clk_set_parent(struct c
field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
&field_mask);

- reg = (void __iomem *)src_sel;
-
if (clk->usecount > 0)
_omap2_clk_disable(clk);

/* Set new source value (previous dividers if any in effect) */
- reg_val = __raw_readl(reg) & ~(field_mask << src_off);
+ reg_val = prcm_read_reg(src_sel) & ~(field_mask << src_off);
reg_val |= (field_val << src_off);
- __raw_writel(reg_val, reg);
+ prcm_write_reg(src_sel, reg_val);

if (clk->flags & DELAYED_APP)
- __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
+ prcm_write_reg(PRCM_CLKCFG_CTRL, 0x01);

if (clk->usecount > 0)
_omap2_clk_enable(clk);
@@ -913,17 +932,17 @@ static int omap2_select_table_rate(struc
done_rate = PRCM_HALF_SPEED;

/* MPU divider */
- CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
+ prcm_write_reg(CM_CLKSEL_MPU, prcm->cm_clksel_mpu);

/* dsp + iva1 div(2420), iva2.1(2430) */
- CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
+ prcm_write_reg(CM_CLKSEL_DSP, prcm->cm_clksel_dsp);

- CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
+ prcm_write_reg(CM_CLKSEL_GFX, prcm->cm_clksel_gfx);

/* Major subsystem dividers */
- CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
+ prcm_write_reg(CM_CLKSEL1_CORE, prcm->cm_clksel1_core);
if (cpu_is_omap2430())
- CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
+ prcm_write_reg(CM_CLKSEL_MDM, prcm->cm_clksel_mdm);

/* x2 to enter init_mem */
omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
@@ -957,7 +976,7 @@ static void __init omap2_get_crystal_rat
{
u32 div, aplls, sclk = 13000000;

- aplls = CM_CLKSEL1_PLL;
+ aplls = prcm_read_reg(CM_CLKSEL1_PLL);
aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
aplls >>= 23; /* Isolate field, 0,2,3 */

@@ -968,7 +987,7 @@ static void __init omap2_get_crystal_rat
else if (aplls == 3)
sclk = 12000000;

- div = PRCM_CLKSRC_CTRL;
+ div = prcm_read_reg(PRCM_CLKSRC_CTRL);
div &= ((1 << 7) | (1 << 6));
div >>= sys->rate_offset;

@@ -987,7 +1006,7 @@ static void __init omap2_disable_unused_
ck->enable_reg == 0)
continue;

- regval32 = __raw_readl(ck->enable_reg);
+ regval32 = prcm_read_reg(ck->enable_reg);
if ((regval32 & (1 << ck->enable_bit)) == 0)
continue;

@@ -1074,3 +1093,21 @@ int __init omap2_clk_init(void)

return 0;
}
+
+int __init omap2_prcm_init(void)
+{
+ u32 rev;
+
+ if (cpu_is_omap2420())
+ prcm_vbase = (void __iomem *)io_p2v(OMAP242X_PRCM_BASE);
+ else if (cpu_is_omap2430())
+ prcm_vbase = (void __iomem *)io_p2v(OMAP243X_PRCM_BASE);
+
+ rev = prcm_read_reg(PRCM_REVISION);
+
+ printk(KERN_INFO "OMAP PRCM hardware version %d.%d\n",
+ (rev >> 4) & 0x0f, rev & 0x0f);
+
+ return 0;
+}
+
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2781dfb..4f53443 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -601,7 +601,7 @@ static struct clk apll96_ck = {
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0x2,
.recalc = &omap2_propagate_rate,
};
@@ -612,7 +612,7 @@ static struct clk apll54_ck = {
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0x6,
.recalc = &omap2_propagate_rate,
};
@@ -627,7 +627,7 @@ static struct clk func_54m_ck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
.src_offset = 5,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0xff,
.recalc = &omap2_propagate_rate,
};
@@ -654,7 +654,7 @@ static struct clk func_96m_ck = {
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0xff,
.recalc = &omap2_propagate_rate,
};
@@ -666,7 +666,7 @@ static struct clk func_48m_ck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
.src_offset = 3,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0xff,
.recalc = &omap2_propagate_rate,
};
@@ -678,7 +678,7 @@ static struct clk func_12m_ck = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
.recalc = &omap2_propagate_rate,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = (void __iomem *)CM_CLKEN_PLL,
.enable_bit = 0xff,
};

@@ -697,7 +697,7 @@ static struct clk sys_clkout = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
.src_offset = 0,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
+ .enable_reg = (void __iomem *)PRCM_CLKOUT_CTRL,
.enable_bit = 7,
.rate_offset = 3,
.recalc = &omap2_clksel_recalc,
@@ -711,7 +711,7 @@ static struct clk sys_clkout2 = {
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
.src_offset = 8,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
+ .enable_reg = (void __iomem *)PRCM_CLKOUT_CTRL,
.enable_bit = 15,
.rate_offset = 11,
.recalc = &omap2_clksel_recalc,
@@ -721,7 +721,7 @@ static struct clk emul_ck = {
.name = "emul_ck",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
+ .enable_reg = (void __iomem *)PRCM_CLKEMUL_CTRL,
.enable_bit = 0,
.recalc = &omap2_propagate_rate,

@@ -760,7 +760,7 @@ static struct clk iva2_1_fck = {
DELAYED_APP | RATE_PROPAGATES |
CONFIG_PARTICIPANT,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_DSP,
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
@@ -786,7 +786,7 @@ static struct clk dsp_fck = {
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_DSP,
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
@@ -797,7 +797,7 @@ static struct clk dsp_ick = {
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT,
.rate_offset = 5,
- .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_DSP,
.enable_bit = 1, /* for ipi */
.recalc = &omap2_clksel_recalc,
};
@@ -808,7 +808,7 @@ static struct clk iva1_ifck = {
.flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
.rate_offset= 8,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_DSP,
.enable_bit = 10,
.recalc = &omap2_clksel_recalc,
};
@@ -818,7 +818,7 @@ static struct clk iva1_mpu_int_ifck = {
.name = "iva1_mpu_int_ifck",
.parent = &iva1_ifck,
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_DSP,
.enable_bit = 8,
.recalc = &omap2_clksel_recalc,
};
@@ -859,7 +859,7 @@ static struct clk usb_l4_ick = { /* FS-U
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
CONFIG_PARTICIPANT,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 0,
.rate_offset = 25,
.recalc = &omap2_clksel_recalc,
@@ -878,7 +878,7 @@ static struct clk ssi_ssr_sst_fck = {
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE, /* bit 1 */
.enable_bit = 1,
.rate_offset = 20,
.recalc = &omap2_clksel_recalc,
@@ -900,7 +900,7 @@ static struct clk gfx_3d_fck = {
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
+ .enable_reg = (void __iomem *)CM_FCLKEN_GFX,
.enable_bit = 2,
.rate_offset= 0,
.recalc = &omap2_clksel_recalc,
@@ -911,7 +911,7 @@ static struct clk gfx_2d_fck = {
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
+ .enable_reg = (void __iomem *)CM_FCLKEN_GFX,
.enable_bit = 1,
.rate_offset= 0,
.recalc = &omap2_clksel_recalc,
@@ -922,7 +922,7 @@ static struct clk gfx_ick = {
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
+ .enable_reg = (void __iomem *)CM_ICLKEN_GFX, /* bit 0 */
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -939,7 +939,7 @@ static struct clk mdm_ick = { /* used b
.flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
+ .enable_reg = (void __iomem *)CM_ICLKEN_MDM,
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
@@ -949,7 +949,7 @@ static struct clk mdm_osc_ck = {
.rate = 26000000,
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP243X | RATE_FIXED,
- .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
+ .enable_reg = (void __iomem *)CM_FCLKEN_MDM,
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
@@ -975,7 +975,7 @@ static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE, /* bit 1 */
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
@@ -992,7 +992,7 @@ static struct clk dss_ick = { /* Enable
.name = "dss_ick",
.parent = &l4_ck, /* really both l3 and l4 */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -1002,7 +1002,7 @@ static struct clk dss1_fck = {
.parent = &core_ck, /* Core or sys */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 0,
.rate_offset = 8,
.src_offset = 8,
@@ -1014,7 +1014,7 @@ static struct clk dss2_fck = { /* Alt c
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 1,
.src_offset = 13,
.recalc = &omap2_followparent_recalc,
@@ -1026,7 +1026,7 @@ static struct clk dss_54m_fck = { /* Alt
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 2,
.recalc = &omap2_propagate_rate,
};
@@ -1041,7 +1041,7 @@ static struct clk gpt1_ick = {
.name = "gpt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP, /* Bit0 */
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -1051,7 +1051,7 @@ static struct clk gpt1_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_WKUP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
+ .enable_reg = (void __iomem *)CM_FCLKEN_WKUP, /* Bit0 */
.enable_bit = 0,
.src_offset = 0,
.recalc = &omap2_followparent_recalc,
@@ -1061,7 +1061,7 @@ static struct clk gpt2_ick = {
.name = "gpt2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* Bit4 */
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1071,7 +1071,7 @@ static struct clk gpt2_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 4,
.src_offset = 2,
.recalc = &omap2_followparent_recalc,
@@ -1081,7 +1081,7 @@ static struct clk gpt3_ick = {
.name = "gpt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* Bit5 */
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
@@ -1091,7 +1091,7 @@ static struct clk gpt3_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 5,
.src_offset = 4,
.recalc = &omap2_followparent_recalc,
@@ -1101,7 +1101,7 @@ static struct clk gpt4_ick = {
.name = "gpt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* Bit6 */
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
@@ -1111,7 +1111,7 @@ static struct clk gpt4_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 6,
.src_offset = 6,
.recalc = &omap2_followparent_recalc,
@@ -1121,7 +1121,7 @@ static struct clk gpt5_ick = {
.name = "gpt5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* Bit7 */
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
@@ -1131,7 +1131,7 @@ static struct clk gpt5_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 7,
.src_offset = 8,
.recalc = &omap2_followparent_recalc,
@@ -1142,7 +1142,7 @@ static struct clk gpt6_ick = {
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 8,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit8 */
.recalc = &omap2_followparent_recalc,
};

@@ -1151,7 +1151,7 @@ static struct clk gpt6_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 8,
.src_offset = 10,
.recalc = &omap2_followparent_recalc,
@@ -1161,7 +1161,7 @@ static struct clk gpt7_ick = {
.name = "gpt7_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit9 */
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
@@ -1171,7 +1171,7 @@ static struct clk gpt7_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 9,
.src_offset = 12,
.recalc = &omap2_followparent_recalc,
@@ -1181,7 +1181,7 @@ static struct clk gpt8_ick = {
.name = "gpt8_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit10 */
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
@@ -1191,7 +1191,7 @@ static struct clk gpt8_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 10,
.src_offset = 14,
.recalc = &omap2_followparent_recalc,
@@ -1201,7 +1201,7 @@ static struct clk gpt9_ick = {
.name = "gpt9_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 11,
.recalc = &omap2_followparent_recalc,
};
@@ -1211,7 +1211,7 @@ static struct clk gpt9_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 11,
.src_offset = 16,
.recalc = &omap2_followparent_recalc,
@@ -1221,7 +1221,7 @@ static struct clk gpt10_ick = {
.name = "gpt10_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 12,
.recalc = &omap2_followparent_recalc,
};
@@ -1231,7 +1231,7 @@ static struct clk gpt10_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 12,
.src_offset = 18,
.recalc = &omap2_followparent_recalc,
@@ -1241,7 +1241,7 @@ static struct clk gpt11_ick = {
.name = "gpt11_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 13,
.recalc = &omap2_followparent_recalc,
};
@@ -1251,7 +1251,7 @@ static struct clk gpt11_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 13,
.src_offset = 20,
.recalc = &omap2_followparent_recalc,
@@ -1261,7 +1261,7 @@ static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit14 */
.enable_bit = 14,
.recalc = &omap2_followparent_recalc,
};
@@ -1271,7 +1271,7 @@ static struct clk gpt12_fck = {
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 14,
.src_offset = 22,
.recalc = &omap2_followparent_recalc,
@@ -1282,7 +1282,7 @@ static struct clk mcbsp1_ick = {
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 15,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE, /* bit16 */
.recalc = &omap2_followparent_recalc,
};

@@ -1291,7 +1291,7 @@ static struct clk mcbsp1_fck = {
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 15,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.recalc = &omap2_followparent_recalc,
};

@@ -1300,7 +1300,7 @@ static struct clk mcbsp2_ick = {
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 16,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.recalc = &omap2_followparent_recalc,
};

@@ -1309,7 +1309,7 @@ static struct clk mcbsp2_fck = {
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 16,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.recalc = &omap2_followparent_recalc,
};

@@ -1317,7 +1317,7 @@ static struct clk mcbsp3_ick = {
.name = "mcbsp3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1326,7 +1326,7 @@ static struct clk mcbsp3_fck = {
.name = "mcbsp3_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1335,7 +1335,7 @@ static struct clk mcbsp4_ick = {
.name = "mcbsp4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1344,7 +1344,7 @@ static struct clk mcbsp4_fck = {
.name = "mcbsp4_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1353,7 +1353,7 @@ static struct clk mcbsp5_ick = {
.name = "mcbsp5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
@@ -1362,7 +1362,7 @@ static struct clk mcbsp5_fck = {
.name = "mcbsp5_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
@@ -1371,7 +1371,7 @@ static struct clk mcspi1_ick = {
.name = "mcspi1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};
@@ -1380,7 +1380,7 @@ static struct clk mcspi1_fck = {
.name = "mcspi1_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};
@@ -1389,7 +1389,7 @@ static struct clk mcspi2_ick = {
.name = "mcspi2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 18,
.recalc = &omap2_followparent_recalc,
};
@@ -1398,7 +1398,7 @@ static struct clk mcspi2_fck = {
.name = "mcspi2_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 18,
.recalc = &omap2_followparent_recalc,
};
@@ -1407,7 +1407,7 @@ static struct clk mcspi3_ick = {
.name = "mcspi3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
@@ -1416,7 +1416,7 @@ static struct clk mcspi3_fck = {
.name = "mcspi3_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
@@ -1425,7 +1425,7 @@ static struct clk uart1_ick = {
.name = "uart1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 21,
.recalc = &omap2_followparent_recalc,
};
@@ -1434,7 +1434,7 @@ static struct clk uart1_fck = {
.name = "uart1_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 21,
.recalc = &omap2_followparent_recalc,
};
@@ -1443,7 +1443,7 @@ static struct clk uart2_ick = {
.name = "uart2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 22,
.recalc = &omap2_followparent_recalc,
};
@@ -1452,7 +1452,7 @@ static struct clk uart2_fck = {
.name = "uart2_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 22,
.recalc = &omap2_followparent_recalc,
};
@@ -1461,7 +1461,7 @@ static struct clk uart3_ick = {
.name = "uart3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1470,7 +1470,7 @@ static struct clk uart3_fck = {
.name = "uart3_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1479,7 +1479,7 @@ static struct clk gpios_ick = {
.name = "gpios_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1488,7 +1488,7 @@ static struct clk gpios_fck = {
.name = "gpios_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_WKUP,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1497,7 +1497,7 @@ static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1506,7 +1506,7 @@ static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_FCLKEN_WKUP,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1515,7 +1515,7 @@ static struct clk sync_32k_ick = {
.name = "sync_32k_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
@@ -1523,7 +1523,7 @@ static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1531,7 +1531,7 @@ static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
@@ -1539,7 +1539,7 @@ static struct clk icr_ick = {
.name = "icr_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = (void __iomem *)CM_ICLKEN_WKUP,
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
@@ -1548,7 +1548,7 @@ static struct clk cam_ick = {
.name = "cam_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 31,
.recalc = &omap2_followparent_recalc,
};
@@ -1557,7 +1557,7 @@ static struct clk cam_fck = {
.name = "cam_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 31,
.recalc = &omap2_followparent_recalc,
};
@@ -1566,7 +1566,7 @@ static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 30,
.recalc = &omap2_followparent_recalc,
};
@@ -1575,7 +1575,7 @@ static struct clk wdt4_ick = {
.name = "wdt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 29,
.recalc = &omap2_followparent_recalc,
};
@@ -1584,7 +1584,7 @@ static struct clk wdt4_fck = {
.name = "wdt4_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 29,
.recalc = &omap2_followparent_recalc,
};
@@ -1593,7 +1593,7 @@ static struct clk wdt3_ick = {
.name = "wdt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 28,
.recalc = &omap2_followparent_recalc,
};
@@ -1602,7 +1602,7 @@ static struct clk wdt3_fck = {
.name = "wdt3_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 28,
.recalc = &omap2_followparent_recalc,
};
@@ -1611,7 +1611,7 @@ static struct clk mspro_ick = {
.name = "mspro_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 27,
.recalc = &omap2_followparent_recalc,
};
@@ -1620,7 +1620,7 @@ static struct clk mspro_fck = {
.name = "mspro_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 27,
.recalc = &omap2_followparent_recalc,
};
@@ -1629,7 +1629,7 @@ static struct clk mmc_ick = {
.name = "mmc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 26,
.recalc = &omap2_followparent_recalc,
};
@@ -1638,7 +1638,7 @@ static struct clk mmc_fck = {
.name = "mmc_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 26,
.recalc = &omap2_followparent_recalc,
};
@@ -1647,7 +1647,7 @@ static struct clk fac_ick = {
.name = "fac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 25,
.recalc = &omap2_followparent_recalc,
};
@@ -1656,7 +1656,7 @@ static struct clk fac_fck = {
.name = "fac_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 25,
.recalc = &omap2_followparent_recalc,
};
@@ -1665,7 +1665,7 @@ static struct clk eac_ick = {
.name = "eac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 24,
.recalc = &omap2_followparent_recalc,
};
@@ -1674,7 +1674,7 @@ static struct clk eac_fck = {
.name = "eac_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 24,
.recalc = &omap2_followparent_recalc,
};
@@ -1683,7 +1683,7 @@ static struct clk hdq_ick = {
.name = "hdq_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 23,
.recalc = &omap2_followparent_recalc,
};
@@ -1692,7 +1692,7 @@ static struct clk hdq_fck = {
.name = "hdq_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 23,
.recalc = &omap2_followparent_recalc,
};
@@ -1702,7 +1702,7 @@ static struct clk i2c2_ick = {
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
@@ -1712,7 +1712,7 @@ static struct clk i2c2_fck = {
.id = 2,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
@@ -1721,7 +1721,7 @@ static struct clk i2chs2_fck = {
.name = "i2chs2_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
@@ -1731,7 +1731,7 @@ static struct clk i2c1_ick = {
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
@@ -1741,7 +1741,7 @@ static struct clk i2c1_fck = {
.id = 1,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
@@ -1750,7 +1750,7 @@ static struct clk i2chs1_fck = {
.name = "i2chs1_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
@@ -1759,7 +1759,7 @@ static struct clk vlynq_ick = {
.name = "vlynq_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN1_CORE,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1768,7 +1768,7 @@ static struct clk vlynq_fck = {
.name = "vlynq_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN1_CORE,
.enable_bit = 3,
.src_offset = 15,
.recalc = &omap2_followparent_recalc,
@@ -1778,7 +1778,7 @@ static struct clk sdrc_ick = {
.name = "sdrc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN3_CORE,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1787,7 +1787,7 @@ static struct clk des_ick = {
.name = "des_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -1796,7 +1796,7 @@ static struct clk sha_ick = {
.name = "sha_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
@@ -1805,7 +1805,7 @@ static struct clk rng_ick = {
.name = "rng_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
@@ -1814,7 +1814,7 @@ static struct clk aes_ick = {
.name = "aes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
@@ -1823,7 +1823,7 @@ static struct clk pka_ick = {
.name = "pka_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN4_CORE,
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
@@ -1832,7 +1832,7 @@ static struct clk usb_fck = {
.name = "usb_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
@@ -1841,7 +1841,7 @@ static struct clk usbhs_ick = {
.name = "usbhs_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
@@ -1850,7 +1850,7 @@ static struct clk mmchs1_ick = {
.name = "mmchs1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
@@ -1859,7 +1859,7 @@ static struct clk mmchs1_fck = {
.name = "mmchs1_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
@@ -1868,7 +1868,7 @@ static struct clk mmchs2_ick = {
.name = "mmchs2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 8,
.recalc = &omap2_followparent_recalc,
};
@@ -1877,7 +1877,7 @@ static struct clk mmchs2_fck = {
.name = "mmchs2_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 8,
.recalc = &omap2_followparent_recalc,
};
@@ -1886,7 +1886,7 @@ static struct clk gpio5_ick = {
.name = "gpio5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
@@ -1895,7 +1895,7 @@ static struct clk gpio5_fck = {
.name = "gpio5_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
@@ -1904,7 +1904,7 @@ static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_ICLKEN2_CORE,
.enable_bit = 11,
.recalc = &omap2_followparent_recalc,
};
@@ -1913,7 +1913,7 @@ static struct clk mmchsdb1_fck = {
.name = "mmchsdb1_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 16,
.recalc = &omap2_followparent_recalc,
};
@@ -1922,7 +1922,7 @@ static struct clk mmchsdb2_fck = {
.name = "mmchsdb2_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = (void __iomem *)CM_FCLKEN2_CORE,
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 7618730..e33cfc8 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -18,7 +18,11 @@ #include <linux/init.h>

#include <asm/io.h>

+#if defined(CONFIG_ARCH_OMAP2420)
#define OMAP24XX_TAP_BASE io_p2v(0x48014000)
+#elif defined(CONFIG_ARCH_OMAP2430)
+#define OMAP24XX_TAP_BASE io_p2v(0x4900A000)
+#endif

#define OMAP_TAP_IDCODE 0x0204
#define OMAP_TAP_PROD_ID 0x0208
@@ -51,6 +55,7 @@ static struct omap_id omap_ids[] __initd
{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
};

+
static u32 __init read_tap_reg(int reg)
{
return __raw_readl(OMAP24XX_TAP_BASE + reg);
@@ -70,7 +75,6 @@ void __init omap2_check_revision(void)
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0x0f;
dev_type = (prod_id >> 16) & 0x0f;
-
#ifdef DEBUG
printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 7d57116..9baedce 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -44,7 +44,21 @@ static struct map_desc omap2_io_desc[] _
.pfn = __phys_to_pfn(L4_24XX_PHYS),
.length = L4_24XX_SIZE,
.type = MT_DEVICE
- }
+ },
+#ifdef CONFIG_ARCH_OMAP2430
+ {
+ .virtual = L4_WK_243X_VIRT,
+ .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
+ .length = L4_WK_243X_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = OMAP243X_GPMC_VIRT,
+ .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
+ .length = OMAP243X_GPMC_SIZE,
+ .type = MT_DEVICE
+ },
+#endif
};

void __init omap2_map_common_io(void)
@@ -66,5 +80,6 @@ void __init omap2_map_common_io(void)
void __init omap2_init_common_hw(void)
{
omap2_mux_init();
+ omap2_prcm_init();
omap2_clk_init();
}
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 1d925d6..30f282b 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -28,11 +28,30 @@ #include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>

-#include "prcm-regs.h"
#include "memory.h"

+#define SDRC_DLLA_CTRL 0x060
+#define DLLPHASE_90 (1 << 1)
+#define UNLOCK_DLL (1 << 2)
+#define SDRC_DLLA_STATUS 0x064
+#define SDRC_DLLB_CTRL 0x068
+#define SDRC_DLLB_STATUS 0x06C
+#define SDRC_POWER 0x070
+#define SDRC_MR_0 0x084
+
+static void __iomem *sdrc_base;
static struct memory_timings mem_timings;

+static inline void sdrc_write_reg(int idx, u32 val)
+{
+ __raw_writel(val, sdrc_base + idx);
+}
+
+static inline u32 sdrc_read_reg(int idx)
+{
+ return __raw_readl(sdrc_base + idx);
+}
+
u32 omap2_memory_get_slow_dll_ctrl(void)
{
return mem_timings.slow_dll_ctrl;
@@ -48,13 +67,27 @@ u32 omap2_memory_get_type(void)
return mem_timings.m_type;
}

+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compenste for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+ /* dlla and dllb are a set */
+ u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+ if ((dll_state & (1 << 2)) == (1 << 2))
+ return 1;
+ else
+ return 0;
+}
+
void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;
u32 fast_dll = 0;

- mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
-
+ /* DDR = 1, SDR = 0 */
+ mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
* In the case of 2422, its ok to use CS1 instead of CS0.
*/
@@ -67,17 +100,17 @@ void omap2_init_memory_params(u32 force_
return;

/* With DDR we need to determine the low frequency DLL value */
- if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
+ if (((mem_timings.fast_dll_ctrl & UNLOCK_DLL) == M_LOCK_CTRL))
mem_timings.dll_mode = M_UNLOCK;
else
mem_timings.dll_mode = M_LOCK;

if (mem_timings.base_cs == 0) {
- fast_dll = SDRC_DLLA_CTRL;
- dll_cnt = SDRC_DLLA_STATUS & 0xff00;
+ fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
+ dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
} else {
- fast_dll = SDRC_DLLB_CTRL;
- dll_cnt = SDRC_DLLB_STATUS & 0xff00;
+ fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
+ dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
}
if (force_lock_to_unlock_mode) {
fast_dll &= ~0xff00;
@@ -95,8 +128,20 @@ void omap2_init_memory_params(u32 force_

/* Turn status into unlock ctrl */
mem_timings.slow_dll_ctrl |=
- ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
+ ((mem_timings.fast_dll_ctrl & 0xF) | UNLOCK_DLL);

/* 90 degree phase for anything below 133Mhz + disable DLL filter */
- mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
+ mem_timings.slow_dll_ctrl |= (DLLPHASE_90 | (3 << 8));
+}
+
+
+static int __init omap2_memory_init(void)
+{
+ if (cpu_is_omap2420())
+ sdrc_base = (void __iomem *)io_p2v(OMAP242X_SDRC_BASE);
+ else if (cpu_is_omap2430())
+ sdrc_base = (void __iomem *)io_p2v(OMAP243X_SDRC_BASE);
+
+ return 0;
}
+arch_initcall(omap2_memory_init);
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index d212eea..3e84d39 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -32,3 +32,4 @@ extern void omap2_init_memory_params(u32
extern u32 omap2_memory_get_slow_dll_ctrl(void);
extern u32 omap2_memory_get_fast_dll_ctrl(void);
extern u32 omap2_memory_get_type(void);
+extern u32 omap2_dll_force_needed(void);
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
index 22ac7be..ee85f96 100644
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ b/arch/arm/mach-omap2/prcm-regs.h
@@ -29,155 +29,165 @@ #define PRCM_FULL_SPEED 2

#ifndef __ASSEMBLER__

-#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
-
-#define PRCM_REVISION PRCM_REG32(0x000)
-#define PRCM_SYSCONFIG PRCM_REG32(0x010)
-#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
-#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
-#define PRCM_VOLTCTRL PRCM_REG32(0x050)
-#define PRCM_VOLTST PRCM_REG32(0x054)
-#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
-#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
-#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
-#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
-#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
-#define PRCM_VOLTSETUP PRCM_REG32(0x090)
-#define PRCM_CLKSSETUP PRCM_REG32(0x094)
-#define PRCM_POLCTRL PRCM_REG32(0x098)
+#define PRCM_REVISION 0x000
+#define PRCM_SYSCONFIG 0x010
+#define PRCM_IRQSTATUS_MPU 0x018
+#define PRCM_IRQENABLE_MPU 0x01C
+#define PRCM_VOLTCTRL 0x050
+#define PRCM_VOLTST 0x054
+#define PRCM_CLKSRC_CTRL 0x060
+#define PRCM_CLKOUT_CTRL 0x070
+#define PRCM_CLKEMUL_CTRL 0x078
+#define PRCM_CLKCFG_CTRL 0x080
+#define PRCM_CLKCFG_STATUS 0x084
+#define PRCM_VOLTSETUP 0x090
+#define PRCM_CLKSSETUP 0x094
+#define PRCM_POLCTRL 0x098

/* GENERAL PURPOSE */
-#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
-#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
-#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
-#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
-#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
-#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
-#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
-#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
-#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
-#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
-#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
-#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
-#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
-#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
-#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
-#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
-#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
-#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
-#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
-#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
+#define GENERAL_PURPOSE1 0x0B0
+#define GENERAL_PURPOSE2 0x0B4
+#define GENERAL_PURPOSE3 0x0B8
+#define GENERAL_PURPOSE4 0x0BC
+#define GENERAL_PURPOSE5 0x0C0
+#define GENERAL_PURPOSE6 0x0C4
+#define GENERAL_PURPOSE7 0x0C8
+#define GENERAL_PURPOSE8 0x0CC
+#define GENERAL_PURPOSE9 0x0D0
+#define GENERAL_PURPOSE10 0x0D4
+#define GENERAL_PURPOSE11 0x0D8
+#define GENERAL_PURPOSE12 0x0DC
+#define GENERAL_PURPOSE13 0x0E0
+#define GENERAL_PURPOSE14 0x0E4
+#define GENERAL_PURPOSE15 0x0E8
+#define GENERAL_PURPOSE16 0x0EC
+#define GENERAL_PURPOSE17 0x0F0
+#define GENERAL_PURPOSE18 0x0F4
+#define GENERAL_PURPOSE19 0x0F8
+#define GENERAL_PURPOSE20 0x0FC

/* MPU */
-#define CM_CLKSEL_MPU PRCM_REG32(0x140)
-#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
-#define RM_RSTST_MPU PRCM_REG32(0x158)
-#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
-#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
-#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
-#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
-#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
-#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
+#define CM_CLKSEL_MPU 0x140
+#define CM_CLKSTCTRL_MPU 0x148
+#define RM_RSTST_MPU 0x158
+#define PM_WKDEP_MPU 0x1C8
+#define PM_EVGENCTRL_MPU 0x1D4
+#define PM_EVEGENONTIM_MPU 0x1D8
+#define PM_EVEGENOFFTIM_MPU 0x1DC
+#define PM_PWSTCTRL_MPU 0x1E0
+#define PM_PWSTST_MPU 0x1E4

/* CORE */
-#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
-#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
-#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
-#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
-#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
-#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
-#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
-#define CM_IDLEST1_CORE PRCM_REG32(0x220)
-#define CM_IDLEST2_CORE PRCM_REG32(0x224)
-#define CM_IDLEST3_CORE PRCM_REG32(0x228)
-#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
-#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
-#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
-#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
-#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
-#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
-#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
-#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
-#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
-#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
-#define PM_WKST1_CORE PRCM_REG32(0x2B0)
-#define PM_WKST2_CORE PRCM_REG32(0x2B4)
-#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
-#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
-#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
+#define CM_FCLKEN1_CORE 0x200
+#define CM_FCLKEN2_CORE 0x204
+#define CM_FCLKEN3_CORE 0x208
+#define CM_ICLKEN1_CORE 0x210
+#define CM_ICLKEN2_CORE 0x214
+#define CM_ICLKEN3_CORE 0x218
+#define CM_ICLKEN4_CORE 0x21C
+#define CM_IDLEST1_CORE 0x220
+#define CM_IDLEST2_CORE 0x224
+#define CM_IDLEST3_CORE 0x228
+#define CM_IDLEST4_CORE 0x22C
+#define CM_AUTOIDLE1_CORE 0x230
+#define CM_AUTOIDLE2_CORE 0x234
+#define CM_AUTOIDLE3_CORE 0x238
+#define CM_AUTOIDLE4_CORE 0x23C
+#define CM_CLKSEL1_CORE 0x240
+#define CM_CLKSEL2_CORE 0x244
+#define CM_CLKSTCTRL_CORE 0x248
+#define PM_WKEN1_CORE 0x2A0
+#define PM_WKEN2_CORE 0x2A4
+#define PM_WKST1_CORE 0x2B0
+#define PM_WKST2_CORE 0x2B4
+#define PM_WKDEP_CORE 0x2C8
+#define PM_PWSTCTRL_CORE 0x2E0
+#define PM_PWSTST_CORE 0x2E4

/* GFX */
-#define CM_FCLKEN_GFX PRCM_REG32(0x300)
-#define CM_ICLKEN_GFX PRCM_REG32(0x310)
-#define CM_IDLEST_GFX PRCM_REG32(0x320)
-#define CM_CLKSEL_GFX PRCM_REG32(0x340)
-#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
-#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
-#define RM_RSTST_GFX PRCM_REG32(0x358)
-#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
-#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
-#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
+#define CM_FCLKEN_GFX 0x300
+#define CM_ICLKEN_GFX 0x310
+#define CM_IDLEST_GFX 0x320
+#define CM_CLKSEL_GFX 0x340
+#define CM_CLKSTCTRL_GFX 0x348
+#define RM_RSTCTRL_GFX 0x350
+#define RM_RSTST_GFX 0x358
+#define PM_WKDEP_GFX 0x3C8
+#define PM_PWSTCTRL_GFX 0x3E0
+#define PM_PWSTST_GFX 0x3E4

/* WAKE-UP */
-#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
-#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
-#define CM_IDLEST_WKUP PRCM_REG32(0x420)
-#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
-#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
-#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
-#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
-#define RM_RSTST_WKUP PRCM_REG32(0x458)
-#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
-#define PM_WKST_WKUP PRCM_REG32(0x4B0)
+#define CM_FCLKEN_WKUP 0x400
+#define CM_ICLKEN_WKUP 0x410
+#define CM_IDLEST_WKUP 0x420
+#define CM_AUTOIDLE_WKUP 0x430
+#define CM_CLKSEL_WKUP 0x440
+#define RM_RSTCTRL_WKUP 0x450
+#define RM_RST_GS (1 << 1)
+#define RM_RST_DPLL (1 << 2)
+#define RM_RSTTIME_WKUP 0x454
+#define RM_RSTST_WKUP 0x458
+#define RM_GLOBAL_COLD_RST (1 << 0)
+#define RM_GLOBAL_WMPU_RST (1 << 1)
+#define RM_SECU_VIOL_RST (1 << 3)
+#define RM_MPU_VIOL_RST (1 << 4)
+#define RM_SECU_WD_RST (1 << 5)
+#define RM_EXTWMPU_RST (1 << 6)
+#define PM_WKEN_WKUP 0x4A0
+#define PM_WKST_WKUP 0x4B0

/* CLOCKS */
-#define CM_CLKEN_PLL PRCM_REG32(0x500)
-#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
-#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
-#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
-#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
+#define CM_CLKEN_PLL 0x500
+#define CM_IDLEST_CKGEN 0x520
+#define CM_AUTOIDLE_PLL 0x530
+#define CM_CLKSEL1_PLL 0x540
+#define CM_CLKSEL2_PLL 0x544

/* DSP */
-#define CM_FCLKEN_DSP PRCM_REG32(0x800)
-#define CM_ICLKEN_DSP PRCM_REG32(0x810)
-#define CM_IDLEST_DSP PRCM_REG32(0x820)
-#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
-#define CM_CLKSEL_DSP PRCM_REG32(0x840)
-#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
-#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
-#define RM_RSTST_DSP PRCM_REG32(0x858)
-#define PM_WKEN_DSP PRCM_REG32(0x8A0)
-#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
-#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
-#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
-#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
-#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
+#define CM_FCLKEN_DSP 0x800
+#define CM_ICLKEN_DSP 0x810
+#define CM_IDLEST_DSP 0x820
+#define CM_AUTOIDLE_DSP 0x830
+#define CM_CLKSEL_DSP 0x840
+#define CM_CLKSTCTRL_DSP 0x848
+#define RM_RSTCTRL_DSP 0x850
+#define RM_RSTST_DSP 0x858
+#define PM_WKEN_DSP 0x8A0
+#define PM_WKDEP_DSP 0x8C8
+#define PM_PWSTCTRL_DSP 0x8E0
+#define PM_PWSTST_DSP 0x8E4
+#define PRCM_IRQSTATUS_DSP 0x8F0
+#define PRCM_IRQENABLE_DSP 0x8F4

/* IVA */
-#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
-#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
+#define PRCM_IRQSTATUS_IVA 0x8F8
+#define PRCM_IRQENABLE_IVA 0x8FC

/* Modem on 2430 */
-#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
-#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
-#define CM_IDLEST_MDM PRCM_REG32(0xC20)
-#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
-#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
-#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
-#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
-#define RM_RSTST_MDM PRCM_REG32(0xC58)
-#define PM_WKEN_MDM PRCM_REG32(0xCA0)
-#define PM_WKST_MDM PRCM_REG32(0xCB0)
-#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
-#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
-#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
+#define CM_FCLKEN_MDM 0xC00
+#define CM_ICLKEN_MDM 0xC10
+#define CM_IDLEST_MDM 0xC20
+#define CM_AUTOIDLE_MDM 0xC30
+#define CM_CLKSEL_MDM 0xC40
+#define CM_CLKSTCTRL_MDM 0xC48
+#define RM_RSTCTRL_MDM 0xC50
+#define RM_RSTST_MDM 0xC58
+#define PM_WKEN_MDM 0xCA0
+#define PM_WKST_MDM 0xCB0
+#define PM_WKDEP_MDM 0xCC8
+#define PM_PWSTCTRL_MDM 0xCE0
+#define PM_PWSTST_MDM 0xCE4

#define OMAP24XX_L4_IO_BASE 0x48000000

#define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000)
#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))

+#if defined(CONFIG_ARCH_OMAP2420)
#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
+#elif defined(CONFIG_ARCH_OMAP2430)
+#define OMAP24XX_GPMC_BASE (0x6E000000)
+#endif
#define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset))

/* FIXME: Move these to timer code */
@@ -262,14 +272,6 @@ #define GPTIMER1_TCAR2 GPT1_REG32(0x044
/* rkw -- base fix up please... */
#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)

-/* SDRC */
-#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
-#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
-#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
-#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
-#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
-
/* GPIO 1 */
#define GPIO1_BASE GPIOX_BASE(1)
#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
@@ -433,6 +435,15 @@ #define GPMC_CONFIG5_3 GPMC_REG32(0x100
#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
#define GPMC_CONFIG7_3 GPMC_REG32(0x108)

+/* GPMC CS5 */
+#define GPMC_CONFIG1_5 GPMC_REG32(0x150)
+#define GPMC_CONFIG2_5 GPMC_REG32(0x154)
+#define GPMC_CONFIG3_5 GPMC_REG32(0x158)
+#define GPMC_CONFIG4_5 GPMC_REG32(0x15C)
+#define GPMC_CONFIG5_5 GPMC_REG32(0x160)
+#define GPMC_CONFIG6_5 GPMC_REG32(0x164)
+#define GPMC_CONFIG7_5 GPMC_REG32(0x168)
+
/* DSS */
#define DSS_CONTROL DISP_REG32(0x040)
#define DISPC_CONTROL DISP_REG32(0x440)
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index d261e4f..5c212b1 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -30,17 +30,31 @@ #include <asm/hardware.h>

#include "prcm-regs.h"

-#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
-
-#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
-#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
-#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
-#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
-#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
-#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
-
-#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
+#if defined(CONFIG_ARCH_OMAP2420)
+#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP242X_32KSYNCT_BASE + 0x010)
+
+#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x544)
+#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x050)
+#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x080)
+#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x500)
+#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x520)
+#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP242X_PRCM_BASE + 0x540)
+
+#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP242X_SDRC_BASE + 0x060)
+#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP242X_SDRC_BASE + 0x0a4)
+#elif defined(CONFIG_ARCH_OMAP2430)
+#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP243X_32KSYNCT_BASE + 0x010)
+
+#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP243X_PRCM_BASE + 0x544)
+#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP243X_PRCM_BASE + 0x050)
+#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP243X_PRCM_BASE + 0x080)
+#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP243X_PRCM_BASE + 0x500)
+#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP243X_PRCM_BASE + 0x520)
+#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP243X_PRCM_BASE + 0x540)
+
+#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP243X_SDRC_BASE + 0x060)
+#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP243X_SDRC_BASE + 0x0a4)
+#endif

.text

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index e75a2ca..333d4e6 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -87,10 +87,18 @@ #define OMAP730_GPIO_INT_STATUS 0x14
/*
* omap24xx specific GPIO registers
*/
+#if defined(CONFIG_ARCH_OMAP2420)
#define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
#define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
#define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
#define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
+#elif defined(CONFIG_ARCH_OMAP2430)
+#define OMAP24XX_GPIO1_BASE (void __iomem *)0x4900C000
+#define OMAP24XX_GPIO2_BASE (void __iomem *)0x4900E000
+#define OMAP24XX_GPIO3_BASE (void __iomem *)0x49010000
+#define OMAP24XX_GPIO4_BASE (void __iomem *)0x49012000
+#define OMAP24XX_GPIO5_BASE (void __iomem *)0x480B6000
+#endif
#define OMAP24XX_GPIO_REVISION 0x0000
#define OMAP24XX_GPIO_SYSCONFIG 0x0010
#define OMAP24XX_GPIO_SYSSTATUS 0x0014
@@ -159,14 +167,23 @@ static struct gpio_bank gpio_bank_730[7]
};
#endif

-#ifdef CONFIG_ARCH_OMAP24XX
-static struct gpio_bank gpio_bank_24xx[4] = {
+#ifdef CONFIG_ARCH_OMAP2420
+static struct gpio_bank gpio_bank_2420[4] = {
{ OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
{ OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
{ OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
{ OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
};
#endif
+#ifdef CONFIG_ARCH_OMAP2430
+static struct gpio_bank gpio_bank_2430[5] = {
+ { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
+ { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
+ { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
+ { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
+ { OMAP24XX_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
+};
+#endif

static struct gpio_bank *gpio_bank;
static int gpio_bank_count;
@@ -961,6 +978,8 @@ static struct irqchip mpuio_irq_chip = {
static int initialized;
static struct clk * gpio_ick;
static struct clk * gpio_fck;
+static struct clk * gpio5_ick;
+static struct clk * gpio5_fck;

static int __init _omap_gpio_init(void)
{
@@ -988,6 +1007,19 @@ static int __init _omap_gpio_init(void)
else
clk_enable(gpio_fck);
}
+
+ if (cpu_is_omap2430()) {
+ gpio5_ick = clk_get(NULL, "gpio5_ick");
+ if (IS_ERR(gpio5_ick))
+ printk("Could not get gpio5_ick\n");
+ else
+ clk_enable(gpio5_ick);
+ gpio5_fck = clk_get(NULL, "gpio5_fck");
+ if (IS_ERR(gpio5_fck))
+ printk("Could not get gpio5_fck\n");
+ else
+ clk_enable(gpio5_fck);
+ }

#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap15xx()) {
@@ -1014,17 +1046,29 @@ #ifdef CONFIG_ARCH_OMAP730
gpio_bank = gpio_bank_730;
}
#endif
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2420
if (cpu_is_omap24xx()) {
int rev;

gpio_bank_count = 4;
- gpio_bank = gpio_bank_24xx;
+ gpio_bank = gpio_bank_2420;
+ rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+ printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
+ (rev >> 4) & 0x0f, rev & 0x0f);
+ }
+#endif
+#ifdef CONFIG_ARCH_OMAP2430
+ if (cpu_is_omap2430()) {
+ int rev;
+
+ gpio_bank_count = 5;
+ gpio_bank = gpio_bank_2430;
rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
}
#endif
+
for (i = 0; i < gpio_bank_count; i++) {
int j, gpio_count = 16;

diff --git a/include/asm-arm/arch-omap/board-sdp2430.h b/include/asm-arm/arch-omap/board-sdp2430.h
new file mode 100644
index 0000000..2a9676e
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-sdp2430.h
@@ -0,0 +1,38 @@
+/*
+ * linux/include/asm-arm/arch-omap/board-sdp2430.h
+ *
+ * Hardware definitions for TI OMAP2430 SDP2430 board.
+ *
+ * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_SDP2430_H
+#define __ASM_ARCH_OMAP_SDP2430_H
+
+/* Placeholder for SDP2430 specific defines */
+/* GPMC CS5 */
+#define OMAP24XX_ETHR_START 0x08000300
+#define OMAP24XX_ETHR_GPIO_IRQ 149
+#define SDP2430_CS0_BASE 0x04000000
+#endif /* __ASM_ARCH_OMAP_SDP2430_H */
+
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 4d226b2..288c07f 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -314,6 +314,10 @@ #ifdef CONFIG_MACH_OMAP_APOLLON
#include "board-apollon.h"
#endif

+#ifdef CONFIG_MACH_OMAP_SDP2430
+#include "board-sdp2430.h"
+#endif
+
#ifdef CONFIG_MACH_OMAP_OSK
#include "board-osk.h"
#endif
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index b726acf..270a6ce 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -73,6 +73,12 @@ #define L3_24XX_SIZE SZ_1M /* 44kB of 1
#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
#define L4_24XX_VIRT 0xd8000000
#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
+#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
+#define L4_WK_243X_VIRT 0xd9000000
+#define L4_WK_243X_SIZE SZ_1M
+#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
+#define OMAP243X_GPMC_VIRT 0xFE000000
+#define OMAP243X_GPMC_SIZE SZ_1M
#define IO_OFFSET 0x90000000
#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 42098d9..f99e93c 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -242,6 +242,7 @@ #define INT_24XX_GPIO_BANK1 29
#define INT_24XX_GPIO_BANK2 30
#define INT_24XX_GPIO_BANK3 31
#define INT_24XX_GPIO_BANK4 32
+#define INT_24XX_GPIO_BANK5 33
#define INT_24XX_MCBSP1_IRQ_TX 59
#define INT_24XX_MCBSP1_IRQ_RX 60
#define INT_24XX_MCBSP2_IRQ_TX 62
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 6e59805..a652211 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -8,6 +8,7 @@ #define __ASM_ARCH_OMAP24XX_H
*/

#define L4_24XX_BASE 0x48000000
+#define L4_WK_243X_BASE 0x49000000
#define L3_24XX_BASE 0x68000000

/* interrupt controller */
@@ -16,9 +17,13 @@ #define VA_IC_BASE IO_ADDRESS(OMAP24XX_
#define OMAP24XX_IVA_INTC_BASE 0x40000000
#define IRQ_SIR_IRQ 0x0040

-#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
-#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000)
+#define OMAP242X_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
+#define OMAP243X_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
+#define OMAP242X_PRCM_BASE (L4_24XX_BASE + 0x8000)
+#define OMAP243X_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
+#define OMAP242X_SDRC_BASE (L3_24XX_BASE + 0x9000)
+#define OMAP243X_SDRC_BASE 0x6D000000
+#define OMAP243X_GPMC_BASE 0x6E000000

#endif /* __ASM_ARCH_OMAP24XX_H */

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